TPS51513_16 [TI]
SINGLE PHASE, D-CAP SYNCHRONOUS BUCK CONTROLLER;
| 型号： | TPS51513_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE PHASE, D-CAP SYNCHRONOUS BUCK CONTROLLER |
| 文件： | 总37页 (文件大小：1089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51513
www.ti.com ...................................................................................................................................................................................................... SLUS956–JUNE 2009
SINGLE PHASE, D-CAP+™ SYNCHRONOUS BUCK CONTROLLER
WITH INTEGRATED DRIVERS FOR GENERAL IC V ™ APPLICATIONS
CORE
1
FEATURES
DESCRIPTION
23
•
Minimum External Parts Count
•
Includes Accurate Output Current Monitor with
Programmable Clamp Voltage
The TPS51513 is a single-phase synchronous buck
controller with integrated gate drivers. Advanced
control features such as the D-CAP+™ architecture
and OSR™ overshoot reduction provide fast transient
response, low output capacitance and high efficiency.
The TPS51513 supports a wide range of IC VCORE
applications with an integrated 3-bit DAC. It also
provides a full complement of signal I/O including a
sleep mode control (SLP), two power good signals
(PGOOD and PG), and an analog current monitor
(IMON). Logic inputs are compatible with either 1-V
or 3.3-V logic levels. VCORE slew rates are controlled
with one resistor. In addition, the TPS51513 includes
high-current FET gate drivers with an integrated P/N
junction diode to drive N-channel FETs with low
switching loss. The TPS51513 is available in the
5 mm × 5 mm, 32-pin QFN package and operates
between –10°C and 100°C.
•
•
•
•
•
•
3-Bit DAC Selects 1 of 8 Output Voltages
Custom VID Definition Available
Supports VID-on-the-Fly Voltage Changes
±8-mV VCORE Accuracy Over Line/Load/Temp.
Optimized Efficiency at Light and Heavy Loads
Patented Output Overshoot Reduction (OSR™)
Reduces Output Capacitance
•
Accurate, Adjustable Voltage Positioning
Including No-Droop Option
•
•
•
•
•
Selectable 250/300/350/500 kHz Frequency
Accurate, 8-level Selectable Current Limit
3-V to 28-V Conversion Voltage Range
Fast FET Driver w/Integrated Boost Diode
5 mm × 5 mm, 32-Pin QFN PowerPAD™
Package
ORDERING INFORMATION
TA
PLASTIC QFN (RHB)
–10°C to 100°C
TPS51513RHB (32-pin)
APPLICATIONS
•
General IC VCORE Applications
VREF
C2
V5FILT
VREF
R2
C3
EN
PG PGOOD
C5
C1
R3
32 31 30 29 28 27 26 25
R1
1
2
3
4
5
6
7
8
GND
PG 24
PGOOD 23
PGND 22
V5IN 21
CSP
CSN
CSNS
CSP
RT1
CSN
R4
C4
GNDFB
VCCFB
GSNS
VSNS
REF
Q1
R5
TP51513RHB
DRVL 20
LL 19
L1
CSN
R6
C6
IMON2
IMON
VBST 18
DRVH 17
VOUT
VCCFB
IMON
+
Q2
C7
R7
5 V
COUT1
VBAT
9
10 11 12 13 14 15 16
GNDFB
C8
CIN1
GNDFB
UDG-09085
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
OSR, PowerPAD, D-CAP+ are trademarks of Texas Instruments.
Mathcad is a registered trademark of Parametric Technology Corporation .
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS51513
SLUS956–JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNIT
VBST
–0.3 V to 36 V
–0.3 V to 6 V
VBST to LL
Input voltage range(2)
Output voltage range(2)
CSP, CSN, EN, IMON2, ISLEW, OSRSEL, REF, SLP,
TONSEL, TRIPSEL, V5IN, V5FILT, VID0, VID1, VID2, VSNS
–0.3 V to 6 V
LL
–5.0 V to 30 V
–5.0 V to 36 V
–0.3 V to 6 V
DRVH
DRVH to LL
DROOP, DRVL, IMON, IMON2 IMONC, PG, PGOOD, VREF
GSNS, PGND
–0.3 V to 6 V
–0.3 V to 0.3 V
–40°C to +150°C
–55°C to +150°C
Operating junction temperature, TJ
Storage temperature, Tstg
:
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATING TABLE (2 OZ. TRACE AND COPPER PAD WITH SOLDER)
TA< 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
32 pin RHB
2.94 W
29.4 mW / °C
1.17 W
RECOMMENDED OPERATING CONDITIONS
MIN
3.0
TYP
MAX
28
UNIT
Conversion voltage (no pin assigned)
Supply voltages
V5IN, V5FILT
V
4.5
5.5
34
VBST
–0.1
–0.8
–0.8
–0.1
–0.1
–0.1
–0.1
–10
Voltage range, conversion pins
DRVH
34
V
LL
28
Voltage range, 5-V pins
Voltage range, 3.3-V pins
Voltage range, low-voltage pins
Ground pins
DRVL, OSRSEL, TONSEL, TRIPSEL
5.5
3.6
2.0
0.1
100
V
V
EN, IMON, IMONC, PG, PGOOD, SLP, VID0, VID1, VID2
CSN, CSP, DROOP, IMON2, ISLEW, REF, VREF, VSNS
GSNS, PGND
V
V
Operating free-air temperature, TA
°C
2
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, V5IN = V5FILT = 5.0V, GSNS = PGND = GND, VSNS = VCORE (Unless
otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY: CURRENTS, UVLO AND POWER-ON RESET
IV5
V5IN + V5FILT supply current
V5IN + V5FILT standby current
VDAC < VSNS < VDAC + 100 mV, EN = ‘HI’
EN = ‘LO’
2
4
mA
IV5STBY
10
µA
V5FILT = V5IN, VSNS < 200 mV, Ramp up;
EN=’HI’; Switching begins.
VUVLOH
V5FILT UVLO ‘OK’ threshold
4.25
4.0
4.4
4.2
4.5
4.3
V
V
V5FILT = V5IN, Ramp down; EN = ’HI’, VSNS =
100 mV, Restart if 5 V dips below VPOR then
rises > VUVLOH, or EN is toggled with 5 V >
VUVLOH
VUVLOL
V5FILT UVLO fault threshold
V5FILT=V5IN, Ramp Down, EN=‘HI’. Can
VPOR
V5FILT fault latch reset threshold restart if 5 V goes up to VUVLOH and no other
faults present.
1.6
1.9
2.3
V
REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE
VVIDSTP
VDAC1
VID step size
Change VID0 HI to LO to HI
0.75 V ≤ VSNS ≤ 1.25 V
12.5
mV
VSNS voltage range 1
VSNS no voltage range 2
VSNS voltage range 3
VSNS voltage range 4
VREF output voltage
VREF output source
VREF output sink
–0.5%
–8
0.5%
8
VDAC2
0.50V ≤ VSNS ≤ 0.75 V
mV
mV
VDAC3
0.30V ≤ VSNS ≤ 0.50 V
–12
12
VDAC4
1.25V ≤ VSNS ≤ 1.50 V
–1%
1%
VVREF
4.5V ≤ V5FILT ≤ 5.5 V, IREF = 0 A
IREF = 0 to 250 µA
1.665 1.700
1.735
V
VVREFSRC
VVREFSNK
VDLDQDRVL
–9
–3
10
mV
mV
mV
IREF = –250 µA to 0 µA
39
Discharge threshold
VSNS < 200 mV, DRVL goes high for 1 ms
200
250
325
VOLTAGE SENSE: VSNS AND GSNS
IVSNS
VSNS input bias current
Not in Fault, Disable or UVLO
9
40
µA
µA
VSNS input bias current,
discharge
IVSNSDQ
Fault, Disable or UVLO, VSNS = 100 mV
90
125
175
IGSNS
GSNS input bias current
GSNS differential
–40
–8
±300
1
µA
mV
V/V
V
VDELGND
AGAINGND
VVSNSCOM
GSNS/GND gain
0.993
–0.3
1.009
2
VSNS common mode dnput
Copyright © 2009, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, V5IN = V5FILT = 5.0V, GSNS = PGND = GND, VSNS = VCORE (Unless
otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE: OVERCURRENT, ZERO CROSSING AND VOLTAGE POSITIONING
ICS
CS input bias current
CSP and CSN
CSP–CSN
–1.0
–1.5
1.0
0.7
µA
Zero crossing comp. internal
offset
VZXOFF
mV
Droop amplifier
transconductance
GM-DROOP
VSNS = 1 V
485
500
519
µS
VDCLAMPN
VDCLAMPP
ACSINT
Droop amplifier clamp voltage
Droop amplifier clamp voltage
Internal current sense gain
VREF – VDROOP
46
600
mV
mV
V/V
VDROOP – VREF
Gain from CSP - CSN to modulator
TRIPSEL = GND; RSLEW tied to GND
TRIPSEL = REF; RSLEW tied to GND
TRIPSEL = 3.3 V; RSLEW tied to GND
TRIPSEL = V5FILT; RSLEW tied to GND
TRIPSEL = GND; RSLEW tied to VREF
TRIPSEL = REF; RSLEW tied to VREF
TRIPSEL = 3.3 V; RSLEW tied to VREF
TRIPSEL = V5FILT; RSLEW tied to VREF
TRIPSEL = GND; RsLEW tied to GND
TRIPSEL = REF; RSLEW tied to GND
TRIPSEL = 3.3 V; RSLEW tied to GND
TRIPSEL = V5FILT; RSLEW tied to GND
TRIPSEL = GND; RSLEW tied to VREF
TRIPSEL = REF; RSLEW tied to VREF
TRIPSEL = 3.3 V; RSLEW tied to VREF
TRIPSEL = V5FILT; RSLEW tied to VREF
5.92
10.1
12.9
16.1
20.4
25.1
31.4
39.2
50.4
14.0
17.2
21.3
28.1
34.5
42.9
54.3
67.6
6
6.06
12.8
15.4
18.8
23.2
28.5
35.3
43.8
55.7
17.4
20.4
24.6
31.1
38.0
46.1
57.9
71.2
11.4
14.0
17.4
21.7
26.7
33.3
41.5
53.1
15.6
19.0
23.1
29.7
36.3
44.6
56.2
69.4
OCP voltage set
(Valley current limit)
VOCPP
mV
Negative OCP voltage set (valley
current limit)
VOCPN
mV
DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER
VBST – LL = 5 V, ‘HI’ State VBST – VDRVH =
0.1 V
0.9
2.5
2.5
RDRVH
DRVH on-resistance
Ω
VBST – LL = 5 V, ‘LO’ State VDRVH – VLL =
0.1 V
0.7
2.2
15
IDRVH
tDRVH
DRVH sink/source current(1)
DRVH transition time
DRVH forced to 2.5 V, VBST – LL forced to 5 V
A
DRVH 10% to 90% or 90% to 10%,
CDRVH = 3 nF
25
ns
‘HI’ State, V5IN – VDRVL = 0.1 V
‘LO’ State, VDRVL – PGND = 0.1 V
DRVL forced to 2.5 V, Source
0.7
0.45
2.7
8
2
1
RDRVL
DRVL on-resistance
Ω
A
A
IDRVL
DRVL Sink/Source current(1)
DRVL transition time
DRVL forced to 2.5 V, Sink
DRVL 90% to 10%, CDRVL = 3 nF
DRVL 10% to 90%, CDRVL = 3 nF
LL falls to 1 V to DRVL rises to 1 V
DRVL falls to 1 V to DRVH rises to 1 V
V5IN – VBST, IF=5 mA, TA = 25°C
VVBST = 34 V, VLL=28 V
12
25
25
25
35
0.8
1
tDRVL
ns
ns
12
15
22
19
tNONOVLP
Driver non-overlap time
27
VFBST
IBSTLK
BST rectifier forward voltage
BST rectifier leakage current
0.6
0.7
0.1
V
µA
(1) Ensured by design. Not production tested.
4
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TPS51513
www.ti.com ...................................................................................................................................................................................................... SLUS956–JUNE 2009
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, V5IN = V5FILT = 5.0V, GSNS = PGND = GND, VSNS = VCORE (Unless
otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OVERSHOOT REDUCTION (OSR) THRESHOLD SETTING
VOSRSEL = GND
85
119
163
133
170
220
VOSRSEL = REF
VOSRSEL = 3.3 V
VOSR
OSR voltage set
mV
mV
VOSRSEL = V5FILT; OSR is OFF
All settings
N/A
20
VOSRHYS
OSR voltage hysteresis(2)
TIMERS: SLEW RATE, ISLEW, ON-TIME AND I/O TIMING
ISLEW 1
ISLEW 2
RSLEW to GND current
RSLEW to VREF current
RSLEW = 125 kΩ from ISLEW to GND
RSLEW = 45 kΩ from VREF to ISLEW
9.9
9.5
10
10
10.15
10.8
µA
µA
ISLEW = |10 µA|, No Faults, Time from EN to
VSNS = VVID = 1.0
tSTARTUP
VSNS startup time
0.6
1.3
1.15
ms
ISLEW = |10 A|, EN goes ‘HI’ (Soft-start)
Non-OVP Fault = ‘Soft-stop’
SLSTRTSTP
VSNS slew soft-start / soft-stop
1.6
1.9 mV/µs
15 mV/µs
ISLEW = |10 µA|, SLP goes low/high. Measure
slew on SLP transition.
SLSLPE
tPGDPO
VSNS slew SLP exit
10
3
12.5
6
PGOOD power-on delay time
PGOOD deglitch time
Time from PG going low to PGOOD going HI
9
ms
Time from VSNS out of +200 mV/–300 mV
VDAC boundary to PGOOD low.
tPGDDGLT
50
100
160
µs
VTON = GND, VLL=12 V, VSNS=1 V
VTON = REF, VLL=12 V, VSNS=1 V
VTON = 3.3 V, VLL=12 V, VSNS=1 V
VTON = 5 V, VLL=12 V, VSNS=1 V
Fixed value
265
215
180
140
80
319
259
215
160
105
385
295
250
185
125
tON
On-time control
ns
tMIN
Controller minimum off-time
VID debounce time(2)
ns
ns
ns
ns
ns
tVIDDBNC
tVCCVID
tVRONPGD
tPGDVCC
100
(2)
VID change to VSNS change
600
100
100
EN low to PGOOD low
PGOOD low to VSNS change(2)
PROTECTION: OVP, PGOOD, FAULTS OFF AND INTERNAL THERMAL SHUTDOWN
Internal high OVP threshold
voltage
VVOVPH
VPGDH
VPGDL
THINT
VSNS > VOVPH for 500 ns, DRVL turns ON
1.50
183
1.55
215
–315
160
10
1.60
247
V
Measured at the VSNS pin wrt/VID code. device
latches OFF, begins soft-stop.
PGOOD high threshold
mV
mV
°C
Measured at the VSNS pin wrt/VID code. device
latches off, begins soft-stop.
PGOOD low threshold
–358
–275
Internal controller thermal
shutdown(2)
Not final tested. Latch off controller, attempt
soft-stop.
Not final tested. Controller will start again after
temperature has dropped.
THHYS
Thermal shutdown hysteresis(2)
°C
(2) Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, V5IN = V5FILT = 5.0V, GSNS = PGND = GND, VSNS = VCORE (Unless
otherwise noted).
PARAMETER
CURRENT MONITOR
CONDITIONS
MIN
TYP
MAX
UNIT
VCSP – VCSN = 0 mV; RIMON = 69.8 kΩ;
RIMON2 = 23.7 kΩ, VIMONC = 3.3 V
VPWRLK
VPWRLO
VPWRMID
VPWRHI
No output current
40
700
mV
mV
V
VCSP – VCSN = 5 mV; RIMON = 69.8 kΩ;
RIMON2 = 23.7 kΩ, VIMONC = 3.3 V
Low-level power output
Mid-level power output
High-level power output
590
1.29
2.92
826
1.51
3.18
VCSP – VCSN = 10 mV; RIMON = 69.8 kΩ;
RIMON2 = 23.7 kΩ, VIMONC = 3.3 V
1.40
VCSP – VCSN = 22 mV; RIMON = 69.8 kΩ;
RIMON2 = 23.7 kΩ, VIMONC = 3.3 V
3.04
2
V
KIMON
Gain factor
µA/mV
µA
IIMONSRC
IMON source
VCSP – VCSN = 30 mV
50
VCSP – VCSN = 40 mV; RIMON = Open;
V=VIMONC
VIMONCL
IMON clamp
V–33
V
V+33
mV
(VV5FILT – VIMONC); Required for Specified
Operation of the IMON Clamp
VIMONC-HR
VIMONC-Z
IMON clamp headroom
1.4
V
IMON clamp input impedance
Resistance to GND
100
kΩ
LOGIC PINS: I/O VOLTAGE AND CURRENT
VCLKPGL
ICLKPGLK
V1VH
PG, PGOOD pul-down voltage
PG, PGOOD leakage current
I/O 1V logic high
Pull down voltage with 3-mA sink current
Hi-Z Leakage Current, Apply 5-V in off state
EN, SLP, VID0, VID1, VID2
0.1
0.2
0.4
2
V
–2
µA
V
0.8
V1VL
I/O 1V logic low
EN, SLP, VID0, VID1, VID2
0.3
1
V
I1VLK
I/O 1V leakage – Off
I/O 1V leakage – On
I/O 1V leakage – Lo
EN current – On
EN = 0V; SLP = VID0 = VID1 = VID2 = 1 V
EN = SLP = VID0 = VID1 = VID2 = 1 V
EN = 1 V; SLP = VID0 = VID1 = VID2 = 0V
EN = 1 V
–1
5
0
µA
µA
µA
µA
µA
µA
I1VLKON
I1VLKLO
IENHI
10
15
1
–3
10
1
IENLO
EN current – OFF
EN = 0 V
–3
–2
ISELECT
Select line current
VTRIPSEL = VOSRSEL = VTONSEL = 5 V
1.5
5
6
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TPS51513
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TPS51513
(Top View)
32 31 30 29 28 27 26 25
24 PG
GND
CSP
1
2
3
4
5
6
7
8
23 PGOOD
22
21
20
19
18
17
PGND
V5IN
DRVL
LL
CSN
GSNS
VSNS
REF
TM
PowerPAD
VBST
DRVH
IMON2
IMON
9
10 11 12 13 14 15 16
Table 1. Pin Functions
PIN # NAME
I/O
DESCRIPTION
Negative current sense input. Connect to the negative node of current sense resistor or inductor DCR sense
RC network.
3
2
CSN
I
Positive current sense input. Connect to the positive node of current sense resistor or inductor DCR sense
RC network.
CSP
I
Output of gM error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the
transient response. Please see Applications Information section for configurations with no droop.
31
DROOP
O
17
20
25
1
DRVH
DRVL
EN
O
O
I
Top N-channel FET gate drive outputs.
Synchronous N-channel FET gate drive outputs.
Chip enable signal. 1-V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.
Analog / signal ground. Tie to quiet ground plane.
GND
—
Voltage sense return tied directly to GND of the microprocessor. Tie to GND with a 10-Ω resistor for
feedback when µP is not present.
4
GSNS
I
Current monitor output. The current out of the IMON output is proportional to the voltage between the CS
inputs.
8
7
IMON
O
O
I
IMON2
IMONC
Connection point for IMON mirror matching resistor.
Clamp reference input for the IMON signal; 3.6-V maximum. Bypass to GND with a ceramic capacitor of 0.1
µF or greater.
12
Precision current set-point for slew rate control. Tie the ISLEW resistor to GND to select the low range of
OCP values; VREF for the higher range.
29
ISLEW
LL
I
19
10
11
13
I/O
Top N-channel FET gate drive return. Also, input for adaptive gate drive timing.
NC
—
No connection; leave floating.
Overshoot reduction (OSR) setting. One of three OSR settings is selected with OSRSEL = GND/VREF/3.3
V. OSRSEL = 5 V disables OSR.
28
24
OSRSEL
PG
I
Negative active power good output. Transitions low of approximately 50 µs after VCORE reaches the
VID-defined level. Open-drain. Leave open if unused.
O
22
23
PGND
—
O
Power return for the synchronous N-channel FET gate driver outputs.
Power Good output. 6-ms nominal delay from PG. Open-drain.
PGOOD
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Table 1. Pin Functions (continued)
PIN # NAME
I/O
DESCRIPTION
6
9
REF
I
I
I
Termination for test circuitry. Connect to VREF.
SLP
Sleep mode control. 1-V I/O level. 100-ns de-bounce.
On-time selection pin. One of four operating frequencies is selected with TONSEL = GND/VREF/3.3V/5V.
27
TONSEL
Overcurrent protection (OCP) setting. One of eight valley-current limits is selected with the combination of
the ISLEW resistor voltage (GND or VREF) and TRIPSEL = GND/VREF/3.3V/5V.
26
30
TRIPSEL
V5FILT
I
I
5-V power input for control circuitry. Has internal 3-Ω resistor to V5IN. Bypass to GND with a ceramic
capacitor of 0.1 µF or greater.
21
18
14
15
16
32
V5IN
VBST
VID0
VID1
VID2
VREF
I
I
5-V driver power input. Bypass to PGND with a ceramic capacitor of 2.2µF or greater.
Top N-channel FET bootstrap voltage inputs.
I
I
VID programming bits (MSB to LSB). 1-V I/O level. 100 ns de-bounce.
I
O
1.7-V, 250-µA voltage reference. Bypass to GND with a 0.22-µF capacitor.
Voltage sense line tied directly to VCORE of P. Tie to VCORE with a 10-Ω resistor to close feedback when µP
is not present.
5
VSNS
—
I
PAD
—
Thermal pad; connect to system GND plane with multiple vias.
FUNCTIONAL BLOCK DIAGRAM
DROOP
32
TONSEL
27
V5FILT
30
TPS51513
Clamp
21 V5IN
18 VBST
17 DRVH
19 LL
VSNS
GSNS
5
4
V
+
D/A
FB
E/A
CLK
CO
+
PWM
On-Time
Generator
+
Smart
Driver
VREF 32
CMP
ILIM
20 DRVL
E
VID0 14
VID1 13
VID2 12
E
P
DAC
DAC
22 PGND
R
O
M
ISLEW 29
VFB
CMP
Analog and
Protection Circuitry
Control Logic and
Status Circuitry
CSP
CSN
2
3
+
I AMP
9
1
6
12
7
8
26 28
25 24 23
UDG-09086
Figure 1. TPS51513 Functional Block Diagram
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APPLICATION DIAGRAMS
R1
R2
R3
0
R4
90.9k
R5 R6
R7
0
C4 C3
5. 23k
2.2uF
33pF
0
OpenOpen
C1
C2
R8
R9
0
10uF
10uF
C5
RT1
2.61k
R10
C7
10uF
C9
C8 Open
0.22uF
10k
12.7k
180nF
C10
R11
Q1
4
5
R12 Open
0
3.16k
1 23
L1
TPS51513RHB
0.60uH
C11
C12
R13
24.3k
+
+
Q2
Q3
5
5
R14
0 C13 1uF
330uF
330uF
4
4
R15
C14
Open
D2
12 3
12 3
3.3nF
47.5k
C16
C15
0.1uF
2.2uF
Figure 2. Inductor DCR Current Sense Typical Application Circuit with Droop
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R1
R2
R3
4. 02k
C2
R4
90.9k
R5 R6
R7
0
C11
C12
+
+
C1
Open
C14
C15
33uF
33uF
2.2uF
1000pF
0
Open Open
+
+
R9
0
33uF
33uF
C3
C5
Open
0.22uF
C6
Q3
4
5
R12
Open
0
1 2 3
L1
0. 60uH
TPS51513RHB
C7
C8
R13
22.6k
+
+
Q1
5
R14
0
C9 1uF
330uF
330uF
4
R15
C10
1 2 3
23.7k
3.3nF
C4
0.1uF
C13
2.2uF
Figure 3. Resistor Current Sense Typical Application Without Droop
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DETAILED DESCRIPTION
Application Circuit List of Materials
Recommended parts for key external components for the circuits in Figure 2 and Figure 3 are in Table 2. These
parts have passed applications tests.
Table 2. Key External Component Recommendations
COMPONENT
MANUFACTURER
TI
PART NUMBER
CSD16409Q3
High-side FET(s)
Infineon
TI
BSC080N03MSG
CSD16401Q5
Low-side FET(s)
Inductors
Infineon
Panasonic
Tokin
BSC030N03MSG
ETQP4L series
MPCG1040L series
FDUE10140D series
IHLP5050 series
EEFSX0D331XE
T528Z series
Toko
Vishay
Panasonic
Kemet
Bulk output capacitors
NEC Proadlizer
Panasonic
Murata
PFAF250E127MNS
ECJ2FB0J106K
GRM21BR60J106KE19L
ERJM1WTJ1M0U
ERTJ1VG103JA
NTCG163JF103HT
Ceramic output capacitors
Sense resistor (resistor sensing only)
NTC thermistors
Panasonic
Panasonic
TDK
Functional Overview
The TPS51513 is a DCAP+™ mode adaptive on-time converter. The output voltage is set using a DAC that
outputs a reference in accordance with either the 3-bit VID code defined in Table 3. VID-on-the-fly transitions are
supported with the slew rate controlled by a single resistor on the ISLEW pin. Powerful integrated FET drivers
support output currents in excess of 25 A. The converter automatically runs in discontinuous mode to optimize
light-load efficiency and battery life. The four switching frequency selections (given in Table 3) enable
optimization of the power chain for the cost, size and efficiency requirements of the design.
Table 3. Frequency Selection Table
TONSEL
GND
FREQUENCY (fSEL) (kHz)
250
300
350
500
VREF
3.3 V
5 V
In adaptive on-time converters, the controller changes the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant
on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in
the TPS51513, the cycle begins when the current feedback reaches an error voltage level which is the amplified
difference between the DAC voltage and the feedback voltage.
This approach has two advantages:
1. The amplifier DC gain sets an accurate linear load-line; this is required for CPU core applications.
2. The error voltage input to the PWM comparator is filtered to improve the noise performance.
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PWM Operation
Referring to Figure 1 and Figure 4, in steady state, continuous conduction mode, the converter operates as
follows:
Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCMP) is higher
than the error amplifier output (VDROOP). VCMP falls until it hits VDROOP, which contains a component of the output
ripple voltage. The PWM comparator senses where the two waveforms cross and triggers the on-time generator.
Current
Feedback
V
CMP
V
DROOP
T
ON
T
T – Time
Figure 4. D-CAP+ Mode Basic Waveforms
The current feedback is an amplified and filtered version of the voltage between the CSP and CSN inputs. The
TPS51513 provides fully differential current and voltage feedback to increase the system accuracy and reduce
the dependence of circuit performance on layout.
PWM Frequency and Adaptive On-Time Control
The on-time is determined by Equation 1.
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
VOUT
1
tON
=
´
+ 30ns
V
fSEL
IN
(1)
where
•
fSEL is the frequency selected by the connection of the TONSEL pin, given in Table 3
The on-time pulse is sent to the top FET; the inductor current and the current feedback rises to its maximum
value. Each ON pulse is latched to prevent double pulsing.
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Droop or No-Droop Compensation
The TPS51513 can be designed to either provide a linear load line (also known as droop) or operate with a flat
load-line (no-droop). This is achieved by the component topology at the DROOP pin.
Droop is obtained by putting a resistor from DROOP to VREF (RDROOP) to limit the gain of the error amplifier. The
equation for droop is shown in Equation 2.
RCS ´ ACSINT ´IOUT
VDROOP
=
RDROOP ´ GM droop
(
)
(2)
where
•
•
•
•
RCS is the effective current sense resistance, whether a sense resistor or inductor DCR is used
ACSINT is the gain of the current sense amplifier
IOUT is the output current,
GMDROOP is the GM of the droop amplifier.
The load-line is defined by the change in output voltage vs. the change in current.
V
DROOP
R
= -
L-L
I
OUT
(3)
The TPS51513 also has the ability to provide an output without a load line. In this case, referring to Figure 2, R2
is left open, and R1 and C2 are populated to break the DC path between DROOP and REF and providing very
high DC loop gain. Means to select R1 and C2 are given in the Design Procedure section.
Overshoot Reduction (OSR™) Feature
The problem of overshoot in low duty-cycle synchronous buck converters is well known, and results from the
output inductor having a small voltage (VCORE) with which to respond to a transient load release.
In Figure 5, with ideal components and the common values of 12-V input and 1-V output, the inductor voltage
(VL) with the upper FET on is 11 V (12V – 1V). With the lower FET on, the inductor voltage is only 1 V.
12 V
Q1 on
Q1
Q2
+
–
11V
–
+
1 V
L
1 V
C
Q2 on
UDG-09079
Figure 5. Representative Schematic of a Synchronous Converter
V
DI
Dt
L
=
L
Because
, the converter can respond much more quickly to a load step than it can to a load release.
The idea of OSR is to turn off the lower FET during a transient load release to force the inductor current through
the body diode of the lower FET, thus increasing the voltage across the inductor to VCORE + VDIODE. This
discharges the inductor more quickly and reduces the peak voltage of the transient overshoot. As a result, less
output capacitance is required to achieve a given output tolerance specification.
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Figure 6 shows the converter operation during transient release. The energy in the inductor is transferred to the
capacitance on the VCORE node above and the output voltage (channel 4) overshoots the desired level (lower
cursor). In this case, the magnitude of the overshoot is 34 mV. Note that the DRVL waveform (channel 2) is high
during the overshoot.
The performance of the same circuit, but with OSR enabled is shown in Figure 7. In this case, the low-side FET
is shut off when overshoot is detected and the energy in the inductor is partially dissipated by the body diodes.
The overshoot is reduced to 18 mV. Also note that the DRVL signal is OFF only long enough to reduce the
overshoot.
Figure 6. Circuit Performance Without Overshoot
Reduction
Figure 7. Transient Release Performance is Greatly
Improved by the OSR Circuit
Implementation
OSR is implemented using a comparator between the DROOP and CMP nodes in Figure 1. To implement OSR,
simply terminate the OSRSEL pin to the desired voltage to set the threshold voltage for the comparator. The
settings are:
1. GND = minimum trigger voltage (Maximum overshoot reduction)
2. VREF = medium trigger voltage
3. +3.3V = maximum trigger voltage (Minimum overshoot reduction)
4. 5V = OSR off
Use the highest setting that provides the desired level of overshoot reduction to eliminate the possibility of false
OSR operation.
Light Load Power Saving Features
The TPS51513 has several power saving features to provide excellent efficiency over a very large load range.
The TPS51513 has an automatic pulse skipping skip mode. Regardless of the state of the logic inputs, the
converter senses negative inductor current flow and prevents it by shutting off DRVL. This saves power by
eliminating re-circulating current. Also, when the bottom FET shuts off, the converter enters discontinuous mode,
and the switching frequency decreases, thus reducing switching losses as well.
The SLP signal is used to enter a sleep (SLP) mode. The SLP pin determines the method of entering sleep
mode. If SLP is HI, the converter is allowed to run in skip mode. In this mode, for loads with low leakage current,
the output voltage slew rate is determined by the output capacitance and the leakage current. If SLP is LO, the
device enters PWM mode, and the voltage is actively pulled down by the rate set by RSLEW. The equations are
given below. Because changing VCORE quickly results in large currents charging/discharging the output
capacitors, and this can cause audible noise in inductors and ceramic capacitors, entering a sleep mode with
SLP=HI is recommended.
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FET Drivers
The TPS51513 incorporates strong, high-performance gate drives with adaptive cross-conduction protection. The
driver uses the state of the DRVL, DRVH, and LL pins to ensure that the top or bottom FET is off before turning
the other on. Fast logic and high-drive currents quickly charge and discharge FET gates to minimize dead-time to
increase efficiency. The top gate driver also includes an internal P-N junction boost diode, decreasing the size
and cost of the external circuitry. For maximum efficiency, this diode can be bypassed externally by connecting a
Schottky diode from V5IN (anode) to VBST (cathode).
Voltage Slewing
The TPS51513 changes the voltage of the internal DAC in a controlled manner to perform SLP entry, SLP exit,
and VID change functions. The slew rate is independent of switching frequency or load. It is set by a resistor
from the ISLEW pin to either GND or VREF (RSLEW). RSLEW sets one rate for SLP exit and VID changes (SR in
the equation below; SR is in units of mV/µs.) A proportional rate is used for soft-start and soft-stop functions. The
ISLEW pin is held at VSLEWREF, which is 1.25 V, nominal.
K
´ V
SLEW
SLEW
R
=
SLEW
SR
(4)
In Equation 4), KSLEW = 1.25x109. VSLEW is equal to VSLEWREF (1.25V) when RSLEW is tied to GND. To access
the upper range of OCL limit values, connect RSLEW to VREF. In this case, VSLEW is 0.45V (VREF – VSLEWREF
and RSLEW must be changed accordingly.
)
The soft-start and soft-stop slew rates are 1/8 of SR. On start-up, the TPS51513 VCORE output ramps to the level
defined by the VID code (VVID). Because of this, the VID code needs to be valid and stable at the time EN is
raised. The calculation for soft-start and soft-stop time is shown in Equation 5.
VVID ´ 8
tSS
=
SR
(5)
After approximately 50µs, PG is set LO. Once PG transitions LO, the VID code can change at any time.
Soft Stop Control with Low Impedance Output Termination
The voltage slewing capability is also used to slowly slew the voltage down for a soft-stop without undershoot.
The soft-stop rate equals the soft-start rate. As long as V5IN is available and EN toggles low, the TPS51513
slews from the current VID to approximately 0.3 V. At this point, the DRVL signal is held LO and an internal
transistor of approximately 1-kΩ is connected from VSNS to GND turns on to keep VCORE from rising up as a
result of stray leakage currents.
Protection Features
The TPS51513 has a full suite of features to protect the converter power chain as well as the system electronics.
Input Undervoltage Protection (UVLO):
The TPS51513 continuously monitors the voltage on the V5FILT pin to be sure the value is high enough to bias
the device properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts
with approximately 4.4 V and has a nominal 200 mV of hysteresis. This function is not latched. Removing and
restoring the 5-V power supply to the device can be used to reset it. Be sure the voltage at the device discharges
below 1.6 V before rising again to reset the device.. The power input (VBAT) does not have a UVLO function, so
the circuit operates with power inputs down to approximately 2 × VCORE
.
Power Good Signals
The TPS51513 has two open-drain power good pins. PGOOD and PG have the following nominal thresholds:
•
•
High: VDAC +200mV (also acts as a proportional OVP signal)
Low : VDAC –300mV
The differences are:
•
PG transitions active shortly after VCORE reaches VDAC on power-up; PGOOD has a 6ms nominal delay after
PG.
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•
PG is negative active; PGOOD is positive active.
Both signals go inactive as soon as the EN pin is pulled low or an undervoltage condition on V5IN is detected.
Both signals are masked during DAC transitions to prevent false triggering during voltage slewing.
Output Overvoltage Protection (OVP):
An OVP condition is detected when VCORE reaches the high PG threshold. When this threshold is reached, the
converter sets PGOOD and PG signals inactive, performs the soft-stop sequence, and latches OFF. The
converter remains in this state until the device is reset by cycling either V5IN or EN.
However, because of the dynamic nature of actively power managed systems, the +200 mV OVP threshold is
blanked during voltage transitions. In order to protect the processor 100% of the time, there is a second OVP
level fixed at 1.55-V nominal which is always active. When a fixed OVP condition is detected, PGOOD and PG
are set inactive and DRVL is driven HI. The converter remains in this state until either V5IN or EN are cycled.
Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described below. If VCORE drops
below the low PGOOD threshold for 80µs, then the converter enters soft-stop mode and latches OFF at the
completion of soft stop.
Current Protection
Two types of current protection are provided in the TPS51513:
•
•
Overcurrent Protection (OCP)
Negative OCP
Overcurrent Protection
The TPS51513 uses a “valley” current limiting circuit. As a result, the OCP set point is the OCP DC limit minus
half of the ripple current. Current limiting occurs on a pulse-by-pulse basis. If the sensed current value is above
the OCP setting, the converter holds off the next ON pulse until the current ramp drops below the OCP limit.
Eight OCP settings are provided in two ranges. The ranges are selected by the termination of the RSLEW resistor
as in Figure 8.
The OCP range is selected by the connection of the RSLEW resistor. Connect RSLEW to VREF to select the high
OCP range as shown in Figure 8. Connect RSLEW to GND to select the low OCP range as shown in Figure 9
29 ISLEW
29 ISLEW
R
SLEW2
R
SLEW2
OPEN
R
1
GND
1
GND
SLEW1
OPEN
R
SLEW1
32 VREF
32 VREF
UDG-09080a
UDG-09080b
Figure 8. Connection to Select High Range Overcurrent
Protection
Figure 9. Connection to Select Low Range Overcurrent
Protection
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The OCP values refer to the voltage between the current sense inputs. Refer to the parameter table to choose
the appropriate TRIPSEL value. The value of RSLEW changes depending on the termination. See the Voltage
Slewing section for details.
In OCP, the voltage droops until the UVP limit is reached. After the UPC limit is reached (approximately 80 µs
later) the converter sets PGOOD and PG signals inactive, performs the soft-stop sequence, and then latches
OFF. The converter remains in this state until the device is reset.
Negative Overcurrent Protection
The negative OCP circuit acts when the converter is sinking current. The converter continues to act in a “valley”
mode, so to have a similar negative DC limit, the absolute value of the negative OCP set point is typically 50%
higher than the positive one.
Thermal Shutdown
The TPS51513 has an internal temperature sensor. When the temperature reaches a nominal 160°C, the device
shuts down until the temperature cools approximately 10°C. Then, the converter latches off until either EN or
V5IN is cycled.
Current Monitor
The TPS51513 includes a current monitor function. The current monitor puts out an analog voltage proportional
to the output power on the IMON pin. The equation is shown in Equation 6.
V
= K
´R
´ V
IMON
IMON
IMON CS
(6)
where
•
•
KIMON is given in the parameter table
VCS is the differential voltage at the inputs to the current sense amplifiers
In order to increase the accuracy of the current monitor over temperature the IMON2 pin is provided to match the
temperature coefficients of two critical resistors in the circuit. Connect a resistor from IMON2 to VREF.
After determining the full-scale voltage on the IMON output (VIMON) and selecting RIMON, the value of RIMON2
resistor can be calculated as shown in Equation 7.
8´ V ´ A
´R
IMON
CS
CSINT
IMON
R
=
IMON2
V
(7)
where
•
•
ACSINT is the gain of the internal current sense amplifier (given in the parameter table)
8 is the internal current mirror ratio
The IMON output requires a ceramic capacitor ≥3.3 nF connected to GSNS (or GND) for stable operation.
IMON Clamp Function
The IMON function also includes a clamp to prevent overvoltage of the device reading the IMON voltage. The
clamp voltage is set by the voltage applied at the IMONC pin (pin 12). IMONC is intended to be connected to the
same supply voltage as the downstream A/D converter, but other implementations are possible. To meet the
specified tolerances, a minimum headroom voltage for the IMON clamp must be observed. The V5FILT voltage
needs to be higher than the IMONC voltage by a minimum amount specified in the parameter table. Bypass
IMONC with a ceramic capacitor ≥0.1µF connected to GND.
VID Table
The TPS51513 belongs to a family of power management devicess that can be programmed to any eight VID
values. These values are from 0.3 V to 1.5 V in 12.5 mV steps. The specific VID selections for the TPS51513 are
given in Table 4. Other VID selections are possible, and are provided under a different device number. Contact
your TI field support team for details.
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Table 4. VID Selections for the TPS51513
VID
VDAC (V)
1.05
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1.00
0.95
0.90
0.85
0.80
0.75
0.70
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APPLICATION INFORMATION
Design Procedure
The TPS51513 has a simple design procedure for a high-performance controller.
Initial Parameters:
Step One: Determine the load requirements. For the purposes of this exercise, the following requirements are
used:
The processor requirements provide the following key parameters:
1. VMAX = 1.050 V
2. RL-L = –3 mΩ
3. IMAX = 22 A; IOCP_MIN = 25 A
4. IDYN-MAX = 10 A
5. Sleep slew rate = 5 mV/µs (minimum)
Step Two: Determine system parameters. The input voltage range and operating frequency are of primary
interest. For example:
1. VIN-MAX = 15 V
2. VIN-MIN = 8 V
3. f = 300 kHz
For an operating frequency of 350 kHz, tie TONSEL to 3.3 V.
Step Three: Determine current sensing method. The TPS51513 supports both resistor sensing and inductor
DCR sensing. Inductor DCR sensing is chosen.
For resistor sensing, substitute the resistor value (1 mΩ recommended for a approximately 25-A application) for
RCS in the subsequent equations and skip Step Five.
Step Four: Determine inductor value and choose inductor. Smaller values of inductor have better transient
performance but higher ripple and lower efficiency. Higher values have the opposite characteristics. It is common
practice to limit the ripple current to 20% to 40% of the maximum current per phase. In this case, we use 20%:
IP-P = 25 A × 0.2 = 5 A
At f = 350 kHz, with 15-V input and 1.05-V output:
I
= 25A ´0.2 = 5A
P-P
where
•
•
V = VIN-MAX – VMAX
dT = VMAX (F × VIN-MAX).
V ´ dT
L =
I
P-P
where
•
L = 0.6 µH
An inductor value of 0.6 µH is chosen. The inductor must not saturate during peak loading conditions. The factor
of 1.2 is to allow for current sensing and current limiting tolerances.
IP-P
æ
ö
ISAT = I
èç INST
+
´1.2´ = 41.5A
÷
2
ø
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The chosen inductor should have the following characteristics:
1. As flat an inductance vs. current curve as possible. Inductor DCR sensing is based on the idea L/DCR is
approximately a constant through the current range of interest.
2. Either high saturation or soft saturation
3. Low DCR for high efficiency, but at least 0.7 mΩ for proper signal levels.
4. DCR tolerance as low as possible for load-line accuracy.
For this application, the Vishay IHLP5050CZ-06 0.6-µH, 1.85-mΩ inductor is chosen.
Step Five: Design the thermal compensation network. In most designs, NTC thermistors are used to
compensate thermal variations in the resistance of the inductor winding. This winding is generally copper, and so
has a resistance coefficient of 3900 PPM/°C. NTC thermistors, on the other hand, have very non-linear
characteristics and need two or three resistors to linearize them over the range of interest. The typical DCR
circuit is shown in Figure 10.
L
R
DCR
I
R
R
R
SEQU
NTC
SERIES
R
PAR
C
SENSE
2
3
CSP
CSN
UDG-09081
Figure 10. Typical DCR Sensing Circuit
In this circuit, good performance is obtained when:
L
= C
´R
EQ
SENSE
R
DCR
(8)
where
•
•
all of the parameters are defined in Figure 10
REQ is the series/parallel combination of the other four discrete resistors
CSENSE should be a capacitor type which is stable overtemperature. Use X7R or better dielectric (C0G preferred).
Because calculating these values by hand is difficult, TI offers a spreadsheet using the Excel Solver function..
Contact your local TI representative to get a copy of the spreadsheet.
In the reference design, the following values are input to the spreadsheet:
•
•
•
•
L
RDCR
Load line
Thermistor R25 and “b” value
The spreadsheet then calculates RSEQU, RSERIES, RPAR, and CSENSE. The RCS_Eff versus temperature curve is
shown in Figure 11.
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EFFECTIVE OUTPUT RESISTANCE
vs
TEMPERATURE
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
R
CS(eff)
R
1.05
1.00
–25
0
25
50
75
100
125
T
– Temperature – °C
J
Figure 11.
In this case, the nearest standard values are:
•
•
•
•
RSEQU = 2.61 kΩ;
RSERIES = 3.16 kΩ;
RPAR = 12.7 kΩ
CSENSE =180 nF
Note the effective divider ratio for the inductor DCR. The effective current sense resistance (RCS_Eff) is:
RP _N
RCS(eff) = RDCR
´
RSEQU + RP _N
RP_N is the series/parallel combination of RNTC, RSERIES and RPAR
.
R
´ R
+ R
+ R
(
)
PAR
NTC
SERIES
R
=
P _N
R
+ R
PAR
NTC
SERIES
RCS_Eff is 1.31mΩ. Choose the value of TRIPSEL so the minimum TRIPSEL voltage is just above the voltage
across the current sense pins at the valley point of the current waveform. Maximize the value of RCS_Eff for
improved circuit performance.
æ
ö
÷
ø
I
æ
ç
è
ö
÷
ø
RIPPLE
V
³ R
´ I
-
ç
è
MAX
TRIPSEL min
(
CS eff
)
( )
2
In this case, the TRIPSEL minimum value needs to be greater than 29.8 mV; the next highest value in the
parameter table is 31.4 mV. This value corresponds to connecting TRIPSEL to VREF and RSLEW to VREF.
Step Six: Determine the output capacitor configuration. In general, for a system with a load-line, the ESR of the
output capacitors should be equal to or less than the load-line value. The magnitude and slew rate of the
dynamic load also drives the capacitor choice, as does the inductor selection. For highly dynamic systems, a
successful design has a combination of bulk and ceramic capacitance totaling approximately 1000µF.
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Step Seven: Set the load line. The load line is set by the droop resistor knowing RL-L and RCS_Eff
´ A
.
R
CS(eff)
CS
L-L
R
=
DROOP
G ´R
M
(9)
RDROOP = 5.23 kΩ.
Step Eight: Select the DROOP capacitor.
The DROOP capacitor is used to provide high-frequency filtering of the voltage loop. Use values under 100 pF. A
higher value provides less jitter for steady-state operation, but slows down the transient response.
Step Nine: Calculate RSLEW. RSLEW sets both slew rates:
1. Sleep exit slew rate.
2. Soft-start and soft-stop exit rate is 1/8 of the sleep exit rate
Set the sleep rate to 6 mV/µs to allow 20% for tolerances. From Equation 3):
K
´ V
SLEW
SLEW
R
=
SLEW
SR
(10)
In this case, RSLEW is terminated to GND. KSLEW = 1.25x109 and VSLEW = 0.45 V. For a slew rate (SR) of 6 mV/µs
nominal, 5 mV/µS minimum, RSLEW = 90.9 kΩ.
Step Ten: Calculate IMON resistors.
From Equation 6,
V
IMON
RIMON
=
KIMON ´ VCS
(11)
(12)
And,
VCS = RCS eff ´IMAX
( )
where
•
•
VCS = 29.8 mV
KIMON = 2µA/mV
The IMONC pin is connected to 3.3 V; to allow for tolerances, a full scale value of 3.1 V (VIMON) is desired. Then,
RIMON = 47.5 kΩ.
In order to increase the accuracy of the current monitor overtemperature the IMON2 pin is provided to match the
temperature coefficients of two critical resistors in the circuit. Connect a resistor from IMON2 to VREF.
After determining the full-scale voltage on the IMON output (VIMON) and selecting RIMON, the value of RIMON2
resistor is from Equation 7:
8´ V ´ A
´R
IMON
CS
CSINT
IMON
R
=
IMON2
V
(13)
where
•
•
ACSINT = 6
RIMON2 = 24.3kΩ
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Step Eleven: Select decoupling and peripheral components.
For TPS51513 peripheral capacitors please use the following minimum values of ceramic capacitance. X5R or
better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always OK.
•
•
•
•
•
V5IN decoupling ≥ 2.2µF, ≥ 10V
V5FILT decoupling ≥ 1µF, ≥ 10V
VREF decoupling 0.22 µF to 1µF, ≥ 4V
Bootstrap capacitors ≥ 0.22µF, ≥ 10V
Bootstrap diode (optional) 30V Schottky diode, BAT-54 or better
For power chain and other component selection, see Table 2.
Control Loop Design
The TPS51513 control architecture (current-mode, constant on-time) has been analyzed by the Center for Power
Electronics Systems (CPES) at Virginia Polytechnic and State University. The following equations are from their
presentation: Equivalent Circuit Representation of Current-Mode Control from November 21, 2008.
One of the benefits of this technology is the lack of the sample and hold effect that limits the bandwidth of fixed
frequency current mode controllers and causes sub-harmonic oscillations.
The loop gain is the gain of the DROOP amplifier multiplied by the control-to-output gain:
Control-to-Output
The control-to-output gain is given by the expression:
vO
vC
w´RESR ´ COUT + 1
1
= KC
´
´
2
2
æ
ö
÷
÷
ø
æ
ö
÷
÷
ø
æ
ö
æ
ç
è
ö
÷
ø
w
w
w
+ 1
1+
+ ç
ç
ç
è
ç
ç
÷
÷
ç
wa
Q ´ w
(
)
w1
1
1
è
ø
è
(14)
where
æ
ö
÷
ø
R
L
ç
R
i
è
K
=
C
æ
ç
ç
è
ö
÷
÷
ø
t
´R
(
)
ON
L
1+
2´L
(
)
S
(15)
(16)
P
w =
1
t
ON
V
OUT
t
=
ON
V
´ f
IN
S
(17)
æ
ç
è
ö
t
´R
ON
L
1+
÷
ø
2´L
S
w =
a
æ
ç
è
ö
÷
ø
t
´R
ON
ESR
R ´C
1+
L
OUT
2´L
S
(18)
(19)
For this converter,
R1 = RCS eff ´ ACS
( )
The frequency response of the control-to-output gain can be graphed using the following parameters:
•
•
VIN = 12 V
VOUT = 1.05 V
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•
•
•
•
•
IOUT = 5 A
FS = 350 kHz
LS = 0.56 µH
COUT = 660 µF
RESR = 3 mΩ
The theoretical waveform is plotted in Figure 12. For comparison purposes, the measured data is in Figure 13.
Note the excellent correlation between the theoretical and actual data. In both cases, the 0-dB bandwidth is
approximately 25 kHz, and the phase margin is >90 degrees! As a result, creating the desired loop response is a
matter of adding a DC gain component (if a load-line is allowed) or adding an appropriate pole-zero or
pole-zero-pole compensation
30
180
30
180
15
90
15
90
Gain
Gain
0
0
0
0
–15
–30
–90
–15
–30
–90
Phase
Phase
–180
1 M
–180
1 M
100
1 k
f
10 k
100 k
100
1 k
10 k
– Frequency – kHz
SW
100 k
– Frequency – kHz
f
SW
Figure 12. Theoretical Control to Output Transfer
Function
Figure 13. Measured Control to Output Transfer Function
Limit the overall open-loop bandwidth below 1/2 of fS to avoid violating the Nyquist Criterion. Also, for the best
performance of the modulator, the characteristic of the compensation should be resistive at the switching
frequency. With this in mind, a zero frequency in the range of 10% to 20% of fS is recommended.
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Because the droop amplifier is a trans-conductance amplifier, for a series RC-CC, the pole is at 0 Hz, mid-band
gain is gM × RC, and the zero frequency is RC × CC. For RC = 4.02 kΩ and CC = 1000 pF, the mid-band gain is
2.01 and the zero frequency is approximately 40 kHz. The droop amplifier gain is graphed in Figure 14 and the
overall loop gain in Figure 15.
60
40
20
0
180
90
60
30
0
180
Gain
Gain
90
90
4A
8A
4A
16 A
16 A
8A
16 A
0
0
Phase
16 A
Phase
8A
–90
–90
4A
4A
8A
1 k
–20
–180
1 M
–30
–180
1 M
100
1 k
10 k
100 k
100
10 k
100 k
f
– Frequency – kHz
f
SW
– Frequency – kHz
SW
Figure 14. Droop Amplifier Gain for Zero Load-line
Compensation
Figure 15. Overall Loop Gain with Zero Load-line
Compensation Shown for 4A, 8A, and 16A Load Current
In this design, the bandwidth is 80 kHz and the phase margin is >90 degrees. The gain margin is low, however,
this analysis omits the affect of ceramic capacitance on the output. Ceramic capacitors reduce the loop gain at
high frequencies. Contact your TI representative to obtain a copy of the Mathcad® spreadsheet used to generate
the above curves.
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.070
1.065
1.060
1.055
1.050
1.045
1.040
1.035
1.030
0.715
V
= 1.05 V
V
= 0.7 V
OUT
Low Power Mode
OUT
High Power Mode
0.710
0.705
V
= 20 V
IN
V
= 8 V
IN
V
= 8 V
IN
0.700
V
= 12 V
IN
0.695
0.690
V
= 12 V
IN
V
= 20 V
IN
0.685
0
5
10
15
20
25
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
I
– Output Current – A
I
– Output Current – A
OUT
OUT
Figure 16.
Figure 17.
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
89
88
87
86
85
84
83
82
81
80
79
78
90
80
V
= 8 V
V
= 1.05 V
V
= 0.7 V
OUT
IN
OUT
V
= 12 V
IN
70
60
V
= 12 V
IN
50
40
V
= 20 V
IN
V
= 20 V
V
= 8 V
IN
IN
30
20
10
0
0
5
10
15
20
25
0
5
10
15
20
25
I
– Output Current – A
I
– Output Current – A
OUT
OUT
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT VOLTAGE
EFICIENCY
vs
INPUT VOLTAGE
92
90
89
V
= 8 V
IN
V
= 0.95 V
I
= 10 A
OUT
OUT
88
87
88
86
84
82
86
V
= 12 V
IN
85
84
80
78
V
= 20 V
IN
76
83
0
5
10
15
20
25
0
5
10
15
20
25
V
– Output Voltage – V
V
– Input Voltage – V
IN
OUT
Figure 20.
Figure 21.
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
INPUT VOLTAGE
450
400
385
V
= 0.95 V
= 10 A
V
= 1.05 V
OUT
OUT
380
375
I
OUT
350
300
V
= 12 V
IN
370
365
V
= 8 V
IN
250
200
360
355
150
V
= 20 V
IN
350
345
340
100
50
0
2
6
10
14
18
0
5
10
15
20
25
0
4
8
12
16
20
I
– Output Current – A
V
– Input Voltage – V
IN
OUT
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
vs
REFERENCE VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
1.710
1.705
1.700
400
V
= 8 V
V
= 1.05 V
IN
OUT
380
360
V
= 12 V
IN
340
320
V
= 20 V
IN
V
= 12 V
IN
300
280
V
= 8 V
IN
260
240
1.695
1.690
V
= 20 V
IN
0.7 V < V
I
< 1.05 V
OUT
220
= 10 A
OUT
200
0.6
0.7
V
0.8
0.9
1.0
1.1
0
5
10
15
20
25
– Output Voltage – V
I
– Output Current – A
OUT
OUT
Figure 24.
Figure 25.
CURRENT MONITOR VOLTAGE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
vs
OUTPUT CURRENT
3.5
3.0
1.35
V
= 8 V
IN
High Power Mode
1.30
1.25
1.20
V
= 20 V
IN
2.5
2.0
1.15
1.5
1.0
0.5
1.10
1.05
0
1.00
–25
0
25
50
75
100
125
0
5
10
15
20
25
I
– Output Current – A
T
– Junction Temperature – °C
OUT
J
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
ON TIME
vs
JUNCTION TEMPERATURE
DAC OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
230
1.055
1.054
V
V
V
=3.3 V
TONSEL
= 12 V
LL
225
220
= 1 V
1.053
1.052
1.051
1.050
SNS
215
1.049
1.048
210
205
1.047
1.046
1.045
200
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
T
– Junction Temperature – °C
J
T
– Junction Temperature – °C
J
Figure 28.
Figure 29.
REFERENCFE VOLTAGE
vs
JUNCTION TEMPERATURE
1.710
1.705
1.700
1.695
1.690
–25
0
25
50
75
100
125
T
– Junction Temperature – °C
J
Figure 30.
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TYPICAL CHARACTERISTICS
Figure 31. Startup
Figure 32. Soft-Stop
XXX
XXX
XXX
XXX
XXX
XXX
Figure 33. Load Transient Response With Droop
Figure 34. Load Onset With Droop
XXX
XXX
XXX
XXX
XXX
XXX
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TYPICAL CHARACTERISTICS (continued)
Figure 35. Transient Load Release With Droop
Figure 36. Transient Load Response Without Droop
XXX
XXX
XXX
XXX
XXX
XXX
Figure 37. Transient Load Onset With Droop
Figure 38. Transient Load Release Without Droop
XXX
XXX
XXX
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PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51513RHBR
TPS51513RHBT
QFN
QFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51513RHBR
TPS51513RHBT
QFN
QFN
RHB
RHB
32
32
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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