TPS53119 [TI]

具有 Eco-Mode 的 3V 至 26V、20A 同步 D-CAP 降压控制器;


型号：	TPS53119
厂家：	TEXAS INSTRUMENTS
描述：	具有 Eco-Mode 的 3V 至 26V、20A 同步 D-CAP 降压控制器控制器
文件：	总37页 (文件大小：1736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

TPS53119 宽输入电压、Eco-Mode、同步降压控制器

1 特性

2 应用

•

转换输入电压范围：3V 至 26V

•

存储

VDD 输入电压范围：4.5V 至 25V

输出电压范围：0.6V 至 5.5V

服务器

多功能打印机

嵌入式计算

内置 0.6V (±0.8%) 基准电压

内置 LDO 线性稳压器

3 说明

自动跳跃 Eco-Mode，™可实现轻负载效率

D-CAP™模式，提供 100ns 的负载阶跃响应

TPS53119 器件是一款具有自适应导通时间 D-CAP 模

式控制的小型单路降压控制器。此器件适合用于低输出

电压、大电流、PC 系统电源轨以及数字消费类产品中

类似的负载点 (POL) 电源。此器件的小型封装和最小

引脚数量节省了 PCB 上的空间，同时可通过专用 EN

引脚和预设频率选项来简化电源设计。轻载情况下的跳

频模式、强大的栅极驱动器以及低侧 FET R_DS(on)电流

检测功能可在广泛的负载范围内支持低损耗和高效率特

性。转换输入电压（高侧 FET 漏极电压）范围介于

4.5V 和 25V 之间，并且输出电压范围介于 0.6V 和

5.5V 之间。TPS53119 采用 16 引脚 VQFN 封装，其

额定工作温度为 –20°C 至 +85°C。

自适应导通时间控制架构，具有 8 种频率设置可供

选择

•

4700ppm/°C R_DS(on)电流检测

0.7ms、1.4ms、2.8ms 和 5.6ms 可选内部电压伺

服器软启动

•

预充电启动能力

内置输出放电

开漏电源正常状态输出

集成升压开关

内置过压保护/欠压保护/过流保护

热关断（非锁存）

3mm × 3mm 16 引脚 VQFN (RGT) 封装

使用 TPS53119 并借助 WEBENCH^®电源设计器

创建定制设计

器件信息⁽¹⁾

器件型号

TPS53119

封装

VQFN (16)

封装尺寸（标称值）

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

V_OUT

V_IN

VREG

VIN

CSD86350

PGOOD NC VBST DRVH

TRIP

SW 12

DRVL 11

VDRV 10

TPS53119

VFB

TGR

VREG

Pad MODE VDD

GND PGND

PGND

VDD

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSD61

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ................................................ 17

Power Supply Recommendations...................... 23

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

10 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 23

10.2 Layout Example .................................................... 24

11 器件和文档支持 ..................................................... 28

11.1 器件支持................................................................ 28

11.2 接收文档更新通知 ................................................. 28

11.3 社区资源................................................................ 28

11.4 商标....................................................................... 28

11.5 静电放电警告......................................................... 28

11.6 术语表 ................................................................... 28

12 机械、封装和可订购信息....................................... 28

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (December 2017) to Revision A

Page

•

已添加添加了 WEBENCH 链接 ............................................................................................................................................. 1

Added "Repetitive spikes up to 9 V can be tolerated for up to 50 ns." to Note 2 of Absolute Maximum Ratings. ................ 4

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

5 Pin Configuration and Functions

RGT Package

16-Pin VQFN With Exposed Thermal Pad

Top View

TRIP

DVRL

VDRV

VREG

TPS53119

VFB

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is

defined by the voltage across VBST to SW node bootstrap flying capacitor.

DRVH

Synchronous MOSFET driver output. The PGND referenced driver. The gate drive voltage is defined by

VDRV voltage.

DRVL

Enable pin. Place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V.

GND

Ground pin. This is the ground of internal analog circuitry. Connect to GND plane at single point.

Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-

start time is detected and stored into internal register during start-up.

MODE

–

No connection.

PAD

Thermal pad. Use five vias to connect to GND plane.

Open-drain power-good flag. Provides 1-ms start-up delay after the VFB pin voltage falls within specified

limits. When VFB goes out specified limits PGOOD goes low after a 2-µs delay.

PGOOD

PGND

Power ground. Connect to GND plane.

Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using

Table 2. The switching frequency is detected and stored during the start-up.

Output of converted power. Connect this pin to the output inductor.

OCL detection threshold setting pin —10 µA at room temp, 4700 ppm/°C current is sourced and set the

OCL trip voltage as follows: V_OCL= V_TRIP/ 8 ( V_TRIP≤ 3 V, V_OCL≤ 375 mV)

TRIP

Supply input for high-side FET gate driver (boost terminal). Connect a capacitor from this pin to SW

node. Internally connected to VREG through bootstrap MOSFET switch.

VBST

VDD

Controller power supply input. The input range is from 4.5 V to 25 V.

VDRV

VFB

Gate drive supply voltage input. Connect to VREG if using LDO output as gate-drive supply.

Output feedback input. Connect this pin to V_OUTthrough a resistor divider.

6.2-V LDO output. This is the supply of internal analog circuitry and driver circuitry.

VREG

(1) I=Input, O=Output, P=Power, G=Ground

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–2

MAX

UNIT

VBST

VBST⁽²⁾

VDD

–7

Input voltage

Pulse < 20 ns, E = 5 µJ

VDRV, EN, TRIP, VFB, RF, MODE

DRVH

DRVH⁽²⁾

–0.3

–2

–0.3

–0.5

–0.3

Output voltage

DRVL, VREG

PGOOD

Junction temperature, T_J

Storage temperature, T_stg

150

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage values are with respect to the SW terminal. Repetitive spikes up to 9 V can be tolerated for up to 50 ns.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

34.5

UNIT

VBST

–0.1

4.5

VDD

Input voltage

–1

VBST⁽¹⁾

–0.1

–1

6.5

34.5

6.5

EN, TRIP, VFB, RF, VDRV, MODE

DRVH

DRVH⁽¹⁾

DRVL, VREG

PGOOD

–0.1

–0.3

–0.1

–20

Output voltage

Operating free-air temperature, T_A

°C

(1) Voltage values are with respect to the SW terminal.

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

6.4 Thermal Information

TPS53119

THERMAL METRIC⁽¹⁾

RGT (VQFN)

16 PINS

51.3

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

85.4

20.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JB

19.4

R_θJC(bot)

6.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range, VDD = 12 V (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

VDD current, T_A= 25°C, no load, V_EN= 5 V,

V_VFB= 0.630 V

I_VDD

VDD supply current

420

590

µA

I_VDDSDN

VDD shutdown current

VDD current, T_A= 25°C, no load, V_EN= 0 V

INTERNAL REFERENCE VOLTAGE

V_VFB

I_VFB

VFB regulation voltage

VFB input current

VFB voltage, CCM condition⁽¹⁾

T_A= 25°C

600

µA

597

595.2

592

603

604.8

608

0°C ≤ T_A≤ 85°C

600

–20°C ≤ T_A≤ 85°C

V_VFB= 0.63 V, T_A= 25°C

600

0.002

0.2

OUTPUT DRIVERS

Source, I_DRVH= –50 mA

Sink, I_DRVH= 50 mA

Source, I_DRVL= –50 mA

Sink, I_DRVL= 50 mA

1.5

0.7

1.8

2.2

1.2

R_DRVH

R_DRVL

t_DEAD

DRVH resistance

DRVL resistance

Dead time

0.5

DRVH-off to DRVL-on

DRVL-off to DRVH-on

LDO OUTPUT

V_VREG

LDO output voltage

LDO output current⁽¹⁾

LDO dropout voltage

0 mA ≤ I_VREG≤ 50 mA

5.76

6.2

6.67

I_VREG

Maximum current allowed from LDO

V_VDD= 4.5 V, I_VREG= 50 mA

V_DO

364

BOOT STRAP SWITCH

V_FBST

Forward voltage

VBST leakagecurrent

V_VREG-VBST, I_F= 10 mA, T_A= 25°C

V_VBST= 23 V, V_SW= 17 V, T_A= 25°C

0.1

0.2

1.5

I_VBSTLK

0.01

µA

DUTY AND FREQUENCY CONTROL

t_OFF(min)

Minimum off-time

Minimum ON-time

T_A= 25°C

150

260

400

V_IN= 17 V, V_OUT= 0.6 V, R_RF= 0 Ω to VREG,

t_ON(min)

T_A= 25°C⁽¹⁾

SOFT START

0 V ≤ V_OUT≤ 95%, R_MODE= 39 kΩ

0 V ≤ V_OUT≤ 95%, R_MODE= 100kΩ

0 V ≤ V_OUT≤ 95%, R_MODE= 200 kΩ

0 V ≤ V_OUT≤ 95%, R_MODE= 470 kΩ

0.7

1.4

2.8

5.6

t_SS

Internal soft-start time

(1) Ensured by design. Not production tested.

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range, VDD = 12 V (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

POWER GOOD

PG in from lower

PG in from higher

PG hysteresis

92.5%

108%

2.5%

96%

111%

98.5%

114%

7.8%

V_THPG

PG threshold

R_PG

PG transistor on-resistance

PG delay after soft start

t_PG(del)

0.8

1.2

LOGIC THRESHOLD AND SETTING CONDITIONS

–20°C ≤ T_A≤ 85°C

1.8

1.7

EN voltage threshold enable

V_EN

0°C ≤ T_A≤ 85°C

EN voltage threshold disable

EN input current

0.5

I_EN

V_EN= 5 V

µA

R_RF= 0 Ω to GND, T_A= 25°C⁽²⁾

R_RF= 187 kΩ to GND, T_A= 25°C⁽²⁾

R_RF= 619 kΩ to GND, T_A= 25°C⁽²⁾

R_RF= open, T_A= 25°C⁽²⁾

R_RF= 866 kΩ to V_REG, T_A= 25°C⁽²⁾

R_RF= 309 kΩ to V_REG, T_A= 25°C⁽²⁾

R_RF= 124 kΩ to V_REG, T_A= 25°C⁽²⁾

R_RF= 0 Ω to V_REG, T_A= 25°C⁽²⁾

200

250

350

450

580

670

770

880

250

300

400

500

650

750

850

970

300

350

450

550

720

820

930

1070

f_SW

Switching frequency

kHz

VO DISCHARGE

I_Dischg

VO discharge current

V_EN= 0 V, V_SW= 0.5 V

PROTECTION: CURRENT SENSE

I_TRIP

TRIP source current

V_TRIP= 1 V, T_A= 25°C

T_A= 25°C⁽¹⁾

µA

TC_ITRIP

TRIP current temp. coef.

4700

ppm/°C

Current limit threshold setting

range

V_TRIP

V_TRIP-GNDvoltage

0.2

V_TRIP= 3 V

V_TRIP= 1.6 V

V_TRIP= 0.2 V

V_TRIP= 3 V

V_TRIP= 1.6 V

V_TRIP= 0.2 V

Positive

355

185

375

200

395

215

V_OCL

Current limit threshold

–406

–215

–33

–375

–200

–25

–355

–185

–17

Negative current limit

threshold

V_OCLN

Auto zero cross adjustable

range

V_AZC(adj)

Negative

–15

–3

PROTECTION: UVP AND OVP

V_OVP

OVP trip threshold voltage

OVP detect

115%

65%

120%

125%

t_OVP(del)

OVP propagation delay time

VFB delay with 50-mV overdrive

µs

Output UVP trip threshold

voltage

V_UVP

UVP detect

70%

75%

Output UVP propagation

delay time

t_UVP(del)

0.8

1.2

t_UVP(en)

Output UVP enable delay time from EN to UVP workable, R_MODE= 39 kΩ

2.55

UVLO

Wake up

VREG UVLO threshold

Hysteresis

4.18

0.25

4.5

V_UVVREG

THERMAL SHUTDOWN

Shutdown temperature⁽¹⁾

Hysteresis⁽¹⁾

145

T_SDNThermal shutdown threshold

°C

(2) Not production tested. Test conditions are V_IN= 12 V, V_OUT= 1.1 V, I_OUT= 10 A and using the application circuit shown in Figure 18

and Figure 22.

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

6.6 Typical Characteristics

700

600

500

400

300

200

100

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

−50

−25

100

125

150

−50

−25

100

125

150

Temperature (°C)

Figure 1. VDD Supply Current vs Temperature

Figure 2. VDD Shutdown Current vs Temperature

140

120

100

140

120

100

OVP

UVP

OVP

UVP

−50

−25

100

125

150

−25

100

125

150

Temperature (°C)

Figure 3. OVP/UVP Threshold vs Temperature

Figure 4. TRIP Pin Current vs Temperature

1000

100

1000

100

f_SET= 300 kHz

V_IN= 12 V

V_OUT= 1.1 V

f_SET= 500 kHz

V_IN= 12 V

V_OUT= 1.1 V

FCC Mode

Skip Mode

FCC Mode

Skip Mode

0.01

0.1

100

0.1

100

Output Current (A)

Figure 5. Switching Frequency vs Output Current

Figure 6. Switching Frequency vs Output Current

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

Typical Characteristics (continued)

1000

100

f_SET=750 kHz

V_IN= 12 V

V_OUT= 1.1 V

f_SET=1 MHz

V_IN= 12 V

V_OUT= 1.1 V

FCC Mode

Skip Mode

FCC Mode

Skip Mode

0.01

0.1

100

0.1

100

Output Current (A)

Figure 7. Switching Frequency vs Output Current

Figure 8. Switching Frequency vs Output Current

1200

1.120

f_SET= 500 kHz

V_IN= 12 V

V_OUT= 1.1 V

f_SET= 1 MHz

1.115

1.110

1.105

1.100

1.095

1.090

1.085

1.080

1000

800

600

400

200

f_SET= 750 kHz

f_SET= 500 kHz

f_SET= 300 kHz

I_OUT=10 A

V_IN= 12 V

FCC Mode

Skip Mode

Output Voltage (V)

Output Current (A)

Figure 9. Switching Frequency vs Output Voltage

Figure 10. Output Voltage vs Output Current

1.110

100

1.108

1.106

1.104

1.102

1.100

1.098

1.096

1.094

1.092

1.090

V_IN= 12 V

V_OUT= 1.1 V

Skip Mode, f_SW= 500 kHz

FCC Mode, f_SW= 500 kHz

Skip Mode, f_SW= 300 kHz

FCC Mode, f_SW= 300 kHz

FCC Mode, No Load

Skip Mode, No Load

All Modes, I_OUT= 20 A

f_SW= 500 kHz

0.01

0.1

100

Input Voltage (V)

Output Current (A)

Figure 11. Output Voltage vs Input Voltage

Figure 12. Efficiency vs Output Current

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

Typical Characteristics (continued)

Figure 13. Start-Up Waveform

Figure 14. Prebias Start-Up Waveform

Figure 15. Turnoff Waveform

Figure 16. Load Transient Response

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS53119 is a high-efficiency, single-channel, synchronous buck regulator controller suitable for low output

voltage point-of-load applications in computing and similar digital consumer applications. The device features

proprietary D-CAP mode control combined with an adaptive ON-time architecture. This combination is ideal for

building modern low duty ratio, ultra-fast load step response DC–DC converters. The output voltage ranges from

0.6 V to 5.5 V. The conversion input voltage range is from 3 V up to 26 V. The D-CAP mode uses the ESR of the

output capacitors to sense the device current. One advantage of this control scheme is that it does not require an

external phase compensation network. This allows a simple design with a low external component count. Eight

preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG.

Adaptive ON-time control tracks the preset switching frequency over a wide input and output voltage range while

allowing the switching frequency to increase at the step-up of the load.

The TPS53119 has a MODE pin to select between auto-skip mode and forced continuous conduction mode

(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to

5.6 ms as shown in Table 1. The strong gate drivers allow low R_DS(on)FETs for high-current applications.

When the device starts (either by EN or VDD UVLO), the TPS53119 sends out a current that detects the

resistance connected to the MODE pin to determine the soft-start time. After that (and before V_OUTstarts to ramp

up) the MODE pin becomes a high-impedance input to determine skip mode or FCCM mode operation. When

the voltage on the MODE pin is higher than 1.3 V, the converter enters into FCCM mode. If the voltage on

MODE pin is less than 1.3 V, then the converter operates in skip mode.

TI recommends connection of the MODE pin to the PGOOD pin if FCCM mode is desired. In this configuration,

the MODE pin is connected to the GND potential through a resistor when the device is detecting the soft-start

time, thus correct soft-start time is used. The device starts up in skip mode and only after the PGOOD pin goes

high does the device enter into FCCM mode. When the PGOOD pin goes high there is a transition between skip

mode and FCCM. A minimum off-time of 60 ns on DRVL is provided to avoid a voltage spike on the DRVL pin

caused by parasitic inductance of the driver loop and gate capacitance of the low-side MOSFET.

For proper operation, the MODE pin must not be connected directly to a voltage source.

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

7.2 Functional Block Diagram

16 PGOOD

0.6 V –30%

0.6 V +10/15%

Delay

0.6 V +20%

0.6 V –5/10%

Control Logic

Enable/SS Control

14 VBST

13 DRVH

PWM

VFB

12 SW

Ramp Comp

XCON

0.6 V

GND

TRIP

10 mA

t_ON

OCP

One-

Shot

x(-1/8)

FCCM

x(1/8)

10 VDRV

11 DRVL

Auto-skip

Auto-skip/FCCM

PGND

Frequency

Setting

Detector

LDO Linear

Regulator

TPS53119

VDD

MODE

VREG

7.3 Feature Description

7.3.1 Enable and Soft-Start

When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-

up sequence. The internal LDO regulator starts immediately and regulates to 6.2 V at the VREG pin. The

controller then uses the first 250 µs to calibrate the switching frequency setting resistance attached to the RF pin

and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In

the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the

MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the

output voltage is maintained during start-up regardless of load current.

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

Table 1. Soft-Start and MODE

MODE

SELECTION

SOFT-START

TIME (ms)

ACTION

R_MODE(kΩ)

0.7

1.4

100

200

475

Auto skip

Pulldown to GND

2.8

5.6

0.7

1.4

100

200

475

Forced CCM⁽¹⁾

Connect to PGOOD

2.8

5.6

(1) Device goes into forced CCM after PGOOD becomes high.

When the EN voltage is higher than 5.5 V, a 1-kΩ series resistor is needed for the EN pin.

7.3.2 Adaptive ON-Time D-CAP Control and Frequency Selection

The TPS53119 does not have a dedicated oscillator that determines switching frequency. However, the device

operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the ON-time one-

shot timer. The adaptive ON-time control adjusts the ON-time to be inversely proportional to the input voltage

and proportional to the output voltage (t_ON∝ V_OUT/V_IN).

This makes the switching frequency fairly constant in steady-state conditions over a wide input voltage range.

The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and

GND or between the RF pin and the VREG pin as shown in Table 2. Leaving the resistance open sets the

switching frequency to 500 kHz.

Table 2. Resistor and Switching Frequency

SWITCHING

RESISTOR (R_RF) CONNECTIONS

FREQUENCY (kHz)

0 Ω to GND

187 kΩ to GND

619 kΩ to GND

Open

250

300

400

500

650

750

850

970

866 kΩ to VREG

309 kΩ to VREG

124 kΩ to VREG

0 Ω to VREG

The OFF-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is

compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM

comparator asserts a set signal to terminate the OFF-time (turn off the low-side MOSFET and turn on high-side

MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time

is extended until the current level falls below the threshold.

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7.3.3 Small Signal Model

From small-signal loop analysis, a buck converter using D-CAP mode can be simplified as shown in Figure 17.

V_IN

TPS53119

Switching Modulator

DRVH

VFB

V_OUT

PWM

Control

Logic

and

DRVL

I_OUT

I_IND

Driver

I_C

0.6 V

ESR

R_LOAD

Voltage Divider

V_C

C_OUT

Output

Capacitor

Figure 17. Simplified Modulator Model

The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).

The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the

comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially

constant.

H s =

( )

s´ESR ´C

OUT

(1)

For the loop stability, the 0-dB frequency, f₀, defined below must be lower than ¼ of the switching frequency.

f =

2p´ESR ´C

OUT

(2)

According to Equation 2, the loop stability of D-CAP mode modulator is mainly determined by the capacitor

chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance on the order of

several 100 µF and ESR in range of 10 mΩ. These yields an f₀on the order of 100 kHz or less and a more stable

loop. However, ceramic capacitors have an f₀at more than 700 kHz, and require special care when used with

this modulator. An application circuit for ceramic capacitor is described in External Parts Selection With All

Ceramic Output Capacitors.

7.3.4 Ramp Signal

The TPS53119 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in

Small Signal Model, the feedback voltage is compared with the reference information to keep the output voltage

in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle

is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start

with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady-state.

During skip mode operation, when the switching frequency is lower than 70% of the nominal frequency (because

of longer OFF-time), the ramp signal exceeds 0 mV at the end of the OFF-time but is clamped at 3 mV to

minimize DC offset.

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7.3.5 Adaptive Zero Crossing

The TPS53119 has an adaptive zero crossing circuit which performs optimization of the zero inductor current

detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and

compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It

prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too

early detection. As a result, better light load efficiency is delivered.

7.3.6 Output Discharge Control

When EN becomes low, the TPS53119 discharges output capacitor using internal MOSFET connected between

the SW pin and the PGND pin while the high-side and low-side MOSFETs are maintained in the OFF state. The

typical discharge resistance is 40 Ω. The soft discharge occurs only as EN becomes low. After VREG becomes

low, the internal MOSFET turns off, and the discharge function becomes inactive.

7.3.7 Low-Side Driver

The low-side driver is designed to drive high-current low-R_DS(on)N-channel MOSFETs. The drive capability is

represented by its internal resistance, which is 1 Ω for VDRV to DRVL and 0.5 Ω for DRVL to GND. A dead time

to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and

low-side MOSFET off to high-side MOSFET on. The bias voltage VDRV can be delivered from 6.2-V VREG

supply or from external power source from 4.5 V to 6.5 V. The instantaneous drive current is supplied by an input

capacitor connected between the VDRV and PGND pins.

The average low-side gate drive current is calculated in Equation 3.

= C ´ V

´ f

VDRV SW

(3)

When VDRV is supplied by external voltage source, the device continues to be supplied by the VREG pin. There

is no internal connection from VDRV to VREG.

7.3.8 High-Side Driver

The high-side driver is designed to drive high current, low R_DS(on)N-channel MOSFETs. When configured as a

floating driver, the bias voltage is delivered from the VDRV pin supply. The average drive current is calculated

using Equation 4.

= C ´ V

´ f

VDRV SW

(4)

The instantaneous drive current is supplied by the flying capacitor between VBST and SW pins. The drive

capability is represented by internal resistance, which is 1.5 Ω for VBST to DRVH and 0.7 Ω for DRVH to SW.

The driving power which needs to be dissipated from TPS53119 package.

P_DRV= I + I_GH´ V

)

(

VDRV

(5)

7.3.9 Power Good

The TPS53119 has a power-good output that indicates high when switcher output is within the target. The power-

good function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of the

target value, internal comparators detect power-good state and the power-good signal becomes high after a 1-

ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good signal

becomes low after two microsecond (2-µs) internal delay. The power-good output is an open-drain output and

must be pulled up externally.

In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic

before the TPS53119 is powered up, TI recommends that the PGOOD pin be pulled up to VREG (either directly

or through a resistor divider if a different pullup voltage is desired) because VREG remains low when the device

is powered off. The pullup resistance can be chosen from a standard resistor value between 1 kΩ and 100 kΩ.

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7.3.10 Current Sense and Overcurrent Protection

TPS53119 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state

and the controller maintains the OFF state during the period in that the inductor current is larger than the

overcurrent trip level. In order to provide both good accuracy and cost-effective solution, TPS53119 supports

temperature compensated MOSFET R_DS(on)sensing. The TRIP pin should be connected to GND through the trip

voltage setting resistor, R_TRIP. The TRIP terminal sources I_TRIPcurrent, which is 10 µA typically at room

temperature, and the trip level is set to the OCL trip voltage V_TRIPas shown in Equation 6.

NOTE

The V_TRIPis limited up to approximately 3 V internally.

mV = R

kW ´I

_TRIP( ) _TRIP( ) _TRIP( )

(6)

The inductor current is monitored by the voltage between GND pin and SW pin so that SW pin should be

connected to the drain terminal of the low-side MOSFET properly. I_TRIPhas 4700-ppm/°C temperature slope to

compensate the temperature dependency of the R_DS(on). The GND pin is used as the positive current-sensing

node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal

of the low-side MOSFET.)

As the comparison is done during the OFF state, V_TRIPsets the valley level of the inductor current. Thus, the load

current at the overcurrent threshold, I_OCP, can be calculated as shown in Equation 7.

- V

´ V

IND ripple

(

)

OUT OUT

TRIP

)

TRIP

OCP

2´L ´ f

8´R

DS on

)

(

DS on

( )

(7)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output

voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down. After a

hiccup delay (16 ms with 0.7-ms sort start), the controller restarts. If the overcurrent condition remains, the

procedure is repeated and the device enters hiccup mode.

During the CCM, the negative current limit (NCL) protects the external FET from carrying too much current. The

NCL detect threshold is set as the same absolute value as positive OCL but negative polarity.

NOTE

The threshold still represents the valley value of the inductor current.

7.3.11 Overvoltage and Undervoltage Protection

TPS53119 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. When the

feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an

internal UVP delay counter begins counting. After 1 ms, TPS53119 latches OFF both high-side and low-side

MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7-ms soft-start). This function is

enabled 1.5-ms after the soft-start is completed.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes

high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The

output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and low-side

MOSFET driver will be OFF and the device restarts after an hiccup delay. If the OV condition remains, both high-

side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.

7.3.12 UVLO Protection

The TPS53119 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95

V, the device shuts off. When the VREG voltage is higher than 4.2 V, the device restarts. This is non-latch

protection.

7.3.13 Thermal Shutdown

The TPS53119 uses temperature monitoring. If the temperature exceeds the threshold value (typically 145°C),

the device is shut off. This is non-latch protection.

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7.4 Device Functional Modes

7.4.1 Light Load Condition in Auto-Skip Operation

While the MODE pin is pulled low through R_MODE, TPS53119 automatically reduces the switching frequency at

light load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current

decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that

its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the

load current further decreases, the converter runs into discontinuous conduction mode (DCM). The ON-time is

kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the

output capacitor with smaller load current to the level of the reference voltage. The transition point to the light

load operation I_O(LL)(that is, the threshold between continuous and discontinuous conduction mode) can be

calculated as shown in Equation 8.

- V

´ V

(

)

OUT OUT

OUT LL

( )

2´L ´ f

where

•

f_SWis the PWM switching frequency

(8)

Switching frequency versus output current in the light load condition is a function of L, V_INand V_OUT, but it

decreases almost proportionally to the output current from the IO_(LL)given in Equation 8. For example, it is 60

kHz at IO_(LL)/ 5 if the frequency setting is 300 kHz.

7.4.2 Forced Continuous Conduction Mode

When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode

(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load

range, which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53119 device is a small-sized, single-buck controller with adaptive ON-time DCAP mode control.

8.2 Typical Applications

8.2.1 Typical Application With Power Block

R10

100 kW

0 W

VREG

V_IN

PGOOD

10 kW

C_IN

VIN

0.1 mF

CSD86350

22 mF x 4

DRVH

86.6 kW

PGOOD NC

VBST

0.44 mH

PA0513.441

TRIP

SW 12

R11

1 kW

DRVL 11

VDRV 10

V_OUT

C_OUT

TPS53119

TGR

VFB

POSCAP

330 mF x 2

PGND

VREG

GND PGND Pad

MODE

VDD

10 kW

187 kW

4.7 mF

1 mF

100 kW

PGOOD

VDD

Figure 18. Typical Application Circuit Diagram With Power Block

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Typical Applications (continued)

8.2.1.1 Design Requirements

This design uses the parameters listed in Table 3.

Table 3. Design Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Voltage range

Maximum input current

V_IN= 5 V, I_OUT= 25 A

I_MAX

V_IN= 12 V, I_OUT= 0 A with auto-skip

mode

No load input current

OUTPUT CHARACTERISTICS

Output voltage

1.2

Line regulation, 5 V ≤ V_IN≤ 14 V with

FCCM

0.2%

V_OUT

Output voltage regulation

Load regulation, V_IN= 12 V, 0 A ≤ I_OUT

≤ 25 A with FCCM

0.5%

V_RIPPLE

I_LOAD

I_OVER

t_SS

Output voltage ripple

V_IN= 12 V, I_OUT= 25 A with FCCM

mV_PP

Output load current

Output overcurrent

Soft-start time

SYSTEMS CHARACTERISTICS

f_SW

Switching frequency

Peak efficiency

500

91%

91.5%

kHz

°C

V_IN= 12 V, V_OUT= 1.2 V, I_OUT= 4 A

V_IN= 12 V, V_OUT= 1.2 V, I_OUT= 8 A

Full load efficiency

Operating temperature

T_A

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS53119 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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8.2.1.2.2 External Components Selection

Selecting external components is a simple process using D-CAP mode.

1. Choose the Inductor

The inductance should be determined to give the ripple current of approximately ¼ to ½ of maximum output

current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps

stable operation.

(

max

(

- V

´ V

)

(

max

(

- V

´ V

OUT OUT

OUT

)

L =

´ f

max

(

OUT

IND ripple

(

max

)

(

)

(

)

(9)

The inductor also requires a low DCR to achieve good efficiency. It also requires enough room above the

peak inductor current before saturation. The peak inductor current can be estimated in Equation 10.

(

max

(

- V

´ V

OUT

)

TRIP

IND peak

(

)

8´R

L ´ f

DS on

max

( )

(

(10)

2. Choose the Output Capacitor

When organic semiconductor capacitors or specialty polymer capacitors are used, for loop stability,

capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 11 is a good starting point

to determine ESR.

_OUT´10mV ´(1-D) 10mV ´L ´ f_SWL ´ f_SW

ESR =

( )

0.6V ´I

0.6V

IND ripple

(

)

where

•

D is the duty factor

the required output ripple slope is approximately 10 mV per t_SW(switching period) in terms of VFB terminal

voltage

(11)

3. Determine the Value of R1 and R2

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 17. R1 is

connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND.

Recommended R2 value is between 10 kΩ and 20 kΩ. Determine R1 using Equation 12.

´ESR

IND ripple

(

)

V_OUT

- 0.6

R1=

´R2

0.6

(12)

TPS53119

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www.ti.com.cn

8.2.1.3 Application Curves

100.00%

90.00%

80.00%

70.00%

60.00%

50.00%

40.00%

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

1.12

1.10

0.01

0.10

1.00

I_OUT(A)

10.00

I_OUT(A)

C009

C008

Figure 20. Efficiency Performance

Figure 19. Load Regulation Performance

700.00

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

600.00

500.00

400.00

300.00

I_OUT(A)

C010

Figure 21. Switching Frequency Performance

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ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

8.2.2 Typical Application With Ceramic Output Capacitors

10 kW

V_IN

R10

100 kW

0 W

C_IN

22 mF x 4

VREG

PGOOD

1 nF

0.1 mF

VIN

0.1 mF

CSD86350

DRVH

20 kW

PGOOD NC

VBST

0.44 mH

PA0513.441

10 kW

TRIP

SW 12

R11

1 kW

DRVL 11

VDRV 10

V_OUT

C_OUT

TPS53119

TGR

VFB

Ceramic

100 mF x 4

PGND

R12

0 W

VREG

GND PGND Pad

10 kW

MODE

VDD

187 kW

4.7 mF

1 mF

100 kW

PGOOD

VDD

Figure 22. Typical Application Circuit Diagram With Ceramic Output Capacitors

8.2.2.1 Design Requirements

This design uses the parameters listed in Table 4.

Table 4. Design Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Voltage range

Maximum input current

V_IN= 5 V, I_OUT= 8 A

2.5

I_MAX

V_IN= 12 V, I_OUT= 0 A with auto-skip

mode

No load input current

OUTPUT CHARACTERISTICS

Output voltage

1.2

Line regulation, 5 V ≤ V_IN≤ 14 V with

FCCM

0.2%

V_OUT

Output voltage regulation

Load regulation, V_IN= 12 V, 0 A ≤ I_OUT

≤ 8 A with FCCM

0.5%

V_RIPPLE

I_LOAD

I_OVER

t_SS

Output voltage ripple

V_IN= 12 V, I_OUT= 8 A with FCCM

mV_PP

Output load current

Output overcurrent

Soft-start time

SYSTEMS CHARACTERISTICS

f_SW

Switching frequency

Peak efficiency

500

91%

91.5%

1000

kHz

°C

V_IN= 12 V, V_OUT= 1.2 V, I_OUT= 4 A

V_IN= 12 V, V_OUT= 1.2 V, I_OUT= 8 A

Full load efficiency

Operating temperature

T_A

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors

When a ceramic output capacitor is used, the stability criteria in Equation 2 cannot be satisfied. The ripple

injection approach as shown in Figure 22 is implemented to increase the ripple on the VFB pin and make the

system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.

The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the

VFB pin has two components, one coupled from SW node and the other coupled from V_OUTand they can be

calculated using Equation 13 and Equation 14.

- V

OUT

(

)

INJ SW

(

)

R7´ C1

(13)

(14)

IND ripple

(

)

= ESR´I

)

INJ OUT

(

IND ripple

(

)

8´ C_OUT´ f_SW

The DC value of VFB can be calculated by Equation 15.

+ V

)

(

= 0.6 +

INJ SW

(

INJ OUT

(

)

(15)

(16)

And the resistor divider value can be determined by Equation 16.

- V

(

)

OUT

R1=

´R2

8.2.2.3 Application Curves

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

100.00%

90.00%

80.00%

70.00%

60.00%

50.00%

40.00%

30.00%

20.00%

10.00%

0.00%

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

0.01

0.10

1.00

10.00

I_OUT(A)

C004

C005

Figure 23. Load Regulation Performance

Figure 24. Efficiency Performance

800.00

700.00

600.00

500.00

400.00

300.00

200.00

5.0Vin_1.2Vout_500kHz_25C

12.0Vin_1.2Vout_500kHz_25C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

I_OUT(A)

C006

Figure 25. Switching Frequency Performance

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ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

9 Power Supply Recommendations

The TPS53119 is a small-sized single-buck controller with adaptive ON-time D-CAP mode control. The device is

suitable for low output voltage, high current, PC system power rail and similar point-of-load (POL) power supplies

in digital consumer products.

10 Layout

10.1 Layout Guidelines

Certain points must be considered before starting a layout work using the TPS53119.

•

Inductors, V_INcapacitors, V_OUTcapacitors and MOSFETs are the power components and must be placed on

one side of the PCB (solder side). Place other small signal components on another side (component side).

Insert at least one inner plane, connected to power ground, in order to shield and isolate the small signal

traces from noisy power lines.

•

Place all sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF away from

high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as

ground planes and shield feedback trace from power traces and components.

The DC–DC converter has several high-current loops. The area of these loops must be minimized in order to

suppress generating switching noise.

–

The most important loop to minimize the area of is the path from the V_INcapacitors through the high and

low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the V_IN

capacitors and the source of the low-side MOSFET at ground as close as possible.

The second important loop is the path from the low-side MOSFET through inductor and V_OUTcapacitors,

and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET

and negative node of VOUT capacitors at ground as close as possible.

The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side

MOSFET, high current flows from VDRV capacitor through gate driver and the low-side MOSFET, and

back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current

flows from gate of the low-side MOSFET through the gate driver and PGND of the device, and back to

source of the low-side MOSFET through ground. Connect negative node of VDRV capacitor, source of the

low-side MOSFET and PGND of the device at ground as close as possible.

•

Because the TPS53119 controls output voltage referring to voltage across V_OUTcapacitor, the high-side

resistor of the voltage divider should be connected to the positive node of V_OUTcapacitor at the regulation

point. Connect the low-side resistor to the GND (analog ground of the device). The trace from these resistors

to the VFB pin must be short and thin. Place on the component side and avoid vias between these resistors

and the device.

•

Connect the overcurrent setting resistors from the TRIP pin to GND and make the connections as close as

possible to the device. The trace from TRIP pin to resistor and from resistor to GND should avoid coupling to

a high-voltage switching node.

Connect the frequency setting resistor from RF pin to GND, or to the PGOOD pin and make the connections

as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to GND

should avoid coupling to a high-voltage switching node.

•

Connect all GND (analog ground of the device) trace together and connect to power ground or ground plane

with a single via or trace or through a 0-Ω resistor at a quiet point

Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider traces of at least 0.5 mm (20

mils) diameter along this trace.

•

The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side

MOSFET, and high-voltage side of the inductor, must be as short and wide as possible.

Connect the ripple injection V_OUTsignal (V_OUTside of the C1 capacitor in Figure 22) from the terminal of

ceramic output capacitor. The AC-coupling capacitor (C7 in Figure 22 ) can be placed near the device.

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

10.2 Layout Example

T^EXAS

I^NSTRUMENTS

Figure 26. TPS53119EVM-690 Top Layer Assembly Drawing, Top View

Figure 27. TPS53119EVM-690 Bottom Assembly Drawing, Bottom View

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

Layout Example (continued)

Figure 28. TPS53119EVM-690 Top Copper, Top View

Figure 29. TPS53119EVM-690 Layer-2 Copper, Top View

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

Layout Example (continued)

Figure 30. TPS53119EVM-690 Layer-3 Copper, Top View

Figure 31. TPS53119EVM-690 Layer-4 Copper, Top View

TPS53119

www.ti.com.cn

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

Layout Example (continued)

Figure 32. TPS53119EVM-690 Layer-5 Copper, Top View

Figure 33. TPS53119EVM-690 Bottom Layer Copper, Top View

TPS53119

ZHCSH67A –DECEMBER 2017–REVISED MARCH 2019

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 TPS53119 器件并借助 WEBENCH® 电源设计器创建定制设计。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

Eco-Mode，, D-CAP, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS53119RGTR

TPS53119RGTT

ACTIVE

VQFN

RGT

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-20 to 85

53119

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS53119RGTR

TPS53119RGTT

VQFN

RGT

3000

250

330.0

180.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS53119RGTR

TPS53119RGTT

VQFN

RGT

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RGT0016A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

1 MAX

SEATING PLANE

0.08

0.05

0.00

1.45 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

12X 0.5

SYMM

1.5

0.30

16X

0.18

0.1

C A B

PIN 1 ID

(OPTIONAL)

SYMM

0.05

0.5

0.3

16X

4219032/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220

www.ti.com

EXAMPLE BOARD LAYOUT

RGT0016A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.45)

SYMM

16X (0.6)

16X (0.24)

SYMM

(2.8)

(0.475)

TYP

12X (0.5)

(

0.2) TYP

VIA

(R0.05)

ALL PAD CORNERS

(0.475) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219032/A 02/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGT0016A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.34)

16X (0.6)

16X (0.24)

SYMM

(2.8)

12X (0.5)

METAL

ALL AROUND

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4219032/A 02/2017

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS53119 [TI]

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