TPS53124PWR [TI]
Dual Synchronous Step-Down Controller For Low-Voltage Power Rails; 双路同步降压控制器用于低压电源轨
| 型号： | TPS53124PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Synchronous Step-Down Controller For Low-Voltage Power Rails |
| 文件： | 总22页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS53124
www.ti.com ..................................................................................................................................................... SLUS825B–FEBRUARY 2008–REVISED MAY 2008
Dual Synchronous Step-Down Controller For Low-Voltage Power Rails
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
•
High Efficiency, Low-Power Consumption
D-Cap Mode Enables Fast Transient Response
High Initial Reference Accuracy
The TPS53124 is a dual, Adaptive on-time DCAP™
mode synchronous controller. The part enables
system designers to cost effectively complete the
suite of digital TV power bus regulators with the
absolute lowest external component count and lowest
standby consumption. The main control loop for the
TPS53124 uses the D-CAP™ mode that optimized
for low ESR output capacitors such as POSCAP or
SP-CAP promises fast transient response with no
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(on) Loss-less Current Sensing
Adaptive Gate Drivers with Integrated Boost
Diode
external compensation. The part provides
a
convenient and efficient operation with conversion
voltages from 4.5 V to 24 V and output voltage from
0.76 V to 5.5 V.
•
•
Internal 1.2-ms Voltage-Servo Soft Start
Built-In 5-V Linear Regulator
The TPS53124 is available in the 24-pin RGE
package and in the 28-pin PW package and is
specified from -40°C to 85°C ambient temperature
range.
APPLICATIONS
•
•
•
Digital TV Power Supply
Networking Home Terminal
Digital STB
TYPICAL APPLICATION DIAGRAM
Input Voltage
C9
SGND
R5
R2
SGND
PGND
R4
R1
6
5
4
3
2
1
7
24
EN2
EN1
C5
0.1uF
8
9
VBST1 23
VBST2
DRVH2
C3
C6
C2
0.1uF
Power PAD
4.7uF
Q3
L2
4.7uF
VO2
1.8V
DRVH1 22
Q1
Q2
L1
VO1
TPS53124RGE
(QFN24)
10
21
LL1
LL2
3.3uH
Q4
3.3uH
1.05 V
11
12
DRVL120
PGND1 19
DRVL2
PGND2
C1
C4
13
14
15
16
17
18
R6
R3
PGND
PGND
C7
4.7 uF
C8
1 uF
PGND
SGND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DCAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS53124
SLUS825B–FEBRUARY 2008–REVISED MAY 2008..................................................................................................................................................... www.ti.com
TSSOP-28 APPLICATION DIAGRAM
DRVH
VIN
C3
C2
0.1uF
Q1
Q2
4.7uF
1
2
DRVH1 28
VBST1
NC
VO1
27
L1
3.3uH
LL1
3
4
DRVL1 26
PGND1 25
EN1
VO1
VFB1
C1
R1
R2
5
6
7
8
9
24
23
TRIP 1
VIN
R3
VIN
C9
NC
TPS53124PW
(TSSOP28)
VREG5 22
V5FILT 21
GND
TEST1
NC
C7
4.7uF
C8
1uF
20
TEST2
R5
R4
R6
10
11
12
19
VFB2
VO2
EN2
TRIP2
18
PGND2
17
Q4
C4
DRVL 2
3.3uH
LL2
16
13
14
NC
L2
VO2
15
DRVH2
4.7uF
C6
Q3
VBST2
C5
0.1uF
VIN
ORDERING INFORMATION(1)
ORDERING PART
PINS
TA
PACKAGE
OUTPUT SUPPLY
ECO PLAN
NUMBER
Plastic quad
Flat pack (QFN)
TSSOP
TPS53124RGET
TPS53124RGER
TPS53124PWR
TPS53124PW
24
24
28
28
Tape and Reel
Tape and Reel
Tape and Reel
Tube
Green (RoHS & no
Sb/Br)
-40°C to 85°C
TSSOP
(1) All packaging options have Cu NIPDAU lead/ball finish.
2
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIN,EN1,EN2
VALUE
-0.3 to 26
-0.3 to 32
-0.3 to 6
-0.3 to 6
-1 to 32
UNIT
VBST1,VBST2
Input Voltage Range
Output Voltage Range
V
VBST1,VBST2(wrt LLx)
V5FILT,VFB1,VFB2,TRIP1,TRIP2,VO1,VO2, TEST1,TEST2
DRVH1, DRVH2
DRVH1, DRVH2 (wrt LLx)
LL1,LL2
-0.3 to 6
-2 to 26
V
DRVL1,DRVL2,VREG5
PGND1, PGND2
-0.3 to 6
-0.3 to 0.3
Operating ambient temperature
range, TA
-40 to 85
°C
Storage Temperature Range, TSTG
Junction Temperature Range, TJ
-55 to 150
-40 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(2 oz. trace and copper pad with solder)
DERATING FACTOR ABOVE TA
PACKAGE
TA <25°C POWER RATING
TA = 85°C POWER RATING
= 25°C
24-pin QFN
2.33 W
0.78 W
23.3 mW/°C
7.8 mW/°C
0.93 W
0.31 W
28-pin TSSOP
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
VIN
Supply Input Voltage Range
V5FILT
4.5
4.5
24
5.5
30
V
VBST1, VBST2
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
1.8
VBST1, VBST2 (wrt LLx)
5.5
5.5
0.3
24
Input Voltage Range
Output Voltage Range
VFB1,VFB2,VO1,VO2
TRIP1,TRIP2
V
EN1,EN2
DRVH1,DRVH2
VBST1, VBST2 (wrt LLx)
LL1,LL2
30
5.5
24
V
DRVL1,DRVL2, VREG5
PGND1, PGND2
-0.1
-0.1
-40
5.5
0.1
85
Operating Free-Air Temperature, TA
Operating Junction Temperature, TJ
°C
-40
125
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted)
PARAMETER
Supply Current
CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, VREG5 tied to V5FLT,
EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V, LL1 =
LL2 = 0.5 V
IIN
VIN supply current
450
800
µA
IVINSDN
VIN shutdown current
VIN current, TA = 25°C, no load, EN1 = EN2 = 0 V
10
VFB Voltage and Discharge Resistance
Bandgap initial regulation
accuracy
VBG
TA = 25°C
-1%
1%
TA = 25°C
755
752
765
775
778
VFB threshold voltage ꢀꢀꢀ
ꢀꢀ
VVFBTH
mV
TA = -40°C to 85°C
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
ENx = 0 V, VOx = 0.5 V,TA = 25°C
-0.01
40
+/-0.1
80
µA
RDISCHG VO discharge resistance
Ω
VREG5 Output
VVREG5
VLN5
VREG5 output voltage
ꢀꢀꢀ ꢀLine regulation
ꢀꢀꢀ ꢀLoad regulation
Output current
TA = 25°C ,5.5 V < VIN < 24 V, 0 < IVREG5 < 10 mA
5.5 V < VIN < 24 V, IVREG5 = 10 mA
1 mA < IVREG5 < 10 mA
4.8
5
5.2
20
40
V
mV
mA
VLD5
IVREG5
VIN = 5.5 V, VREG5 = 4.0 V, TA = 25°C
170
Output: N-Channel MOSFET Gate Drivers
Source, IDRVHx = -100 mA
Sink, IDRVHx = 100 mA
Source, IDRVLx = - 100 mA
Sink, IDRVLx = 100 mA
5.5
2.5
4
11
5
RDRVH
RDRVL
TD
DRVH resistance
DRVL resistance
Dead time
Ω
Ω
8
2
4
DRVHx-low to DRVLx-on
DRVLx-low to DRVHx-on
20
20
50
40
80
80
ns
Internal BST Diode
VFBST
Forward voltage
VBST leakage current
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
VBST = 29 V, LL = 24 V, TA = 25°C
0.7
0.8
0.1
0.9
1
V
IVBSTLK
µA
ON-Time Timer Control
TON1
CH1 ON time
CH2 ON time
CH2 ON time
LL1 = 12 V, VO1 = 1.5 V
390
210
160
390
TON2
LL2 = 12 V, VO2 = 1.05 V
LL2 = 12 V, VO2 = 0.76 V
LL = 0.7 V TA = 25°C, VFB = 0.7 V
ns
TON(min)
TOFF(min) CH1/CH2 min OFF time
Soft Start
TSS
Internal SS time
Internal soft start VFB = 0.735 V
0.85
1.2
1.4
ms
4
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
Wake up
3.7
4
4.3
VUV5VFILT V5FILT UVLO threshold
V
Hysteresis
0.2
0.3
0.4
LOGIC Threshold
VENH
VENL
ENx H-level input voltage
ENx L-level input voltage
EN 1/2
EN 1/2
2
V
0.3
Current Sense
ITRIP
TRIP source current
ITRIP temperature coefficient
VTRIPx = 0.1 V, TA = 25°C
On the basis of 25°C
8.5
10
11.5
µA
TCITRIP
4000
ppm/°C
(VTRIPx-GND - VPGNDx-LLx) voltage,VTRIPx-GND = 60
mV, TA = 25°C
-10
-15
30
0
10
15
VOCL(off) OCP compensation offset
(VTRIPx-GND - VPGNDx-LLx) voltage, VTRIPx-GND = 60
mV
mV
Current limit threshold setting
VR(trip)
range
VTRIPx-GND voltage
200
Output Undervoltage and Overvoltage Protection
VOVP
Output OVP trip threshold
OVP detect
110%
65%
115%
1.5
120%
75%
TOVPDEL Output OVP prop delay
µs
UVP detect
70%
10%
30
VUVP
Output UVP trip threshold
Hysteresis (recovery < 20 µs)
TUVPDEL Output UVP delay
17
40
µs
TUVPEN
Output UVP enable delay
1.2
2
2.5
ms
Thermal Shutdown
Shutdown temperature(1)
Hysteresis(1)
150
20
TSDN
Thermal shutdown threshold
°C
(1) Ensured by design. Not production tested.
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DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
VBST1,
GFN24
TSSOP28
Supply input for high-side NFET driver (boost terminal). Connect
capacitor from this pin to respective LL terminals. An internal PN diode is
connected between VREG5 to each of these pins. User can add external
schottky diode if forward drop is critical to drive the NFET.
23, 8
1, 14
I
VBST2
EN1, EN2
VO1, VO2
24, 7
1, 6
3, 12
4, 11
I
I
Channel 1 and Channel 2 enable pins.
Output connections to SMPS. These terminals serve ON-time adjustment,
output discharge.
VFB1, VFB2
GND
2, 5
3
5, 10
7
I
I
SMPS feedback inputs. Connect with feedback resistor divider.
Signal ground pin.
High-side NFET driver outputs. LL referenced floating drivers. The gate
drive voltage is defined by the voltage across VBST to LL node flying
capacitor.
DRVH1,
DRVH2
22, 9
28, 15
O
Switch-node connections for high-side drivers. Also serve as input to
current comparators.
LL1, LL2
21, 10
20, 11
27, 16
26, 17
I/O
O
DRVL1,
DRVL2
Synchronous NFET driver outputs. PGND referenced drivers. The gate
drive voltage is defined by VREG5 voltage.
Ground returns for DRVL1 and DRVL2. Also serve as input of current
comparators. Connect PGND1, PGND2 and GND strongly together near
the device.
PGND1,
PGND2
19, 12
18, 13
25, 18
24, 19
I/O
I
Over-current trip point set input. Connect resistor from this pin to GND to
set threshold for synchronous RDS(on) sense. Voltage across this pin and
GND is compared to voltage across PGND and LL at over current
comparator.
TRIP1,
TRIP2
VIN
17
15
23
21
I
I
Supply Input for 5-V linear regulator.
5-V supply input for the entire control circuit except the NFET drivers.
Connect capacitor (typical 1 µF) from GND to V5FILT. V5FILT is
connected to VREG5 via internal resistor.
V5FILT
5-V power supply output. VREG5 is connected to V5FILT via internal
resistor.
VREG5
16
20
O
TEST1,
TEST2
4, 14
8, 20
I/O
Used for test only. Pin should be connected to GND
6
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Pinout Diagrams
QFN Package (Top View)
TSSOP Package (Top View)
28 DRVH1
1
VBST1
NC
27
26
25
24
23
2
LL1
3
EN1
DRVL1
PGND1
TRIP1
VIN
4
VO1
TRIP1
VIN
18
17
16
VO1
VFB1
GND
1
2
3
5
VFB1
NC
6
VREG5
V5FILT
TEST1
VFB2
VO2
22 VREG5
4
5
15
14
13
7
GND
TEST1
NC
TEST2
TRIP2
21
20
19
18
17
16
15
V5FILT
TEST2
TRIP2
8
6
9
10
11
12
13
14
VFB2
VO2
PGND2
DRVL2
LL2
EN2
NC
DRVH2
VBST2
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Functional Block Diagram
8
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DETAILED DESCRIPTION
PWM Operation
The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulse
width modulation (PWM) controller. It supports a proprietary D-CAP™ Mode. D-CAP™ Mode uses internal
compensation circuit and is suitable for low external component count configuration with appropriate amount of
ESR at the output capacitor(s). The output ripple bottom voltage is monitored at a feedback point voltage.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This
MOSFET is turned off, or becomes OFF state, after internal one-shot timer expires. This one shot is determined
by the converter’s input voltage ,VIN, and the output voltage ,VOUT, to keep frequency fairly constant over the
input voltage range, hence it is called adaptive on-time control. The high-side MOSFET is turned on again when
feedback information indicates insufficient output voltage. Repeating operation in this manner, the controller
regulates the output voltage.
Low-Side Driver
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance. A dead time to prevent shoot through is internally generated between
high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V bias
voltage is delivered from internal regulator VREG5 output. The instantaneous drive current is supplied by an
input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at
VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V
makes the driving power which need to be dissipated from TPS53124 package.
High-Side Driver
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a
floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by
the gate charge at VGS = 5 V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance.
PWM Frequency and Adaptive On-Time Control
TPS53124 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the
on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the
output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time.
Soft Start
The TPS53124 has an internal, 1.2 ms, voltage servo softstart for each channel. When the ENx pin becomes
high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the
output voltage is maintained during start up. As TPS53124 shares one DAC with both channels, if ENx pin is set
to high while another channel is starting up, soft start is postponed until another channel soft start has
completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
Output Discharge Control
TPS53124 discharges the output when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). TPS53124 discharges outputs using an internal 40-Ω MOSFET
which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on for the output discharge
operation to avoid the possibility of causing negative voltage at the output.
This discharge ensures that, on start, the regulated voltage always start from zero volts.
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Current Protection
TPS53124 has cycle-by-cycle over current limiting control. The inductor current is monitored during the ‘OFF’
state and the controller keeps the OFF state during the inductor current is larger than the over-current trip level.
In order to provide both good accuracy and cost effective solution, TPS53124 supports temperature
compensated MOSFET RDS(on) sensing. TRIPx pin should be connected to GND through the trip voltage setting
resistor, RTRIP. TRIPx terminal sources 10-µA ITRIP current at the ambient temperature and the trip level is set to
the OCL trip voltage VTRIP as below:
VTRIP( mV ) = RTRIP( kW )´10( mA)
(1)
The trip level should be in the range of 30 mV to 200 mV over all operational temperature. The inductor current is
monitored by the voltage between PGNDx pin and LLx pin. ITRIP has 4000ppm/°C temperature slope to
compensate the temperature dependency of the RDS(on). PGNDx is used as the positive current sensing node so
that PGNDx should be connected to the source terminal of the bottom MOSFET.
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at over-current threshold, IOCP, can be calculated as follows:
VTRIP
IRIPPLE
VTRIP
1
(VIN -VOUT )´VOUT
´
VIN
IOCP
=
+
=
+
RDS( on ) 2´ L´ f
RDS( on )
2
(2)
In an over-current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
Over/Under Voltage Protection
TPS53124 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 30 µs, TPS53124 latches OFF both top and
bottom MOSFET drivers, and shut off both drivers of another channel. This function is enabled approximately 2.0
ms.
UVLO Protection
TPS53124 has V5FILT Under Voltage Lock Out protection (UVLO). When the V5FILT voltage is lower than
UVLO threshold voltage TPS53124 is shut off. This is non-latch protection.
Thermal Shutdown
TPS53124 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C),
the switchers will be shut off as both DRVH and DRVL at low, the output discharge function enabled. Then
TPS53124 is shut off. This is non-latch protection.
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Typical Characteristics
VIN SUPPLY CURRENT
vs
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
600
500
400
300
200
100
0
8
6
4
2
0
-50
0
50
100
150
-50
0
50
100
150
TJ Junction Temperature - °C
TJ Junction Temperature - °C
Figure 1.
Figure 2.
ITRIP SOURCE CURRENT
vs
SWITCHING FREQUENCY IO = 1A
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
20
15
10
5
500
400
300
CH2
CH1
200
100
0
0
-50
0
50
100
150
0
5
10
15
20
25
TJ Junction Temperature - °C
VIN - Input Voltage - V
Figure 3.
Figure 4.
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Typical Characteristics (continued)
SWITCHING FREQUENCY IO = 1A
1.05-V OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
500
1100
1075
1050
CH2
400
300
VI = 24 V
CH1
200
100
VI = 5.5 V
VI = 12 V
1025
1000
0
0
1.0
2.0
3.0
4.0
0
1.0
2.0
3.0
4.0
IOUT - Output Current - A
IOUT1 - Output Current - A
Figure 5.
Figure 6.
1.8-V OUTPUT VOLTAGE
vs
1.05-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
INPUT VOLTAGE
1.875
1.850
1100
1075
1050
VI = 24 V
IO = 0 A
1.825
1.800
1.775
VI = 5.5 V
VI = 12 V
IO = 2 A
1025
1000
1.750
1.725
0
1.0
2.0
3.0
4.0
0
5
10
15
20
25
IOUT2 - Output Current - A
VIN - Input Voltage - V
Figure 7.
Figure 8.
12
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www.ti.com ..................................................................................................................................................... SLUS825B–FEBRUARY 2008–REVISED MAY 2008
Typical Characteristics (continued)
1.8-V OUTPUT VOLTAGE
1.8-V LOAD TRANSIENT RESPONSE
vs
INPUT VOLTAGE
1.875
VOUT2
1.850
(100 mV/div)
IO = 0 A
1.825
1.800
IOUT2
IO = 2 A
(2 A/div)
1.775
1.750
1.725
0
5
10
15
20
25
t - Time - 20 ms/div
VIN - Input Voltage - V
Figure 9.
Figure 10.
1.05-V LOAD TRANSIENT RESPONSE
VOUT1
(100 mV/div)
IOUT1
(2 A/div)
t - Time - 20 ms/div
Figure 11.
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SLUS825B–FEBRUARY 2008–REVISED MAY 2008..................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Loop Compensation and External Parts Selection
A buck converter system using D-CAP™ Mode can be simplified as below.
Voltage Devider
R1
Vin
DRVH
DRVL
PWM
R2
Logic
control
Lx
Ref
Driver
ESR
Co
Vc
SwitchingModulator
Figure 12. Simplifying the Modulator
The output voltage is compared with internal reference voltage after divider resistors,R1 and R2. The PWM
comparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough
to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The dc
output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase.
For the loop stability, the 0dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
1
fSW
£
fO =
2p ´ ESR´CO
3
(3)
Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, a sufficient amount of feedback signal needs to be provided by
external circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The required
signal level is approximately 10 mV at the comparing point(VFB terminal). This gives Vripples at the output node
becomes Equation 4. The output capacitor’s ESR should meet this requirement.
VOUT
VRIPPLE
=
´10 mV
[ ]
VFBx
(4)
14
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The external components selection is much simpler in D-CAP™ Mode.
1. Choose inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to a
stable operation.
- ´
V IN(max) V OUT V OUT
- ´
V IN(max) V OUT V OUT
(
)
(
)
1
3
L =
×
=
´
´ f
´ f
V IN(max)
V IN(max)
I IND( ripple )
IOUT(max)
(5)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as follows.
(VIN(max) -VOUT )´VOUT
VTRIP
1
=
+
RDS( on ) L´ f
´
IIND( peak )
VIN(max)
(6)
2. Choose output capacitor.
Polymer aluminum capacitor, organic semiconductor capacitor or specialty polymer capacitor are
recommended. Determine ESR to meet required ripple voltage indicated previously.
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PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS53124RGER
TPS53124RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
4.3
4.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53124RGER
TPS53124RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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