TPS53128 [TI]

DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS; 双路同步降压控制器，适用于低压电源轨


型号：	TPS53128
厂家：	TEXAS INSTRUMENTS
描述：	DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS 双路同步降压控制器，适用于低压电源轨控制器
文件：	总29页 (文件大小：772K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS53128

www.ti.com

SLVSAE4 –JULY 2010

DUAL SYNCHRONOUS STEP-DOWN CONTROLLER

FOR LOW VOLTAGE POWER RAILS

Check for Samples: TPS53128

FEATURES

•

350-kHz Switching Frequency

•

D-CAP2™ Mode Control

Cycle-by-Cycle Over-Current Limiting Control

30-mV to 300-mV OCP Threshold Voltage

–

Fast Transient Response

No External Parts Required for Loop

Compensation

Thermally Compensated OCP by 4000 ppm/°C

at I_TRIP

–

Compatible With Ceramic Output

Capacitors

APPLICATIONS

•

Point-of-Load Regulation in Low Power

Systems for Wide Range of Applications

•

High Initial Reference Accuracy (±1%)

Low Output Ripple

–

Digital TV Power Supply

Networking Home Terminal

Digital Set-Top Box (STB)

DVD Player/Recorder

Gaming Consoles

Wide Input Voltage Range: 4.5 V to 24 V

Output Voltage Range: 0.76 V to 5.5 V

Low-Side R_DS(ON)Loss-Less Current Sensing

Adaptive Gate Drivers with Integrated Boost

Diode

•

Adjustable Soft Start

Non-Sinking Pre-Biased Soft Start

DESCRIPTION

The TPS53128 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables

system designers to cost effectively complete the suite of various end equipment's power bus regulators with a

low external component count and low standby consumption. The main control loop for the TPS53128 uses the

D-CAP2™ Mode topology which provides a very fast transient response with no external component.

The TPS53128 also has a proprietary circuit that enables the device to adapt not only low equivalent series

resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic capacitor. The fixed frequency

emulated adaptive on-time control supports seamless operation between PWM mode at heavy load condition

and reduced frequency operation at light load for high efficiency down to milliampere range. The part provides a

convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to

5.5 V.

The TPS53128 is available in 4-mm x 4-mm 24 pin QFN (RGE) or 24 pin TSSOP (PW) packages, and is

specified from -40°C to 85°C ambient temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D-CAP2 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS53128

SLVSAE4 –JULY 2010

www.ti.com

TYPICAL APPLICATION CIRCUITS

Input Voltage

4.5V to 24V

10uF

C10

4700pF

SGND

10kΩ

PGND

3.52kΩ

13kΩ

EN1

EN2

VBST2

FDS8878

0.1uF

10uF

0.1uF

VBST1 ²³

DRVH1 ²²

10uF

SPM6530T

1.5uH

SPM6530T

1.5uH

Power PAD

DRVH2

SW2

TPS53128 RGE

(QFN )

SW1

VO2

1.05V/4A

VO1

1.8V/4A

FDS8690

DRVL1 ²⁰

PGND1 ₁₉

DRVL2

¹²PGND2

22uFx4

4.7uF

R３

C８

1uF

PGND

4.3kΩ

3.3kΩ

PGND

SGND

C11

4700pF

Figure 1. QFN

FDS8878

10uF

0.1uF

SPM6530T

1.5uH

DRVH1

VBST1

VO1

1.8V/4A

SW1

FDS8690

DRVL1

22uFx4

EN1

VO1

PGND1

R３

13kΩ

3.3kΩ

TRIP1 ²¹

PGND

Input Voltage

TPS53128PW

TSSOP24

VIN ²⁰

VFB1

GND

SS1

10kΩ

4.5V to 24V

4.7uF

VREG5¹⁹

10uF

V5FILT ¹⁸

C10

4700pF

SGND

C８

1uF

PGND

10kΩ

VFB2

SS2 ¹⁷

C11

4700pF

VO2

TRIP2 ¹⁶

3.52kΩ

SGND

4.3kΩ

PGND

PGND2

EN2

FDS8690

VBST2

DRVL2

22uFx4

DRVH2

SW2

SPM6530T

1.5uH

VO2

1.05V/4A

10uF

0.1uF

FDS8878

Figure 2. TSSOP

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SLVSAE4 –JULY 2010

ORDERING INFORMATION⁽¹⁾

ORDERING

T_A

PACKAGE^{(2) (3)}

PINS

OUTPUT SUPPLY

ECO PLAN

PART NUMBER

TPS53128RGET

TPS53128RGER

TPS53128PWR

TPS53128PW

Tape-and-Reel

Tube

Plastic Quad

Flat Pack (QFN)

Green

(RoHS and no Sb/Br)

–40°C to 85°C

TSSOP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) All packaging options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.3 to 26

–0.3 to 32

–0.3 to 6

UNIT

VIN, EN1, EN2

VBST1, VBST2

VBST1 - SW1, VBST2 - SW2

V_I

Input voltage range

Output voltage range

V5FILT, VFB1, VFB2, TRIP1, TRIP2,

VO1, VO2

–0.3 to 6

SW1, SW2

–2 to 26

–1 to 32

DRVH1, DRVH2

DRVH1 - SW1, DRVH2 - SW2

DRVL1, DRVL2, VREG5, SS1, SS2

PGND1, PGND2

–0.3 to 6

–0.3 to 0.3

–40 to 85

–55 to 150

–40 to 150

V_O

T_A

Operating ambient temperature range

Storage temperature range

°C

T_STG

T_J

Junction temperature range

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS

2-oz. trace and copper pad with solder

T_A< 25°C

POWER RATING

DERATING FACTOR

ABOVE T_A= 25°C

T_A= 85°C

POWER RATING

PACKAGE

24-pin QFN

2.33 W

23.3 mW/°C

7.8 mW/°C

0.93 W

0.31 W

24-pin TSSOP

0.778 W

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

VIN

V_IN

Supply input voltage

Input voltage

V5FILT

4.5

5.5

VBST1, VBST2

–0.1

–1.8

VBST1 - SW1, VBST2 - SW2

VFB1, VFB2, VO1, VO2

TRIP1, TRIP2

5.5

0.3

V_I

EN1, EN2

SW1, SW2

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RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

–0.1

–40

MAX

UNIT

DRVH1, DRVH2

VBST1 - SW1, VBST2 - SW2

5.5

0.1

V_O

Output voltage

DRVL1, DRVL2, VREG5, SS1, SS2

PGND1, PGND2

T_A

T_J

Operating free-air temperature

Operating junction temperature

°C

–40

125

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN current, T_A= 25°C, VREG5 tied

to V5FILT, EN1 = EN2 = 5 V,

VFB1 = VFB2 = 0.8 V,

I_IN

VIN supply current

450

800

SW1 = SW2 = 0.5 V

VIN current, T_A= 25°C,

no load , EN1 = EN2 = 0 V,

VREG5 = ON

I_VINSDN

VIN shutdown current

VFB VOLTAGE AND DISCHARGE RESISTANCE

V_BG

Bandgap initial regulation accuracy

T_A= 25°C

–1

T_A= 25°C, SW_inj= OFF

755

765

775

TA = 0°C to 70°C,

SW_inj= OFF⁽¹⁾

753.5

776.5

778

V_VFBTHx

VFBx threshold voltage

T_A= -40°C to 85°C,

752

(1)

SW_inj= OFF

I_VFB

VFB input current

VFBx = 0.8 V, T_A= 25°C

–100

–10

100

R_Dischg

VO discharge resistance

ENx = 0 V, VOx = 0.5 V, T_A= 25°C

Ω

VREG5 OUTPUT

T_A= 25°C, 5.5 V < VIN < 24 V,

0 < I_VREG5< 10 mA

V_VREG5

VREG5 output voltage

4.8

5.0

5.2

V_LN5

V_LD5

Line regulation

Load regulation

5.5 V < VIN < 24 V, I_VREG5= 10 mA

1 mA < I_VREG5< 10 mA

VIN = 5.5 V, V_REG5= 4.0 V,

T_A= 25°C

I_VREG5

Output current

170

OUTPUT: N-CHANNEL MOSFET GATE DRIVERS

Source, I_DRVHx= –100 mA

Sink, I_DRVHx= 100 mA

Source, I_DRVLx= –100 mA

Sink, I_DRVLx= 100 mA

5.5

2.5

R_DRVH

R_DRVL

T_D

DRVH resistance

DRVL resistance

Dead time

Ω

DRVHx-low to DRVLx-on

DRVLx-low to DRVHx-on

INTERNAL BOOST DIODE

V_FBST

Forward voltage

V_VREG5-VBSTx, I_F= 10 mA, T_A= 25°C

0.7

0.8

0.1

0.9

VBSTx = 29 V, SWx = 24 V,

T_A= 25°C

I_VBSTLK

VBST leakage current

ON-TIME TIMER CONTROL

T_ON1L

T_ON2L

CH1 on time

CH2 on time

SW1 = 12 V, VO1 = 1.8 V

SW2 = 12 V, VO2 = 1.8 V

490

390

(1) Not production tested - ensured by design.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SW1 = 0.7 V, T_A= 25°C,

VFB1 = 0.7 V

T_OFF1L

T_OFF2L

CH1 min off time

285

SW2 = 0.7 V, T_A= 25°C,

VFB2 = 0.7 V

CH2 min off time

285

SOFT START

I_SSC

SS1/SS2 charge current

V_SS1/V_SS2= 0 V, T_A= 25°C

On the basis of 25°C⁽¹⁾

V_SS1/V_SS2= 0.5 V

–1.5

–4

–2

–2.5

nA/°C

TC_ISSC

I_SSD

I_SSCtemperature coefficient

SS1/SS2 discharge current

100

150

UVLO

Wake up

3.7

0.2

4.0

0.3

4.3

0.4

V_UV5VFILT

V5FILT UVLO threshold

Hysteresis

LOGIC THRESHOLD

V_ENH

V_ENL

ENx high-level input voltage

ENx low-level input voltage

EN 1/2

2.0

0.3

CURRENT SENSE

I_TRIP

TRIP source current

VTRIPx = 0.1 V, T_A= 25°C

On the basis of 25°C

8.5

11.5

TC_ITRIP

I_TRIPtemperature coefficient

OCP compensation offset

4000

ppm/°C

(V_TRIPx-GND-V_PGNDx-SWx) voltage,

V_TRIPx-GND= 60 mV, T_A= 25°C

–15

V_OCLoff

(V_TRIPx-GND-V_PGNDx-SWx) voltage,

V_TRIPx-GND= 60 mV

–20

V_Rtrip

Current limit threshold setting range V_TRIPx-GNDvoltage

300

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

V_OVP

Output OVP trip threshold

Output OVP prop delay

OVP detect

110

115

1.5

120

T_OVPDEL

UVP detect

V_UVP

Output UVP trip threshold

Hysteresis (recover < 20 ms)

T_UVPDEL

T_UVPEN

Output UVP delay

Output UVP enable delay

UVP enable delay / soft-start time

x1.4

x1.7

x2.0

THERMAL SHUTDOWN

(2)

Shutdown temperature

150

T_SDN

Thermal shutdown threshold

°C

(2)

Hysteresis

(2) Not production tested - ensured by design.

TERMINAL FUNCTIONS

PIN Fucntion Table

TERMINAL

I/O

DESCRIPTION

QFN

TSSOP

NAME

Supply input for high-side NFET driver. Bypass to SWx with a high-quality

0.1-mF ceramic capacitor. An external schottky diode can be added from

VREG5 if forward drop is critical to drive the high-side FET.

VBST1,

VBST2

23, 8

2, 11

EN1, EN2

VO1, VO2

24, 7

1, 6

3, 10

4, 9

Enable. Pull High to enable SMPS.

Output voltage inputs for on-time adjustment and output discharge. Connect

directly to the output voltage.

VFB1,

VFB2

2, 5

5, 8

D-CAP2 feedback inputs. Connect to output voltage with resistor divider.

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PIN Fucntion Table (continued)

TERMINAL

I/O

DESCRIPTION

QFN

TSSOP

NAME

Signal ground pin. Connect to PGND1, PGND2 and system ground at a single

point.

GND

DRVH1,

DRVH2

High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers

switch between SWx (OFF) and VBSTx (ON).

22, 9

21, 10

20, 11

1, 12

24, 13

23, 14

Switch node connections for both the high-side drivers and the over current

comparators.

SW1, SW2

I/O

DRVL1,

DRVL2

Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers

switch between PGNDx (OFF) and VREG5 (ON).

Power ground connections for both the low-side drivers and the over current

comparators. Connect PGND1, PGND2 and GND strongly together near the

IC.

PGND1,

PGND2

19, 12

22, 15

I/O

TRIP1,

TRIP2

Over current threshold programming pin. Connect to GND with a resistor to

GND to set threshold for low-side R_DS(ON)current limit.

18, 13

21, 16

Supply Input for 5-V linear regulator. Bypass to GND with a minimum

high-quality 0.1-mF ceramic capacitor.

VIN

5-V supply input for the entire control circuitry except the MOSFET drivers.

Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT

is connected to VREG5 via an internal 10-Ω resistor.

V5FILT

Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND

with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to

V5FILT via an internal 10-Ω resistor.

VREG5

Soft-start programming pin. Connect capacitor from SSx pin to GND to program

soft-start time.

SS1, SS2

4,14

7, 17

xxx

TSSOP PACKAGE

(TOP VIEW)

QFN PACKAGE

(TOP VIEW)

DRVH1

VBST1

EN1

SW1

DRVL1

22 PGND1

TRIP1

VIN

VO1

VFB1

GND

VO1

TRIP1

VREG5

VIN

VFB1

GND

V5FILT

SS2

SS1

VFB2

VO2

VREG5

V5FILT

SS2

TRIP2

PGND2

DRVL2

SW2

SS1

VFB2

VO2

EN2

VBST2

TRIP2

DRVH2

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SLVSAE4 –JULY 2010

FUNCTIONAL BLOCK DIAGRAM

SW1

SW2

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ERR

COMP

SWX

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DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS53128 is an adaptive on-time pulse width modulation (PWM) controller using a

proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal

compensation circuit for pseudo-fixed frequency and low external component count configuration with both low

ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer

expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot

timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage

VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal

ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output

ripple from D-CAP mode control.

Light-Load Condition

TPS53128 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This

reduction of frequency is achieved smoothly and without increase of V_OUTripple or load regulation. Detail

operation is described as follows. As the output current decreases from heavy-load condition, the inductor

current is also reduced, and eventually comes to the point that its valley touches zero current, which is the

boundary between continuous conduction and discontinuous condition modes. The low-side MOSFET is turned

off when this zero inductor current is detected. As the load current is further decreased, the converter runs in

discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that

requires the next ON cycle. The ON time is kept the same as that in the heavy-load condition. In reverse, when

the output current increases from light load to heavy load, the switching frequency increases to the preset value

as the inductor current reaches the continuous conduction. The transition load point to the light load operation,

I_OUT(LL)(i.e., threshold between continuous and discontinuous condition mode) can be calculated as follows.

V_IN-Vox

´Vox

I_{OUT (LL)}

2´ L´ fsw V_IN

(1)

Where f_SWis the PWM switching frequency.

Switching frequency versus output current in the light-load condition is a function of L, f_SW, V_INand V_OUT, but it

decreases almost proportional to the output current from the I_OUT(LL)given in Equation 1.

Drivers

Each channel of the TPS53128 contains two high-current resistive MOSFET gate drivers. The low-side driver is a

PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low R_DS(ON)N-channel

MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered

driver designed to drive the gate of a high-current, low R_DS(ON)N-channel MOSFET. To maintain the VBST

voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws

average current equal to gate charge (Q_gat V_gs= 5 V) times switching frequency (f_SW).

To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF

between each driver transition. During this time the inductor current is carried by one of the MOSFETs body

diodes.

PWM Frequency and Adaptive On-Time Control

TPS53128 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.

TPS53128 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time

one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.

Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

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5-Volt Regulator

The TPS53128 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers

and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is required to

stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's

analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from

V5FILT to GND to filter switching noise from VREG5.

Soft Start

The TPS53128 has a programmable soft-start . When the ENx pin becomes high, 2.0-mA current begins charging

the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control

comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference

for smooth control of the output voltage during start up.

Pre-Bias Support

The TPS53128 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the

low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start

becomes greater than feedback voltage (VFB)), then the TPS53128 slowly activates synchronous rectification by

limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle

basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the

pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the

control loop is given time to transition from pre-biased start-up to normal mode operation.

Output Discharge Control

TPS53128 discharges the outputs when ENx is low, or the controller is turned off by the protection functions

(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which

is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge

operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start

the regulated voltage always initializes from 0 V.

Over Current Limit

TPS53128 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by

monitoring the voltage drop across the low-side MOSFET R_DS(ON)during the low-side driver on-time. If the

inductor current is larger than the over current limit (OCL), the TPS53128 delays the start of the next switching

cycle until the sensed inductor current falls below the OCL current. MOSFET R_DS(ON)current sensing is used to

provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin

should be connected to GND through a trip voltage setting resistor, according to the following equations.

(V_IN- V_O)

V_O

V_TRIP

I_OCL

· R_DS(ON)

( )

2 · L1 · f_SW

V_IN

(2)

(3)

V_TRIP(mV)

R_TRIP(kW) =

I_TRIP(mA)

The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the

4000-ppm/°C temperature slope compensation for the temperature dependency of the R_DS(ON)

If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions

continues the output voltage will fall below the under voltage protection threshold and the TPS53128 will shut

down.

In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output

voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and

shutdown.

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Over/Under Voltage Protection

TPS53128 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage

is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the

high-side MOSFET driver OFF and the low-side MOSFET driver ON.

When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high

and an internal UVP delay counter begins counting. After 30 ms, TPS53128 latches OFF both top and bottom

MOSFET drivers. This function is enabled approximately 1.7 x T_SSafter power-on. The OVP and UVP latch off is

reset when EN goes low level.

UVLO Protection

TPS53128 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.

When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF

and output discharge is ON. The UVLO is non-latch protection.

Thermal Shutdown

The TPS53128 includes an over temperature protection shut-down feature. If the TPS53128 die temperature

exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output

voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal

shutdown is a non-latch protection.

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TYPICAL CHARACTERISTICS

VIN SUPPLY CURRENT

VIN SHUTDOWN CURRENT

JUNCTION TEMPERATURE

700

600

500

400

300

200

100

VREG5=ON

-50

100

150

-50

100

150

T_J- Junction Temperature - °C

Figure 3.

Figure 4.

TRIP SOURCE CURRENT

VREG5 VOLTAGE

JUNCTION TEMPERATURE

5.070

5.060

5.050

5.040

5.030

5.020

5.010

5.000

-50

100

150

T_J- Junction Temperature - °C

Figure 5.

Figure 6.

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TYPICAL CHARACTERISTICS (continued)

VREG5 VOLTAGE

VFB1 VOLTAGE

INPUT VOLTAGE

5.500

5.300

5.100

4.900

4.700

4.500

0.800

0.795

0.790

0.785

0.780

0.775

0.770

0.765

0.760

0.755

0.750

VIN - Input Voltage - V

Figure 7.

Figure 8.

VFB2 VOLTAGE

VFB1 VOLTAGE

INPUT VOLTAGE

JUNCTION TEMPERATURE

0.800

0.795

0.790

0.785

0.780

0.775

0.770

0.765

0.760

0.755

0.750

0.800

0.795

0.790

0.785

0.780

0.775

0.770

0.765

0.760

0.755

0.750

-50

100

150

VIN - Input Voltage - V

T_J- Junction Temperature - °C

Figure 9.

Figure 10.

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TYPICAL CHARACTERISTICS (continued)

VFB2 VOLTAGE

JUNCTION TEMPERATURE

0.800

0.795

0.790

0.785

0.780

0.775

0.770

0.765

0.760

0.755

0.750

-50

100

150

T_J- Junction Temperature - °C

Figure 11.

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TYPICAL APPLICATION PERFORMANCE

SWITCHING FREQUENCY (I_O1 = 3 A)

SWITCHING FREQUENCY (I_O2 = 3 A)

INPUT VOLTAGE (CH1)

INPUT VOLTAGE (CH2)

500

400

300

200

100

400

300

200

100

V_O2 = 1.05 V

V_O1=1.8V

VIN - Input Voltage - V

Figure 12.

Figure 13.

SWITCHING FREQUENCY

OUTPUT CURRENT (CH1)

OUTPUT CURRENT (CH2)

400

350

300

250

200

150

100

400

350

300

250

200

150

100

VO2=1.05V

VO1=1.8V

0.01

0.1

0.01

0.1

I_O- Output Current - A

Figure 14.

Figure 15.

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OUTPUT VOLTAGE (VIN = 12 V)

OUTPUT CURRENT (CH1)

OUTPUT CURRENT (CH2)

1.880

1.870

1.860

1.850

1.840

1.830

1.820

1.810

1.800

1.790

1.780

1.770

1.760

0.001

1.100

1.090

1.080

1.070

1.060

1.050

1.040

1.030

1.020

1.010

1.000

VO1=1.8V

VO2=1.05V

0.001

0.01

0.1

0.01

0.1

I_OUT- Output Current - A

Figure 16.

Figure 17.

OUTPUT VOLTAGE (VIN = 12 V)

INPUT VOLTAGE (CH1)

INPUT VOLTAGE (CH2)

1.100

1.090

1.080

1.070

1.060

1.050

1.040

1.030

1.020

1.010

1.000

1.880

1.870

1.860

1.850

1.840

1.830

1.820

1.810

1.800

1.790

1.780

1.770

1.760

VO2=1.05V

VO1=1.8V

V_I- Input Voltage - V

Figure 18.

Figure 19.

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LOAD TRANSIENT RESPONSE

VO2=1.05V (50mV/div)

VO1=1.8V (50mV/div)

IOUT2 (2A/div)

IOUT1 (2A/div)

Figure 20.

Figure 21.

START-UP WAVEFORMS

EN2 (5 V/div)

EN1 (5 V/div)

SS2 (0.2 V/div)

SS1 (0.2 V/div)

VO1 = 1.8 V (0.5 V/div)

VO2 = 1.05 V (0.5 V/div)

Figure 22.

Figure 23.

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1.8-V EFFICIENCY

1.05-V EFFICIENCY

OUTPUT CURRENT (CH1)

OUTPUT CURRENT (CH2)

100

VO1=1.8V

VO2=1.05V

0.001

0.01

0.1

0.001

0.01

0.1

I_OUT- Output Current - A

Figure 24.

Figure 25.

1.8-V OUTPUT RIPPLE VOLTAGE

1.05-V OUTPUT RIPPLE VOLTAGE

VO2 (20mV/div)

VO1 (20mV/div)

VO1=1.8V

VO2=1.05V

Figure 26.

Figure 27.

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APPLICATION INFORMATION

1. Choose inductor.

The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.

Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.

Equation 4 can be used to calculate L1.

-Vo1

3´

-Vo1

(

)

(

)

V _{IN (max)}

I _L1(ripple)

V _{IN (max)}

Io1´ fsw

Vo1

L1=

´ fsw

V _{IN (max)}

(4)

The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)

current. The RMS and peak inductor current can be estimated as follows.

V_IN(MAX)- V_O1

L1 · f_SW

V_o1

V_IN(MAX)

I_L1(RIPPLE)

(5)

V_TRIP

R_DS(ON)

I_L1(PEAK)

+ I_L1(RIPPLE)

(6)

(7)

_O1 +

I_L1(RMS)

)

L1(RIPPLE)

Note: The calculation above shall serve as a general reference. To further improve transient response, the

output inductance could be reduced further. This needs to be considered along with the selection of the

output capacitor.

2. Choose output capacitor.

The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it

is recommended to use a ceramic output capacitor.

I_L1(RIPPLE)

f_SW

C1 =

8 · V_O1_(RIPPLE)

(8)

(9)

· L1

load

2 · V_O1 · DV_OS

· L1

load

2 · K · DV_US

(10)

Where

T_on1

T 1 + T_min(off)

K = (V_IN- V

_O1) ·

(11)

Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and

Equation 10. The capacitance for C1 should be greater than 66 mF.

Where

ΔV_OS= The allowable amount of overshoot voltage in load transition

ΔV_US= The allowable amount of undershoot voltage in load transition

T_min(off)= Minimum off time

3. Choose input capacitor.

The TPS53128 requires an input decoupling capacitor and a bulk capacitor is needed depending on the

application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The

capacitor voltage rating needs to be greater than the maximum input voltage.

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4. Choose bootstrap capacitor.

The TPS53128 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the

high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating

should be greater than 10 V.

5. Choose VREG5 and V5FILT capacitor.

The TPS53128 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF

high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A

minimum 1-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper

operation. Both of these capacitors’ voltage ratings should be greater than 10 V.

6. Choose output voltage divider resistors.

The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is

recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use

Equation 12 or Equation 13 to calculate R1.

V_O1

) )

V_IN

f_SW

V_swinj= (V_IN- V_O1 · 0.5875) ·

4975

(

(12)

(13)

_O1

V_FB(RIPPLE)

- 1

· R2

R1 =

swinj

( )

V_FB+

Where

V_FB(RIPPLE)= Ripple voltage at VFB

V_swinj= Ripple voltage at error comparator

7. Choose register setting for over current limit.

(V_IN- V_O)

V_O

V_TRIP

I_OCL

· R_DS(ON)

(

R_TRIP(kW) =

)

2 · L1 · f_SWV_IN

(14)

(15)

V_TRIP(mV) - V_OCLoff

I_TRIP(min)(mA)

Where

R_DS(ON)= Low side FET on-resistance

I_TRIP(min)= TRIP pin source current （8.5 mA）

V_OCL0ff= Minimum over current limit offset voltage (–20 mV)

I_OCL= Over current limit

8. Choose soft start capacitor.

Soft start time equation is as follows.

T_SS· I_SSC

V_FB

C_SS=

(16)

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LAYOUT SUGGESTIONS

•

Keep the input switching current loop as small as possible.

•

Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept

as small as possible.

•

Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin (FBx) of the device.

•

Keep analog and non-switching components away from switching components.

Make a single point connection from the signal ground to power ground.

Do not allow switching current to flow under the device.

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Sep-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS53128PW

TPS53128PWR

TPS53128RGER

TPS53128RGET

ACTIVE

TSSOP

VQFN

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Purchase Samples

2000

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

Purchase Samples

RGE

Green (RoHS

& no Sb/Br)

VQFN

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Sep-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS53128PWR

TPS53128RGER

TPS53128RGET

TSSOP

VQFN

RGE

2000

3000

250

330.0

180.0

16.4

12.4

6.95

4.25

8.3

1.6

8.0

16.0

12.0

4.25

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Sep-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS53128PWR

TPS53128RGER

TPS53128RGET

TSSOP

VQFN

RGE

2000

3000

250

346.0

190.5

346.0

212.7

33.0

29.0

31.8

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TPS53128 [TI]

相关型号：

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TPS53128PWR

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TPS53128RGET

TPS53129

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TPS53129PWR

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TPS53211