TPS53128RGET [TI]
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS; 双路同步降压控制器,适用于低压电源轨型号: | TPS53128RGET |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS |
文件: | 总29页 (文件大小:772K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS53128
www.ti.com
SLVSAE4 –JULY 2010
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER
FOR LOW VOLTAGE POWER RAILS
Check for Samples: TPS53128
1
FEATURES
•
•
•
•
350-kHz Switching Frequency
2
•
D-CAP2™ Mode Control
Cycle-by-Cycle Over-Current Limiting Control
30-mV to 300-mV OCP Threshold Voltage
–
–
Fast Transient Response
No External Parts Required for Loop
Compensation
Thermally Compensated OCP by 4000 ppm/°C
at ITRIP
–
Compatible With Ceramic Output
Capacitors
APPLICATIONS
•
Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
•
•
•
•
•
•
High Initial Reference Accuracy (±1%)
Low Output Ripple
–
–
–
–
–
Digital TV Power Supply
Networking Home Terminal
Digital Set-Top Box (STB)
DVD Player/Recorder
Gaming Consoles
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(ON) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost
Diode
•
•
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
DESCRIPTION
The TPS53128 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables
system designers to cost effectively complete the suite of various end equipment's power bus regulators with a
low external component count and low standby consumption. The main control loop for the TPS53128 uses the
D-CAP2™ Mode topology which provides a very fast transient response with no external component.
The TPS53128 also has a proprietary circuit that enables the device to adapt not only low equivalent series
resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic capacitor. The fixed frequency
emulated adaptive on-time control supports seamless operation between PWM mode at heavy load condition
and reduced frequency operation at light load for high efficiency down to milliampere range. The part provides a
convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to
5.5 V.
The TPS53128 is available in 4-mm x 4-mm 24 pin QFN (RGE) or 24 pin TSSOP (PW) packages, and is
specified from -40°C to 85°C ambient temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP2 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS53128
SLVSAE4 –JULY 2010
www.ti.com
TYPICAL APPLICATION CIRCUITS
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
SGND
R1
R5
R2
R4
10kΩ
10kΩ
PGND
3.52kΩ
13kΩ
6
5
4
3
2
1
7
24
EN1
EN2
VBST2
Q3
FDS8878
Q1
FDS8878
C5
0.1uF
C6
10uF
C2
0.1uF
8
9
VBST1 23
DRVH1 22
C3
10uF
L2
SPM6530T
1.5uH
L1
SPM6530T
1.5uH
Power PAD
DRVH2
SW2
TPS53128 RGE
(QFN )
10
11
21
SW1
L1
VO2
1.05V/4A
VO1
1.8V/4A
Q4
FDS8690
Q2
FDS8690
DRVL1 20
PGND1 19
DRVL2
12 PGND2
13
14
15
16
17
18
C4
22uFx4
C1
22uFx4
C7
4.7uF
R6
R3
C8
1uF
PGND
PGND
4.3kΩ
3.3kΩ
PGND
SGND
C11
4700pF
Figure 1. QFN
Q1
FDS8878
L1
C3
10uF
C2
0.1uF
SPM6530T
1.5uH
1
2
24
DRVH1
VBST1
VO1
1.8V/4A
SW1
Q2
FDS8690
23
DRVL1
C1
22uFx4
22
3
4
EN1
VO1
R1
PGND1
R3
13kΩ
3.3kΩ
TRIP1 21
PGND
Input Voltage
R2
TPS53128PW
TSSOP24
VIN 20
C7
5
6
7
VFB1
GND
SS1
10kΩ
4.5V to 24V
4.7uF
VREG519
C9
10uF
V5FILT 18
C10
4700pF
SGND
C8
1uF
PGND
R5
10kΩ
8
9
VFB2
SS2 17
C11
4700pF
R4
VO2
TRIP2 16
3.52kΩ
R6
SGND
4.3kΩ
10
11
12
15
PGND
C4
PGND2
EN2
Q4
FDS8690
VBST2
14
DRVL2
22uFx4
13
DRVH2
SW2
L2
SPM6530T
1.5uH
VO2
1.05V/4A
C6
10uF
C5
0.1uF
Q3
FDS8878
Figure 2. TSSOP
2
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SLVSAE4 –JULY 2010
ORDERING INFORMATION(1)
ORDERING
TA
PACKAGE(2) (3)
PINS
OUTPUT SUPPLY
ECO PLAN
PART NUMBER
TPS53128RGET
TPS53128RGER
TPS53128PWR
TPS53128PW
Tape-and-Reel
Tape-and-Reel
Tape-and-Reel
Tube
Plastic Quad
Flat Pack (QFN)
Green
(RoHS and no Sb/Br)
–40°C to 85°C
24
TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All packaging options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 26
–0.3 to 32
–0.3 to 6
UNIT
VIN, EN1, EN2
VBST1, VBST2
VBST1 - SW1, VBST2 - SW2
VI
Input voltage range
Output voltage range
V
V5FILT, VFB1, VFB2, TRIP1, TRIP2,
VO1, VO2
–0.3 to 6
SW1, SW2
–2 to 26
–1 to 32
DRVH1, DRVH2
DRVH1 - SW1, DRVH2 - SW2
DRVL1, DRVL2, VREG5, SS1, SS2
PGND1, PGND2
–0.3 to 6
–0.3 to 6
–0.3 to 0.3
–40 to 85
–55 to 150
–40 to 150
VO
V
TA
Operating ambient temperature range
Storage temperature range
°C
°C
°C
TSTG
TJ
Junction temperature range
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
2-oz. trace and copper pad with solder
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
24-pin QFN
2.33 W
23.3 mW/°C
7.8 mW/°C
0.93 W
0.31 W
24-pin TSSOP
0.778 W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
24
UNIT
VIN
VIN
Supply input voltage
Input voltage
V
V5FILT
4.5
5.5
30
VBST1, VBST2
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
VBST1 - SW1, VBST2 - SW2
VFB1, VFB2, VO1, VO2
TRIP1, TRIP2
5.5
5.5
0.3
24
VI
V
EN1, EN2
SW1, SW2
24
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.1
–0.1
–0.1
–0.1
–40
MAX
30
UNIT
DRVH1, DRVH2
VBST1 - SW1, VBST2 - SW2
5.5
5.5
0.1
85
VO
Output voltage
V
DRVL1, DRVL2, VREG5, SS1, SS2
PGND1, PGND2
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
–40
125
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, VREG5 tied
to V5FILT, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V,
IIN
VIN supply current
450
30
800
60
mA
mA
%
SW1 = SW2 = 0.5 V
VIN current, TA = 25°C,
no load , EN1 = EN2 = 0 V,
VREG5 = ON
IVINSDN
VIN shutdown current
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG
Bandgap initial regulation accuracy
TA = 25°C
–1
1
TA = 25°C, SWinj = OFF
755
765
775
TA = 0°C to 70°C,
SWinj = OFF(1)
753.5
776.5
778
VVFBTHx
VFBx threshold voltage
mV
TA = -40°C to 85°C,
752
(1)
SWinj = OFF
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
–100
–10
40
100
80
nA
RDischg
VO discharge resistance
ENx = 0 V, VOx = 0.5 V, TA = 25°C
Ω
VREG5 OUTPUT
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VVREG5
VREG5 output voltage
4.8
5.0
5.2
V
VLN5
VLD5
Line regulation
Load regulation
5.5 V < VIN < 24 V, IVREG5 = 10 mA
1 mA < IVREG5 < 10 mA
20
40
mV
mV
VIN = 5.5 V, VREG5 = 4.0 V,
TA = 25°C
IVREG5
Output current
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVHx = –100 mA
Sink, IDRVHx = 100 mA
Source, IDRVLx = –100 mA
Sink, IDRVLx = 100 mA
5.5
2.5
4
11
5
RDRVH
RDRVL
TD
DRVH resistance
DRVL resistance
Dead time
Ω
Ω
8
2
4
DRVHx-low to DRVLx-on
DRVLx-low to DRVHx-on
20
20
50
40
80
80
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
0.7
0.8
0.1
0.9
1
V
VBSTx = 29 V, SWx = 24 V,
TA = 25°C
IVBSTLK
VBST leakage current
mA
ON-TIME TIMER CONTROL
TON1L
TON2L
CH1 on time
CH2 on time
SW1 = 12 V, VO1 = 1.8 V
SW2 = 12 V, VO2 = 1.8 V
490
390
ns
ns
(1) Not production tested - ensured by design.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW1 = 0.7 V, TA = 25°C,
VFB1 = 0.7 V
TOFF1L
TOFF2L
CH1 min off time
285
ns
SW2 = 0.7 V, TA = 25°C,
VFB2 = 0.7 V
CH2 min off time
285
ns
SOFT START
ISSC
SS1/SS2 charge current
VSS1/VSS2 = 0 V, TA = 25°C
On the basis of 25°C(1)
VSS1/VSS2 = 0.5 V
–1.5
–4
–2
–2.5
3
mA
nA/°C
mA
TCISSC
ISSD
ISSC temperature coefficient
SS1/SS2 discharge current
100
150
UVLO
Wake up
3.7
0.2
4.0
0.3
4.3
0.4
VUV5VFILT
V5FILT UVLO threshold
V
Hysteresis
LOGIC THRESHOLD
VENH
VENL
ENx high-level input voltage
ENx low-level input voltage
EN 1/2
EN 1/2
2.0
V
V
0.3
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
On the basis of 25°C
8.5
10
11.5
mA
TCITRIP
ITRIP temperature coefficient
OCP compensation offset
4000
ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
0
15
VOCLoff
mV
mV
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
–20
30
20
VRtrip
Current limit threshold setting range VTRIPx-GND voltage
300
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
Output OVP prop delay
OVP detect
110
65
115
1.5
70
120
75
%
TOVPDEL
ms
UVP detect
VUVP
Output UVP trip threshold
%
Hysteresis (recover < 20 ms)
10
TUVPDEL
TUVPEN
Output UVP delay
17
30
40
ms
Output UVP enable delay
UVP enable delay / soft-start time
x1.4
x1.7
x2.0
ms
THERMAL SHUTDOWN
(2)
Shutdown temperature
150
20
TSDN
Thermal shutdown threshold
°C
(2)
Hysteresis
(2) Not production tested - ensured by design.
TERMINAL FUNCTIONS
PIN Fucntion Table
TERMINAL
I/O
DESCRIPTION
QFN
24
TSSOP
24
NAME
Supply input for high-side NFET driver. Bypass to SWx with a high-quality
0.1-mF ceramic capacitor. An external schottky diode can be added from
VREG5 if forward drop is critical to drive the high-side FET.
VBST1,
VBST2
23, 8
2, 11
I
EN1, EN2
VO1, VO2
24, 7
1, 6
3, 10
4, 9
I
I
Enable. Pull High to enable SMPS.
Output voltage inputs for on-time adjustment and output discharge. Connect
directly to the output voltage.
VFB1,
VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
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PIN Fucntion Table (continued)
TERMINAL
I/O
DESCRIPTION
QFN
24
TSSOP
24
NAME
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
point.
GND
3
6
I
DRVH1,
DRVH2
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
switch between SWx (OFF) and VBSTx (ON).
22, 9
21, 10
20, 11
1, 12
24, 13
23, 14
O
Switch node connections for both the high-side drivers and the over current
comparators.
SW1, SW2
I/O
O
DRVL1,
DRVL2
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
switch between PGNDx (OFF) and VREG5 (ON).
Power ground connections for both the low-side drivers and the over current
comparators. Connect PGND1, PGND2 and GND strongly together near the
IC.
PGND1,
PGND2
19, 12
22, 15
I/O
TRIP1,
TRIP2
Over current threshold programming pin. Connect to GND with a resistor to
GND to set threshold for low-side RDS(ON) current limit.
18, 13
17
21, 16
20
I
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum
high-quality 0.1-mF ceramic capacitor.
VIN
5-V supply input for the entire control circuitry except the MOSFET drivers.
Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-Ω resistor.
V5FILT
15
18
I
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ω resistor.
VREG5
16
19
O
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
soft-start time.
SS1, SS2
4,14
7, 17
xxx
xxx
TSSOP PACKAGE
(TOP VIEW)
QFN PACKAGE
(TOP VIEW)
DRVH1
VBST1
EN1
1
SW1
24
23
2
DRVL1
3
22 PGND1
4
TRIP1
VIN
21
20
19
18
17
16
15
14
13
VO1
5
VFB1
GND
VO1
TRIP1
1
2
3
18
17
VREG5
6
VIN
VFB1
GND
V5FILT
SS2
7
SS1
VFB2
VO2
VREG5
V5FILT
SS2
16
8
TRIP2
PGND2
DRVL2
SW2
9
SS1
VFB2
VO2
4
5
15
14
13
10
11
12
EN2
VBST2
TRIP2
6
DRVH2
6
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FUNCTIONAL BLOCK DIAGRAM
SW1
SW2
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ERR
COMP
SWX
8
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DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS53128 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control.
Light-Load Condition
TPS53128 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of VOUT ripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy-load condition, the inductor
current is also reduced, and eventually comes to the point that its valley touches zero current, which is the
boundary between continuous conduction and discontinuous condition modes. The low-side MOSFET is turned
off when this zero inductor current is detected. As the load current is further decreased, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is kept the same as that in the heavy-load condition. In reverse, when
the output current increases from light load to heavy load, the switching frequency increases to the preset value
as the inductor current reaches the continuous conduction. The transition load point to the light load operation,
IOUT(LL) (i.e., threshold between continuous and discontinuous condition mode) can be calculated as follows.
1
VIN -Vox
=
´Vox
IOUT (LL)
2´ L´ fsw VIN
(1)
Where fSW is the PWM switching frequency.
Switching frequency versus output current in the light-load condition is a function of L, fSW, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given in Equation 1.
Drivers
Each channel of the TPS53128 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
PWM Frequency and Adaptive On-Time Control
TPS53128 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53128 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
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5-Volt Regulator
The TPS53128 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
Soft Start
The TPS53128 has a programmable soft-start . When the ENx pin becomes high, 2.0-mA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
Pre-Bias Support
The TPS53128 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53128 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the
pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
Output Discharge Control
TPS53128 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
Over Current Limit
TPS53128 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53128 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(VIN - VO)
VO
·
¾
VTRIP
=
IOCL
-
· RDS(ON)
( )
2 · L1 · fSW
VIN
(2)
(3)
VTRIP (mV)
RTRIP (kW) =
ITRIP (mA)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the
4000-ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON)
.
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53128 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
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Over/Under Voltage Protection
TPS53128 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 ms, TPS53128 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
UVLO Protection
TPS53128 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
Thermal Shutdown
The TPS53128 includes an over temperature protection shut-down feature. If the TPS53128 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
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TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT
VIN SHUTDOWN CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
60
50
40
30
20
10
0
700
600
500
400
300
200
100
VREG5=ON
0
-50
0
50
100
150
-50
0
50
100
150
TJ - Junction Temperature - °C
Figure 3.
Figure 4.
TRIP SOURCE CURRENT
vs
VREG5 VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
5.070
5.060
5.050
5.040
5.030
5.020
5.010
5.000
-50
0
50
100
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
VREG5 VOLTAGE
VFB1 VOLTAGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
5.500
5.300
5.100
4.900
4.700
4.500
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0
5
10
15
20
25
VIN - Input Voltage - V
0
5
10
15
20
25
VIN - Input Voltage - V
Figure 7.
Figure 8.
VFB2 VOLTAGE
vs
VFB1 VOLTAGE
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0
5
10
15
20
25
-50
0
50
100
150
VIN - Input Voltage - V
TJ - Junction Temperature - °C
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
VFB2 VOLTAGE
vs
JUNCTION TEMPERATURE
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
-50
0
50
100
150
TJ - Junction Temperature - °C
Figure 11.
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TYPICAL APPLICATION PERFORMANCE
SWITCHING FREQUENCY (IO1 = 3 A)
SWITCHING FREQUENCY (IO2 = 3 A)
vs
vs
INPUT VOLTAGE (CH1)
INPUT VOLTAGE (CH2)
500
500
400
300
200
100
0
400
300
200
100
0
VO2 = 1.05 V
VO1=1.8V
0
5
10
15
20
25
VIN - Input Voltage - V
0
5
10
15
20
25
VIN - Input Voltage - V
Figure 12.
Figure 13.
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
OUTPUT CURRENT (CH1)
OUTPUT CURRENT (CH2)
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
VO2=1.05V
VO1=1.8V
0
0
0.01
0.1
1
10
0.01
0.1
1
10
IO - Output Current - A
IO - Output Current - A
Figure 14.
Figure 15.
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OUTPUT VOLTAGE (VIN = 12 V)
vs
OUTPUT VOLTAGE (VIN = 12 V)
vs
OUTPUT CURRENT (CH1)
OUTPUT CURRENT (CH2)
1.880
1.870
1.860
1.850
1.840
1.830
1.820
1.810
1.800
1.790
1.780
1.770
1.760
0.001
1.100
1.090
1.080
1.070
1.060
1.050
1.040
1.030
1.020
1.010
1.000
VO1=1.8V
VO2=1.05V
0.001
0.01
0.1
1
10
0.01
0.1
1
10
IOUT - Output Current - A
IOUT - Output Current - A
Figure 16.
Figure 17.
OUTPUT VOLTAGE (VIN = 12 V)
vs
OUTPUT VOLTAGE (VIN = 12 V)
vs
INPUT VOLTAGE (CH1)
INPUT VOLTAGE (CH2)
1.100
1.090
1.080
1.070
1.060
1.050
1.040
1.030
1.020
1.010
1.000
1.880
1.870
1.860
1.850
1.840
1.830
1.820
1.810
1.800
1.790
1.780
1.770
1.760
0
VO2=1.05V
VO1=1.8V
5
10
15
20
25
0
5
10
15
20
25
VI - Input Voltage - V
VI - Input Voltage - V
Figure 18.
Figure 19.
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LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VO2=1.05V (50mV/div)
VO1=1.8V (50mV/div)
IOUT2 (2A/div)
IOUT1 (2A/div)
Figure 20.
Figure 21.
START-UP WAVEFORMS
START-UP WAVEFORMS
EN2 (5 V/div)
EN1 (5 V/div)
SS2 (0.2 V/div)
SS1 (0.2 V/div)
VO1 = 1.8 V (0.5 V/div)
VO2 = 1.05 V (0.5 V/div)
Figure 22.
Figure 23.
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1.8-V EFFICIENCY
vs
1.05-V EFFICIENCY
vs
OUTPUT CURRENT (CH1)
OUTPUT CURRENT (CH2)
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
VO1=1.8V
VO2=1.05V
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT - Output Current - A
IOUT - Output Current - A
Figure 24.
Figure 25.
1.8-V OUTPUT RIPPLE VOLTAGE
1.05-V OUTPUT RIPPLE VOLTAGE
VO2 (20mV/div)
VO1 (20mV/div)
VO1=1.8V
VO2=1.05V
Figure 26.
Figure 27.
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APPLICATION INFORMATION
1. Choose inductor.
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 4 can be used to calculate L1.
-Vo1
3´
-Vo1
(
)
(
)
´
V IN (max)
I L1(ripple)
V IN (max)
Io1´ fsw
Vo1
Vo1
L1=
´
=
´ fsw
V IN (max)
V IN (max)
(4)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)
current. The RMS and peak inductor current can be estimated as follows.
VIN(MAX) - VO1
L1 · fSW
Vo1
¾
VIN(MAX)
·
IL1(RIPPLE)
=
(5)
VTRIP
¾
RDS(ON)
IL1(PEAK)
=
+ IL1(RIPPLE)
(6)
(7)
2
2
O1 +
1
12
IL1(RMS)
=
(I
)
I
¾
L1(RIPPLE)
Note: The calculation above shall serve as a general reference. To further improve transient response, the
output inductance could be reduced further. This needs to be considered along with the selection of the
output capacitor.
2. Choose output capacitor.
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it
is recommended to use a ceramic output capacitor.
IL1(RIPPLE)
1
fSW
·
C1 =
C1 =
C1 =
¾
8 · VO1(RIPPLE)
(8)
(9)
2
I
· L1
D
load
2 · VO1 · DVOS
2
I
· L1
D
load
2 · K · DVUS
(10)
Where
Ton1
T 1 + Tmin(off)
K = (VIN - V
O1) ·
on
(11)
Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and
Equation 10. The capacitance for C1 should be greater than 66 mF.
Where
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
3. Choose input capacitor.
The TPS53128 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
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4. Choose bootstrap capacitor.
The TPS53128 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the
high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating
should be greater than 10 V.
5. Choose VREG5 and V5FILT capacitor.
The TPS53128 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF
high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A
minimum 1-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper
operation. Both of these capacitors’ voltage ratings should be greater than 10 V.
6. Choose output voltage divider resistors.
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is
recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use
Equation 12 or Equation 13 to calculate R1.
VO1
¾
) )
VIN
1
fSW
Vswinj = (VIN - VO1 · 0.5875) ·
¾
·
·
4975
(
(
(12)
(13)
V
O1
VFB(RIPPLE)
- 1
· R2
R1 =
V
+
swinj
( )
VFB +
2
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
7. Choose register setting for over current limit.
(VIN - VO)
VO
¾
VTRIP
=
·
IOCL
-
· RDS(ON)
(
RTRIP (kW) =
)
2 · L1 · fSW VIN
(14)
(15)
VTRIP (mV) - VOCLoff
ITRIP(min) (mA)
Where
RDS(ON) = Low side FET on-resistance
ITRIP(min) = TRIP pin source current (8.5 mA)
VOCL0ff = Minimum over current limit offset voltage (–20 mV)
IOCL = Over current limit
8. Choose soft start capacitor.
Soft start time equation is as follows.
TSS · ISSC
¾
VFB
CSS =
(16)
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LAYOUT SUGGESTIONS
•
Keep the input switching current loop as small as possible.
•
Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
•
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (FBx) of the device.
•
•
•
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS53128PW
TPS53128PWR
TPS53128RGER
TPS53128RGET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
24
24
24
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
Request Free Samples
Purchase Samples
RGE
RGE
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53128PWR
TPS53128RGER
TPS53128RGET
TSSOP
VQFN
VQFN
PW
RGE
RGE
24
24
24
2000
3000
250
330.0
330.0
180.0
16.4
12.4
12.4
6.95
4.25
4.25
8.3
1.6
8.0
8.0
8.0
16.0
12.0
12.0
Q1
Q2
Q2
4.25
4.25
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53128PWR
TPS53128RGER
TPS53128RGET
TSSOP
VQFN
VQFN
PW
RGE
RGE
24
24
24
2000
3000
250
346.0
346.0
190.5
346.0
346.0
212.7
33.0
29.0
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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