TPS53211RGTT [TI]
Single-Phase PWM Controller with Light-Load Efficiency Optimization; 单相PWM控制器，带有轻载效率优化
| 型号： | TPS53211RGTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single-Phase PWM Controller with Light-Load Efficiency Optimization |
| 文件： | 总21页 (文件大小：708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS53211
www.ti.com
SLUSAA9 –SEPTEMBER 2011
Single-Phase PWM Controller with Light-Load Efficiency Optimization
1
FEATURES
APPLICATIONS
•
•
•
•
1.5-V to 19-V Conversion Voltage Range
4.5-V to 14-V Supply Voltage Range
Voltage Mode Control
•
Server and Desktop Computer Subsystem
Power Supplies
•
•
•
DDR Memory and Termination Supply
Distributed Power Supply
General DC/DC Converter
Skip Mode at Light Load for Efficiency
Optimization
•
•
High Precision 0.5% Internal 0.8-V Reference
DESCRIPTION
TPS53211 is a single phase PWM controller with
integrated high-current drivers. It is used for 1.5 V up
to 19 V conversion voltage.
Adjustable Output Voltage from 0.8 V to
0.7×VIN
•
•
•
•
Internal Soft-Start
Supports Pre-biased Startup
Supports Soft-Stop
TPS53211 features
a skip mode solution that
optimizes the efficiency at light load condition without
compromising the output voltage ripple. The device
provides pre-biased startup, soft-stop, integrated
bootstrap switch, power good function, EN/Input
UVLO protection. It supports conversion voltages up
to 19 V, and output voltages adjustable from 0.8 V to
0.7×VIN.
Programmable Switching Frequency from
250 kHz to 1 MHz
•
•
•
•
•
•
•
Overcurrent Protection
Inductor DCR Sensing for Overcurrent
RDS(on) Sensing for Zero Current Detection
Overvoltage and Undervoltage Protection
Open Drain Power Good Indication
Internal Bootstrap Switch
The TPS53211 is available in the 3 mm × 3 mm,
16-pin, QFN package (Green RoHs compliant and Pb
free) and is specified from –40°C to 85°C.
Integrated High-Current Drivers Powered by
VCCDR
•
Small 3 mm x 3 mm, 16-Pin QFN Package
VIN
Power
Enable
7
Good
8
6
5
COMP EN PGOOD UGATE
9
FB
BOOT
PHASE
LGATE
VCCDR
4
VOUT
10 VSEN
11 FBG
12 CSN
3
2
1
TPS53211
CSP OSC VCC GND
13
14
15
16
PVCC
UDG-11173
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS53211
SLUSAA9 –SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
ORDERABLE
DEVICE NUMBER
MINIMUM
QUANTITY
TA
PACKAGE
PINS
OUTPUT SUPPLY
ECO PLAN
TPS53211RGTR
TPS53211RGTT
Tape and Reel
Mini Reel
3000
250
Plastic QFN
(RGT)
Green (RoHS and
no Pb/Br)
–40°C to 85°C
16
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNITS
VCC, EN
VCCDR
–0.3
–0.3
–0.3
–0.3
–5
15
7.7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
BOOT
dc
36
dc
7.7
BOOT to PHASE
transient < 200ns
dc
7.7
Input voltage range(2)
–3
26
PHASE
transient < 200ns
–5
30
FB, VSEN, OSC
CSP, CSN
UGATE
–0.3
–0.7
–0.7
–0.3
–0.3
–5
3.6
V
VCC > 6.8 V
VCC ≤ 6.8 V
5.3
V
VCC-1.5
36
dc
7.7
UGATE to PHASE,
LGATE
Output voltage
range(3)
transient < 200 ns
7.7
COMP
PGOOD
GND
–0.3
–0.3
–0.3
–0.3
3.6
15
0.3
Ground pins
FBG
0.3
Human Body Model (HBM)
1500
500
150
150
Electrostatic
discharge
V
Charged Device Model (CDM)
Storage junction temperature
Operating junction temperature
–55
–40
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
THERMAL INFORMATION
TPS53211
THERMAL METRIC(1)
QFN
16 PINS
51.3
85.4
20.1
1.3
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
19.4
6
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Copyright © 2011, Texas Instruments Incorporated
TPS53211
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SLUSAA9 –SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
TYP
MAX UNITS
VCC
14
EN
–0.1
4.5
VVCC+0.1
VCCDR
BOOT
7
34
dc
–0.1
–0.1
–3
dc
7
BOOT to PHASE
Input voltage range
transient < 200ns
dc
7
V
–1
24
PHASE
transient < 200ns
–3
28
FB, VSEN, OSC
CSP, CSN
UGATE
–0.1
–0.1
–0.1
–0.1
–0.1
–3
3.3
5
V
VCC > 6.8 V
VCC ≤ 6.8 V
V
V
VCC–2
34
dc
7
UGATE to PHASE, LGATE
Output voltage range
transient < 200 ns
7
COMP
–0.1
–0.1
–0.1
–0.1
–40
–40
3.3
12
V
PGOOD
GND
0.1
0.1
125
85
Ground pins
FBG
Junction temperature range, TJ
°C
°C
Operating free-air temperature, TA
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MAX UNIT
ELECTRICAL CHARACTERISTICS(1)
over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
INPUT SUPPLY
VVCC
VCC supply voltage
VCC POR threshold
VCC POR hysteresis
Standby current
Nominal input voltage range
Ramp up; EN =’HI’
4.5
4.1
12
V
V
VPOR
4.25
200
4.4
VPORHYS
ICC_STBY
RBoot
VCCDR POR hysteresis
EN pin is low. VVCC= 12 V
mV
µA
Ω
60
Rds(on) of the boot strap switch
10
DRIVER SUPPLY
VCCDR
VCCDR Supply voltage
Nominal input voltage range
Ramp up; EN =’HI’
4.5
7.0
V
V
VPORDR
VCCDR POR threshold
VCCDR POR hysteresis
Standby current
3.15
3.32
220
3.50
VPORHYSDR
ICCDR_STBY
REFERENCE
VVREF
VCCDR POR hysteresis
EN pin is low. VVCC = 12 V
mV
µA
100
VREF
Internal precision reference voltage
0.8
V
TOLVREF
VREF tolerance
Close loop trim. 0°C ≤ TJ ≤ 70°C
–0.5%
0.5%
ERROR AMPLIFIER
UGBW(2)
AOL(2)
IFB(int)
Unity gain bandwidth
14
80
MHz
dB
Open loop gain
FB Input leakage current
Output sinking and sourcing current
Slew rate
Sourced from FB pin
10
2.5
5
nA
IEA(max)
SR(2)
mA
V/µs
ENABLE
VENH
EN logic high
EN logic low
EN pin current
2.2
V
VENL
600
12
mV
µA
IEN
SOFT START
tSS_delay
tPGDELAY
RAMP
Delay after EN asserting
PGOOD startup delay time
EN = ‘HI’ to “switching enabled”
1024/fSW
1560/fSW
ms
ms
PG delay after soft-start begins
Ramp amplitude
4.5V < VVCC < 12 V
2
V
PWM
(2)
tMIN(on)
Minimum ON time
40
ns
(2)
DMAX
Maximum duty cycle
fSW = 1 MHz
70%
SWITCHING FREQUENCY
fSW(typ)
fSW(min)
fSW(max)
fSW(tol)
Typical switching frequency
ROSC = 61.9 kΩ
ROSC = 250 kΩ
ROSC = 14 kΩ
360
400
250
1
440 kHz
kHz
Minumum switching frequency
Maximum switching frequency
Switching frequency tolerance
MHz
ROSC > 12.4 kΩ
–20%
20%
OVERCURRENT
CSP-CSN threshold for DCR
sensing
VOC_TH
TA = 25°C
17
20
23
mV
(1) See PS pin description for levels.
(2) Ensured by design. Not production tested.
4
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SLUSAA9 –SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS(1) (continued)
over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GATE DRIVERS
(3)
RHDHI
High-side driver sourcing resistance (VBOOT – VPH) forced to 5 V, high state
High-side driver sinking resistance (VBOOT – VPH) forced to 5 V, low state
Low-side driver sourcing resistance (VCCDR– GND) = 5 V, high state
1
0.5
Ω
Ω
Ω
Ω
RHDLO
RLDHI
0.7
RLDLO
Low-side driver sinking resistance
VCCDR– GND = 5 V, low state
0.33
POWER GOOD
VPGDL
PG lower threshold
PG upper threshold
PG hysteresis
Measured at VSEN w/r/t VREF
Measured at VSEN w//rt VREF
Measured at VSEN w/r/t VREF
87%
113%
3.5%
89%
VPGDU
110%
116%
VPGHYS
Time from VSEN out of +12.5% of VREF to
PG low
tOVPGDLY
tUVPGDLY
VINMINPG
PG delay time at OVP
PG delay time at UVP
2.3
2.3
1
µs
µs
V
Time from VSEN out of –12.5% of VREF to
PG low
Minimum VCC voltage for valid PG at Measured at VVCC with 1 mA (or 2 mA) sink
startup.
current on PG pin at startup.
VPGPD
IPGLK
PG pull-down voltage
PG leakage current
Pull down voltage with 4 mA sink current
Hi-Z leakage current, apply 6.5 V in off state
0.2
12
0.4
V
7.8
16.2
µA
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
VOVth
VUVth
OVP threshold
UVP threshold
Measured at the VSEN wrt. VREF.
Measured at the VSEN wrt. VREF.
110%
113%
87%
116%
89%
Time from VSEN out of +12.5% of VREF to
OVP fault
tOVPDLY
OVP delay time
UVP delay time
2.3
80
µs
µs
Time from VSEN out of –12.5% of VREF to
UVP fault
(3)
tUVPDLY
THERMAL SHUTDOWN
THSD(3)
Thermal shutdown
Latch off controller, attempt soft-stop
130
140
40
150
°C
°C
Controller starts again after temperature has
dropped
(3)
THSDHYS
Thermal shutdown hysteresis
(3) Ensured by design. Not production tested.
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DEVICE INFORMATION
TPS53211
16 PINS
(TOP VIEW)
16
15
14
13
1
2
3
4
12
11
10
9
VCCDR
LGATE
PHASE
BOOT
CSN
FBG
VSEN
FB
TPS53211
5
6
7
8
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
BOOT
COMP
CSN
NO.
4
I
O
I
Supply input for high-side drive (boot strap pin). Connect capacitor from this pin to SW pin
8
Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
Current sense negative input.
12
13
7
CSP
I
Current sense positive input
EN
I
Enable.
FB
9
I
Voltage feedback. Use for OVP, UVP and PGD determination.
Feedback ground for output voltage sense.
Logic ground and low-side gate drive return.
Output inductor connection to integrated power devices.
Low-side gate drive output.
FBG
11
16
3
G
G
O
O
O
O
O
I
GND
PHASE
LGATE
OSC
2
14
6
Frequency programming input.
PGOOD
UGATE
VCC
Power good output flag. Open drain output. Pull up to an external rail via a resistor.
High-side gate drive output.
5
15
1
Supply input for analog control circuitry.
Bias voltage for integrated drivers.
VCCDR
VSEN
I/O
I
10
Output voltage sense
6
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FUNCTIONAL BLOCK DIAGRAM
VCCDR
VSEN
LDO
VCCDR UVLO
+
FBG
BOOT
UV
OV
+
+
0.8 V x 87%
UV
OV
UV/OV
0.8 V
Threshold
Control
Logic
HDRV
UGATE
PHASE
Generation
0.8 V x 113%
XCON
FB
PWM
+
PWM
+
LL One-Shot
Overtemp
COMP
E/A
0.8 V
Ramp
LDRV
LGATE
GND
+
VOUT Discharge
SS
VCC
UVLO
OCP Logic
Enable
Control
VCC
OSC
OSC
TPS53211
EN
CSP
CSN
PGOOD
UDG-11172
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TYPICAL CHARACTERISTICS
5
4
3
2
1
0
430
420
410
400
390
380
370
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
G000
G000
Figure 1. VCC Current vs. Junction Temperature
Figure 2. Switching Frequency vs. Junction Temperature
10
120
115
110
105
Measured at VSEN w/r/t VREF
9
8
7
6
5
4
3
2
1
0
Lower Threshold
Upper Threshold
100
95
90
85
80
PGOOD Lower Hysteresis
PGOOD Upper Hysteresis
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
G000
G000
Figure 3. Power Good Hysteresis vs. Junction
Temperature
Figure 4. Power Good Threshold vs. Junction
Temperature
8
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DETAILED DESCRIPTION
Introduction
The TPS53211 is a single-channel synchronous buck controller with integrated high-current drivers. The
TPS53211 is used for 1.5 V up to 19 V conversion voltage, and provides output voltage from 0.8 V to 0.7 VIN. It
operates with programmable switching frequency ranging from 250 kHz to 1 MHz.
This device employs a skip mode solution that optimizes the efficiency at light-load condition without
compromising the output voltage ripple. The device provides pre-bias startup, integrated bootstrap switch, power
good function, EN/Input UVLO protection. The TPS53211 is available in the 3 mm by 3mm 16-pin QFN package
and is specified from –40°C to 85°C.
Switching Frequency Setting
The clock frequency is programmed by the value of the resistor connected from the OSC pin to ground. The
switching frequency is programmable from 250 kHz to 1 MHz. The relation between the frequency and the OSC
resistance is given by Equation 1.
106
fSW = 200 +
R
(
´ 78.5 +150
)
OSC
where
•
ROSC is the resistor connected from the OSC pin to ground in kΩ
•
fSW is the desired switching frequency in kHz
(1)
Soft-Start Function
The soft-start function reduces the inrush current during the start-up. A slow rising reference voltage is generated
by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than
800 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 800 mV, a
fixed 800 mV reference voltage is utilized for the error amplifier. The soft-start function is implemented only when
VCC and VCCDR are above the respective UVLO thresholds and the EN pin is released.
When the soft-start begins, the device initially waits for 1024 clock cycles and then starts to ramp up the
reference. After the reference voltage begins to rise, the PGOOD signal goes high after a 1560 clock-cycle delay.
UVLO Function
The TPS53211 provides UVLO protection for the input supply (VCC) and driver supply (VCCDR). If the supply
voltage is lower than UVLO threshold voltage minus the hysteresis, the device shuts off. When the voltage rises
above the threshold voltage, the device restarts. The typical UVLO rising threshold is 4.25 V for VCC and 3.32 V
for VCCDR. Hysteresis of 200 mV for VCC and 220 mV for VCCDR are also provided to prevent glitch.
Overcurrent Protection
The TPS53211 continuously monitors the current flowing through the inductor. The inductor DCR current sense
is implemented by comparing and monitoring the difference between the CSP and CSN pins. DCR current
sensing requires time constant matching between the inductor and the sensing network:
L
= R´ C
DCR
(2)
TPS53211 has two level OC thresholds: 20 mV and 30 mV for the voltage between the CSP and CSN pins.
If the voltage between the CSP and CSN pins exceeds the 20 mV current limit threshold, an OC counter starts to
increment to count the occurrence of the overcurrent events. The converter shuts down immediately when the
OC counter reaches four (4). The OC counter resets if the detected current is lower than the OC threshold after
an OC event. Normal operation can only be restored by cycling the VCC voltage.
If the voltage between the CSP and CSN pins is higher than 30 mV, the device latches off immediately. Normal
operation can be restored only by cycling the VCC voltage.
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The TPS53211 has thermal compensation to adjust the OCP threshold in order to reduce the influence of
inductor DCR variation due to temperature change. The OCP level has a change rate of 0.35%/°C.
Overvoltage and Undervoltage Protection
The TPS53211 monitors the VSEN pin voltage to detect the overvoltage and undervoltage conditions. A resistor
divider with the same ratio as on the FB input is recommended for the VSEN input. The overvoltage and
undervoltage thresholds are set to ±13% of VOUT
.
When the VSEN voltage is greater than 113% of the reference, the overvoltage protection is activated. The
high-side MOSFET turns off and the low-side MOSFET turns on. Normal operation can be restored only by
cycling the VCC pin voltage.
When the VSEN voltage is lower than 87% of the reference voltage, the undervoltage protection is triggered and
the PGOOD signal goes low. After 80 µs, the controller is latched off with both the upper and lower MOSFETs
turned off.
After both the undervoltage and overvoltage events, the device is latched off. Normal operation can be restored
only by cycling the VCC pin voltage.
Power Good
The TPS53211 monitors the output voltage through the VSEN. During start up, the power good signal delay after
the reference begins to rise is 1560 clock cycles. After this delay, if the output voltage is within ±9.5% of the
target value, PGOOD signal goes high.
At steady state, if the VSEN voltage is within 113% and 87% of the reference voltage, the power good signal
remains high. If VSEN voltage is outside of this limit, PGOOD pin is pulled low by the internal open drain output.
The PGOOD output is an open drain and requires an external pull-up resistor.
Over-Temperature Protection
The TPS53211 continuously monitors the die temperature. If the die temperature exceeds the threshold value
(140˚C typical), the device shuts off. When the device temperature lowers to 40˚C below the over-temperature
threshold, it restarts and return to normal operation.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for a single output synchronous
buck converter using TPS53211. The schematic of a design example is shown in Figure 5. The specifications of
the converter are listed in Table 1.
Table 1. Specification of the Single Output Synchronous Buck Converter
PARAMETER
Input voltage
Output voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
V
VIN
10.8
12
1.05
13.2
VOUT
V
VRIPPLE Output ripple
IOUT = 20 A
1% of VOUT
20
V
IOUT
fSW
Output current
A
Switching frequency
400
kHz
VIN
Power
Good
Enable
7
8
6
5
COMP EN PGOOD UGATE
9
FB
BOOT
PHASE
LGATE
VCCDR
4
3
2
1
VOUT
10 VSEN
11 FBG
12 CSN
TPS53211
CSP OSC VCC GND
13
14
15
16
PVCC
UDG-11173
Figure 5. Typical 12-V Input Application Circuit
Output Inductor Selection
Determine an inductance value that yields a ripple current of approximately 20% to 40% of maximum output
current. The inductor ripple current is determined by Equation 3:
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
L ripple
(
)
L ´ f
SW
(3)
The inductor requires a low DCR to achieve good efficiency, as well as enough room above peak inductor
current before saturation.
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Output Capacitor Selection
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has three components:
V
= V
+ V
+ V
RIPPLE
RIPPLE(C)
RIPPLE(ESR) RIPPLE(ESL)
(4)
I
8´ C
= I
L(ripple)
V
=
RIPPLE(C)
´ f
OUT
SW
(5)
(6)
V
´ESR
RIPPLE(ESR)
L(ripple)
V
IN ´ESL
VRIPPLE(ESL)
=
L
(7)
When a ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple
output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in
parallel.
When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also
varies with load current and can be expressed as shown in Equation 8.
2
a ´I
-IOUT
(
)
2´ fSW ´ COUT ´IL(ripple)
L(ripple)
VRIPPLE(DCM)
=
where
tON dcm
(
)
)
a =
tON ccm
(
•
α is the DCM On-Time coefficient and can be expressed as
(8)
I
L
V
OUT
a x I
L(ripple)
V
RIPPLE
I
OUT
t1
a x T
UDG-11174
Figure 6. DCM VOUT Ripple Calculation
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Input Capacitor Selection
The selection of input capacitor should be determined by the ripple current requirement. The ripple current
generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS
ripple current from the converter can be expressed as:
I
= I
´ D´ 1- D
(
)
OUT
IN ripple
(
)
where
V
OUT
D =
V
IN
•
D is the duty cycle and can be expressed as
(9)
To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be
placed close to the device. The ceramic capacitor is recommended due to the inherent low ESR and low ESL.
The input voltage ripple can be calculated as below when the total input capacitance is determined:
I
´D
OUT
V
=
IN ripple
(
)
f
´ C
IN
SW
(10)
Output Voltage Setting Resistors Selection
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 7. R1 is connected
between FB pin and the output, and R2 is connected between the FB pin and FBG. The recommended value for
R1 is between 1 kΩ and 5 kΩ. Determine R2 using Equation 11.
æ
ç
ç
è
ö
÷
÷
ø
0.8
- 0.8
R1=
´R1
V
(
)
OUT
(11)
Compensation Design
The TPS53211 employs voltage mode control. To effectively compensation the power stage and ensures fast
transient response, Type III compensation is typically used.
The control to output transfer function can be described in Equation 12.
1+ s´ C
´ESR
OUT
G
= 4´
CO
æ
ç
è
ö
L
2
1+ s´
+ C
´(ESR + DCR) + s ´L ´C
÷
OUT OUT
DCR + R
LOAD
ø
(12)
The output LC filter introduces a double pole, calculated in Equation 13.
1
f
=
DP
2´ p´ L ´ C
OUT
(13)
(14)
The ESR zero of can be calculated calculated in Equation 14
1
f
=
ESR
2´ p´ESR´ C
OUT
Copyright © 2011, Texas Instruments Incorporated
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13
TPS53211
SLUSAA9 –SEPTEMBER 2011
www.ti.com
Figure 7 shows the configuration of Type III compensation and typical pole and zero locations. Equation 15
through Equation 17 describe the compensator transfer function and poles and zeros of the Type III network.
1+ s´C ´(R + R ) 1+ s´R ´C
2
(
)(
)
1
1
3
4
GEA
=
æ
ç
è
ö
÷
ø
C2 ´ C3
C2 + C3
s´R ´(C + C ) ´ 1+ s´C ´R ´ 1+ s´R
(
) (
)
1
2
3
1
3
4
(15)
(16)
(17)
1
f
=
Z1
2´ p´R ´ C
4
2
1
1
f
=
@
Z2
2´ p´(R + R )´ C
2´ p´R ´ C
1 1
1
3
1
C3
C1
C2
R4
R1
R3
COMP
VREF
+
R2
UGD-11176
f
Z1
f
Z2
f
f
P3
P2
Frequency
UDG-11175
Figure 7. Type III Compensation Network
Configuration
Figure 8. Type III Compensation Network
Waveform
f
= 0
P1
(18)
(19)
1
f
=
P2
2´ p´R ´ C
3
1
1
1
f
=
@
P3
2´ p´R ´ C
æ
ç
è
ö
÷
ø
C ´ C
4
3
2
3
2´ p´R ´
4
C + C
2
3
(20)
The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One
pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to
attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a
compromise between high phase margin and fast response. A phase margin higher than 45 degrees is required
for stable operation.
14
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Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS53211RGTR
TPS53211RGTT
ACTIVE
ACTIVE
QFN
QFN
RGT
RGT
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53211RGTR
TPS53211RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53211RGTR
TPS53211RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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