TPS53624RHAR [TI]
具有 8 位 VID 的两相 D-CAP 双路降压稳压器 | RHA | 40 | -40 to 125;型号: | TPS53624RHAR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 8 位 VID 的两相 D-CAP 双路降压稳压器 | RHA | 40 | -40 to 125 稳压器 |
文件: | 总47页 (文件大小:2002K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
双相位, D-CAP+™, Eco-mode™ 降压控制器,此控制器具有 8 位数模
转换器 (DAC)
查询样品: TPS53624
1
特性
说明
2
•
可选双相位或单相位
TPS53624 是一款具有集成栅极驱动器的双相位降压
控制器。 PCNT 引脚在双相位或单相位模式中启用运
行来根据负载要求优化效率。 先进的控制特性包括诸
如 D-CAP+™ 架构和 OSR 等使用低输出电容提供快
速瞬态响应的特性。 DAC 支持快速电压识别 (VID
OTF) 来优化传送给处于运行状态的系统的输出电压以
减少静态功耗。 TPS53624 的自动跳跃特性优化了单
相位运行中的轻负载效率。 系统管理特性包括可调热
监控输入和输出 (THRM,THAL),输出电流监控
(IMON),以及互补电源正常信号(PG和 PGD)。 提
供了输出电压转换率和电压配置的可调节控制。 此
外,TPS53624 包括 2 个高电流场效应晶体管 (FET)
栅极驱动器来以极高的速度和低开关损耗驱动高侧和低
侧 N 通道 FET。 所有逻辑输入和输出引脚具有灵活的
LV 输入和输出阀值,此阀值能够在 1V 至 3.6V 的逻
辑电压范围内启用接口。
•
•
•
•
最小外部部件数量
8 位 DAC 支持广泛应用
轻负载与重负载下已优化的效率
已获专利的输出过冲减少 (OSR)
减少了输出电容
•
•
•
•
•
•
精确的、可调电压配置
可选 200,300,400 和 500kHz 频率
正在申请专利的 自动平衡相位均衡
可选 8 级电流限制
3V 至 28V 转换电压范围
具有集成型升压二极管的快速金属氧化物半导体场
效应晶体管 (MOSFET) 驱动器
•
•
集成过压保护 (OVP)
小型 6 x 6,40 引脚,四方扁平无引线封装 (QFN)
PowerPAD™ 封装
TPS53624 采用节省空间、耐热增强型、符合 RoHS
环保标准的 40 引脚 QFN 封装,额定运行稳定介于 -
10°C 至 105°C 之间。
应用范围
•
高电流、低压特定用途集成电路 (ASIC) 或微处理
器内核稳压器
XXX
订购信息(1)
TA
器件
编号
输出
电源
最少
订购数量
封装
引脚
TPS53624RHAT
TPS53624RHAR
250
-10°C 至 105°C
塑料四方扁平封装 (QFN)
40
卷带包装
2500
(1) 要获得最新的封装和订购信息,请参见本文档末尾的封装信息,或者浏览德州仪器 (TI) 的网站www.ti.com。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP+, Eco-mode, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLUSB66
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.)
VALUE
UNIT
MIN
–0.3
–0.3
MAX
36
VBST1, VBST2
VBST1to LL1. VBST2 to LL2
6
Input voltage range(2)
V
CSP1, CSN1, CSP2, CSN2, MODE, OSRSEL, PCNT, SLEW,
THRM, TRIPSEL, TONSEL, V5FILT, V5IN, VID0, VID1, VID2,
VID3, VID4, VID5, VID6, VID7, VFB, EN, THAL
–0.3
6
LL1, LL2
–5
30
36
6
DRVH1, DRVH2
–5
Output voltage range(2)
DRVH1, DRVH2 to LL1 or LL2
VREF, DROOP, DRVL1, DRVL2, IMON, PG, PGD
PGND, GFB
–0.3
–0.3
–0.3
–40
–55
V
6
0.3
125
150
Operating junction temperature, TJ
Storage junction temperature, Tstg
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
THERMAL METRIC(1)
RHA (40 PIN)
UNITS
θJA
Junction-to-ambient thermal resistance
32
10
θJB
Junction-to-board thermal resistance
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
3.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, all voltages wrt GND (unless otherwise noted)
MIN
3
TYP
MAX
28
UNIT
Conversion voltage (no pin assigned)
V5IN, V5FILT
Supply voltages
V
4.5
5.5
34
VBST1, VBST2
–0.1
–0.8
–0.8
Voltage range, conversion
pins
DRVH1, DRVH2
34
V
V
LL1, LL2
28
CSN1, CSN2, CSP1, CSP2, DROOP, DRVL1, DRVL2, IMON,
MODE, OSRSEL PG, PGD, SLEW, THRM, TONSEL, TRIPSEL,
VREF, VFB
Voltage range, 5-V pins
Voltage range, 3.3-V pins
–0.1
5.5
EN
–0.1
–0.1
3.6
1.3
0.1
V
V
Voltage range, VCCP I/O
pins
PCNT, VID0, VID1, VID2, VID3, VID4, VID5, VID6, VID7, THAL
Ground pins
PGND, GFB
–0.1
2
Human body model (HBM)
Charged device model (CDM)
Electrostatic Discharge
Protection (ESD)
kV
°C
1.5
–10
Operating free air temperature, TA
105
2
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VV5FILT = VV5IN = 5.0 V, GFB = PGND = GND, VVFB = VOUT (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY: CURRENTS, UVLO AND POWER-ON RESET
IV5
V5IN + V5FILT supply current
V5IN + V5FILT standby current
VDAC < VVFB < VDAC + 100 mV, EN = HI
EN = LO
2.3
4
1
mA
IV5STBY
μA
VV5FILT = VV5IN, VVFB < 200 mV, Ramp up;
VEN = HI; Switching begins
VUVLOH
VUVLOL
VPOR
V5FILT UVLO OK threshold
V5FILT UVLO fault threshold
V5FILT fault latch reset threshold
4.25
4
4.4
4.2
1.9
4.5
4.3
2.3
V
V
V
VV5FILT = VV5IN. Ramp down; VEN = HI, VVFB = 100 mV,
Restart if 5 V falls below VPOR then rises > VUVLOH is
toggled with 5 V > VUVLOH
VV5FILT = VV5IN, Ramp Down, EN = HI, Can restart if 5-V
goes up to VUVLOH and no other faults present
1.4
REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE
VVIDSTP
VDAC1
VID step size
Change VID0 HI to LO to HI
0.750 V ≤ VVFB ≤ 1.250 V
0.500 V ≤ VVFB ≤ 0.750 V
0.300V ≤ VVFB ≤ 0.500 V
1.250 V ≤ VVFB ≤ 1.6 V
4.5 V ≤ VV5FILT ≤ 5.5 V, IREF = 0
IREF = 0 μA to 250 μA
6.25
mV
VFB no load active
-1.35%
–11
1.35%
11
VDAC2
VFB no load active/sleep
VFB deeper sleep
mV
mV
VDAC3
–14
14
VDAC4
VFB above microcontroller VID
VREF output
–1.35%
1.665
–9
1.35%
1.750
VVREF
1.700
–3
V
mV
mV
V
VVREFSRC
VVREFSNK
VVBOOT
VREF output source
VREF output sink
IREF = –250 μA to 0 μA
Initial DAC boot voltage
10
35
Internal VFB initial boot voltage
0.99
1.00
1.01
VOLTAGE SENSE: VFB AND GNDSNS
Not in fault, disable or UVLO;
VVFB = 2 V, GFB = 0 V
IVFB
VFB input bias current
9
40
μA
IVFBDQ
VFB input bias current, discharge
GNDSNS input bias current
GNDSNS differential
Fault, disable or UVLO, VVFB = 100 mV
90
125
–8
175
μA
μA
mV
V/V
V
IGFB
Not in fault, disable or UVLO; VVFB = 2 V, GSNS = 0 V
–40
VDELGND
AGAINGND
VVFBCOM
±300
1.000
GNDSNS/GND gain
0.995
–0.3
1.011
2
VFB common mode input
CURRENT MONITOR
VIMONLK
VIMONLO
VIMINMID
VIMONHI
KIMON
Zero-level current output
ΣΔCS = 0 mV, RIMON = 12.7 kΩ
ΣΔCS = 10 mV, RIMON = 12.7 kΩ
ΣΔCS = 20 mV, RIMON = 12.7 kΩ
ΣΔCS = 40 mV, RIMON = 12.7 kΩ
0
202
460
958
5
250
500
1000
2
150
302
mV
mV
Low-level current output
Mid-level current output
High-level current output
Gain factor
538
mV
1058
mV
μA/mV
μA
IIMONSRC
VIMONSNK
Current monitor source
Current monitor clamp
ΣΔCS = 60 mV
108
130
ΣΔCS = 40 mV, RIMON = OPEN
1.02
1.11
V
Copyright © 2013, Texas Instruments Incorporated
3
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5FILT = VV5IN = 5.0 V, GFB = PGND = GND, VVFB = VOUT (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING
VTRIPSEL = GND, RSLEW to GND
VTRIPSEL = REF, RSLEW to GND
VTRIPSEL = 3.3 V, RSLEW to GND
8.2
11.4
14.5
19.3
24.0
30.2
38.1
48.9
12.5
15.8
19.2
25.5
32.1
40.5
51.9
64.9
13.5
16.8
20.3
25.3
30.5
37
VTRIPSEL = VV5FILT, RSLEW to GND
VTRIPSEL = GND, RSLEW to VREF
VTRIPSEL = REF, RSLEW to VREF
VTRIPSEL = 3.3 V, RSLEW to VREF
VTRIPSEL = VV5FILT, RSLEW to VREF
VTRIPSEL = GND, RSLEW to GND
VTRIPSEL = REF, RSLEW to GND
VTRIPSEL = 3.3 V, RSLEW to GND
VTRIPSEL = VV5FILT, RSLEW to GND
VTRIPSEL = GND, RSLEW to VREF
VTRIPSEL = REF, RSLEW to VREF
VTRIPSEL = 3.3 V, RSLEW to VREF
VTRIPSEL = VV5FILT, RSLEW to VREF
(CSP1–CSN1) – (CSP2–CSN2) at OCP for each channel
CSPx and CSNx
OCP voltage set
(valley current limit)
VOCPP
mV
45.5
57
17.7
21.5
25
31.5
38.3
46.7
58.5
71.8
Negative OCP voltage
(minimum magnitude)
VOCPN
mV
VOCPCC
ICS
gM-DROOP
IDROOP
Channel-to-channel OCP matching
CS pin input bias current
±1.0
0.2
mV
μA
μs
–1
482
50
1
522
150
Droop amplifier transconductance
Droop amplifier sink/source current
VVSNS = 1 V
500
100
μA
Droop amplifier clamp voltage
(negative)
VDCLAMPN
VDCLAMPP
IBAL_TOL
ACSINT
(VVREF – VDROOP
)
46
mV
V
Droop amplifier clamp voltage
(positive)
(VDROOP – VVREF
VDAC = 0.750 V;
)
1.2
Internal current share tolerance
Internal current sense gain
–3%
5.93
3%
VCSP1 – VCSN1 = VCSP2 – VCSN2 = VOCPP_MIN
Gain from CSPx – CSNx to PWM comparator
6.11
V/V
DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER
(VVBSTx – VLLx) = 5 V, HI state, (VVBST – VDRVH) = 0.1 V
1.2
0.8
2.2
2.2
17
2.5
2.5
RDRVH
DRVH on-resistance
Ω
A
(VVBSTx – VLLx) = 5 V, LO state, (VDRVH – VLL) = 0.1 V
VDRVHx = 2.5 V, (VVBSTx – VLLx) = 5 V, source
VDRVHx = 2.5 V, (VVBSTx – VLLx) = 5 V, sink
DRVHx 10% to 90% CDRVHx = 3 nF
DRVHx 90% to 10% CDRVHx = 3 nF
HI state, (VV5IN – VDRVL) = 0.1 V
IDRVH
DRVH sink/source current(1)
DRVH transition time
DRVL on-resistance
30
30
2
tDRVH
ns
Ω
13
0.9
0.4
2.7
8
RDRVL
LO state, (VDRVL – VPGND) = 0.1 V
VDRVLx = 2.5 V, source
1
IDRVL
DRVL sink/source current(1)
DRVL transition time
A
VDRVLx = 2.5 V, sink
DRVLx 90% to 10%, CDRVLx = 3 nF
DRVLx 10% to 90%, CDRVLx = 3 nF
LLx falls to 1V to DRVLx rises to 1 V
DRVLx falls to 1V to DRVHx rises to 1 V
VV5IN – VVBST, IF = 5 mA, TA = 25°C
VVBST = 34 V, VLL = 28 V
10
30
30
29
40
0.8
1
tDRVL
ns
ns
14
14
21
19
tNONOVLP
Driver non-overlap time
29
VFBST
IBSTLK
BST rectifier forward voltage
BST rectifier leakage current
0.6
0.7
0.1
V
μA
(1) Specified by design. Not production tested.
4
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5FILT = VV5IN = 5.0 V, GFB = PGND = GND, VVFB = VOUT (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERSHOOT REDUCTION (OSR) THRESHOLD SETTING
VOSRSEL = GND
78
111
151
106
140
186
OFF
20
135
174
224
VOSRSEL = REF
VOSRSEL = 3.3 V
VOSRSEL = V5FILT
All settings
VOSR
OSR voltage set
mV
mV
VOSRHYS
OSR voltage Hysteresis(2)
TIMERS: SLEW RATE, SLEW, ON-TIME AND I/O TIMING
ISLEW 1
ISLEW 2
RSLEW to GND current
RSLEW to VREF current
RSLEW = 125 kΩ from SLEW to GND
RSLEW = 45 kΩ from VREF to SLEW
9.9
9.5
10
10.2
10.8
μA
μA
10.2
ISLEW = |10 μA|, No Faults, Time from EN
to VSNS = VBOOT – 12%
tSTARTUP
VFB startup time
0.60
0.80
0.90
ms
SLSTRT
SR
VFB slew soft-start
VFB slew rate
ISLEW = |10 μA|, EN goes HI (soft-start)
ISLEW = |10 μA|
1.3
10
1.6
12.5
0.7
1.9 mV/μs
15 mV/μs
tPGDPO
PGD power-on delay time
Time from PG going low to PG going high
0.4
1
ms
Time from VFB out of +300 mV VDAC boundary to PGOOD
low
tPGDDGLTO
tPGDDGLTU
PGD deglitch time
PGD deglitch time
40
50
74
100
μs
Time from VFB out of –300 mV VDAC boundary to PGOOD
low
105
150
μs
VTON = GND, VLLx = 12 V, VVFB = 1 V
VTON = VREF, VLLx = 12 V, VVFB = 1 V
VTON = 3.3 V, VLLx = 12 V, VVFB = 1 V
VTON = VV5FILT, VLLx = 12 V, VVFB = 1
Fixed value
315
215
170
145
70
400
260
200
170
102
465
300
230
190
125
tTON
On-time control
ns
tMIN
Controller minimum OFF time
VID debounce time(2)
PCNT debounce Time(2)
VID change to VFB Change(2)
EN low to PGD low
ns
ns
ns
ns
ns
ns
ms
tVIDDBNC
tPSIDBNC
tVCCVID
tVRONPGD
tPGDVCC
tVRTDGLT
100
100
600
100
100
3
20
74
1
PGD low to VFB change(2)
THAL deglitch time
0.3
PROTECTION: OVP, PGOOD, VR, VR_TT FAULTS OFF AND INTERNAL THERMAL SHUTDOWN
VOVPH
VPGDH
Fixed OVP voltage
PGD high threshold
VFB > VOVPH for 1 μs, DRVL turns ON
1.6
1.8
V
Measured at the VFB pin wrt / VID code, device latches
OFF, begins soft-stop
180
258
mV
Measured at the VFB pin wrt / VID code, device latches off,
begins soft-stop
VPGDL
PGD low threshold
–367
–273
mV
VTHRM
ITHRM
Thermal shutdown voltage
THERM current
Measured at THERM; THAL goes LO
Measure ITHERM to GND
0.69
57.5
4.75
0.75
61
0.81
67.5
5
V
μA
V
VNOFLT
All faults OFF
THRM > V5FILT + VTH; not latched
4.9
Internal controller thermal
shutdown(2)
THINT
Latch off controller
160
°C
(2) Specified by design. Not production tested.
Copyright © 2013, Texas Instruments Incorporated
5
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5FILT = VV5IN = 5.0 V, GFB = PGND = GND, VVFB = VOUT (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC PINS: I/O VOLTAGE AND CURRENT
VVRTTL
IVRTTLK
VCLKPGL
ICLKPGLK
VVCCPH
VVCCPL
THAL pull-down voltage
THAL leakage current
PG, PG pull-down voltage
PG, PGOOD leakage current
I/O LV logic high
Pul- down voltage with 20-mA sink current
Hi-Z leakage current, Apply 5-V in off state
Pull-down voltage with 3-mA sink current
Hi-Z leakage current, Apply 5-V in off state
0.15
0.2
0.1
0.1
0.40
2
V
μA
V
–2
0.4
2
–2
μA
V
0.83
PCNT, EN, VID0, VID1, VID2, VID3, VID4, VID5, VID6,
VID7
I/O LV logic low
0.3
V
Leakage current, VVID = VPCNT = 1 V;
VEN = 0 V
IVCCPLK
I/O LV leakage
–1.00
0.01
10
1.00
μA
Leakage current, VVID = VPCNT = 1 V;
EN = 3.3 V
IVIDLK
IENH
I/O LV leakage
5
10
–3
15
25
1
μA
μA
μA
I/O 3.3-V leakage
Leakage current, VEN = 3.3 V
VVID0 = VVID1= VVID2= VVID3= VVID4= VVID5= VVID6= VVID7 = 0
V, VEN = 3.3 V
IVIDL
–1.5
1.5
ISELECT
ICTRL
IMODEL
IMODEH
VTRIPSEL = VOSRSEL = VTONSEL = 5 V
VPCNT = 0 V; VEN = 3.3 V
VMODE = 0 V
–2
–1
–5
10
5
1
μA
μA
μA
μA
5
VMODE = 5 V
40
6
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
DEVICE INFORMATION
RHA PACKAGE
40 PINS
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
MODE
GND
1
2
30
29
28
27
26
25
24
23
22
21
DRVH2
VBST2
LL2
CSP2
CSN2
CSN1
CSP1
GFB
3
4
DRVL2
V5IN
5
TPS53624
6
PGND
DRVL1
LL1
7
VFB
8
THRM
THAL
9
VBST1
DRVH1
10
11 12 13 14 15 16 17 18 19 20
Table 1. PIN FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
NO.
6
CSP1
I
I
I
I
Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR
sense R-C network.
CSP2
3
CSN1
5
Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR
sense RC network.
CSN2
4
Output of gM error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the
transient response.
DROOP
39
O
DRVH1
DRVH2
DRVL1
DRVL2
21
30
24
27
O
O
O
O
High-side N-channel MOSFET gate drive outputs.
Synchronous N-channel MOSFET gate drive outputs.
Controller enable. 3.3-V I/O level; 100-ns de-bounce. Logic high 3.3-V enables the controller. Logic low stops
the controller.
EN
35
2
I
—
I
GND
GFB
Return for analog circuits.
Voltage sense return tied directly to GND of the microprocessor. Tie to GND with a 100-Ω resistor to close
feedback when the microprocessor is not in the socket.
7
Current monitor output. VIMON = ΣVISENSE × K × RIMON. Reference RIMON to GNDSNS. Voltage is clamped at
1.1-V maximum.
IMON
11
O
LL1
23
28
1
I/O
I/O
—
High-side N-channel MOSFET gate drive return. Also, input for adaptive gate drive timing.
LL2
MODE
OSRSEL
Tie to GND to select CPU mode.
32
O
Overshoot reduction (OSR) setting. The OSR threshold can be selected or OSR can be disabled.
Negative active power good output; Open drain. Transitions low of approximately 50 ms after VOUT reaches
the VID level. Leave open if unused.
PG
34
O
Copyright © 2013, Texas Instruments Incorporated
7
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Table 1. PIN FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PGND
25
—
O
I
Synchronous N-channel MOSFET gate drive return.
Power good output; Open-drain. 6ms delay from voltage reaching the power good threshold. Leave open if
unused
PG
33
13
37
10
9
PCNT
SLEW
THAL
THRM
Single or dual phase control. 1-V I/O level. A low is single phase mode.
Precision current set-point for slew rate control. Tie the RSLEW resistor to GND for the low OCP range; tie
RSLEW to VREF for the high OCP range.
I
O
I/O
Thermal flag open drain output - active low. Fall time < 100ns with 56Ω pull-up to 1V. 1ms de-glitch filter.
Thermal sensor input. An internal, 60-μA current source flows into an NTC thermistor connected to GND.
The voltage threshold is 0.75 V. Also is a faults off input, (THERM = V5FILT) for debug mode.
On-time selection pin. The operating frequency can be set between 200 kHz and 500 kHz in 100 kHz steps.
Frequency can be changed during operation.
TONSEL
TRIPSEL
36
31
I
I
Overcurrent protection (OCP) setting. TRIPSEL is set with the RSLEW connection. The valley current limit at
the CS inputs can be selected in a range from approximately 10 mV to approximately 50 mV.
VBST1
VBST2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
22
29
20
19
18
17
16
15
14
12
I
I
High-side N-channel MOSFET bootstrap voltage inputs.
VID bits (MSB to LSB). 1-V I/O level; 100ns de-bounce
I
5-V power input for control circuitry. Has internal 3-Ω resistor to 5VIN; bypass to GND with a ≥1-µF ceramic
capacitor.
V5FILT
38
I
V5IN
26
40
I
5-V power input for drivers; bypass to PGND with ≥2.2 μF ceramic capacitor.
1.7-V, 250-μA voltage reference. Bypass to GND with a 0.22-μF ceramic capacitor.
VREF
O
Voltage sense line tied directly to VCORE of the microprocessor. Tie to VOUT with a 100-Ω resistor to close
feedback when the microprocessor is not in the socket.
VFB
8
I
Thermal Pad
Connect directly to system GND plane with multiple vias.
8
Copyright © 2013, Texas Instruments Incorporated
TPS53624
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ZHCSAY4 –MARCH 2013
FUNCTIONAL BLOCK DIAGRAM
DROOP
39
TONSEL
36
V5FILT
38
Differential Amplifier
26 V5IN
VFB
8
7
VFB
+
22 VBST1
21 DRVH1
E/A
CLK
CO
CO1
+
CMP PWM
On-Time
Generator
GNDSNS
+
De-MUX
Smart
Driver
LL
VREF 40
VID0 20
VID1 19
VID2 18
VID3 17
VID4 16
VID5 15
VID6 14
VID7 12
SLEW 37
23 LL1
ADDR
LL1
LL2
ILIM
MUX
24 DRVL1
ISHARE
25 PGND
DAC
DAC
29 VBST2
30 DRVH2
28 LL2
CO2
Smart
Driver
27 DRVL2
CSP1
CSN1
CSP2
CSN2
6
5
3
4
IS1
IS2
+
I AMP
+
?
+
Current
Sensing
Circuitry
ADDR
+
I AMP
IS2
IS1
Analog and Protection
Circuitry
Control Logic and Status
Circuitry
VFB
TPS53624
2
9
10 11 31 32
1
13 35 34 33
UDG-12126
Copyright © 2013, Texas Instruments Incorporated
9
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
APPLICATION DIAGRAMS
VREF
C1
C2
R2
VBAT
R1
C8
R3
0.1 mF
CSP2
C3
C4
40 39 38 37 36 35 34 33 32 31
RT2
VBAT
R5
C5
R6
Q4
1
MODE
DRVH2 30
L2
CSN2
C6
VCORE
2
3
4
5
6
7
8
GND
VBST2 29
LL2 28
VCORE
+
CSP2
CSN2
CSN1
CSP1
CSP2
CSN2
CSN1
CSP1
GNDSNS
VFB
C7
C8
Q3
V5
DRVL2 27
V5IN 26
PGND 25
DRVL1 24
LL1 23
U1
TPS53624RHA
R7
VSSSENSE
VCCSENSE
Q1
L1
C9
9
THERM
CSN1
Thermal Pad
VBST1 22
DRVH1 21
THAL
R9
10 THAL
RT1
Q2
R8
R10
C18
VBAT
R11
11 12 13 14 15 16 17 18 19 20
R12
CSP1
VBAT
C11
C10
UDG-12129
Figure 1. Inductor DCR Current Sense Application Diagram
10
Copyright © 2013, Texas Instruments Incorporated
TPS53624
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ZHCSAY4 –MARCH 2013
Application Circuit List of Materials
Recommended part numbers for key external components for the circuits in Figure 1 is listed in Table 2. These
components have passed applications tests.
Table 2. Key External Component Recommendations
FUNCTION
High-side MOSFET
MANUFACTURER
Infineon
COMPONENT NUMBER
BSC080N03MSG
Low-side MOSFET (x2)
Infineon
Panasonic
Tokin
BSC030N03MSG
ETQP4LR36AFC
Inductors
MPCG1040LR36
Toko
FDUE10140D-R36M
EEFLX0D331R4
Panasonic
Sanyo
Bulk Output Capacitors
2TPLF330M5
Kemet
T528Z337M2R5ATE005-6666
ECJ2FB0J106K
Panasonic
Murata
Ceramic Output Capacitors
NTC Thermistors
GRM21BR60J106KE19L
ERTJ1VV154J
Panasonic
Murata
NCP18XF151J03RB
Copyright © 2013, Texas Instruments Incorporated
11
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
DETAILED DESCRIPTION
FUNCTIONAL OVERVIEW
The TPS53624 is a D-CAP+™ mode adaptive on-time converter. The output voltage is set using a DAC that
outputs a reference in accordance with the 8-bit VID code defined in Table 5. VID-on-the-fly transitions are
supported with the slew rate controlled by a single resistor on the SLEW pin. Two powerful integrated drivers
support output currents in excess of 50 A. The converter enters single phase mode under PCNT control to
optimize light-load efficiency. Four switching frequency selections are provided in 100-kHz increments from 200
kHz to 500 kHz per phase to enable optimization of the power chain for the cost, size and efficiency
requirements of the design. (See Table 3)
Table 3. Frequency Selection Table
TONSEL VOLTAGE
FREQUENCY (kHz)
(VTONSEL) (V)
GND (0)
200
300
400
500
VREF (1.7)
3.3
5
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant on-
time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in the
TPS53624, the cycle begins when the current feedback reaches an error voltage level which is the amplified
difference between the DAC voltage and the feedback voltage.
This approach has two advantages:
1. The amplifier DC gain sets an accurate linear load-line; this is required for CPU core applications.
2. The error voltage input to the PWM comparator is filtered to improve the noise performance.
In a steady-state condition, the two phases of the TPS53624 switch 180° out-of-phase. The phase displacement
is maintained both by the architecture (which does not allow both hig-side gate drives to be on in any condition)
and the current ripple (which forces the pulses to be spaced equally). The controller forces current sharing
adjusting the on-time of each phase. Current balancing requires no user intervention, compensation, or extra
components.
Multi-Phase, PWM Operation
Referring to the Functional Block Diagram and , in dual-phase steady state, continuous conduction mode, the
converter operates as follows:
Starting with the condition that both high-side MOSFETs are off and both low-side MOSFETs are on, the
summed current feedback (VCMP) is higher than the error amplifier output (VDROOP). VCMP falls until it hits VDROOP
,
which contains a component of the output ripple voltage. The PWM comparator senses where the two
waveforms cross and triggers the on-time generator.
12
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TPS53624
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ZHCSAY4 –MARCH 2013
Summed Current Feedback
tON
t
V
V
CMP
DROOP
Time - ms
Figure 2. D-CAP+ Mode Basic Waveforms
The summed current feedback is an amplified and filtered version of the CSPx and CSNx inputs. The TPS53624
provides dual independent channels of current feedback to increase the system accuracy and reduce the
dependence of circuit performance on layout compared to an externally summed architecture.
PWM Frequency and Adaptive on Time Control
The on-time (at the LL node) is determined by Equation 1.
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
VOUT
1
tON
=
´
+ 30ns
V
fSEL
IN
where
•
f SEL is the frequency selected by the connection of the TONSEL pin
(1)
The on-time pulse is sent to the high-side MOSFET. The inductor current and summed current feedback rise to
their maximum value, and the multiplexer and de-multiplexer switch to the next phase. Each ON pulse is latched
to prevent double pulsing.
The current sharing circuitry compares the average values of the individual phase currents, then adds or
subtracts a small amount from each on-time in order to bring the phase currents into line. No user design is
required.
Accurate droop is provided by the finite gain of the droop amplifier. The calculation for output voltage droop,
VDROOP is shown in Equation 2.
RCS ´ ACS
´
åI(L)
VDROOP
=
RDROOP ´ GM
where
•
•
•
•
•
RCS is the effective current sense resistance, regardless if a sense resistor or inductor DCR is used
ACS is the gain of the current sense amplifier
ΣI(L) is the DC sum of inductor currents
RDROOP is the value of resistor from the DROOP pin to VREF
GM(droop) is the GM of the droop amplifier
(2)
13
Copyright © 2013, Texas Instruments Incorporated
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
The capacitor in parallel with RDROOP matches the slew rate of the DROOP pin with the current feedback signals
to prevent ring-back during transient load conditions.
R
LL ´ DIOUT ´ gM ´L
CDROOP
=
- 30pF
R
CS ´ ACS ´DMAX ´ V L
( )
where
•
•
•
•
RLL is load-line slope defined by proicessor mnufacturer
ΔIOUT is maximum dynamic load current for the processor
DMAX = tON / tON+tOFF(min)
V(L) is the voltage across the inductor (VBAT – VCORE).
(3)
The 30-pF term accounts for the slew rate limit of the amplifier without external capacitance.
AutoBalance Current Sharing
The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of
each phase to equalize the current in each phase. The block diagram is shown in Figure 3.
TPS53624
LL1 28
MUX
LL2 23
VDAC
R(tON
)
CSP1
CSN1
CSP2
CSN2
4
5
+
+
K ´ I1 - I2
(
+
I AMP
)
)
5 ms
Filter
–
+
PWM
–
MUX
+
6
–
K ´ I2 - I1
+
I AMP
(
5 ms
Filter
C(tON
)
7
UDG-12128
Figure 3. Current Sharing Block Diagram
Figure 3 also shows the TI D-CAP+™ constant on-time modulator. The PWM comparator (not shown) starts a
pulse when the feedback voltage meets the reference. This pulse turns on the gate of the high-side MOSFET.
After the MOSFET turns on, the LL voltage for that phase is driven up to the battery input. This charges C(tON
)
through R(tON). The pulse is terminated when the voltage at C(tON) matches the tON reference, normally the DAC
voltage (VDAC).
The circuit operates in the following fashion, using Figure 3 as the block diagram and to show the circuit action at
the level of an individual pulse (PWM1). First assume that the 5 µs averaged value of I1 = I2. In this case, the
PWM modulator terminates at VDAC, and the normal pulse width is delivered to the system. If instead, I1 > I2,
then an offset is subtracted from VDAC, and the pulse width for phase one is shortened, reducing the current in
phase one to compensate. If I1 < I2, then a longer pulse is produced, again compensating on a pulse-by-pulse
basis.
14
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TPS53624
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ZHCSAY4 –MARCH 2013
PWM (Low)
PWM (Nom)
PWM (High)
I1 < 12
V
DAC
I1 > 12
PWM1 Output Pulse
t - Time - ms
Figure 4.
Because the increase in pulse width is proportional to the difference between the actual phase current and the
ideal current, the system converges smoothly to equilibrium. Because the filtering is so much lighter than
conventional current sharing schemes, the settling time is very fast. Analysis shows the response to be single
pole with a bandwidth of approximately 60 kHz.
The speed advantage of the TPS53624 is beneficial because processors quickly move from full speed to idle and
back to save power when processing light and moderate loads. A multi-phase converter that takes milliseconds
to implement current sharing is never in equilibrium and thermal hot-spots can result. The TPS53624 allows rapid
dynamic current and output voltage changes while maintaining current balance.
Overshoot Reduction (OSR) Feature
The problem of overshoot in low duty-cycle synchronous buck converters results from the output inductor having
a small voltage (VCORE) with which to respond to a transient load release.
In Figure 5, a single phase converter is shown for simplicity. In an ideal converter, with the common values of 12-
V input and 1.2-V output, the inductor has 10.8 V (12 V – 1.2 V) to respond to a transient step, and 1.2 V to
respond once the load releases.
12 V
+
10.8V
–
+
1.2 V
L
–
1.2 V
C
UDG-07187
Figure 5. Synchronous Converter
Copyright © 2013, Texas Instruments Incorporated
15
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Figure 6 shows a two-phase converter. The energy in the inductor is transferred to the capacitance on the VCORE
node above and the output voltage (green trace) overshoots the desired level (lower cursor, also green). In this
case, the magnitude of the overshoot is approximately 40 mV. The LLx waveforms (yellow and blue traces)
remain flat during the overshoot, indicating the DRVLx signals are on.
The performance of the same dual phase circuit, but with OSR enabled is shown in Figure 7. In this case, the
low side FETs shut off when overshoot is detected and the energy in the inductor is partially dissipated by the
body diodes. The overshoot is reduced by 25 mV. The dips in the LLx waveforms show the DRVLx signals are
OFF only long enough to reduce the overshoot.
Figure 6. Circuit Performance Without Overshoot Figure 7. Transient Release Performance Improved
Reduction
with Overshoot Reduction
Implementation
OSR is implemented using a comparator between the DROOP and ISUM nodes. To implement OSR, simply
terminate the OSRSEL pin to the desired voltage to set the threshold voltage for the comparator. The settings
are:
•
•
•
•
GND = Minimum voltage (Maximum reduction)
VREF = Medium voltage
+3.3V = Maximum voltage
5V = OSR off
Use the highest setting that provides the desired level of overshoot reduction to eliminate the possibility of false
OSR operation.
Light Load Power Saving Features
The TPS53624 has several power saving features to provide excellent efficiency over a very large load range.
This feature is implemented with PCNT pin.. This pin is a VCCP I/O level. A LO on this pin puts the converter
into single phase mode, thus eliminating the quiescent power of phase two when high power is not needed.
In addition, the TPS53624 has an automatic pulse skipping skip mode. Regardless of the state of the logic
inputs, the converter senses negative inductor current flow and prevents it by shutting off the low-side
MOSFET(s). This saves power by eliminating recirculating current.
16
Copyright © 2013, Texas Instruments Incorporated
TPS53624
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ZHCSAY4 –MARCH 2013
MOSFET Drivers
The TPS53624 incorporates a pair of strong, high-performance gate drives with adaptive cross-conduction
protection. The driver uses the state of the DRVLx and LLx pins to be sure the high-side or low-side MOSFET is
off before turning the other on. Fast logic and high drive currents (up to 8 A typical!) quickly charge and
discharge MOSFET gates to minimize dead-time to increase efficiency. The high-side gate driver also includes
an internal P-N junction boost diode, decreasing the size and cost of the external circuitry. For maximum
efficiency, this diode can be bypassed externally by connecting Schottky diodes from V5IN (anode) to VBSTx
(cathode).
Voltage Slewing
The TPS53624 ramps the internal DAC up and down as the VID is changing. These timings are independent of
switching frequency, as well as output resistive and capacitive loading. The slew rate is set by a resistor from the
SLEW pin to AGND (RSLEW). RSLEW sets both the slew rate and the soft-start rate.
K
´ V
SLEW
SLEW
R
=
SLEW
SR
where
•
•
KSLEW = 1.25 × 109
VSLEW is equal to the slew reference VSLEWREFwhen RSLEW is tied to GND
(4)
Connecting RSLEW to VREF enables the high range of overcurrent protection and changes VSLEW in Equation 4 to
0.45 V (VREF – VSLEWREF). The soft-start rate is 1/8 the slew rate.
At start-up the VID code should be stable at the time EN goes high. For example, the VVID for IMVP6.5 is 1.1 V.
The soft-start time to VBOOT is shown in Equation 5.
1.1V ´8
t
=
s
( )
SS
SR
(5)
Protection Features
The TPS53624 features full protection of the converter power chain as well as the system electronics.
Input Undervoltage Protection (UVLO)
The TPS53624 continuously monitors the voltage on the V5FILT pin to ensure the value is high enough to bias
the devices properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts
with approximately 4.4 V and has a nominal 200 mV of hysteresis. This function is not latched, therefore
removing and restoring 5-V power to the device resets it. The power input (VIN) does not include a UVLO
function, so the circuit runs with power inputs down to approximately 3 × VCORE
.
Copyright © 2013, Texas Instruments Incorporated
17
TPS53624
ZHCSAY4 –MARCH 2013
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Power Good Signals
The TPS53624 has two open-drain powergood pins. PGD and PG have the following nominal thresholds:
•
•
High: VDAC + 200 mV
Low : VDAC – 300 mV
The differences are:
•
•
PG transitions active low shortly ( approxiimately 50 µs) after VOUT reaches the VID voltage on power-up.
PGD rises at the same time as PG reaches the power good threshold defined above. PGD is high when
power is good and low when power is not good.
Both power good signals go inactive when the EN pin is pulled low or an undervoltage condition on V5IN is
detected. Both are also masked during DAC transitions to prevent false triggering during voltage slewing.
Output Overvoltage Protection (OVP)
In addition to the power good function described above, the TPS53624 has additional OVP and UVP thresholds
and protection circuits.
An OVP condition is detected when VOUT is > 200 mV greater than VDAC. In this case, the converter sets PGD
signals inactive and then latches OFF. The converter remains in this state until the device is reset by cycling
either V5IN or EN
However, because of the dynamic nature of VR systems, the +200 mV OVP threshold is blanked much of the
time. In order to provide protection to the processor 100% of the time, there is a second OVP level fixed at 1.55
V which is always active. If the fixed OVP condition is detected, the PGD signals are forced inactive and the
DRVLx signals are driven HI. The converter remains in this state until either V5IN or EN are cycled.
Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described below. If VOUT drops
below the low PGD threshold for 80 μs, then the drivers are turned OFF until either V5IN or EN are cycled.
Current Protection
Two types of current protection are provided in the TPS53624.
•
•
Overcurrent protection (OCP)
Negative overcurrent protection
Overcurrent Protection (OCP)
The TPS53624 uses a valley current limiting scheme, so the ripple current must be considered. The DC current
value at OCP is the OCP limit value plus half of the ripple current. Current limiting occurs on a phase-by-phase
and pulse-by-pulse basis. If the voltage between CSPx and CSNx is above the OCP value (selected by
combination of TRIPSEL pin connection and RSLEW termination), the converter holds off the next ON pulse until it
drops below the OCP limit. For inductor current sensing circuits, the voltage between CSPx and CSNx is the
inductor DCR value multiplied by the resistor divider which is part of the NTC compensation network. As a result,
a wide range of OCP values can be obtained by changing the resistor divider value. In general, use the highest
TRIPSEL setting possible with the least attenuation in the resistor divider to provide as much signal to the device
as possible. This provides the best performance for all parameters related to current feedback.
In OCP mode, the voltage droops until the UVP limit is reached. Then, the converter sets the PGD pins inactive,
and the drivers are turned OFF. The converter remains in this state until the device is reset by the EN or the
V5IN pin.
18
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TPS53624
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ZHCSAY4 –MARCH 2013
Settings use both the TRIPSEL pin and the RSLEW termination. The eight possible OCP settings are shown in
Table 4. For the levels in mV for a specific setting, see the Electrical Characteristics table.
Table 4. TRIPSEL Settings
OCP
RSLEW Tied to GND
RSLEW Tied to VREF
TRIPSEL
GND
1
VREF
2
3.3V
3
5V
4
GND
5
VREF
6
3.3V
7
5V
8
Setting Level
Negative Overcurrent Protection
The negative OCP circuit acts when the converter is sinking current. The converter continues to act in a valley
mode, so to have a similar negative DC limit, the absolute value of the negative OCP set point is typically 50%
higher than the positive OCP set point.
Thermal Protection
Two types of thermal protection are provided in the TPS53624
•
•
Thermal flag open drain ouptut signal (THAL)
Thermal shutdown
Thermal Flag Open Drain Ouptut Signal THAL
The THAL signal is an Intel-defined open-drain signal that is used to protect the power chain. To use THAL,
place an NTC thermistor at the hottest area of the PC board and connect it to the THRM pin. THRM sources a
precise 60-μA current, and THAL goes LO when the voltage on THERM reaches 0.7 V. Therefore, the NTC
thermistor needs to be 11.7 kΩ at the trip level. A series or parallel resistor can be used to trim the resistance to
the desired value at the trip level.
THAL signal does not change the operation of TPS53624
Thermal Shutdown
The TPS53624 also has an internal temperature sensor. When the temperature reaches a nominal 160°C, the
device shuts down. The converter remains in this state until either V5IN or EN is cycled.
Current Monitor
The TPS53624 includes a power monitor function. The power monitor puts out an analog voltage proportional to
the output power on the IMON pin.
V
= ACS ´ GM
´
VCS = KIMON
´
VCS
IMON
IMON
å
å
where
•
•
KIMON is given in the Electrical Characteristics table
Σ VCS is the sum of the voltages at the inputs to the current sense amplifiers
(6)
Copyright © 2013, Texas Instruments Incorporated
19
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ZHCSAY4 –MARCH 2013
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Single-Phase Operation
The TPS53624 is a two-phase controller. This controller can also be configured for single-phase operation. There
are two ways the controller operates in single-phase mode.
•
PCNT = 0 V. In this case, the controller starts up as dual-phase but goes into single-phase after start-up is
completed. This mode is used for improving efficiency of a two-phase converter while operating under light
load conditions.
•
PCNT = 5 V. In this case, the controller operates in a complete single-phase mode. The drivers for Phase 2
are totally disabled in this mode.
In order to use the controller purely as a single-phase controller, connect PCNT to V5FILT. Also, the current
sense input pins of the second phase (CSN2, CSP2) must be grounded. All the other pins of the second phase
must be left open.
VID Table
The TPS53624 incorporates the 8-bit VID table shown in Table 5.
Table 5. VID Table (continued)
Table 5. VID Table
VID
VDAC
Hex
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VID
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VDAC
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
Hex
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
1
OFF
2
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
20
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
Table 5. VID Table (continued)
Table 5. VID Table (continued)
VID
4
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
VID
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VDAC
VDAC
Hex
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
3
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
0.49375
0.48750
0.48125
0.47500
0.46875
0.46250
0.45625
0.45000
Copyright © 2013, Texas Instruments Incorporated
21
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Table 5. VID Table (continued)
Table 5. VID Table (continued)
VID
4
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
VID
VDAC
VDAC
Hex
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
2
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
7
6
5
4
3
2
1
0
0.21250(1)
0.20625(1)
0.20000(1)
0.19375(1)
0.18750(1)
0.18125(1)
0.17500(1)
0.16875(1)
0.16250(1)
0.15625(1)
0.15000(1)
0.14375(1)
0.13750(1)
0.13125(1)
0.12500(1)
0.11875(1)
0.11250(1)
0.10625(1)
0.10000(1)
0.09375(1)
0.08750(1)
0.08125(1)
0.07500(1)
0.06875(1)
0.06250(1)
0.05625(1)
0.05000(1)
0.04375(1)
0.44375
0.43750
0.43125
0.42500
0.41875
0.41250
0.40625
0.40000
0.39375
0.38750
0.38125
0.37500
0.36875
0.36250
0.35625
0.35000
0.34375
0.33750
0.33125
0.32500
0.31875
0.31250
0.30625
0.30000
E0
1
1
1
0
0
0
0
0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.29375(1)
0.28750(1)
0.28125(1)
0.27500(1)
0.26875(1)
0.26250(1)
0.25625(1)
0.25000(1)
0.24375(1)
0.23750(1)
0.23125(1)
0.22500(1)
0.21875(1)
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0.03750(1)
0.03125(1)
OFF
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
OFF
(1) Device operating characteristics and tolerances below 0.3 V
are not specified.
22
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
APPLICATION INFORMATION
Design Procedure
The TPS53624 has the simplest design procedure of any IMVP6.5 CORE controller on the market.
Choosing Initial Parameters
Step One
Determine the processor specifications. For the purposes of this document, the Intel® Auburndale 45-V
Processor from Table 2 of the RS – Intel® IMVP-6.5 Mobile Processor and Mobile Chipset Voltage Regulation
Specification, Reference Number 24779, Revision 1.0 is used.
The processor requirements provide the following key parameters.
•
•
•
•
•
•
VHFM = 1.075 V
RIMVP = -1.9 mΩ
ICC(max) = 50 A
IDYN(max) = 35 A
ICC(tdc) = 37 A
Slew rate = 5 mV/μs (minimum)
The last requirement shows that the converter must support a 25% overcurrent for 10 μs without going out of
tolerance. The TPS53624 is designed to support the momentary OCP requirement internally, so only the DC
OCP limit needs to be considered when calculating OCP levels. This also means that the power-chain does not
have to be over-designed to meet Intel requirements.
Step Two
Determine system parameters.
The input voltage range and operating frequency are of primary interest.
For example
•
•
•
VIN(max) = 20 V
VIN(min) = 9 V
fSW = 300 kHz
Step Three
Determine current sensing method.
The TPS53624 supports both resistor sensing and inductor DCR sensing. Inductor DCR sensing is chosen.
For resistor sensing, substitute the resistor value (1 mΩ recommended for a 50-A application) for RCS in the
subsequent equations and skip Step Five.
Copyright © 2013, Texas Instruments Incorporated
23
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Step Four
Determine inductor value and choose inductor.
Smaller inductor values have better transient performance but higher ripple and lower efficiency. Higher values
have the opposite characteristics. It is common practice to limit the ripple current to between 30% and 50% of the
maximum current per phase. In this case, use 40%:
50A
I
=
´ 0.4 = 10A
P-P
2phases
(7)
At fSW = 300 kHz, with a 20-V input and a 1.075-V output.
V ´ dT
L =
I
P-P
where
V = V
(
- VHFM
)
IN(max)
•
æ
ö
V
HFM
ç
ç
è
÷
÷
dT =
f ´ V
(
)
IN(max)
ø
•
(8)
L=0.34 µH
An inductance value of 0.36 μH is chosen. Ensure that the inductor does not saturate during peak loading
conditions.
I
æ
ö
IP-P
CC(max)
ISAT
=
+
´1.2´1.25 = 45A
ç
÷
ç
÷
NPHASE
2
è
ø
(9)
The factor of 1.2 is included to allow for current sensing and current limiting tolerances. The factor of 1.25 is due
to Intel’s 25% momentary OCP requirement described above.
The chosen inductor should have the following characteristics:
•
As flat an inductance vs. current curve as possible. Inductor DCR sensing is based on the idea L/DCR is
approximately a constant through the current range of interest.
•
•
•
Either high saturation or soft saturation
Low DCR for improved efficiency, but at least 0.7 mΩ for proper signal levels.
DCR tolerance as low as possible for load-line accuracy.
For this application, a 0.36-μH, 1.0-mΩ inductor is chosen.
Step Five
Design the thermal compensation network.
In most designs, NTC thermistors are used to compensate thermal variations in the resistance of the inductor
winding. This winding is generally copper, and therefore has a resistance coefficient of 3900 PPM/°C. NTC
thermistors, however, have very non-linear characteristics and need two or three resistors to linearize them over
the range of interest. The typical DCR circuit is shown in Figure 8.
24
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
L
R
DCR
I
R
R
R
SEQU
NTC
SERIES
R
PAR
C
SENSE
CSP
CSN
UDG-07188
Figure 8. Typical DCR Sensing Circuit
In this circuit, good performance is obtained when:
L
= C
´R
EQ
SENSE
R
DCR
(10)
In Equation 10, all of the parameters are defined in Figure 8 except REQ, which is the series/parallel combination
of the other four discrete resistors. CSENSE should be a capacitor type which is stable over temperature. Use X7R
or better dielectric (C0G preferred).
Because calculating these values by hand is difficult, TI offers a spreadsheet using the Excel Solver function.
Contact your local TI representative to get a copy of the spreadsheet.
In the reference design, the following values are input to the spreadsheet:
•
•
•
•
•
L = 0.36 µH
RDCR = 1 mΩ
Load Line (typically -1.9 mΩ for SV processors)
Minimum overcurrent limit = 56 A
Thermistor R25 and “B” value = 4700 kΩ
The spreadsheet then calculates the TRIPSEL setting and the values of:
•
•
•
•
RSEQU
RSERIES
RPAR
CSENSE
In this case, the TRIPSEL setting is TRIPSEL = 5 V with RSLEW to GND and the nearest standard component
values are:
•
•
•
•
RSERIES = 43.2 kΩ
RPAR = 143 kΩ
RSEQU = 24.3 kΩ
CSENSE = 18 nF
Copyright © 2013, Texas Instruments Incorporated
25
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Note the effective divider ratio for the inductor DCR. The effective current sense resistance (RCS(eff)) is shown in
Equation 11.
RP _N
RCS(eff) = RDCR
´
R
SEQU + RP _N
where
•
RP_N is the series/parallel combination of RNTCRSERIES and RPAR
(11)
(12)
R
=
´(R
+ R
+ R
+ R
)
PAR
NTC
SERIES
R
P _N
R
PAR
NTC
SERIES
RCS(eff) is 0.77 mΩ.
Step Six
Determine the output capacitor configuration.
Intel has several recommended configurations in the specifications. The TPS53624 meets every requirement
with margin using the minimum configuration given in the Intel specification (Option 3). Depending on the layout,
it is possible to reduce the output capacitance further, or to use alternate capacitor technologies. A good rule of
thumb is that a successful design has a combination of bulk and ceramic capacitance totaling at least 1600 μF.
Step Seven
Set the load line.
The load line is set by the droop resistor using RIMVP and RCS(eff)
´ A
.
R
CS(eff)
CS
R
=
= 4.75kW
DROOP
G ´R
M
IMVP
(13)
(14)
Step Eight
Calculate the droop capacitor value.
LL ´ DIOUT ´ gM ´L
CS ´ ACS ´DMAX ´ V L
R
CDROOP
=
- 30pF = 105pF
R
( )
Because better overall transient performance is obtained by allowing a small ring-back, a small value capacitor
(between 33 pF and 68 pF) is used. This capacitor also helps in eliminating any noise that may be present at the
DROOP pin.
Step Nine
Calculate RSLEW
.
RSLEW sets the slew rate and the soft-start rate. The soft-start rate is 1/8 of the slew rate. Given the Intel
requirements, the slew rate minimum requirement is 5 mV/µs.
K
´ V
SLEW
SLEW
R
=
SLEW
SR
here
•
•
•
From the overcurrent limit setting in Step Five, RSLEW is terminated to GND
KSLEW = 1.25 × 109
VSLEW = 1.25 V
(15)
Taking into account the tolerance on KSLEW, RSLEW = 250 kΩ.
26
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
Step Ten
Calculate RIMON
.
RIMON is calculated to set the voltage on the IMON pin to approximately 1.0 V at maximum processor current.
V
IMON
R
=
W
( )
IMON
K
´I
´R
IMON CC(max) CS(eff)
here
•
•
•
•
•
•
VIMON = 1.0 V
KIMON = 2 µA/mV
ICC(max) = 50 A
RCS(eff) = 0.77 mΩ
RIMON = 13.1 kΩ
CIMON = 3300pF and is added in parallel to RIMON to give a smooth response on IMON pin.
(16)
Step Eleven
Calculate THAL pin components.
The THERM pin produces a nominal 61 µA current. The trip voltage is 0.75 V. Therefore, the resistance at the
trip point needs to be 0.75V / 61 µA = 12.3 kΩ. For a trip temperature of 85°C, the recommended 150 kΩ NTC
thermistor is 10.3 kΩ. To move the trip point to the correct resistance, we add a series resistance of 2.0 kΩ.
Depending on the thermistors selection and desired trip point, adding a parallel resistance to obtain the correct
resistance at the trip point is also possible. In order to keep the sensing as accurate as possible in both cases,
the contribution of the fixed resistance at the trip point should be as small as possible.
•
•
•
•
•
V5IN decoupling ≥ 2.2 μF, ≥ 10 V
V5FILT decoupling ≥ 1 μF, ≥ 10 V
VREF decoupling 0.22 μF to 1 μF, ≥ 4 V
Bootstrap capacitors ≥ 0.22 μF, ≥ 10 V Bootstrap diodes (optional) 30 V Schottky diode, BAT-54 or better
Pull-up resistors on PGOOD, PG, THAL, and PCNT pins per Intel guidelines
For power chain and other component selection, see Table 2.
Step Twelve
Select decoupling and peripheral components.
For peripheral capacitors use the following minimum values of ceramic capacitance. A capacitor with an X5R or
better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always
appropriate.
•
•
•
•
•
•
V5IN decoupling ≥ 2.2 µF, ≥ 10V
V5FILT decoupling ≥ 1 µF, ≥ 10V
VREF decoupling 0.22 µF to 1 µF, ≥ 4 V
Bootstrap capacitors ≥ 0.22 µF, ≥ 10 V
Bootstrap diodes (optional) 30 V Schottky diode, BAT-54 or better
Pull-up resistors on PGOOD, PG, THAL, and PCNT pins per Intel guidelines
Copyright © 2013, Texas Instruments Incorporated
27
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Layout Guidelines
The TPS53624 has fully differential current and voltage feedback. As a result, no special layout considerations
are required. However, all high-performance multi-phase power converters, like the TPS53624, require a certain
level of care in layout.
Schematic Review
Because the voltage and current feedback signals are fully differential it is a good idea to double check the
polarity.
•
•
•
CSP1 / CSN1
CSP2 / CSN2
VCCSENSE to VFB / VSSSENSE to GSNS
Specific Guidelines
Separate Noisy Driver Interface Lines from Sensitive Analog Interface Lines
The TPS53624 makes this as easy as possible, as the two sets of pins are on opposite sides of the device. In
addition, the CPU interface signals are grouped on one side of the device, and the MCH and platform interface
signals are grouped on the opposite side. This arrangement is shown in Figure 9.
Sensitive
Analog
Interface
Control/
Platform
Logic
Interface
40 39 38 37 36 35 34 33 32 31
MODE
GND
1
2
30
29
28
27
26
25
24
23
22
21
DRVH2
VBST2
LL2
3
CSP2
CSN2
CSN1
CSP1
GFB
4
DRVL2
V5IN
5
TPS53624
RHA PACKAGE
Driver
Interface
6
PGND
DRVL1
LL1
7
8
VFB
9
THRM
THAL
VBST1
DRVH1
10
11 12 13 14 15 16 17 18 19 20
CPU
Interface
UDG-12127
Figure 9. Device Layout by Pin Function
Given the physical layout of most systems, the current feedback (CSPx, CSNx) may have to pass near the
power chain. Clean current feedback is required for good load-line, current sharing, and current limiting
performance of the TPS53624. This requires the designer take the following precautions.
•
Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 10 for a
layout example.
•
•
Lay out the current feedback signals as a differential pair to the device.
Lay out the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
28
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
•
•
•
Design the compensation capacitor for DCR sensing (CSENSE) as close to the CS pins as possible.
Place RPAR near CSENSE
Place any noise filtering capacitors directly under the TPS53624 and connect to the CS pins with the shortest
trace length possible.
.
Noisy
Quiet
Inductor
Outline
LLx
VCORE
CSNx
CSPx
R
SEQ
R
SERIES
Thermistor
UDG-07189
Figure 10. Make Kelvin Connections to the Inductor for DCR Sensing
•
•
•
•
•
Ensure that all vias in the CSPx and CSNx traces are isolated from all other signals
Lay out the dotted signal traces in internal planes
If possible, change the name of the CSNx trace to prevent unintended connections to the VCORE plane
Design CSPx and CSNx as a differential pair in a quiet layer
Design the capacittor as near to the device pins as possible
Copyright © 2013, Texas Instruments Incorporated
29
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
Minimize High Current Loops
Figure 11 shows the primary current loops in each phase, numbered in order of importance. The most important
loop to minimize the area of is Loop 1, the path from the input capacitor through the high and low-side
MOSFETs, and back to the capacitor through ground.
V
C
BAT
B
C
1
IN
Q1
4b
DRVH
4a
L
V
CORE
LL
2
Q1
C
D
C
3b
OUT
DRVH
3a
PGND
UDG-07190
Figure 11. Major Current Loops Requiring Minimization
Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low-side gate drive
(Loops 3a and 3b) is important. The guidelines for gate drive layout are:
•
•
•
Make the low side gate drive as short as possible (1 inch or less preferred).
Make the DRVL width to length ratio of 1:10, wider (1:5) if possible
If changing layers is necessary, use at least two vias
30
Copyright © 2013, Texas Instruments Incorporated
TPS53624
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ZHCSAY4 –MARCH 2013
Power Chain Symmetry
The TPS53624 does not require special care in the layout of the power chain components, because independent
isolated current feedback is provided. Make every effort to lay out the phases in a symmetrical manner. The
current feedback from each phase must be free of noise and have the same effective current sense resistance. A
value of 1 mΩ of current feedback resistance is recommended.
Place Analog Components as Close to the Device as Possible
Place components close to the device in the following order.
1. CS pin noise filtering components
2. DROOP pin compensation component
3. Decoupling capacitor
4. SLEW resistor (RSLEW
)
Grounding Recommendations
The TPS53624 has separate analog and power grounds, and a thermal pad. The normal procedure for
connecting these is:
1. Connect the thermal pad to PGND.
2. Tie the thermal pad to the system ground plane with at least 4 small vias or one large via.
3. GND can be connected to any quiet space. A quiet space is defined as a spot where no power supply
switching currents are likely to flow. This applies to both the VCORE regulator and other regulators. Use a
single point connection to the point, and pour a GND island around the analog components.
4. Make sure the low-side MOSFET source connection and the decoupling capacitors have plenty of vias.
Decoupling Recommendations
•
Decouple V5 to PGND with at least a 2.2-μF ceramic capacitor. This fits best on the opposite side of the
device.
•
•
•
Use double vias to connect to the device.
Decouple V5FILT with 1-μF to AGND with leads as short as possible.
Decouple VREF to AGND with 0.22-μF, with short leads as short as possible.
Conductor Widths
•
•
•
Follow Intel guidelines with respect to the voltage feedback and logic interface connection requirements.
Maximize the widths of power, ground and drive signal connections.
For conductors in the power path, be sure there is adequate trace width for the amount of current flowing
through the traces.
•
•
Make sure there are sufficient vias for connections between layers.
Use a minimum of 1 via per ampere of current
Copyright © 2013, Texas Instruments Incorporated
31
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
REFERENCE VOLTAGE
vs
JUNCTION TEMPERATURE
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.4
1.2
1.0
1.708
1.706
1.704
1.702
1.700
1.698
1.696
1.694
1.692
.
–10
0
10 20 30 40 50 60 70 80 90 100 110
–10
0
10 20 30 40 50 60 70 80 90 100 110
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 12.
Figure 13.
DAC OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
DAC OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
1.2472
748.85
748.8
V
= 1.25 V
V
= 0.75 V
VID
VID
1.24715
1.2471
1.24705
1.2470
1.24695
1.2469
1.24685
1.2468
1.24675
1.2467
748.75
748.7
748.65
748.6
748.55
748.5
748.45
748.4
–10
0
10 20 30 40 50 60 70 80 90 100 110
–10
0
10 20 30 40 50 60 70 80 90 100 110
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 14.
Figure 15.
32
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
TYPICAL CHARACTERISTICS (continued)
HIGH FREQUENCY OUTPUT VOLTAGE
LOW FREQUENCY OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
1150
920
900
880
860
840
820
V
(V)
V
IN
(V)
IN
20
9
20
9
DCM Operation
Spec Max
Nominal
Nominal
1100
1050
1000
950
DCM Operation
Spec Max
V
V
T
= 1 V
V
V
T
= 0 V
PCNT
PCNT
= 1.075 V
= 0.875 V
VID
VID
Spec Min
= 25°C
= 25°C
A
Spec Min
10 12
A
0
5
10 15 20 25 30 35 40 45 50
0
2
4
6
8
14 16
18
Output Current (A)
Output Current (A)
Figure 16.
Figure 17.
HIGH FREQUENCY MODE (HFM) EFFICIENCY
LOW FREQUENCY MODE (LFM) EFFICIENCY
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
95
95
93
91
89
87
85
83
81
93
91
89
87
85
83
81
V
IN
= 9 V
V
= 9 V
IN
V
IN
= 20 V
V
= 20 V
IN
79
77
75
79
77
75
V
V
T
= 0.875 V
= 0 V
V
V
T
= 1.075 V
= 1 V
VID
VID
PCNT
PCNT
= 25°C
= 25°C
A
A
0
2
4
6
8
10
12
14
16
18
0
5
10 15 20 25 30 35 40 45 50
Output Current (A)
Output Current (A)
Figure 18.
Figure 19.
Copyright © 2013, Texas Instruments Incorporated
33
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
CURRENT SHARE IMBALANCE
CURRENT MONITOR VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
20
1.2
V
(V)
V
(V)
IN
T
= 25°C
IN
A
18
16
V
= 20 V/9 V
20
10
20/9
IN
1.0
0.8
Ideal V
IMON
14
12
10
8
0.6
0.4
0.2
0
V
= 9 V
IN
6
4
2
0
V
= 20 V
IN
Ideal V
IMON
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
I
– Output Current – A
I
– Output Current – A
OUT
OUT
Figure 20.
Figure 21.
VOLTAGE REFERENCE
vs
OUTPUT CURRENT
OPERATING FREQUENCY
vs
OUTPUT CURRENT
1.704
1.703
1.702
1.701
350
300
LFM, V = 9 V
IN
LFM, V = 20 V
IN
9-V HFM
20-V HFM
250
200
150
HFM, V = 9 V
IN
1.700
1.699
HFM, V = 20 V
IN
9-V LFM
20-V LFM
100
50
1.698
1.697
V
= V
V
= V
TONSEL REF
TONSEL
REF
HFM: V
LFM: V
= 1.075, V
= 1 V
= 0 V
HFM: V
= 1.075, V
PCNT
= 1 V
=0 V
VID
VID
PCNT
PCNT
VID
= 0.875, V
LFM: V
= 0.875, V
VID PCNT
1.696
0
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
Output Current (A)
Output Current (A)
Figure 22.
Figure 23.
34
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
EFFICIENCY
vs
vs
OUTPUT VOLTAGE
INPUT VOLTAGE
95
92.5
92.0
I
= 20 A
V
= 9 V
IN
OUT
90
85
91.5
91.0
90.5
V
= 20 V
IN
90.0
89.5
80
75
89.0
88.5
88.0
I
= 20 A
OUT
V
= 1.25 V
OUT
70
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
6
8
10
12
14
16
18
20
22
V
– Output Voltage – V
V
– Input Voltage – V
IN
OUT
Figure 24.
Figure 25.
Figure 26. Start-Up, VIN = 20 V
Figure 27. Start-Up, VIN = 9 V
Copyright © 2013, Texas Instruments Incorporated
35
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
Figure 28. PG and PGOOD, VIN = 20 V
Figure 29. PG and PGOOD, VIN = 9 V
Figure 30. Output Ripple, VIN = 20 V
Figure 31. Output Ripple, VIN = 9 V
36
Copyright © 2013, Texas Instruments Incorporated
TPS53624
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ZHCSAY4 –MARCH 2013
TYPICAL CHARACTERISTICS (continued)
Figure 32. Load Insertion, VIN = 20 V, IDC = 15 A, IAC = 35 A,
Figure 33. Load Insertion, VIN = 20 V, IDC = 15 A, IAC = 35 A
Persistence Mode
Figure 34. Load Insertion, VIN = 9 V, IDC = 15 A, IAC = 35 A,
Persistence Mode
Figure 35. Load Insertion, VIN = 9 V, IDC = 15 A, IAC = 35 A
Copyright © 2013, Texas Instruments Incorporated
37
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
Figure 36. Load Release, VIN = 20 V, IDC = 15 A, IAC = 35 A,
Figure 37. Load Release, VIN = 20 V, IDC = 15 A, IAC = 35 A
Persistence Mode
Figure 38. Load Release, VIN = 9 V, IDC = 15 A, IAC = 35 A,
Persistence Mode
Figure 39. Load Release, VIN = 9 V, IDC = 15 A, IAC = 35 A,
38
Copyright © 2013, Texas Instruments Incorporated
TPS53624
www.ti.com.cn
ZHCSAY4 –MARCH 2013
TYPICAL CHARACTERISTICS (continued)
Figure 40. VID Change from 1.075 V to 0.875 V, IDC = 15 A
Figure 41. VID Change from 1.075 V to 0.875 V, IDC = 3 A
Figure 42. PCNT Toggle: VIN = 20 V
Figure 43. PCNT Toggle: VIN = 9 V
Copyright © 2013, Texas Instruments Incorporated
39
TPS53624
ZHCSAY4 –MARCH 2013
www.ti.com.cn
GAIN AND PHASE
vs
FREQUENCY
OUTPUT IMPEDANCE AND PHASE
vs
FREQUENCY
50
40
225
180
4.5
4.0
80
60
Phase
30
20
135
90
3.5
3.0
2.5
2.0
1.5
Z
40
20
0
OUT_Target
Z
OUT_Phase
10
0
45
0
–10
–45
–20
–40
–20
–30
–90
Gain
–135
Z
OUT_Magnitude
1.0
0.5
–60
–80
–40
–180
–50
1000
–225
10 k
100 k
1 M
1000
10 k
100 k
1 M
f – Frequency – kHz
f – Frequency – kHz
Figure 44.
Figure 45.
In Figure 44 and Figure 45
•
•
•
•
Output bulk capacitance = 4 × 330 µF, 4.5 mΩ, Low ESL
Output MLCC capacitance = 7 × 22 µF + 21 × 10 µF
VIN = 20 V
VVID = 1.075 V
40
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS53624RHAR
TPS53624RHAT
ACTIVE
VQFN
VQFN
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
TPS
53624
ACTIVE
RHA
NIPDAU
TPS
53624
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040B
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
2X 4.5
4.15 0.1
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
4.5
SYMM
41
30
0.27
40X
1
0.17
PIN 1 ID
(OPTIONAL)
0.1
C A B
40
31
SYMM
0.05
0.5
0.3
40X
4219052/A 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.15)
SYMM
40X (0.6)
40X (0.22)
40
31
1
30
(0.25) TYP
36X (0.5)
SYMM
41
(5.8)
(0.685)
TYP
(1.14)
TYP
(
0.2) TYP
VIA
10
21
(R0.05) TYP
20
11
(0.685)
TYP
(1.14)
TYP
(5.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MIN
ALL SIDES
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219052/A 06/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.17)
(1.37) TYP
40X (0.6)
40X (0.22)
31
40
1
30
41
(1.37)
TYP
(0.25) TYP
SYMM
(5.8)
36X (0.5)
(R0.05) TYP
10
21
11
20
METAL
TYP
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4219052/A 06/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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