TPS53632RSMR [TI]
具有 I2C 控制的 3-2-1 相 D-CAP+ 降压无驱动控制器 | RSM | 32 | -10 to 105;
| 型号： | TPS53632RSMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 控制的 3-2-1 相 D-CAP+ 降压无驱动控制器 | RSM | 32 | -10 to 105 驱动 控制器 开关 输出元件 |
| 文件： | 总39页 (文件大小：2533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS53632
ZHCSCU1 –SEPTEMBER 2014
TPS53632 具有 I2C 接口控制功能且适用于低压应用的
3-2-1 相 D-CAP+™ 降压无驱动器控制器
1 特性
3 说明
1
•
•
可选相位数：（3，2 或 1）
针对 VID 控制和遥感勘测的 I2C 接口（具有 8 个器
件地址）
TPS53632 器件是一款采用串行控制的降压无驱动器
控制器。 具有 D-CAP+ 架构等高级特性，可实现快速
瞬态响应、最低输出波纹和高效率。 TPS53632 器件
支持标准 I2C Rev 3.0 接口，能够实现输出电压动态控
制以及电流监视器遥测。 它还具有动态相位增加和下
降控制功能，可进入单相断续电流模式，从而大大增加
轻负载时的效率。
•
•
•
•
•
•
•
•
•
•
•
•
针对快速瞬态响应提供 D-CAP+™ 控制
动态相位增加和下降操作
开关频率：300kHz 至 1MHz
数字电流监控
7 位数模转换器 (DAC) 输出范围：0.50V 至 1.52V
轻负载与重负载下实现最优效率
精确、可调电压定位或零斜率负载线路
已获专利 AutoBalance™ 相位均衡
可选 8 级电流限制
其它特性包括可调整控制 VCORE 转换率以及电压定
位。 TPS51604 器件驱动器专门针对这一系列控制器
而设计。 此外，TPS53632 器件还可配合德州仪器
(TI) 功率级器件（MOSFET 驱动器）使用。
TPS53632 器件采用节省空间的耐热增强型 32 引脚
VQFN 封装，额定工作温度范围为 –10°C 至 105°C。
2.5V 至 24V 转换电压范围
默认启动电压：1.00V
器件信息
小型 4mm x 4mm 32 引脚超薄四方扁平无引线
(VQFN) PowerPAD 封装
部件号
封装
封装尺寸
TPS53632
VQFN
4mm x 4mm
2 应用
•
•
高电流低压应用
微服务器的内核电源、定制微控制器、专用集成电
路 (ASIC)
简化电路原理图
Power Stage
TPS53632
PWM1
Power
Block
Driver
Power Stage
Power
Block
Control BUS
PWM2
Driver
Power Stage
PWM3
SKIP
VO
Power
Block
Driver
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLUSBW8
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
目录
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 20
7.5 Configuration and Programming ............................. 20
7.6 Register Maps ........................................................ 21
Applications and Implementation ...................... 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
Power Supply Recommendations...................... 31
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 8
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics (2-Phase Operation) ............ 9
6.9 Typical Characteristics (3-Phase Operation) .......... 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 35
11 器件和文档支持 ..................................................... 35
11.1 商标....................................................................... 35
11.2 静电放电警告......................................................... 35
11.3 术语表 ................................................................... 35
12 机械封装和可订购信息 .......................................... 35
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
日期
修订版本
注释
2014 年 9 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
5 Pin Configuration and Functions
RSM (QFN) PACKAGE
32 PINS
(TOP VIEW)
SDA
VDD
1
2
3
4
5
6
7
8
24 VFB
23 GFB
22 CSN3
21 CSP3
20 CSP2
19 CSN2
PGOOD
PWM3
PWM2
PWM1
SKIP
TPS53632
CSN1
CSP1
18
17
EN
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Error amplifier summing node. Resistors between the VREF pin and the COMP pin (RCOMP) and
between the COMP pin and the DROOP pin (RDROOP) set the droop gain.
COMP
26
I
CSP1
CSP2
CSP3
CSN1
CSN2
CSN3
17
20
21
18
19
22
Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor
DCR sense network. Tie CSP3, CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the phase.
I
I
Negative current sense inputs. Connect to the most negative node of current sense resistor or
inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop,
pull-down transistor.
Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP pin
DROOP
EN
25
8
O
I
and this pin sets the droop gain. ADROOP = 1 + RDROOP / RCOMP
.
Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when
brought low.
A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to VREF
to disable dynamic phase add and drop operation.
FREQ-P
GFB
10
23
I
Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the
microprocessor is not populated.
I
GND
29
13
–
Analog circuit reference. Tie this pin to a quiet point on the ground plane.
IMON
O
Analog current monitor output. VIMON = ΣVISENSE × (1 + RIMON/ROCP).
Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this
pin and GND (ROCP) selects 1 of 8 OCP levels (per phase, latched at start-up).
OCP-I
12
I/O
PU
9
3
I
Pull-up to VREF through 10-kΩ resistor.
PGOOD
PWM1
PWM2
PWM3
O
Power good output. Open-drain.
4
PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level
when needed.
5
O
–
6
30
32
NC
No connect.
Copyright © 2014, Texas Instruments Incorporated
3
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can be
used to override the factory ramp setting.
RAMP
11
I
SCL
SDA
31
1
I
Serial digital clock line.
Serial digital I/O line.
I/O
When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-state
level on this pin puts the drivers into a low power sleep mode.
SKIP
7
O
The voltage sets the 3 LSBs of the I2C address. The resistance to GND selects 1 of 8 slew rates. The
start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE values are
latched at start-up.
SLEWA
15
I
VINTF
V5A
14
28
I
I
Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V.
5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with
ceramic capacitor with a value of at least 1 µF.
10-kΩ resistor to the VIN pin provides input voltage information to the on-time circuits for both
converters.
VIN
16
2
I
I
VDD
3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF.
Voltage sense line. Tie directly to VOUT sense point of processor. Tie to VOUT on PCB with a 10-Ω
resistor to provide feedback when the microprocessor is not populated. The resistance between VFB
and GFB is > 1 MΩ
VFB
24
I
VREF
PAD
27
O
–
1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.
Thermal pad Tie to the ground plane with multiple vias.
GND
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
6.0
UNIT
PWM3, PWM2, PWM1, SKIP, V5A
VIN
30.0
COMP, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, DROOP, EN,
FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VDD,
VFB, VINTF, VREF
Input voltage
V
–0.3
3.6
GFB
–0.2
–0.3
–40
0.2
3.6
Output voltage
PGOOD
V
Operating junction temperature, TJ
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
–55
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature
Human body model (HBM) ESD stress voltage(1)
Charged device model (CDM) ESD stress voltage(2)
kV
(1)
V(ESD)
–750
750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
CSN1, CSN2, CSN3, CSP1, CSP2, CSP3,
IMON, , OCP-I, O-USR, RAMP, SCL, SDA, VDD,
VFB, VINTF, VREF
–0.1
3.5
V
VIN
–0.1
–0.1
28
VI
Input voltage
COMP, DROOP, EN, FREQ-P, PWM3, PWM2,
PWM1, SKIP, SLEWA, V5A
5.5
GFB
–0.1
–0.1
–10
0.1
3.5
VO
TA
Output voltage
PGOOD
V
Operating ambient temperature
105
°C
6.4 Thermal Information
TPS53632
RSM (VQFN)
32 PINS
37.2
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
31.9
8.1
°C/W
ψJT
0.4
ψJB
7.9
θJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
版权 © 2014, Texas Instruments Incorporated
5
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
6.5 Electrical Characteristics
over recommended free-air temperature range, 4.5 V ≤ VV5A ≤ 5.5 V, 3.0 V ≤ VVDD ≤ 3.6 V, VGFB = GND, VVFB = VCORE (unless
otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET
IV5-3P
V5A supply current
VDD supply current
V5A supply current
VDD supply current
3-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = ‘HI’
3.6
0.2
3.5
0.2
6.0
0.8
6.0
0.8
3-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = ‘HI’,
digital buses idle
IVDD-3P
IV5-1P
mA
1-phase operation, VDAC < VVFB < (VDAC + 100 mV) , EN = ‘HI’
1-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = ‘HI’,
digital buses idle
IVDD-1P
IV5STBY
V5A standby current
VDD standby current
VINTF supply current
EN = ‘LO’
125
23
200
40
IVDDSTBY
IVDD-1P8
EN = ‘LO’
µA
All conditions, digital buses idle
1.7
5.0
VVFB < 200 mV, Ramp up, VVDD > 3 V, EN = ’HI’, switching
begins.
VUVLOH
V5A UVLO ‘OK’ threshold
V5A UVLO fault threshold
4.2
4.4
4.2
4.52
4.35
Ramp down, EN = ’HI’, VVDD > 3 V, VVFB = 100 mV, restart if 5-
V falls below VPOR then rises > VUVLOH, or EN is toggled w/ VV5A
> VUVLOH
VUVLOL
4.00
Ramp down, EN = ‘HI’, VVDD > 3 V. Can restart if 5-V rises to
VUVLOH and no other faults present.
VPOR
V5A fault latch reset threshold
VDD UVLO ‘OK’ threshold
1.2
2.5
1.9
2.8
2.5
3.0
VVFB < 200 mV. Ramp up, VV5A > 4.5 V, EN = ’HI’, Switching
begins.
V3UVLOH
V
Ramp down, EN = ’HI’, V5A > 4.5V, VFB = 100 mV, restart if 5-
V dips below VPOR then rises > VUVLOH or EN is toggled with 5 V
> VUVLOH
V3UVLOL
Fault threshold
VDD fault latch
2.4
1.2
2.6
1.9
2.8
2.5
Ramp down, EN = ‘HI’, VV5A > 4.5 V, can restart if 5-V supply
rises to VUVLOH and no other faults present.
VPOR
VINTFUVLOH
VINTFUVLOL
VINTF UVLO OK
Ramp up, EN = ’HI’, VV5A > 4.5 V, VVFB = 100 mV
Ramp down, EN = ’HI’, VV5A > 4.5 V, VVFB = 100 mV
1.4
1.3
1.5
1.4
1.6
1.5
VINTF UVLO falling
REFERENCES: DAC, VREF, VFB DISCHARGE
VVIDSTP
VDAC1
VID step size
VFB tolerance
Change VID0 HI to LO to HI
10
No load active, 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A
No load medium, 1.0 V ≤ VVFB ≤ 1.35 V, IOUT = 0 A
No load medium, 0.5 V ≤ VVFB ≤ 0.99 V, IOUT = 0 A
VREF output 4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A
0 A ≤ IREF ≤ 500 µA, HP-2
–9
–8
9
8
mV
VDAC2
VFB tolerance
-7
7
VVREF
VREF output
1.66
–4
1.700
-3
1.74
V
mV
V
VVREFSRC
VVREFSNK
VVBOOT
VREF output source
VREF output sink
–500 A ≤ IREF ≤ 0 A, HP-2
3
4
Internal VFB initial boot voltage Initial DAC boot voltage
0.99
1.00
1.01
RAMP SETTINGS
RRAMP = 30 kΩ
RRAMP = 56 kΩ
RRAMP = 100 kΩ
60
120
160
40
VRAMP
Compensation ramp
mV
RRAMP ≥ 150 kΩ
VOLTAGE SENSE: VFB AND GFB
Not in fault, disable or UVLO, VVFB = VDAC = 1.5 V,
VGFB = 0 V, measure from VFB to GFB
RVFB
VFB/GFB Input resistance
1
MΩ
VDELGND
GFB Differential
GND to GFB
±100
mV
CURRENT MONITOR
∑∆CS = 0 mV, AIMON = 3.867
∑∆CS = 1.5 mV, AIMON = 3.867
∑∆CS = 7.5 mV, AIMON = 3.867
∑∆CS = 15 mV, AIMON = 3.867
Each phase, CSPx – CSNx
00h
19h
80h
FFh
VALADC
IMON ADC output
LRIMON
IMON linear range
50
mV
6
版权 © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
Electrical Characteristics (接下页)
over recommended free-air temperature range, 4.5 V ≤ VV5A ≤ 5.5 V, 3.0 V ≤ VVDD ≤ 3.6 V, VGFB = GND, VVFB = VCORE (unless
otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE: OVER CURRENT PROTECTION, PHASE ADD AND DROP, AND PHASE BALANCE
ROCP-I = 20 kΩ
ROCP-I = 24 kΩ
ROCP-I = 30 kΩ
3.7
6.6
7.6
10.5
14.5
19.5
25.4
32.5
40.5
49.3
11.4
14.1
18.0
23.0
29.0
36.2
44.0
53.0
10.6
15.4
21.3
28.4
36.3
45.0
ROCP-I = 39 kΩ
OCP voltage (valley current
limit)
VOCPP
mV
ROCP-I = 56 kΩ
ROCP-I = 75 kΩ
ROCP-I = 100 kΩ
ROCP-I = 150 kΩ
Valley current, % of OCP value, mode changes from 2-phase
CCM to 3-phase CCM
IAD23
IAD12
IAD32
Phase add
Phase add
Phase drop
25%
10%
15%
Valley current, % of OCP value, mode changes from 1-phase
DCM to 2-phase CCM
Valley current, % of OCP value, mode changes from 3-phase
CCM to 2-phase CCM
Valley current, % of OCP value, mode changes from 2-phase
CCM to 1-phase DCM
IAD21
ICS
Phase drop
7%
0.2
CS pin input bias current
CSPx and CSNx
VFB to DROOP
–500
80
500
nA
dB
Error amplifier total voltage
gain(1)
AV-EA
IEA_SR
IEA_SK
ACSINT
RSFTSTP
Error amplifier source current
Error amplifier sink current
Internal current sense gain
Soft-stop transistor resistance
IDROOP, VVFB = VDAC + 50 mV, RCOMP = 1 kΩ
IDROOP, VVFB = VDAC – 50mV, RCOMP = 1 kΩ
Gain from CSPx – CSNx to PWM comparator, RSKIP = Open
Connected to CSN1
1
–1
mA
5.8
6.0
100
6.2
V/V
200
Ω
Voltage to disable dynamic
phase add/drop
VDP_OFF
VDP_ON
VDP_HYS
Voltage at FREQ-P at start-up
Voltage at FREQ-P at start-up
Voltage at FREQ-P at start-up
0.70
V
Voltage to enable dynamic
phase add/drop
0.40
600
Hysteresis voltage of phase
add/drop circuit
80
mV
EN = HI
350
kΩ
RVIN
VIN resistance
EN = LOW or STBY
10
MΩ
PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
VOVPH
VPGDH
VPGDL
Fixed OVP voltage
VCSN1 > VOVPH for 1 µs
1.60
190
1.70
1.80
245
V
PGOOD high threshold
PGOOD low threshold
Measured at the VFB pin w/r/t VID code, device latches OFF
Measured at the VFB pin w/r/t VID code, device latches OFF
mV
-348
-280
PWM AND SKIP OUTPUTS: I/O VOLTAGE AND CURRENT
VP-S_L
PWMx/SKIP - Low
PWMx/SKIP - High
PWMx tri-state
PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA
PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA
PWMILOAD = ± 100 µA
0.15
1.7
0.3
1.8
VP-S_H
4.2
1.6
V
VPW-SKLK
LOGIC INTERFACE: VOLTAGE AND CURRENT
RVRTTL
VSDA = 0.31
4
-2
15
50
2
Pull-down resistance
RVRPG
Ω
µA
V
VPGOOD= 0.31
36
IVRTTLK
VIL
Logic leakage current
Low-level Input voltage
High-level Input voltage
I/O leakage, EN
VSCL= 1.8 V, VSDA = 1.8 V, VPGOOD = 3.3 V
0.2
0.6
SCL, SDA; VVINTF = 1.8 V
VIH
1.2
IENH
Leakage current , VEN = 1.8 V
24
40
µA
(1) Specified by design. Not propduction tested.
版权 © 2014, Texas Instruments Incorporated
7
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
6.6 Timing Requirements
The TPS53632 requires the ENABLE signal on Pin 8 to go from low to high only after the V5A (5V), the VDD
(3.3V) and the VIN rails have gone high.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Controller minimum OFF
time
tOFF(min)
tON(min)
Fixed value
RCF = 150 kΩ, VVIN = 20 V, VVFB = 0 V
20
ns
Controller minimum ON
time
20
TIMERS: SLEW RATE, ADDR, SLEEP EXIT, ON TIME AND I/O TIMING
tSTART-CB
tSTBY-E
Cold boot time(1)
Standby exit time(2)
VBOOT > 0V , EN = high, CREF = 0.33 µF
VVID = 1.28 V, RSLEW = 39 kΩ
RSLEW = 20 kΩ
1.2
ms
µs
250
6
12
18
24
30
RSLEW = 24 kΩ
Slew rate setting for VID
change
SLSET
RSLEW = 30 kΩ
mV/µs
mV/µs
RSLEW = 39 kΩ
RSLEW = 56 kΩ
Slew rate setting for start-
up
(3)
SLSTART
ADDR
EN goes high, RSLEW = 39 kΩ
12
VSLEWA ≤ 0.30 V (Addr = 100 0xxx)
0.75 V ≤ VSLEWA ≤ 0.85 V
000b
011b
101b
Address setting 3 LSB of
I2C address
1.15 V ≤ VSLEWA ≤ 1.25 V
PGOOD deglitch time
(over)(4)
tPGDDGLTO
tPGDDGLTU
1
µs
ns
PGOOD deglitch time
(under)(5)
31
RCF = 20 kΩ
295
230
164
140
128
RCF = 24 kΩ, VVIN = 12 V, VVFB = 1 V (400 kHz)
RCF = 39 kΩ, VVIN = 12 V, VVFB = 1 V (600 kHz)
RCF = 75 kΩ, VVIN = 12 V, VVFB = 1 V (800 kHz)
RCF = 150 kΩ, VVIN = 12 V, VVFB = 1 V (1 MHz)
tON
On time
PWM AND SKIP OUTPUTS
PWMx/SKIP H-L transition
time
(3)
tP-S_H-L
tP-S_TRI
10% to 90%, both edges
7
5
20
20
ns
µs
(3)
PWMx tri-state transition
10% or 90% to tri-state level, both edges
PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
PGOOD low after enable
tPG2
Low state time after EN goes low.
225
250
275
goes low
(1) Cold boot time is defined as the time from UVLO detection to VOUT ramp.
(2) Standby exit time is defined as the time from EN assertion until PGOOD goes high
(3) Specified by design. Not production tested.
(4) PGOOD deglitch time (over) is defined as the time from when the VFB pin rises above the 250-mV VDAC boundary to when the PGOOD
pin goes low.
(5) PGOOD deglitch time (under) is defined as the time from when the VFB pin falls below the –300-mV VDAC boundary to when the
PGOOD pin goes low.
8
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TPS53632
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ZHCSCU1 –SEPTEMBER 2014
6.8 Typical Characteristics (2-Phase Operation)
VIN = 12 V
VIN = 12 V
VIN = 12 V
VOUT = 1 V
Load = 1 A
Load = 4 A to 20 A
Load = 1 A to 25 A
VIN = 12 V
VOUT = 1 V
Load = 10 A
图 1. Startup
图 2. Switching Waveform
VOUT = 1 V
Δ VOUT, 1.0 V to 1.1 V
I2C command
图 3. Load Transient
图 4. Output Voltage Change
VOUT = 1 V
VIN = 12 V
VOUT = 1 V
Load = 25 A to 1 A
图 5. Auto Phase Add
图 6. Auto Phase Drop
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TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
6.9 Typical Characteristics (3-Phase Operation)
VIN = 12 V
VIN = 12 V
VIN = 12 V
VOUT = 1 V
Load = 1 A
Load = 9 A to 35 A
Load = 1 A to 31 A
VIN = 12 V
VOUT = 1 V
Load = 30 A
图 7. Startup
图 8. Switching Waveform
Δ VOUT, 1.0 V to 1.1 V
I2C command
VOUT = 1 V
图 10. Output Voltage Change
图 9. Load Transient
VOUT = 1 V
VIN = 12 V
VOUT = 1 V
Load = 31 A to 1 A
图 11. Auto Phase Add
图 12. Auto Phase Drop
10
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TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
7 Detailed Description
7.1 Overview
The TPS53632 device is a DCAP+ mode adaptive on-time controller. The DAC outputs a reference in
accordance with the 8-bit VID code as defined in 表 2. This DAC sets the output voltage.
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. With conventional voltage-mode constant
on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in
the TPS53632 device, the cycle begins when the current feedback reaches an error voltage level which
corresponds to the amplified difference between the DAC voltage and the feedback output voltage. In the case of
two-phase or three-phase operation, the device sums the current feedback from all the phases at the output of
the internal current-sense amplifiers.
This approach has two advantages:
•
•
The amplifier DC gain sets an accurate linear load-line slope, which is required for CPU core applications.
The device filters the error voltage input to the PWM comparator to improve the noise performance.
In addition, a value representing the difference between the DAC-to-output voltage and the current feedback,
goes through an integrator to give an approximately linear load-line slope even at light loads where the inductor
current is in discontinuous conduction mode (DCM).
During a steady-state condition, the phases of the TPS53632 switch 180° phase-displacement for two-phase
mode and 120° phase-displacement for three-phase mode. The phase displacement is maintained both by the
architecture (which does not allow the high-side gate drive outputs of more than one phase to be ON in any
condition except transients) and the current ripple (which forces the pulses to be spaced equally). The controller
forces current-sharing by adjusting the ON-time of each phase. Current balancing requires no user intervention,
compensation, or extra components.
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TPS53632
ZHCSCU1 –SEPTEMBER 2014
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7.2 Functional Block Diagram
COMP
DROOP
VDD
V5A
GND
VBAT
VREF
Clamp
Differential
Amplifier
PWM1
PWM2
PWM3
Ramp
Comparator
PWM1
On-Time
1
VFB
GFB
PWM1
PWM2
+
CLK1
Voltage
Amplifier
+
+
+
CLK
Phase
Manager
CLK2
CLK3
PWM2
PWM3
DAC
On-Time
2
Error
Amplifier
Integrator
CSP1
+
+
IS1
BLANK
IAMP
ISUM
CSN1
CSP2
USR
ISUM
DROOP
OSR/USR
On-Time
3
OSR
ILIM
PWM3
+
IS2
IS3
IAMP
ISHARE
ADDR
Current
Sharing
Circuitry
+6
CSN2
CSP3
+
+
+
OCP
PS0
PS1
PS2
PS3
VD
IAMP
CSN3
EN
CPU
SKIP
Logic, Protection,
and Status Circuitry
ISUM
IS1
DAC
DAC
PGOOD
SCL
IS2
IS3
SVID
Interface
SDA
FSEL
VREF
7.3 Feature Description
7.3.1 Current Sensing
The TPS53632 device provides independent channels of current feedback for every phase. These independent
channels increase the system accuracy and reduce the dependence of circuit performance on layout compared
to an externally summed architecture. The design can use inductor DCR sensing to yield the best efficiency or
resistor current sensing to yield the most accuracy across wide temperature ranges. DCR sensing can be
optimized by using a NTC thermistor to reduce the variation of current sense with temperature.
The pins CSP1, CSN1, CSP2, CSN2 and CSP3, CSN3 are the current sensing pins.
7.3.2 Load Transients
When the load increases suddenly, the output voltage immediately drops. This voltage drop is reflected as a
rising voltage on the DROOP pin. This rising voltage forces the PWM to pulse sooner and more frequently which
causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-
state operating condition is reached and the PWM switching resumes the steady-state frequency. Similarly, when
the load releases suddenly, the output voltage rises. This rise is reflected as a falling voltage on the COMP pin.
This rising voltage forces a delay in the PWM pulses until the inductor current reaches the new load current,
when the switching resumes and steady-state switching continues.
7.3.3 AutoBalance™ Current Sharing
The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of
each phase to equalize the current in each phase.
12
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TPS53632
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ZHCSCU1 –SEPTEMBER 2014
Feature Description (接下页)
The PWM comparator (not shown) starts a pulse when the feedback voltage equals the reference voltage. The
VIN voltage charges the Ct(on) capacitor through the resistor Rt(on). The pulse is terminated when the voltage at
capacitor Ct(on) matches the on-time (tON) reference, normally the DAC voltage (VDAC).
A current sharing circuit is shown in 图 13. For example, assume that the 5 µs averaged value of I1 = I2 = I3. In
this case, the PWM modulator terminates at VDAC, and the normal pulse width is delivered to the system. If
instead, I1 > IAVG, then an offset is subtracted from VDAC, and the pulse width for Phase 1 is shortened, reducing
the current in Phase 1 to compensate. If I1 < IAVG, then a longer pulse is produced, again compensating on a
pulse-by-pulse basis.
VIN
Rt(on)
VDAC
CSP1
CSN1
K x (I1-IAVG
)
)
)
+
PWM1
+
+
+
5 ms
Filter
+
Current
Amplifier
Ct(on)
IAVG
Rt(on)
VDAC
+
CSP2
CSN2
K x (I2-IAVG
PWM2
5 ms
Filter
+
Current
Amplifier
Ct(on)
IAVG
Rt(on)
Averaging
Circuit
IAVG
VDAC
+
CSP3
CSN3
K x (I3-IAVG
PWM3
5 ms
Filter
+
Current
Amplifier
Ct(on)
IAVG
UDG-12197
图 13. AutoBalance Current Sharing
7.3.4 PWM and SKIP Signals
The PWM and SKIP signals are outputs of the controller and serve as input to the driver or DrMOS type devices.
Both are 5-V logic signals. The PWM signals are logic high when the high-side driver turns ON. The PWM signal
must be low for the low-side drive to turn ON. When both the drive signals are OFF, the PWM is in tri-state.
7.3.5 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
The TPS53632 device continuously monitors the voltage on the V5A, VDD and VINTF pins to ensure a value
high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The
converter starts with a voltage of approximately 4.4 V and has a nominal 200 mV of hysteresis. After the 5VA,
VDD or VINTF pins go below the VUVLOL level, the corresponding voltage must fall below VPOR (1.5 V) to reset
the device.
The input voltage (VVIN) does not include a UVLO function, so the circuit runs with power inputs as low as
approximately 3 x VOUT
.
7.3.6 Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described in the Overcurrent
Protection (OCP) section. If the output voltage drops below the low PGOOD voltage threshold, then the drivers
are turned OFF until the EN pin power is cycled.
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TPS53632
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Feature Description (接下页)
7.3.7 Overcurrent Protection (OCP)
The TPS53632 device uses a valley current limiting scheme, so the ripple current must be considered. The DC
current value at OCP (IOCP) is the OCP limit value plus half of the ripple current. Current limiting occurs on a
phase-by-phase and pulse-by-pulse basis. If the voltage between the CSPx and CSNx pins is above the OCP
value, the converter delays the next ON pulse until that voltage difference drops below the OCP limit. For
inductor current sensing circuits, the voltage between the CSPx and CSNx pins is the inductor DCR value
multiplied by the resistor divider which is part of the NTC compensation network. As a result, a wide range of
OCP values can be obtained by changing the resistor divider value. In general, use the highest OCP setting
possible with the least attenuation in the resistor divider to provide as much signal to the device as possible. This
provides the best performance for all parameters related to current feedback.
In OCP mode, the voltage drops until the UVP limit is reached. Then the converter sets the PGOOD to inactive,
and the drivers are turned OFF. The converter remains in this state until the device is reset by the V5A, VDD or
VINTF rails.
7.3.8 Overvoltage Protection
An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than VDAC
.
VOUT > + VPGDH greater than VDAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for
the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or
VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the
processor 100% of the time, there is a second OVP level fixed at VOVPH which is always active. If the fixed OVP
condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter
remains in this state until the V5A, VDD or VINTF pin is reset.
7.3.9 Analog Current Monitor, IMON and Corresponding Digital Output Current
The TPS53632 device includes a current monitor function. The current monitor supplies an analog voltage,
proportional to the load current, on the IMON pin.
The current monitor function is related to the OCP selection resistors. The ROCP is the resistor between the OCP-
I pin and GND and RCIMON is the resistor between the IMON pin to the OCP-I pin that sets the current monitor
gain. 公式 1 shows the calculation for the current monitor gain.
:
;
ìÜØß×æ
ꢀH Í 8¼Ìá 1ÛÛÛ. 8
4ÂÆÈÇ
8
ÂÆÈÇ
L sr H s E
:
;
4ȼÉ
where
•
Σ VCS is the sum of the DC voltages at the inputs to the current sense amplifiers
(1)
To ensure stable current monitor operation and at the same time provide a fast dynamic response, connect a
capacitor with a value between 4.7-nF and 10-nF between the IMON pin and GND.
Set the analog current monitor so that at the maximum processor current (ICC(max)) level, the IMON voltage is 1.7
V. This corresponds to a digital output current value of ‘FF’ in register 03H.
7.3.10 Addressing
The TPS53632 device can be configured for three different base addresses by setting a voltage on the SLEWA
pin. Configure a resistor divider on SLEWA from VREF to GND. A resistor between the SLEWA pin and GND
sets the slew rate. Once the slew rate resistor is selected, the resistor from the VREF pin to the SLEWA pin can
be chosen based on the required base address. For a base address of 0, the VREF to SLEWA resistor can be
left open.
7.3.11 I2C Interface Operation
The TPS53632 device includes a slave I2C interface accessed via the SCL (serial clock) and SDA (serial data)
pins. The interface sets the base VID value, receives current monitor telemetry, and controls functions described
in this section. It operates when EN = low, with the bias supplies in regulation. It is compliant with I2C
specification UM10204, Revision 3.0. The characteristics are:
•
Addressing
14
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TPS53632
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ZHCSCU1 –SEPTEMBER 2014
Feature Description (接下页)
–
–
7-bit addressing; address range is 100 0xxx (binary)
Last three bits are determined by the SLEWA pin at start-up
•
•
Byte read / byte write protocols only (See figures below)
Frequency
–
–
–
–
100 kHz
400 kHz
1 MHz
3.4 MHz
•
Logic inputs are 1.8-V logic levels (3.3-V tolerant)
7.3.11.1 Key for Protocol Examples
Master Drives SDA
Slave Drives SDA
NAK
S
P
Start
Stop
W
R
Write
A
ACK
A
Read
UDG-13045
7.3.11.2 Protocol Examples
The good byte read transaction the controller ACKs and the master terminates with a NAK/stop.
S
Slave Address
W
A
Reg Address
A
S
Slave Address
R
A
Reg data
A
P
UDG-13046
图 14. Good Byte Read Transaction
The controller issues a NAK to the read command with an invalid register address.
S
Slave Address
W
A
Reg Address
A
UDG-13047
图 15. NAK Invalid Register Address
图 16 illustrates a good byte write.
S
Slave Address
W
A
Reg Address
A
Reg Data
A
P
UDG-13048
图 16. Good Byte Write
The controller issues a NAK to a write command with an invalid register address.
S
Slave Address
W
A
Reg Address
A
UDG-13049
图 17. Invalid NAK Register Address
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TPS53632
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www.ti.com.cn
Feature Description (接下页)
The controller issues a NAK to a write command for the condition of invalid data.
S
Slave Address
W
A
Reg Address
A
Reg Data
A
P
UDG-13050
图 18. Invalid NAK Register Data
The following master code sequence is executed to enter Hs (3.4-MHz SCL) mode.
8'b00001xxx
S
A
UDG-13051
图 19. Master Code Sequence
7.3.12 Start-Up Sequence
The TPS53632 initializes when all of the supply voltages rise above the UVLO thresholds. This function is also
know as a cold boot. The device then reads all of the various settings (such as frequency and overcurrent
protection). This process takes less than 1.2 ms. During this time, the VSR pin initializes to the BOOT voltage.
The output voltage rises to the voltage select register (VSR) level when the EN pin (enable) goes high. As soon
as the BOOT sequence completes, PGOOD is HIGH and the I2C interface can be used to change the voltage
select register. The current VSR value is held when EN goes low and returns to a high state This function is also
know as a warm boot). The VSR can be changed when EN is low, however, this is not recommended prior to
completion of the cold boot process.
7.3.13 Phase Add and Drop Operation
The phase add and phase drop operations are enabled by default in the TPS53632 device. The converter starts
up in multi-phase CCM mode and reduces phase count until reaching single phase DCM mode as the load is
reduced. This action takes place at a fixed percentage of the OCP level defined in the Electrical Characteristics
table. The controller automatically adds phases when the current exceeds the defined percentage of the OCP
value.
To disable the automatic phase and drop operation, connect a resistor between the VREF pin and the FREQ-P
pin so that the voltage is above the value specified in the parameter table.
7.3.14 Power Good Operation
PGOOD is an open-drain output pin that is designed to be pulled up with an external resistor to a voltage 3.6 V
or less. Normal PGOOD operation (exclusive of OC or MAXVID interrupt action) is shown in 图 20. On initial
power-up, a power good status occurs within 6 µs of the DAC reaching its target value. When EN is brought low,
the PGOOD pin is also brought low for 250 µs and then is allowed to float. The TPS53632 device pulls down the
PGOOD signal when the EN signal subsequently goes high and returns high again within 6 µs of the end of the
DAC ramp. The delay period between the EN pin going high and the PGOOD pin going low in this case is less
than 1 µs.
图 20 shows the power good operation at initial start up and with falling and rising EN.
16
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TPS53632
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ZHCSCU1 –SEPTEMBER 2014
Feature Description (接下页)
VBIAS
VOUT
EN
1 Ps
PGOOD
1.2 ms
6 Ps
250 Ps
250 Ps
UDG-13096
图 20. Power Good Operation
7.3.15 Input Voltage Limits
The number of input phases supported varies with the input voltage. See 表 1 for limits. The minimum input
voltage is lower for lower frequency operation and/or lower output voltages.
表 1. Input Voltage Limits vs Number of Phases at 1-MHz Switching Frequency
NUMBER OF PHASES
VIN(min) (V)
VOUT(max) (V)
3
2
1
5.5
3.7
2.5
1.28
7.3.16 Fault Behavior
The TPS53632 device has a complete suite of fault detection and protection functions, including input
undervoltage lockout (UVLO) on all power inputs, overvoltage and overcurrent limiting and output undervoltage
detection. The protection limits are summarized in 表 1. The converter suspends switching when the limits are
exceeded and the PGOOD pin goes low. In this state, the fault register 14h is readable. To exit fault protection
mode, power must be cycled.
表 2. TPS53632 VID Table
VID6
0
VID5
0
VID4
1
VID3
1
VID2
0
VID1
0
VID0
1
HEX
19
VOLTAGE
0.5000
0.5100
0.5200
0.5300
0.5400
0.5500
0.5600
0.5700
0.5800
0.5900
0.6000
0.6100
0.6200
0
0
1
1
0
1
0
1A
1B
1C
1D
1E
1F
20
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
1
21
0
1
0
0
0
1
0
22
0
1
0
0
0
1
1
23
0
1
0
0
1
0
0
24
0
1
0
0
1
0
1
25
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TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
表 2. TPS53632 VID Table (接下页)
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
VID3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
VID2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
HEX
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
VOLTAGE
0.6300
0.6400
0.6500
0.6600
0.6700
0.6800
0.6900
0.7000
0.7100
0.7200
0.7300
0.7400
0.7500
0.7600
0.7700
0.7800
0.7900
0.8000
0.8100
0.8200
0.8300
0.8400
0.8500
0.8600
0.8700
0.8800
0.8900
0.9000
0.9100
0.9200
0.9300
0.9400
0.9500
0.9600
0.9700
0.9800
0.9900
1.0000
1.0100
1.0200
1.0300
1.0400
1.0500
1.0600
1.0700
1.0800
1.0900
18
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TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
表 2. TPS53632 VID Table (接下页)
VID6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOLTAGE
1.1000
1.1100
1.1200
1.1300
1.1400
1.1500
1.1600
1.1700
1.1800
1.1900
1.2000
1.2100
1.2200
1.2300
1.2400
1.2500
1.2600
1.2700
1.2800
1.2900
1.3000
1.3100
1.3200
1.3300
1.3400
1.3500
1.3600
1.3700
1.3800
1.3900
1.4000
1.4100
1.4200
1.4300
1.4400
1.4500
1.4600
1.4700
1.4800
1.4900
1.5000
1.5100
1.5200
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19
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
7.4 Device Functional Modes
7.4.1 PWM Operation
The Functional Block Diagram and 图 21 show how the converter operates in continuous conduction mode
(CCM).
V
CORE
I
SUM
V
DROOP
SW_CLK
Phase 1
Phase 2
Phase 3
UDG-12192
Time
图 21. D-CAP+™ Mode Basic Waveforms
Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current
feedback (ISUM) is higher than the error amplifier output (VCOMP). ICMP falls until it hits VCOMP, which contains a
component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and
triggers the on-time generator, which generates the internal SW_CLK signal. Each SW_CLK signal corresponds
to one switching ON pulse for one phase.
During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, ISUM
voltage corresponds to a single-phase inductor current only.
During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.
Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives
the required interleaving of 360/n, where n is the number of phases.
7.5 Configuration and Programming
After the 5-V, 3.3-V, or VINTF power is applied to the controller (all are above UVLO level), the following
information is latched and cannot be changed anytime during operation. The Electrical Characteristics table
defines the values of the selections.
7.5.1 Operating Frequency
The resistor between the FREQ-P pin and GND sets the switching frequency. See the Electrical Characteristics
table for the resistor settings corresponding to each frequency selection.
注
The operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed
based on the input voltage (at the VIN pin) and output voltage (set by VID). The OFF time
varies based on various factors such as load and power-stage components.
7.5.2 Overcurrent Protection (OCP) Level
The resistor from OCP-I to GND sets the OCP level of the CPU channel. See the Electrical Characteristics table
for the resistor settings corresponding to each OCP level.
20
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ZHCSCU1 –SEPTEMBER 2014
Configuration and Programming (接下页)
7.5.3 IMON Gain
The resistors from IMON to OCP-I and OCP-I to GND set the DC load current monitor (IMON) gain.
7.5.4 Slew Rate
The SetVID fast slew rate is set by the resistor from SLEWA pin to GND. See the Electrical Characteristics table
for the resistor settings corresponding to each slew rate setting.
7.5.5 Base Address
The voltage on SLEWA pin sets the device base address.
7.5.6 Ramp Selection
The resistor from RAMP to GND sets the ramp compensation level. See the Electrical Characteristics table for
the resistor settings corresponding to each ramp level.
7.5.7 Active Phases
Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to
a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V
supply and tie the CSN2 and CSN3 pins to GND.
7.6 Register Maps
The I2C interface can support 400-kHz, 1-MHz, and 3.4-MHz clock frequencies. The I2C interface is accessible
even when EN is low. The following registers are accessible via I2C.
7.6.1 Voltage Select Register (VSR) (00h)
•
•
•
•
•
Type: Read and write
Power-up value: 48h. This value can be changed before the rising edge of EN to change BOOT voltage.
EN rising (after power-up): prior programmed value
See 表 2 for exact values
A command to set VSR < 19h (minimum VID) generates a NAK and the VSR remains at the prior value
b7
b6
b5
b4
b3
b2
b1
b0
–
VID[6:0]
7.6.2 IMON Register (03h)
•
•
•
Type: Read only
Power-up value: 00h
EN rising (after power-up):00h
b7
b6
b5
b4
b3
b2
b1
b0
MSB
–
–
–
–
–
–
LSB
7.6.3 VMAX Register (04h)
•
•
•
Type: Read / write (see below)
Power-up value: 1.28 V (OTP value)
EN rising (after power-up): Last written value
b7
b6
b5
b4
b3
b2
b1
b0
Lock
MSB
–
–
–
–
–
LSB
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21
TPS53632
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www.ti.com.cn
Bit definitions:
BIT
NAME
DEFINITION
0 - 6
VMAX
Maximum VID setting
Access protection of the VMAX register
0: No protection, R/W access to bits 0-6
7
Lock
1: Access is read only; reset after UVLO event.
7.6.4 Power State Register (06h)
•
•
•
Type: Read and write
Power-up value: 00h
EN rising (after power-up): 00h
b7
b6
b5
b4
b3
b2
b1
b0
–
–
–
–
–
–
MSB
LSB
Bit definitions:
VALUE
DEFINITION
0
1
2
Multi-phase CCM
Single-phase CCM
Single-phase DCM
7.6.5 SLEW Register (07h)
•
•
•
•
Type: Read and write (see below)
Power-up value: Defined by SLEWA pin at power-up
EN rising (after power-up): Last written value
Write only a single ‘1’ for the SLEW rate desired
b7
b6
b5
b4
b3
b2
b1
b0
48 mV/µs
42mV/µs
36 mV/µs
30 mV/µs
24 mV/µs
18 mV/µs
12 mV/µs
6 mV/µs
7.6.6 Lot Code Registers (10-13h)
•
•
Type: 8-bits; read only
Power-up value: Programmed at factory
7.6.7 Fault Register (14h)
•
•
Type: 8-bits; read only
Power-up value: 00h
b7
b6
b5
b4
b3
b2
b1
b0
–
–
–
–
Device thermal
shutdown
OVP
UVP
OCP
22
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TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
8 Applications and Implementation
8.1 Application Information
The TPS53632 device has a very simple design procedure. A Microsoft Excel®-based component value
calculation tool is available. Please contact your local TI representative to get a copy of the spreadsheet.
8.2 Typical Application
8.2.1 3-Phase D-CAP+™, Step-Down Application
C26
0.1 µF
5V_DRV
VREF
C35 10 PF
C25
22 µF
R46
0 ꢀꢀ 0 ꢀꢀ
R40
IMON
R18
DNP
R9
1.47 Nꢀ
R14
DNP
R20
C36 10 PF
5
3
8
9
R152
DNP
169 N
RT1
10 N
R8
10 N
C1
3 x 10 µF
VIN
7
R83
30 N
R82
20 N
R2
10
R84
24 N
R5
C3
1 nF
12 PWM
11 NC
C5
680 nF
30.1 Nꢀ
VINTF
R142
R10
SLEWA
VIN_C
L1
300 nH
1.65 N
CSD95372A
Q1
10 Nꢀ
1
2
NC
NC
VSW
6
4
VOUT
R3
DNP
16
15
14
13
12
11
10
9
PGND
C57
16 x 22 µF
C14
4 x 470 µF
C31
DNP
10
17 CSP1
18 CSN1
19 CSN2
20 CSP2
21 CSP3
22 CSN3
23 GFB
EN
8
7
6
5
VR_ON
R21 0 ꢀ
SKIP
PWM1
PWM2
5V_DRV
C27
0.1 µF
TPS53632
U1
C29
22 µF
R49
0 ꢀꢀ 0 ꢀꢀ
R41
PWM3
4
R43
1.47 Nꢀ
R4 10 Nꢀ
3.3-V
5
3
8
9
GFB
VFB
PGOOD
VDD
3
2
1
PGOOD
3.3-V
RT2
10 N
C2
3 x 10 µF
Thermal Pad
VIN
7
24 VFB
R125
1 ꢀ
R11
30.1 Nꢀ
C6
1 nF
12 PWM
11 NC
C7
680 nF
SDA
R44
1.65 N
VDD
L2
300 nH
CSD95372A
Q2
C34
1 PF
25
26
27
28
29
30 31 32
1
2
NC
NC
VSW
6
4
VOUT
C145
DNP
R6
DNP
PGND
C13
DNP
10
R16
10 Nꢀ
R13
9.75 Nꢀ
R240
1 Nꢀ
R21 0 ꢀ
VINTF
R239
1 Nꢀ
5V_DRV
C37
DNP
R77
DNP
C28
0.1 µF
C24
VREF
0.1 PF
C30
22 µF
R52
0 ꢀꢀ 0 ꢀꢀ
R42
C33
0.33 PF
R73
1.47 Nꢀ
5
3
8
9
R22
0 ꢀ
R156 10 ꢀ C9 1 PF
RT5
10 N
5V_CON
C4
3 x 10 µF
VIN
7
VOUT
R5
R53
30.1 Nꢀ
C8
1 nF
12 PWM
11 NC
C10
680 nF
R74
1.65 N
10 ꢀ
L3
300 nH
CSD95372A
Q3
R52 0 ꢀ
VFB
To controller
GFB
VCPU_SENSE
1
2
NC
NC
VSW
6
4
VOUT
From processor
VSS_SENSE
R49 0 ꢀ
R133
DNP
PGND
R6
C18
DNP
10 ꢀ
10
R12 0 ꢀ
图 22. 3-Phase D-CAP+™, Step-Down Application with Power Stages
8.2.1.1 Design Requirements
Design example specifications:
•
•
•
•
•
Number of phases: 3
Input voltage range: 10 V to 14 V
VOUT = 1.0 V
ICC(max) = 80 A
Slew rate (minimum): 12 mV/µs
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TPS53632
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www.ti.com.cn
Typical Application (接下页)
•
Load-line = 1 mΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Step 1: Select Switching Frequency
The switching frequency is selected by a resistor (RF) between the FREQ_P pin and GND. The frequency is
approximate and expected to vary based on load and input voltage.
表 3. TPS53632 Device Frequency Selection Table
SELECTION
RESISTOR (RF) VALUE (kΩ)
OPERATING FREQUENCY
(fSW) (kHz)
20
24
300
400
500
600
700
800
900
1000
30
39
56
75
100
150
For this design, choose a switching frequency of 300 kHz. So, RF = 20 kΩ.
8.2.1.2.2 Step 2: Set The Slew Rate
A resistor to GND (RSLEWA) on SLEWA pin sets the slew rate. For a minimum 12 mV/µs slew rate, the resistor
RSLEWA = 24 kΩ.
表 4. Slew Rate Versus Selection Resistor
SELECTION RESISTOR
MINIMUM SLEW RATE
(mV/µs)
RSLEWA (kΩ)
20
24
6
12
18
24
30
36
42
48
30
39
56
75
100
150
注
The voltage on the SLEWA pin also sets the base address. For a base address of 00, the
SLEWA pin should have only one resistor, RSLEW to GND. For other base addresses, a
resistor can be connected between the SLEWA pin and the VREF pin (1.7 V). This
resistor can be calculated to set the corresponding voltage for the required address listed
in 表 5.
24
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TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
表 5. Address Selection
SLEWA
BASE
VOLTAGE
ADDRESS
VSLEWA ≤ 0.30 V
0
1
2
3
4
5
6
7
0.35 V ≤ VSLEWA ≤ 0.45 V
0.55 V ≤ VSLEWA ≤ 0.65 V
0.75 V ≤ VSLEWA ≤ 0.85 V
0.95 V ≤ VSLEWA ≤ 1.05 V
1.15 V ≤ VSLEWA ≤ 1.25 V
1.35 V ≤ VSLEWA ≤ 1.45 V
1.55 V ≤ VSLEWA ≤ 1.65 V
8.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor
Applications with smaller inductor values have better transient performance but also have higher voltage ripple
and lower efficiency. Applications with higher inductor values have the opposite characteristics. It is common
practice to limit the ripple current between 20% and 40% of the maximum current per phase. In this case, use
30%.
80 A
( )
3
IP-P
=
´ 0.4 = 10.6 (A)
(2)
(3)
V ´ dT
L =
I
P-P
In this equation,
V = V
- VOUT = 13V
IN max
(
)
(4)
(5)
VOUT
f ´ V
dT =
= 238ns
)
(
IN max
(
)
So, calculating, L = 0.29 µH.
Choose an inductance value of 0.3 µH. The inductor must not saturate during peak loading conditions.
I
æ
ç
ö
÷
CC max
(
I
)
P-P
I
=
+
´1.2 = 38.4A
SAT
ç
è
÷
ø
n
2
where
•
n is the number of phases
(6)
The factor of 1.2 allows for current sensing and current limiting tolerances.
The chosen inductor should have the following characteristics:
•
As flat as an inductance versus current curve as possible. Inductor DCR sensing is based on the idea L /
DCR is approximately a constant through the current range of interest
•
•
•
Either high saturation or soft saturation
Low DCR for improved efficiency, but at least 0.6 mΩ for proper signal levels
DCR tolerance as low as possible for load-line accuracy
For this application, choose a 0.3-µH, 0.29-mΩ inductor.
8.2.1.2.4 Step 4: Determine Current Sensing Method
The TPS53632 device supports both resistor sensing and inductor DCR sensing. Inductor DCR sensing is
chosen. For resistor sensing, substitute the resistor value for RCS(eff) in the subsequent equations.
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25
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
8.2.1.2.5 Step 5: DCR Current Sensing
Design the thermal compensation network and selection of OCP. In most designs, NTC thermistors are used to
compensate thermal variations in the resistance of the inductor winding. This winding is generally copper, and so
has a resistance coefficient of 3900 PPM/°C. NTC thermistors, as an alternative, have very non-linear
characteristics and need two or three resistors to linearize them over the range of interest. A typical DCR circuit
is shown in 图 23.
L
RDCR
I
RSEQU
RNTC
RSERIES
RPAR
CSENSE
CSP
CSN
UDG-12199
图 23. Typical DCR Sensing Circuit
In this design example, the voltage across the CSENSE capacitor exactly equals the voltage across RDCR when:
.
F %5'05' × 4'3
4&%4
(7)
42_0
4'3
=
45'37 F42_0
where
•
REQ is the series (or parallel) combination of RSEQU, RNTC, RSERIES and RPAR
(8)
(9)
:
;
42#4 × 406% + 45'4+'5
42_0
=
42#4 + 406% + 45'4+'5
Ensure that CSENSE is a capacitor type which is stable over temperature. Use X7R or better dielectric (C0G
preferred).
Because calculating these values by hand is difficult, TI offers a spreadsheet using the Excel solver function
available to calculate them for you. Contact a TI representative to get a copy of the spreadsheet.
In this design, the following values are input to the spreadsheet.
•
•
•
•
L = 0.3 µH
RDCR = 0.29 mΩ
Minimum Overcurrent Limit = 110 A
Thermistor R25 = 10 kΩ and “B” value = 3380 kΩ
The spreadsheet then calculates the OCP setting and the values of RSEQU, RSERIES, RPAR, and CSENSE. In this
case, the OCP setting is the value of the resistor that is conencted between the OCP-I pin and GND. (100 kΩ )
The nearest standard component values are:
•
RSEQU = 1.47 kΩ
26
版权 © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
•
•
•
RSERIES = 1.65 kΩ
RPAR = 30.1 kΩ
CSENSE = 680 nF
Consider the effective divider ratio for the inductor DCR. 公式 10 shows the effective current sense resistance
(RCS(eff) calculation.
42_0
4%5 ABB = 4
×
:
;
&%4
45'37 + 42_0
(10)
(11)
RP_N is the series and parallel combination of RNTC, RSERIES, and RPAR
.
:
;
42#4 × 406% + 45'4+'5
42_0
=
42#4 + 406% + 45'4+'5
RCS(eff) is 0.244 mΩ.
8.2.1.2.6 Step 6: Select OCP Level
Set the OCP threshold level that corresponds to 公式 12.
+
× 4%5 ABB; = 8
: :
%5 K?L
;
8#..';
(12)
(13)
+
+
=
1%2 F 0.5 F +4+22.'
8#..';
02*
表 6. OCP Selection(1)
SELECTION RESISTOR
TYPICAL VCS(OCP)
(mV)
ROCP (kΩ)
20
24
4
8
30
13
19
25
32
40
49
39
56
75
100
150
(1) If a corresponding match is not found, then select the next higher
setting.
8.2.1.2.7 Step 7: Set the Load-Line Slope
The load-line slope is set by resistor, RDROOP (between the DROOP pin and the COMP pin) and resistor RCOMP
(between the COMP pin and the VREF pin). The gain of the DROOP amplifier (ADROOP) is calculated in 公式 14.
æ
ç
ç
è
ö
R
(
CS(eff) ´ ACS
æ
ö
÷
÷
ø
)
æ
ç
è
ö
÷
ø
RDROOP
0.244m´ 6
1.0m
÷
ADROOP = 1+
=
=
= 1.46
ç
ç
è
÷
ø
RCOMP
RLL
(14)
(15)
Set the value of RDROOP to 10 kΩ, RCOMP as shown in 公式 15.
RDROOP
RCOMP
=
= 21.5kW
A
-1
(
)
DROOP
Based on measurement, this value is adjusted to 9.75 kΩ.
注
See Loop Compensation for Zero Load-Line for zero-load line.
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8.2.1.2.8 Step 8: Current Monitor (IMON) Setting
Set the analog current monitor so that at ICC(max) the IMON pin voltage is 1.7 V. This corresponds to a digital IOUT
value of ‘FF’ in I2C register 03H. The voltage on the IMON pin is shown in 公式 16.
:
;
ìÜØß×æ
ꢀH Í 8¼Ìá 1ÛÛÛ. 8
4ÂÆÈÇ
8
ÂÆÈÇ
L sr H s E
:
;
4ȼÉ
(16)
So,
4+/10
41%2
1.7 = 10 × l1 +
p × 4%5 ABB; × +
:
%%(I=T )
where
•
•
•
ICC(max)is 80 A
RCS(eff) is 0.244 mΩ
ROCP is 24 kΩ
(17)
Solving, RIMON = 169 kΩ. RIMON is connected from IMON pin to OCP-I pin.
28
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ZHCSCU1 –SEPTEMBER 2014
8.2.1.3 Application Performance Plots
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
100.0
98.0
96.0
94.0
92.0
90.0
88.0
86.0
84.0
82.0
80.0
Vin = 10 V
Vin = 12 V
Vin = 14 V
Vin = 10 V
Vin = 12 V
Vin = 14 V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
IOUT (A)
IOUT (A)
C001
C002
图 24. Output Voltage vs Output Current
图 25. Efficiency vs Output Current
320
310
300
290
280
270
260
250
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vin = 10 V
Vin = 10 V
Vin = 12 V
Vin = 14 V
Vin = 12 V
Vin = 14 V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
IOUT (A)
IOUT (A)
C003
C004
图 26. Switching Frequency vs Output Current
图 27. IMON Voltage vs Output Current
版权 © 2014, Texas Instruments Incorporated
29
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
8.2.1.4 Loop Compensation for Zero Load-Line
The TPS53632 device control architecture (current mode, constant on-time) has been analyzed by the Center for
Power Electronics Systems (CPES) at Virginia Polytechnic and State University. The following equations are
from the presentation: Equivalent Circuit Representation of Current-Mode Control from November 21, 2008.
A simplified control loop diagram is shown in 图 28. One of the benefits of this technology is the lack of the
sample and hold effect that limits the bandwidth of fixed frequency current mode controllers and causes sub-
harmonic oscillations.
The open loop gain, GOL, is the gain of the error amplifier, multiplied by the control-to-output gain and is
calculated in 公式 18.
)
1.
= )%1/2 × )%1
(18)
The control-to-output gain circuitry is shown in 图 28.
COMP
DROOP
Current Sense
Amplifier
R1
DAC
+
+
Voltage
Amplifier
C2
ESR
C1
ISUM
C1
RLOAD
R2
VREF
图 28. Control To Output Gain Circuitry
The control-to-output gain is calculated in 公式 19.
:
;
R1
R%
1
ñ × 4'54 × %176 + 1
= -% ×
×
ñ
ñ2
A + l 2p
ñ1
ñ
@
A + 1
1 + @
ñ=
31 × ñ1
where
4
@
.1#& A
4E
-% =
P10 × 4
1 + @
.1#& A
2 × .5
•
•
•
è
P10
2
ñ1 =
31 =
è
8176
8 × B
59
P10
=
•
+0
P10 × 4
1 + @
.1#& A
2 × .5
ñ= =
P10 × 4
4.1#& × %176 × F1 + @
.1#& AG
2 × .5
•
(19)
30
版权 © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
For this converter, Ri = RCS(eff) × ACS
The theoretical control-to-output transfer function shows 0-dB bandwidth is approximately 20 kHz and the phase
margin is greater than 90°. As a result, creating the desired loop response is a matter of adding an appropriate
pole-zero or pole-zero-pole compensation for the high-gain system.
The loop compensation is designed to meet the following criteria:
1. Phase margin ≥ 60°
(a) More stable and settles more quickly for repetitive transients
B
B
59
59
R $9 R
2. Bandwidth:
5
3
(a) High-enough BW for good transient response.
(b) If too high, the response for the voltage changes gets very “bumpy”, as each voltage step causes several
pulses very quickly.
3. The phase angle of the compensation at the switching frequency needs to be very near to 0 degrees
(resistive)
(a) Otherwise, there is a phase shift between DROOP and ISUM
(b) Practically, this means the zero frequency should be < fSW / 2, and any high-frequency pole (for noise
rejection) needs to be > 2 × fSW
.
The voltage error amplifier is used in the design. The compensation technique used here is a type II
compensator. 公式 20 describes the transfer function, which has a pole that occurs at the origin. The type II
amplifier also has a 0 (fZ) that can be programmed by selecting R1 and C1 values. In addition, the type II
compensation network has a pole (fP) that can be programmed by selecting R1 and C2.
1
(O × 41 × %1 + 1)
%1 × %2
)
%1/2
=
×
:
;
O × %1 + %2 × 42
O × 41 × @
A + 1
%1 + %2
(20)
(21)
1
B =
<
2è × 41 × %1
1
B =
2
%1 × %2
%1 + %2
2è × 41 ×
(22)
R1 sets the loop crossover to correct for the gain at control to output function. In this design, select R2 = 2 kΩ.
-G
æ
ö
CO fc
( )
-10dB
20
æ
ö
ç
ç
è
÷
÷
ø
-
ç
è
÷
ø
20
R1= R2´10
= 2kW´10
(23)
Capacitor C1 adds phase margin at crossover frequency and can be set between 10% and 20% of the switching
frequency.
1
C1=
2p´ f
´ 0.1´R1
SW
(24)
The last consideration for the voltage loop compensation design is C2. The purpose of C2 is to cancel the phase
gain caused by the ESR of the output capacitor in the control-to-output function after the loop crossover. To
ensure the gain continues to roll off after the voltage loop crossover, the C2 is selected to meet 公式 25.
COUT ´ESR
C2 =
R1
(25)
9 Power Supply Recommendations
This device is designed to operate from a supply voltage at the V5A pin (5-V power input for analog circuits) from
4.5 V to 5.5 V and a supply voltage at the VDD pin (3.3-V digital power input) from 3.1 V to 3.5 V, and a supply
voltage at the VINTF pin from 1.7 V to 3.5 V. Use only a well-regulated supply. The VIN pin input must be
connected to the conversion input voltage and must not exceed 28 V. Proper bypassing of the V5A and VDD
input supplies is critical for noise performance, as is PCB layout and grounding scheme. See the
recommendations in the Layout section.
版权 © 2014, Texas Instruments Incorporated
31
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
10.1.1 PCB Layout
•
•
•
•
•
Check the pinout of the controller on schematic against the pinout of the datasheet.
Have a component value calculator tool ready to check component values.
Carefully check the choice of inductor and DCR.
Carefully check the choice of output capacitors.
Because the voltage and current feedback signals are fully differential, double check their polarity.
–
–
–
–
CSP1 / CSN1
CSP2 / CSN2
CSP3 / CSN3
VOUT_SENSE to VFB / GND_SENSE to GFB
•
•
Make sure the pull-up on the SDA, and SCL lines are correct. Ensure there is a bypass capacitor close to the
device on the pull-up VINTF rail to GND of the device.
TI strongly recommends that the device GND be separate from the system and Power GND.
Most Critical Layout Rule
Make sure to separate noisy driver interface lines.
The driver (TPS51604) is outside of the device. All gate-drive and switch-node traces must be local to the
inductor and MOSFETs.
10.1.2 Current Sensing Lines
Given the physical layout of most systems, the current feedback (CSPx and CSNx) may have to pass near the
power chain.
Noisy
Quiet
Inductor
Outline
LLx
VCORE
CSNx
CSPx
R
SEQ
R
SERIES
Thermistor
UDG-12198
图 29. Kelvin Connections To The Inductor For DCR Sensing
32
版权 © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
Layout Guidelines (接下页)
Good load-line, current sharing, and current limiting performance of the TPS53632 device requires clean current
feedback, so take the following precautions:
•
•
•
•
•
•
•
Ensure all vias in the CSPx and CSNx traces are isolated from all other signals.
TI recommends dotted signal traces be run in internal planes.
If possible, change the name of the CSNx trace if possible to prevent automatic ties to the VCORE plane.
Put RSEQU at the boundary between noisy and quiet areas.
Run CSPx and CSNx as a differential pair in a quiet layer.
Place the capacitor as near to the device pins as possible.
Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See 图 29 for a
layout example.
•
•
•
•
Run the current feedback signals as a differential pair to the device.
Run the lines in a quiet layer. Isolate the lines from noisy signals by a voltage or ground plane.
Put the compensation capacitor for DCR sensing (CSENSE) as close to the CS pins as possible.
Place any noise filtering capacitors directly under or near the TPS53632 device and connect to the CS pins
with the shortest trace length possible.
10.1.3 Feedback Voltage Sensing Lines
The voltage feedback coming from the CPU socket must be routed as a differential pair all the way to the VFB
and GFB pins of the TPS53632 device. Avoid routing over switch-node and gate-drive traces.
10.1.4 PWM And SKIP Lines
The PWM and SKIP lines should be routed from the TPS53632 device to the driver without crossing any switch-
node or the gate drive signals.
10.1.4.1 Minimize High Current Loops
图 30 shows the primary current loops in each phase, numbered in order of importance.
VBAT
CIN
CB
1
Q1
4b
DRVH
4a
L
VCORE
LL
2
Q2
CD
DRVL
3a
COUT
3b
PGND
UDG-12191
图 30. Major Current Loops To Minimize
The most important loop to minimize the area of is loop 1, the path from the input capacitor through the high and
low-side FETs, and back to the capacitor through ground.
版权 © 2014, Texas Instruments Incorporated
33
TPS53632
ZHCSCU1 –SEPTEMBER 2014
www.ti.com.cn
Layout Guidelines (接下页)
Loop 2 is from the inductor through the output capacitor, ground, and Q2. The layout of the low-side gate drive
(Loops 3a and 3b) is important. The guidelines for the gate drive layout are:
•
•
•
Make the low-side gate drive as short as possible (1 in or less preferred).
Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.
If changing layers is necessary, use at least two vias.
10.1.5 Power Chain Symmetry
The TPS53632 device does not require special care in the layout of the power chain components because
independent isolated current feedback is provided. Lay out the phases in a symmetrical manner, if possible. The
rule is: the current feedback from each phase needs to be clean of noise and have the same effective current-
sense resistance.
10.1.6 Component Location
Place components as close to the device in the following order.
1. CS pin noise filtering components
2. COMP pin and DROOP pin compensation components
3. Decoupling capacitors for VREF, VDD, V5A, and VINTF
4. Decoupling capacitor for VINTF rail, which is pullup voltage for the digital lines. This decoupling should be
placed near the device to have good signal integrity.
5. OCP-I resistors, FREQ_P resistors, SLEWA resistors, and RAMP resistors
10.1.7 Grounding Recommendations
The TPS53632 device has an analog ground and a thermal pad. The usual procedure for connecting these is:
•
Keep the analog GND of the device and the power GND of the power circuit separate. The device analog
GND and the power circuit power GND can be connected at one single quiet point in the layout.
•
The thermal pad does not have an electrical connection to device. But the thermal pad must be connected to
GND pin (pin 29) of the device to give good ground shielding. Do not connect the thermal pad to system
GND.
•
•
Tie the thermal pad to a ground island with at least 4 vias. All the analog components can connect to this
analog ground island.
The analog ground can be connected to any quiet spot on the system ground. A quiet spot is defined as a
spot where no power supply switching currents are likely to flow. Use a single point connection from analog
ground to the system ground.
•
Ensure that the low-side MOSFET source connection and the input decoupling capacitors have a sufficient
number of vias.
10.1.8 Decoupling Recommendations
•
•
Decouple V5A and VDD to GND with a ceramic capacitor (with a value of at least 1 µF) .
Decouple VINTF to GND with a capacitor (with a value of at least 0.1 µF) to GND.
10.1.9 Conductor Widths
•
•
•
Follow TI guidelines with respect to the voltage feedback and logic interface connection requirements.
Maximize the widths of power, ground, and drive signal connections.
For conductors in the power path, be sure there is adequate trace width for the amount of current flowing
through the traces.
•
Make sure there are sufficient vias for connections between layers. Use 1 via minimum per ampere of current.
34
版权 © 2014, Texas Instruments Incorporated
TPS53632
www.ti.com.cn
ZHCSCU1 –SEPTEMBER 2014
10.2 Layout Example
1.8 V and IMON to GND
decoupling capacitor
PWM
signals
Differential routing
of CSP and CSN in
quiet internal layers.
V5A, VREF, VCCIO
and VDD decoupling
capacitor to analog GND
Differential routing
of VFB and GFB
I2C Interface
signals
Compensation
Network
图 31. Example Layout
11 器件和文档支持
11.1 商标
针对快速瞬态响应提供 D-CAP+, AutoBalance are trademarks of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS53632RSMR
TPS53632RSMT
ACTIVE
VQFN
VQFN
RSM
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 105
-10 to 105
TPS
53632
ACTIVE
RSM
NIPDAU
TPS
53632
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
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