TPS536C7B1RSLR_技术文档

TPS536C7

SLUSDI9 – SEPTEMBER 2020

TPS536C7B1 Dual-Channel D-CAP+™, Dual-Channel (N+M ≤ 12 Phases)

Step-Down, Multiphase Controller with PMBus^™Interface

1 Features

3 Description

•

Input Voltage Range: 4.5 V to 18 V

The TPS536C7B1 is a step-down controller with

dual channels, built-in non-volatile memory (NVM),

and PMBus interface, and is fully compatible with

TI NexFET^™smart power stages. Advanced control

features such as the D-CAP+ architecture provide

fast transient response, low output capacitance, and

good current sharing. The device also provides

a novel phase interleaving strategy and flexible

firing order. Adjustable control of output voltage

slew rate and adaptive voltage positioning are

also supported. In addition, the device supports

the PMBus communication interface for reporting

telemetry of voltage, current, power, temperature, and

fault conditions to the system host. All programmable

parameters can be configured by the PMBus

interface, and can be stored in NVM as the new

default values to minimize the external component

count.

Output Voltage Range: 0.25 V to 5.5 V

Per-phase switching frequency range: 300 kHz to

2000 kHz

Dual Output Supporting N+M Phase

Configurations (N+M ≤ 12, M ≤ 6)

PMBus v1.3.1 system interface for configuration,

control and telemetry of voltage, current, power,

temperature, and fault status

Adaptive voltage scaling (AVS) through

VOUT_COMMAND

Enhanced D-CAP+ control to provide super

transient performance with excellent dynamic

current sharing

Programmable loop compensation

Flexible phase-firing order

External pinstrap for Ch. A boot voltage settings

Individual phase current calibrations and reporting

Phase thermal balance management (TBM)

Full support for dynamic phase shedding (DPS)

Fast phase-adding for undershoot reduction (USR)

Body-diode braking for overshoot reduction (OSR)

Driverless Configuration for efficient high-

frequency switching

Fully Compatible with TI NexFET^™power stage for

high-density solutions

Accurate, Programmable Adaptive Voltage

Positioning (AVP)

Patented AutoBalance^™Phase Balancing

6 mm × 6 mm, 48-Pin, QFN Package

•

The TPS536C7B1 device if offered in a thermally

enhanced 48-pin QFN packaged and is rated to

operate from –40°C to 125°C.

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

TPS536C7B1

QFN (48)

6 mm × 6 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

TPS536C7B1

PWM1

Power

2 Applications

Stage

CSP1

•

Data center network switches

Campus and branch switches

Core and edge routers

Hardware accelerator cards

High performance CPU/ASIC/FPGA power

PWM2

CSP2

PMBus

Power

Stage

PWM12

CSP12

Power

Stage

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS536C7

SLUSDI9 – SEPTEMBER 2020

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Electrical Specifications.............................................. 7

6.5 Typical Characteristics..............................................32

7 Detailed Description......................................................33

7.1 Overview...................................................................33

7.2 Functional Block Diagram.........................................33

7.3 Power-up and initialization........................................34

7.4 Pin connections and bevahior...................................35

7.5 Advanced power management functions..................46

7.6 Control Loop Theory of Operation............................ 57

7.7 Power supply fault protection....................................63

7.8 Device Functional Modes..........................................77

7.9 Programming............................................................ 79

8 Application and Implementation................................127

8.1 Typical Application.................................................. 127

9 Power Supply Recommendations..............................141

10 Layout.........................................................................142

11 Mechanical, Packaging, and Orderable

Information.................................................................. 145

11.1 Tape and Reel Information....................................146

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

September 2020

*

Initial Release

2

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5 Pin Configuration and Functions

36

35

34

33

32

31

30

29

28

27

26

25

APWM12 / BPWM1

APWM11 / BPWM2

APWM10 / BPWM3

APWM9 / BPWM4

APWM8 / BPWM5

APWM7 / BPWM6

1

2

ACSP10 / BCSP3

TPS536C7B1

ACSP9 / BCSP4

ACSP8 / BCSP5

ACSP7 / BCSP6

ACSP6

3

4

5

Thermal

Pad

ACSP5

6

ACSP4

APWM6

APWM5

APWM4

APWM3

APWM2

APWM1

7

ACSP3

8

ACSP2

9

ACSP1

10

11

12

AVSN

AVSP

Figure 5-1. RSL Package 48-Pin QFN Top View

Table 5-1. Default functionality of multifunction pins

DEFAULT

1, 2, 3, 4, 5, 6, 33, 34, 35, 36, 37, 38

Based on ADDR_CONFIG pinstrap resistors

19

43

44

BVR_EN

BTSEN

ATSEN

Pin Functions

I/O

DESCRIPTION

NAME

ACSP1

ACSP2

ACSP3

ACSP4

ACSP5

ACSP6

NO.

27

28

29

30

31

32

33

I

Current sense input for channel A. Connect to the IOUT pin of TI smart power stages. Float unused

CSP pins.

ACSP7 / BCSP6

Current sense input for phase 7 of channel A or phase 6 of channel B. Float unused CSP pins.

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

34

35

36

37

38

ACSP8 / BCSP5

ACSP9 / BCSP4

ACSP10 / BCSP3

ACSP11 / BCSP2

ACSP12 / BCSP1

I

Current sense input for phase 8 of channel A or phase 5 of channel B. Float unused CSP pins.

Current sense input for phase 9 of channel A or phase 4 of channel B. Float unused CSP pins.

Current sense input for phase 10 of channel A or phase 3 of channel B. Float unused CSP pins.

Current sense input for phase 11 of channel A or phase 2 of channel B. Float unused CSP pins.

Current sense input for phase 12 of channel A or phase 1 of channel B. Float unused CSP pins.

Connect a voltage divider from VREF to ADDR_CONFIG to GND. The value of the resistor

between this pin and ground selects the phase configuration, and the pin voltage selects the

PMBus address. Both are latched at VCC power-up. See Pinstrapping for more information. Use

the PIN_DETECT_OVERRIDE command to select options which are not available by pinstrapping.

ADDR_CONFIG

42

I

PWM signal for phase 1 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM1

12

11

10

9

O

PWM signal for phase 2 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM2

PWM signal for phase 3 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM3

PWM signal for phase 4 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM4

PWM signal for phase 5 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM5

8

PWM signal for phase 6 of channel A. Connect to the PWM pin of the TI smart power stage. Float

unused PWM pins.

APWM6

7

PWM signal for phase 7 of channel A, or phase 6 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

APWM7 / BPWM6

APWM8 / BPWM5

APWM9 / BPWM4

6

PWM signal for phase 8 of channel A, or phase 5 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

5

PWM signal for phase 9 of channel A, or phase 4 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

4

APWM10 /

BPWM3

PWM signal for phase 10 of channel A, or phase 3 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

3

APWM11 /

BPWM2

PWM signal for phase 11 of channel A, or phase 2 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

2

APWM12 /

BPWM1

PWM signal for phase 12 of channel A, or phase 1 of channel B. Connect to the PWM pin of the TI

smart power stage. Float unused PWM pins.

1

Multi-function pin. Configure through PMBus.

ATSEN (default): Connect to the TAO pin of the TI smart power stages of channel A to sense the

highest temperature of the power stages and to sense the built-in fault signal from the power stages.

BTSEN: Connect to the TAO pin of the TI smart power stages of channel B to sense the highest

temperature of the power stages and to sense the built-in fault signal from the power stages.

Float unused TSEN pins.

ATSEN / BTSEN

44

I

Active high enable input for channel A. By default, asserting the AVR_EN pin activates channel A.

Polarity and enable conditions are programmable through ON_OFF_CONFIG.

AVR_EN

17

16

I

VRD "Ready" output signal of channel A. This open drain output requires an external pull-up resistor.

The AVR_RDY pin is pulled low when a shutdown event occurs.

AVR_RDY

O

AVSN

AVSP

26

25

I

Negative input of the remote voltage sense of channel A.

Positive input of the remote voltage sense of channel A.

Multi-function pin. Configure through PMBus.

BTSEN (default): Connect to the TAO pin of the TI smart power stages of channel B to sense the

highest temperature of the power stages and to sense the built-in fault signal from the power stages.

BTSEN: Connect to the TAO pin of the TI smart power stages of channel A to sense the highest

temperature of the power stages and to sense the built-in fault signal from the power stages.

TSEN: Connect to the TAO pin of the TI smart power stages of channels A and B to sense the highest

temperature of the power stages and to sense the built-in fault signal from the power stages.

Float unused TSEN pins.

BTSEN . / ATSEN /

TSEN

43

I

4

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NAME

Pin Functions (continued)

I/O

DESCRIPTION

NO.

Multi-function pin. Configure through PMBus.

BVR_EN (Default) : Active high enable input for channel B. Asserting the BVR_EN pin activates

channel B. Polarity and enable conditions are programmable through ON_OFF_CONFIG.

RESET#: Active low signal which causes both channels output voltage target to revert to their

respective VBOOT values when asserted. Pull-up to 3.3 V.

SYNC: If assigned as an output, this pin provides a free-running clock for other TPS536C7B1 devices

to synchronize to. If assigned as an input, an internal phase locked-loop can synchronize switching of

one or both channels to a clock supplied to this pin. Phase shift and data direction are programmable

through NVM.

BVR_EN /

RESET# / SYNC

19

I

VRD "Ready" output signal of channel B. This open drain output requires an external pull-up resistor.

The BVR_RDY pin is pulled low when a shutdown event occurs.

BVR_RDY

BVSN

20

39

40

O

I

Negative input of the remote voltage sense of channel B. If channel B is not used, connect BVSN to

GND.

Positive input of the remote voltage sense of channel B. If channel B is not used, connect BVSP to

GND.

BVSP

I

Positive terminal of the integrated high-side current sensing amplifier. Connect to the supply side of

the input current sense element. Tie to VIN_CSNIN, and to the input voltage, if measured input current

sensing is not used.

CSPIN

NC

45

I

21

22

23

24

15

14

13

-

Do not connect.

-

SMB_ALERT#

SMB_CLK

O

SMBus or I²C bi-directional alert pin interface. (Open drain)

SMBus or I²C serial clock interface. (Open drain)

I

SMB_DIO

I/O SMBus or I²C bi-directional serial data interface. (Open drain)

Connect a resistor divider from VREF to VBOOT_CHA to GND. Pinstrap for Channel A boot

VBOOT_CHA

VCC

18

47

46

I

P

I

voltage. The value is latched at VCC power-up. See Pinstrapping for more information. Use the

PIN_DETECT_OVERRIDE command to select options which are not available by pinstrapping.

3.3-V power input. Bypass to GND with a ceramic capacitor with a value greater than or equal to 1 µF

effective capacitance.

Negative terminal of the integrated high-side current sense amplifier. Connect to the power-stage side

of the current sense element. The VIN_CSNIN voltage is also used to determine the correct on-time

for the converter. Tie to CSPIN, and to the input voltage, if measured input current sensing is not used.

VIN_CSNIN

1.5-V LDO reference voltage. Bypass to GND with a minimum effective 1-µF ceramic capacitor.

Connect the VREF pin to the REFIN pin of the TI smart power stages as the current sense common-

mode voltage.

VREF

48

41

O

VR fault indicator. (Open-drain). This alert pulls low to indicate the converter has experienced

a potentially catastrophic fault. The failures include the high-side FETs short, over-voltage, over-

temperature, and the input over-current conditions. Use the fault signal on the platform to remove the

power source by turning off the AC power supply. When the failure occurs, the VR_FAULT# pin is

LOW, and put the controller into latch-off mode.

VR_FAULT#

Thermal Pad

O

G

Analog ground pad. Connect to GND plan with vias.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

CSPIN, VIN_CSNIN

–0.3

19

Pin voltage, duration less than 100 ns

ACSP1, ACSP2, ACSP3, ACSP4, ACSP5, ACSP6, ACSP7 / BCSP6, ACSP8 /

BCSP5, ACSP9 / BCSP4, ACSP10 / BCSP3, ACSP11 / BSPC2, ACSP12 /

BCSP1, ADDR_CONFIG, ATSEN / BTSEN, AVR_EN, AVSP, VBOOT_CHA,

BTSEN / ATSEN / TSEN, BVSP, BVR_EN, SMB_CLK, SMB_DIO, SYNC,

RESET#, VCC

-0.3

5.0

3.6

Input voltage ^{(1) (2)}

V

Pin voltage, duration greater than or equal to 100 ns

ACSP1, ACSP2, ACSP3, ACSP4, ACSP5, ACSP6, ACSP7 / BCSP6, ACSP8 /

BCSP5, ACSP9 / BCSP4, ACSP10 / BCSP3, ACSP11 / BSPC2, ACSP12 /

BCSP1, ADDR_CONFIG, ATSEN / BTSEN, AVR_EN, AVSP, VBOOT_CHA,

BTSEN / ATSEN / TSEN, BVSP, BVR_EN, SMB_CLK, SMB_DIO, SYNC,

RESET#, VCC

–0.3

AGND, AVSN, BVSN

–0.3

0.3

5.0

Pin voltage, duration less than 100 ns

APWM1, APWM2, APWM3, APWM4, APWM5, APWM6, APWM7 / BPWM6,

APWM8 / BPWM5, APWM9 / BPWM4, APWM10 / BPWM3, APWM11 / BPWM2,

APWM12 / BPWM1, AVR_RDY, BVR_RDY, SMB_ALERT#, SYNC, VR_FAULT#

Output voltage ^{(1) (2)}Pin voltage, duration greater than or equal to 100 ns

APWM1, APWM2, APWM3, APWM4, APWM5, APWM6, APWM7 / BPWM6,

V

–0.3

3.6

APWM8 / BPWM5, APWM9 / BPWM4, APWM10 / BPWM3, APWM11 / BPWM2,

APWM12 / BPWM1, AVR_RDY, BVR_RDY, SMB_ALERT#, SYNC, VR_FAULT#

VREF

–0.3

–40

–55

1.8

150

Operating junction temperature, T_J

Storage temperature, T_STG

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

4.5

NOM

12

MAX

18

UNIT

CSPIN, VIN_CSNIN

VCC

2.97

3.3

3.6

ACSP1, ACSP2, ACSP3, ACSP4, ACSP5, ACSP6, ACSP7 /

BCSP6, ACSP8 / BCSP5, ACSP9 / BCSP4, ACSP10 / BCSP3,

ACSP11 / BSPC2, ACSP12 / BCSP1, ADDR_CONFIG, ATSEN /

BTSEN, AVR_EN, AVSP, VBOOT_CHA, BTSEN / ATSEN / TSEN,

BVSP, BVR_EN, SMB_CLK, SMB_DIO, SYNC, RESET#

Input voltage

V

–0.1

3.6

0.1

AGND, AVSN, BVSN

6

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MIN

NOM

MAX

UNIT

V

VREF

–0.1

1.52

APWM1, APWM2, APWM3, APWM4, APWM5, APWM6, APWM7 /

BPWM6, APWM8 / BPWM5, APWM9 / BPWM4, APWM10 /

BPWM3, APWM11 / BPWM2, APWM12 / BPWM1, AVR_RDY,

BVR_RDY, SMB_ALERT#, SYNC, VR_FAULT#

Output voltage

–0.1

–40

3.6

Ambient temperature, T_A

125

°C

6.4 Electrical Specifications

6.4.1 Thermal Information

TPS536C7B1

THERMAL METRIC⁽¹⁾

RSL (VQFN)

48 PINS

25.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

14.8

7.9

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Y_JB

7.8

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4.2 Supply

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply: Currents, UVLO, and Power-On Reset

VCC supply current with all phases

active

I_VCC

Enable = 'HI '

100

mA

V_CCNORMAL

V_CCUVLOH

V_CCUVLOL

V_CCUVLOH

VCC Normal Range

Normal operation

Ramp up

2.97

2.92

2.68

138

3.6

2.97

2.82

600

V

VCC UVLO 'OK ' Threshold

VCC UVLO Fault Threshold

VCC UVLO Hysteresis

Ramp down

Hyseteresis

V

mV

6.4.3 DAC and Voltage Feedback

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

References: DAC and VREF

ULINEAR16, Absolute,

N = -10 exponent

V_MODE

Supported VOUT_MODE

VDAC range

VOUT_MODE = 16h

-

No external divider.

VOUT_MAX ≤ 1.87 V

V_DACRNG

0.25

0.50

1.87

V

Ω

No external divider

VOUT_MAX > 1.87 V

3.74

External resistor for output voltage

scaling with Vout > 3.74 V

R_DIV

VOUT to VSP resistor

500

VSP to VSN resistor

Ω

mV

%

V_DAC

VSP accuracy

0.25 ≤ VSP ≤ 1 V, I_CORE= 0A

1 V < VSP ≤ 1.87 V; I_CORE= 0A

1.87 V < VSP ≤ 5 V; I_CORE= 0A

VCC = 2.97 V to 3.6 V, I_VREF= 0

I_VREF= 0A to 10 mA

-5

-0.5

-1

5

0.5

1

%

V_VREF

VREF output accuracy

1.493

-8

1.5

1.507

V

V_VREF(REG)

VREF load regulation (sourcing)

mV

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

VREF load regulaiton (sinking)

Vout offset NVM resolution ⁽¹⁾

I_VREF= -10 mA to 0A

8

V_TRIM(RES)

MFR_SPECIFIC_ED[13:12] = 00b

MFR_SPECIFIC_ED[13:12] = 01b

MFR_SPECIFIC_ED[13:12] = 10b

MFR_SPECIFIC_ED[13:12] = 11b

VOUT_TRIM in SLINEAR16 format

0.9765

1.9531

3.9063

7.8125

mV

V_TRIM(RNG)

Vout offset NVM range ⁽¹⁾

-128

127

50

LSB

Voltage Sense: AVSP/BVSP and AVSN/BVSN

Not in Fault, Disable or UVLO;

AVSP = VDAC = 1.8 V

AVSN = 0 V

I_AVSP

I_AVSN

I_BVSP

I_BVSN

AVSP Input Bias Current

AVSN Input Bias Current

BVSP Input Bias Current

BVSN Input Bias Current

µA

Not in Fault, Disable or UVLO;

AVSP = VDAC = 1.8 V,

AVSN = 0 V

-55

Not in Fault, Disable or UVLO;

BVSP = VDAC = 1.8 V,

BVSN = 0 V

50

Not in Fault, Disable or UVLO;

BVSP = VDAC = 1.8 V,

BVSN = 0 V

(1) Guaranteed by Design.

6.4.4 Control Loop Parameters

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Programmable Loadline and Loop Compensation

R_DCLL(RES)

DC load line resolution

VOUT_DROOP = 0 to 1 mΩ

VOUT_DROOP = 1 to 2 mΩ

VOUT_DROOP = 2 to 4 mΩ

VOUT_DROOP = 4 to 8 mΩ

VOUT_DROOP > 0.3 mΩ

7.8125

15.625

31.25

62.5

µΩ

%

R_DCLL(ACC)

R_ACLL(RES)

DC load line accuracy

-2.5

2.5

USER_DATA_01[47:32] = 0 to 1.0 mΩ

(program in SLINEAR11 format)

AC loadline resolution ⁽¹⁾

15.625

31.25

62.5

µΩ

USER_DATA_01[47:32] = 1 to 2 mΩ

(program in SLINEAR11 format)

USER_DATA_01[47:32] = 2 to 4 mΩ

(program in SLINEAR11 format)

USER_DATA_01[47:32] = 4 to 8 mΩ

(program in SLINEAR11 format)

125

R_ACLL(RES)

t_INT

AC loadline accuracy ⁽¹⁾

AC loadline > 0.3 mΩ

-5

0.9

1.8

2.7

3.6

4.5

5.4

6.3

7.2

8.1

9

5

1.1

2.2

3.3

4.4

5.5

6.6

7.7

8.8

9.9

11

%

µs

Static integration-time constant ⁽¹⁾

USER_DATA_01[23:20] = 0000b

USER_DATA_01[23:20] = 0001b

USER_DATA_01[23:20] = 0010b

USER_DATA_01[23:20] = 0011b

USER_DATA_01[23:20] = 0100b

USER_DATA_01[23:20] = 0101b

USER_DATA_01[23:20] = 0110b

USER_DATA_01[23:20] = 0111b

USER_DATA_01[23:20] = 1000b

USER_DATA_01[23:20] = 1001b

USER_DATA_01[23:20] = 1010b

1

2

3

4

5

6

7

8

9

10

11

9.9

12.1

8

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_01[23:20] = 1011b

USER_DATA_01[23:20] = 1100b

USER_DATA_01[23:20] = 1101b

USER_DATA_01[23:20] = 1110b

USER_DATA_01[23:20] = 1111b

MIN

10.8

11.7

12.6

13.5

14.4

0.8

TYP

12

13

14

15

16

1

MAX

13.2

14.3

15.4

16.5

17.6

1.2

UNIT

µs

t_DINT

Dynamic integration-time constant ⁽¹⁾USER_DATA_01[27:24] = 0000b

USER_DATA_01[27:24] = 0001b

USER_DATA_01[27:24] = 0010b

USER_DATA_01[27:24] = 0011b

USER_DATA_01[27:24] = 0100b

USER_DATA_01[27:24] = 0101b

USER_DATA_01[27:24] = 0110b

USER_DATA_01[27:24] = 0111b

USER_DATA_01[27:24] = 1000b

USER_DATA_01[27:24] = 1001b

USER_DATA_01[27:24] = 1010b

USER_DATA_01[27:24] = 1011b

USER_DATA_01[27:24] = 1100b

USER_DATA_01[27:24] = 1101b

USER_DATA_01[27:24] = 1110b

USER_DATA_01[27:24] = 1111b

1.9

2

2.1

2.85

3.8

3

3.15

4.2

4

4.75

5.7

5

5.25

6.3

6

6.65

7.6

7

7.35

8.4

8

8.55

9.5

9

9.45

10.5

11.55

12.6

13.65

14.7

15.75

16.8

10

11

12

13

14

15

16

10.45

11.4

12.35

13.3

14.25

15.2

Scaling factor for integration time

USER_DATA_01[4] = 0b

constants ⁽¹⁾

G_INTTC

1

x

USER_DATA_01[4] = 1b

6

0.5

1

x

K_AC

AC gain settings ⁽¹⁾

USER_DATA_01[13:12] = 00b

USER_DATA_01[13:12] = 01b

USER_DATA_01[13:12] = 10b

USER_DATA_01[13:12] = 11b

USER_DATA_01[15:14] = 00b

USER_DATA_01[15:14] = 01b

USER_DATA_01[15:14] = 10b

USER_DATA_01[15:14] = 11b

0.45

0.9

0.55

1.1

1.35

1.8

1.5

2

1.65

2.2

K_INT

Integration gain settings ⁽¹⁾

0.45

0.9

0.5

1

0.55

1.1

1.35

1.8

1.5

2

1.65

2.2

Dynamic Integration Voltage Setting.

Based on V_ERR

V_DINT

USER_DATA_01[11:8] = 000b

48

60

72

mV

(1)

USER_DATA_01[11:8] = 001b

USER_DATA_01[11:8] = 010b

USER_DATA_01[11:8] = 011b

USER_DATA_01[11:8] = 100b

USER_DATA_01[11:8] = 101b

USER_DATA_01[11:8] = 110b

USER_DATA_01[11:8] = 111b

68

88

80

100

92

112

132

152

172

192

mV

108

128

148

168

120

140

160

180

Disabled

Ramp Selections

V_RAMP

Ramp Setting ⁽¹⁾

USER_DATA_01[19:17] = 000b

USER_DATA_01[19:17] = 001b

USER_DATA_01[19:17] = 010b

USER_DATA_01[19:17] = 011b

70

110

150

190

80

120

160

200

90

130

170

210

mV

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_01[19:17] = 100b

USER_DATA_01[19:17] = 101b

USER_DATA_01[19:17] = 110b

USER_DATA_01[19:17] = 111b

MIN

230

270

310

350

TYP

240

280

320

360

MAX

250

290

330

370

UNIT

mV

(1) Guaranteed by Design.

6.4.5 Dynamic VID (DVID) Tuning

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Dynamic Voltage Transitions

V_OFS(WAKE)

V_DACoffset during soft-start ⁽¹⁾

USER_DATA_04[1:0] = 00b

USER_DATA_04[1:0] = 01b

0

mV

(independently programmable for each

channel)

30

USER_DATA_04[1:0] = 10b

USER_DATA_04[1:0] = 11b

60

90

mV

V_DACoffset during upward

transitions ⁽¹⁾

V_OFS(UP)

USER_DATA_04[11:10] = 00b

USER_DATA_04[11:10] = 01b

0

mV

(independently programmable for each

channel)

10

USER_DATA_04[11:10] = 10b

USER_DATA_04[11:10] = 11b

20

30

mV

V_DACoffset during downward

transitions ⁽¹⁾

V_OFS(DOWN)

USER_DATA_04[9:8] = 00b

USER_DATA_04[9:8] = 01b

0

mV

(independently programmable for each

channel)

10

USER_DATA_04[9:8] = 10b

USER_DATA_04[9:8] = 11b

20

30

mV

VOUT_DROOP = 0.0 to 1.0 mΩ

USER_DATA_04[36:32] = 00h to 1Fh

Resolution = 0.03125 mΩ

Dynamic DC load line during up

transitions ⁽¹⁾

R_DCLL(UP)

0

0.96875

1.9375

3.8750

7.75

mΩ

VOUT_DROOP = 1.0 to 2.0 mΩ

USER_DATA_04[36:32] = 00h to 1Fh

Resolution = 0.0625 mΩ

(independently programmable for each

channel)

VOUT_DROOP = 2.0 to 4.0 mΩ

USER_DATA_04[36:32] = 00h to 1Fh

Resolution = 0.125 mΩ

VOUT_DROOP = 4.0 to 8.0 mΩ

USER_DATA_04[36:32] = 00h to 1Fh

Resolution = 0.250 mΩ

R_ACLL= 0.0 to 1.0 mΩ

USER_DATA_04[19:16] = 0h to Fh

Resolution = 0.0625 mΩ

Dynamic AC load line during up

transitions ⁽¹⁾

R_ACLL(UP)

0.9375

1.875

3.75

R_ACLL= 1.0 to 2.0 mΩ

USER_DATA_04[19:16] = 0h to Fh

Resolution = 0.125 mΩ

(independently programmable for each

channel)

R_ACLL= 2.0 to 4.0 mΩ

USER_DATA_04[19:16] = 0h to Fh

Resolution = 0.250 mΩ

R_ACLL= 4.0 to 8.0 mΩ

USER_DATA_04[19:16] = 0h to Fh

Resolution = 0.500 mΩ

7.5

10

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT_DROOP = 0.0 to 1.0 mΩ

USER_DATA_04[44:40] = 00h to 1Fh

Resolution = 0.03125 mΩ

Dynamic DC load line during down

transitions ⁽¹⁾

R_DCLL(DOWN)

0

0.96875

mΩ

VOUT_DROOP = 1.0 to 2.0 mΩ

USER_DATA_04[44:40] = 00h to 1Fh

Resolution = 0.0625 mΩ

(independently programmable for each

channel)

0

1

2

4

1.9375

mΩ

VOUT_DROOP = 2.0 to 4.0 mΩ

USER_DATA_04[44:40] = 00h to 1Fh

Resolution = 0.125 mΩ

3.8750

VOUT_DROOP = 4.0 to 8.0 mΩ

USER_DATA_04[44:40] = 00h to 1Fh

Resolution = 0.250 mΩ

7.75

R_ACLL= 0.0 to 1.0 mΩ

USER_DATA_04[27:24] = 0h to Fh

Resolution = 0.0625 mΩ

Dynamic AC load line during down

transitions ⁽¹⁾

R_ACLL(DOWN)

1

2

4

8

R_ACLL= 1.0 to 2.0 mΩ

USER_DATA_04[27:24] = 0h to Fh

Resolution = 0.125 mΩ

(independently programmable for each

channel)

R_ACLL= 2.0 to 4.0 mΩ

USER_DATA_04[27:24] = 0h to Fh

Resolution = 0.250 mΩ

R_ACLL= 4.0 to 8.0 mΩ

USER_DATA_04[27:24] = 0h to Fh

Resolution = 0.500 mΩ

Dynamic load line up recovery delay

(PWM cycles) ⁽¹⁾

t_LLR(UP)

USER_DATA_04[23:22] = 00b

USER_DATA_04[23:22] = 01b

1

2

clks

(independently programmable for each

channel)

USER_DATA_04[23:22] = 10b

USER_DATA_04[23:22] = 11b

4

8

clks

Dynamic load line down recovery

delay (PWM cycles) ⁽¹⁾

t_LLR(DOWN)

USER_DATA_04[31:30] = 00b

USER_DATA_04[31:30] = 01b

1

2

clks

(independently programmable for each

channel)

USER_DATA_04[31:30] = 10b

4

8

clks

USER_DATA_04[31:30] = 11b

clks

SR_VOUT

Slew Rate Setting

VOUT_TRANSITION_RATE = E050h

VOUT_TRANSITION_RATE = E0A0h

VOUT_TRANSITION_RATE = E0F0h

VOUT_TRANSITION_RATE = E140h

VOUT_TRANSITION_RATE = E190h

VOUT_TRANSITION_RATE = E1E0h

VOUT_TRANSITION_RATE = E230h

VOUT_TRANSITION_RATE = E280h

5

10

15

20

25

30

35

39

5.875

11.75

17.625

23.5

mV/µs

29.375

35.25

41.125

47

0.36718

8

VOUT_TRANSITION_RATE = E005h

VOUT_TRANSITION_RATE = E00Ah

0.3125

0.625

mV/µs

0.73437

5

1.10156

3

VOUT_TRANSITION_RATE = E00Fh

VOUT_TRANSITION_RATE = E014h

VOUT_TRANSITION_RATE = E019h

0.9375

1.25

mV/µs

1.46875

1.83593

8

1.5625

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.20312

5

VOUT_TRANSITION_RATE = E01Eh

1.875

mV/µs

2.57031

3

VOUT_TRANSITION_RATE = E023h

VOUT_TRANSITION_RATE = E028h

2.1875

2.5

mV/µs

2.9375

(1) Guaranteed by Design.

6.4.6 Undershoot Reduction (USR) and Overshoot Reduciton (OSR)

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

Multi-Level OSR and USR

USR Level 1 Voltage Setting (V_DAC

V_DROOP

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-

V_USR1

USER_DATA_02[12:8] = 00010b

5

15

25

mV

)

USER_DATA_02[12:8] = 00011b

USER_DATA_02[12:8] = 00100b

USER_DATA_02[12:8] = 00101b

USER_DATA_02[12:8] = 00110b

USER_DATA_02[12:8] = 00111b

USER_DATA_02[12:8] = 01000b

USER_DATA_02[12:8] = 01001b

USER_DATA_02[12:8] = 01010b

USER_DATA_02[12:8] = 01011b

USER_DATA_02[12:8] = 01100b

USER_DATA_02[12:8] = 01101b

USER_DATA_02[12:8] = 01110b

USER_DATA_02[12:8] = 01111b

USER_DATA_02[12:8] = 10000b

USER_DATA_02[12:8] = 10001b

USER_DATA_02[12:8] = 10010b

USER_DATA_02[12:8] = 10011b

USER_DATA_02[12:8] = 10100b

USER_DATA_02[12:8] = 10101b

USER_DATA_02[12:8] = 10110b

USER_DATA_02[12:8] = 10111b

USER_DATA_02[12:8] = 11000b

USER_DATA_02[12:8] = 11001b ⁽¹⁾

USER_DATA_02[12:8] = other ⁽¹⁾

7.5

10

17.5

20

27.5

30

mV

12.5

15

22.5

25

32.5

35

17.5

20

27.5

30

37.5

40

22.5

25

32.5

35

42.5

45

27.5

30

37.5

40

47.5

50

32.5

35

42.5

45

52.5

55

37.5

40

47.5

50

57.5

60

42.5

45

52.5

55

62.5

65

47.5

50

57.5

60

67.5

70

52.5

55

62.5

65

72.5

75

57.5

60

67.5

70

77.5

80

62.5

72.5

Disabled

82.5

USR Level 2 Voltage Setting (V_DAC

-

V_USR2

USER_DATA_02[36:32] = 00000b

5

15

25

mV

V_DROOP

)

USER_DATA_02[36:32] = 00001b

USER_DATA_02[36:32] = 00010b

USER_DATA_02[36:32] = 00011b

USER_DATA_02[36:32] = 00100b

USER_DATA_02[36:32] = 00101b

USER_DATA_02[36:32] = 00110b

USER_DATA_02[36:32] = 00111b

USER_DATA_02[36:32] = 01000b

7.5

10

17.5

20

27.5

30

mV

12.5

15

22.5

25

32.5

35

17.5

20

27.5

30

37.5

40

22.5

25

32.5

35

42.5

45

12

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

27.5

30

TYP

37.5

40

MAX

47.5

50

UNIT

mV

USER_DATA_02[36:32] = 01001b

USER_DATA_02[36:32] = 01010b

USER_DATA_02[36:32] = 01011b

USER_DATA_02[36:32] = 01100b

USER_DATA_02[36:32] = 01101b

USER_DATA_02[36:32] = 01110b

USER_DATA_02[36:32] = 01111b

USER_DATA_02[36:32] = 10000b

USER_DATA_02[36:32] = 10001b

USER_DATA_02[36:32] = 10010b

USER_DATA_02[36:32] = 10011b

USER_DATA_02[36:32] = 10100b

USER_DATA_02[36:32] = 10101b

USER_DATA_02[36:32] = 10110b

USER_DATA_02[36:32] = 10111b

USER_DATA_02[36:32] = 11000b

USER_DATA_02[36:32] = 11001b ⁽¹⁾

USER_DATA_02[36:32] = others ⁽¹⁾

32.5

35

42.5

45

52.5

55

37.5

40

47.5

50

57.5

60

42.5

45

52.5

55

62.5

65

47.5

50

57.5

60

67.5

70

52.5

55

62.5

65

72.5

75

57.5

60

67.5

70

77.5

80

62.5

65

72.5

75

82.5

85

67.5

77.5

Disabled

87.5

Maximum phase added in USR level 1

PH_USR1

USER_DATA_02[1:0] = 00b

3

phases

(1)

USER_DATA_02[1:0] = 01b

USER_DATA_02[1:0] = 10b

4

5

phases

All

available

USER_DATA_02[1:0] = 11b

phases

V_OSR

OSR Voltage Setting

USER_DATA_02[19:16] = 0000b

USER_DATA_02[19:16] = 0001b

USER_DATA_02[19:16] = 0010b

USER_DATA_02[19:16] = 0011b

USER_DATA_02[19:16] = 0100b

USER_DATA_02[19:16] = 0101b

USER_DATA_02[19:16] = 0110b

USER_DATA_02[19:16] = 0111b

USER_DATA_02[19:16] = 1000b

USER_DATA_02[19:16] = 1001b

USER_DATA_02[19:16] = 1010b

USER_DATA_02[19:16] = 1011b

USER_DATA_02[19:16] = 1100b

USER_DATA_02[19:16] = 1101b

USER_DATA_02[19:16] = 1110b

USER_DATA_02[19:16] = 1111b ⁽¹⁾

USER_DATA_02[7] = 0b

8

18

20

30

32

42

mV

28

40

52

38

50

62

48

60

72

58

70

82

68

80

92

78

90

102

112

122

132

142

152

162

172

88

100

98

110

108

118

128

138

148

120

130

140

150

160

Disabled

Disable

Enable

BB_OSR

OSR pulse truncation for 1ph ⁽¹⁾

USER_DATA_02[7] = 1b

OSR body braking for normal phases USER_DATA_02[5] = 0b

BB_OSR

Disable

(1)

and USER_DATA_02[7] = 0b

USER_DATA_02[5] = 1b

or USER_DATA_02[7] = 1b

Enable

0.4

TB_OSR

OSR body braking time durations ⁽¹⁾

USER_DATA_02[4:2] = 000b

0.3

0.5

µs

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_02[4:2] = 001b

USER_DATA_02[4:2] = 010b

USER_DATA_02[4:2] = 011b

USER_DATA_02[4:2] = 100b

USER_DATA_02[4:2] = 101b

USER_DATA_02[4:2] = 110b

USER_DATA_02[4:2] = 111b

MIN

0.4

0.5

0.8

0.9

1

TYP

0.5

0.6

0.9

1

MAX

0.6

0.7

1

UNIT

µs

1.1

1.2

2

µs

1.1

1.9

2

µs

1.8

1.9

µs

2.1

µs

(1) Specified by Design

6.4.7 Dynamic Phase Shedding (DPS)

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Dynamic Phase Shedding

Minimum operating phase numbers

with DPS enabled ⁽¹⁾

PH_DPS

t_DPAFIL

I_DPA2

USER_DATA_07[3:2] = 00b

1

Phase

USER_DATA_07[3:2] = 01b

USER_DATA_07[3:2] = 10b

USER_DATA_07[3:2] = 11b

2

4

8

Phase

Filter time constant for phase adding

USER_DATA_07[7:6] = 00b

0.5

µs

(1)

USER_DATA_07[7:6] = 01b

USER_DATA_07[7:6] = 10b

USER_DATA_07[7:6] = 11b

1

1.5

2

µs

Dynamic phase adding thresholds

(1-2ph)

USER_DATA_07[11:8] = 0h

8.2

8.8

12

15.4

17.3

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[11:8] = 1h

13

A

USER_DATA_07[11:8] = 2h

USER_DATA_07[11:8] = 3h

USER_DATA_07[11:8] = 4h

USER_DATA_07[11:8] = 5h

USER_DATA_07[11:8] = 6h

USER_DATA_07[11:8] = 7h

USER_DATA_07[11:8] = 8h

USER_DATA_07[11:8] = 9h

USER_DATA_07[11:8] = Ah

USER_DATA_07[11:8] = Bh

USER_DATA_07[11:8] = Ch

USER_DATA_07[11:8] = Dh

USER_DATA_07[11:8] = Eh

USER_DATA_07[11:8] = Fh

12.2

13.3

14.3

15.1

16.2

17.3

17.9

19.2

20.2

21.3

22.3

23.2

24

14

15

16

17

18

19

20

21

22

23

24

25

26

27

15.7

16.7

17.7

18.7

19.7

20.7

21.7

22.7

23.7

24.8

25.8

26.8

27.8

28.8

A

24.9

Dynamic phase adding thresholds

(2-3ph)

I_DPA3

USER_DATA_07[23:20] = 0h

25.2

27.5

30

35.8

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[23:20] = 1h

32

37.4

A

14

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_07[23:20] = 2h

USER_DATA_07[23:20] = 3h

USER_DATA_07[23:20] = 4h

USER_DATA_07[23:20] = 5h

USER_DATA_07[23:20] = 6h

USER_DATA_07[23:20] = 7h

USER_DATA_07[23:20] = 8h

USER_DATA_07[23:20] = 9h

USER_DATA_07[23:20] = Ah

USER_DATA_07[23:20] = Bh

USER_DATA_07[23:20] = Ch

USER_DATA_07[23:20] = Dh

USER_DATA_07[23:20] = Eh

USER_DATA_07[23:20] = Fh

MIN

29.1

31.9

33.5

35.6

37.8

39.7

45.6

55.6

65.8

75.3

85.8

95.8

105.7

114.3

TYP

34

MAX

40

UNIT

A

36

41.2

43.5

45.4

47

A

38

A

40

A

42

A

44

49.3

55.2

65.3

75.2

85.5

95

A

50

A

60

A

70

A

80

A

90

A

100

110

120

105

A

114.9

125.9

A

Dynamic phase adding thresholds

(3-4ph)

I_DPA4

USER_DATA_07[19:16] = 0h

40.6

46

52.2

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[19:16] = 1h

43.5

48

53.6

USER_DATA_07[19:16] = 2h

USER_DATA_07[19:16] = 3h

USER_DATA_07[19:16] = 4h

USER_DATA_07[19:16] = 5h

USER_DATA_07[19:16] = 6h

USER_DATA_07[19:16] = 7h

USER_DATA_07[19:16] = 8h

USER_DATA_07[19:16] = 9h

USER_DATA_07[19:16] = Ah

USER_DATA_07[19:16] = Bh

USER_DATA_07[19:16] = Ch

USER_DATA_07[19:16] = Dh

USER_DATA_07[19:16] = Eh

USER_DATA_07[19:16] = Fh

43.2

47.5

50

52

57.4

57.6

A

48.2

54

60.2

51.5

56

61.4

52.8

58

64.4

54.7

60

66.3

74.7

80

86

94.6

100

120

140

160

180

200

220

106.1

125.4

145.4

166.1

185.5

205.6

226.7

114.9

135.2

154.6

175.1

194.5

213.4

Dynamic phase adding thresholds

(4-5ph)

I_DPA5

USER_DATA_07[31:28] = 0h

55.9

62

69

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[31:28] = 1h

59.5

64

69.6

A

USER_DATA_07[31:28] = 2h

USER_DATA_07[31:28] = 3h

USER_DATA_07[31:28] = 4h

USER_DATA_07[31:28] = 5h

USER_DATA_07[31:28] = 6h

USER_DATA_07[31:28] = 7h

USER_DATA_07[31:28] = 8h

USER_DATA_07[31:28] = 9h

59.6

63.4

65.1

67.3

69

66

68

73.2

73.3

76

A

70

72

77.3

79.6

81.4

95.4

105.8

74

71.1

85.1

94.9

76

90

100

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_07[31:28] = Ah

USER_DATA_07[31:28] = Bh

USER_DATA_07[31:28] = Ch

USER_DATA_07[31:28] = Dh

USER_DATA_07[31:28] = Eh

USER_DATA_07[31:28] = Fh

MIN

104.9

115.2

135.2

154.5

175.2

193.4

TYP

110

120

140

160

180

200

MAX

115.8

125.4

145.4

165.6

185.2

206.7

UNIT

A

Dynamic phase adding thresholds

(5-6ph)

I_DPA6

I_DPA7

I_DPA8

USER_DATA_07[27:24] = 0h

71.7

78

84.8

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[27:24] = 1h

74.8

81

87.1

USER_DATA_07[27:24] = 2h

USER_DATA_07[27:24] = 3h

USER_DATA_07[27:24] = 4h

USER_DATA_07[27:24] = 5h

USER_DATA_07[27:24] = 6h

USER_DATA_07[27:24] = 7h

USER_DATA_07[27:24] = 8h

USER_DATA_07[27:24] = 9h

USER_DATA_07[27:24] = Ah

USER_DATA_07[27:24] = Bh

USER_DATA_07[27:24] = Ch

USER_DATA_07[27:24] = Dh

USER_DATA_07[27:24] = Eh

USER_DATA_07[27:24] = Fh

77.9

81.6

84

87

90.6

92.8

A

84.5

90

95.7

87.2

93

99.5

89.9

96

102.7

105.5

117

93

99

103.4

114.5

124

110

120

130

140

160

180

200

220

126.5

137.1

145.1

166.6

185.5

205.8

227.3

134.7

154.1

174.8

194.2

213.2

Dynamic phase adding thresholds

(6-7ph)

USER_DATA_07[39:36] = 0h

100.1

105

110.5

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[39:36] = 1h

105.6

110

114.7

A

USER_DATA_07[39:36] = 2h

USER_DATA_07[39:36] = 3h

USER_DATA_07[39:36] = 4h

USER_DATA_07[39:36] = 5h

USER_DATA_07[39:36] = 6h

USER_DATA_07[39:36] = 7h

USER_DATA_07[39:36] = 8h

USER_DATA_07[39:36] = 9h

USER_DATA_07[39:36] = Ah

USER_DATA_07[39:36] = Bh

USER_DATA_07[39:36] = Ch

USER_DATA_07[39:36] = Dh

USER_DATA_07[39:36] = Eh

USER_DATA_07[39:36] = Fh

109.8

115.5

120.2

125.2

130.6

135.3

155.1

175.2

195.2

215

115

120

125

130

135

140

160

180

200

220

240

280

320

360

120.8

125

A

130.2

135.4

140.1

144.8

165.2

185.1

205

225.3

245.2

285.7

325.7

366.1

235

274.7

314.3

353.9

Dynamic phase adding thresholds

(7-8ph)

USER_DATA_07[35:32] = 0h

139.5

145

150.8

A

16

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[35:32] = 1h

145.4

150

155.3

A

USER_DATA_07[35:32] = 2h

USER_DATA_07[35:32] = 3h

USER_DATA_07[35:32] = 4h

USER_DATA_07[35:32] = 5h

USER_DATA_07[35:32] = 6h

USER_DATA_07[35:32] = 7h

USER_DATA_07[35:32] = 8h

USER_DATA_07[35:32] = 9h

USER_DATA_07[35:32] = Ah

USER_DATA_07[35:32] = Bh

USER_DATA_07[35:32] = Ch

USER_DATA_07[35:32] = Dh

USER_DATA_07[35:32] = Eh

USER_DATA_07[35:32] = Fh

149.7

154.9

160.4

165.1

169.9

175.5

214.9

234.7

254.9

274.6

334.1

373.7

413.3

452.9

155

160

165

170

175

180

220

240

260

280

340

380

420

460

160.4

165.5

170.1

174.9

180.3

185.1

225.3

245.4

265.1

285.8

345.9

386.3

426.7

467.1

A

Dynamic phase adding thresholds

(8-9ph)

I_DPA9

USER_DATA_07[47:44] = 0h

180.2

188

194.8

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[47:44] = 1h

186.9

194

200.6

A

USER_DATA_07[47:44] = 2h

USER_DATA_07[47:44] = 3h

USER_DATA_07[47:44] = 4h

USER_DATA_07[47:44] = 5h

USER_DATA_07[47:44] = 6h

USER_DATA_07[47:44] = 7h

USER_DATA_07[47:44] = 8h

USER_DATA_07[47:44] = 9h

USER_DATA_07[47:44] = Ah

USER_DATA_07[47:44] = Bh

USER_DATA_07[47:44] = Ch

USER_DATA_07[47:44] = Dh

USER_DATA_07[47:44] = Eh

USER_DATA_07[47:44] = Fh

192.8

198.8

205.4

211.2

216.9

223.6

243

200

206

212

218

224

230

250

270

290

330

370

410

450

490

206.6

212.6

217.9

224.1

230.3

235.8

256.2

276.4

295.7

336.4

376.6

417.1

457.5

498

A

262.9

283.3

323

362.9

402.9

442.5

482

Dynamic phase adding thresholds

(9-10ph)

I_DPA10

USER_DATA_07[43:40] = 0h

217.5

225

231.7

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[43:40] = 1h

224

230

235.6

A

USER_DATA_07[43:40] = 2h

USER_DATA_07[43:40] = 3h

USER_DATA_07[43:40] = 4h

USER_DATA_07[43:40] = 5h

USER_DATA_07[43:40] = 6h

227.4

232.8

238.7

243.3

247.7

235

240

245

250

255

241.1

246.6

250.7

256.1

261.6

A

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

USER_DATA_07[43:40] = 7h

USER_DATA_07[43:40] = 8h

USER_DATA_07[43:40] = 9h

USER_DATA_07[43:40] = Ah

USER_DATA_07[43:40] = Bh

USER_DATA_07[43:40] = Ch

USER_DATA_07[43:40] = Dh

USER_DATA_07[43:40] = Eh

USER_DATA_07[43:40] = Fh

MIN

253.3

273.1

292.7

332.8

373

TYP

260

280

300

340

380

420

460

500

540

MAX

266.1

286.2

306.1

346.4

386.6

427.4

467.9

508.4

548.9

UNIT

A

412.6

452.1

491.6

531.1

A

Dynamic phase adding thresholds

(10-11ph)

I_DPA11

USER_DATA_07[55:52] = 0h

257.4

265

271.7

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[55:52] = 1h

262.7

270

276.6

USER_DATA_07[55:52] = 2h

USER_DATA_07[55:52] = 3h

USER_DATA_07[55:52] = 4h

USER_DATA_07[55:52] = 5h

USER_DATA_07[55:52] = 6h

USER_DATA_07[55:52] = 7h

USER_DATA_07[55:52] = 8h

USER_DATA_07[55:52] = 9h

USER_DATA_07[55:52] = Ah

USER_DATA_07[55:52] = Bh

USER_DATA_07[55:52] = Ch

USER_DATA_07[55:52] = Dh

USER_DATA_07[55:52] = Eh

USER_DATA_07[55:52] = Fh

267.8

273.1

278

275

280

285

290

295

300

320

340

360

400

440

480

520

560

281.2

285.6

291.4

296

A

283.4

288.2

292.7

312.9

332.7

352.7

392.3

431.9

471.3

510.8

550.2

300.9

306.7

326.5

346.7

367

407.3

448.1

488.7

529.2

569.8

Dynamic phase adding thresholds

(11-12ph)

I_DPA12

USER_DATA_07[51:48] = 0h

297.9

305

311.3

A

Average current, assuming DPA

Hysteresis is set equal to 1/2 I_SUM

ripple for active phase number,

accounting for ripple cancellation

USER_DATA_07[51:48] = 1h

302.7

310

316

A

USER_DATA_07[51:48] = 2h

USER_DATA_07[51:48] = 3h

USER_DATA_07[51:48] = 4h

USER_DATA_07[51:48] = 5h

USER_DATA_07[51:48] = 6h

USER_DATA_07[51:48] = 7h

USER_DATA_07[51:48] = 8h

USER_DATA_07[51:48] = 9h

USER_DATA_07[51:48] = Ah

USER_DATA_07[51:48] = Bh

USER_DATA_07[51:48] = Ch

USER_DATA_07[51:48] = Dh

USER_DATA_07[51:48] = Eh

306.8

313

315

320

325

330

335

340

360

380

420

440

480

520

560

321.8

326.2

331.3

336.3

341.5

346.5

367.1

387.4

427.7

448

A

317.7

322.7

328.1

332.1

352.8

372.7

412.4

432.1

471.2

510.6

550

488.9

529.5

570.1

18

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USER_DATA_07[51:48] = Fh

589.4

600

610.7

A

DPA Hysteresis (1-2ph)

Set equal to 1/2 I_SUMripple with 1

phase operational

I_HYST2

I_HYST3

I_HYST4

I_HYST5

I_HYST6

I_HYST7

I_HYST8

I_HYST9

I_HYST10

I_HYST11

USER_DATA_07[59:56] = 0h to Fh

USER_DATA_07[71:68] = 0h to Fh

USER_DATA_07[67:64] = 0h to Fh

USER_DATA_07[79:76] = 0h to Fh

USER_DATA_07[75:72] = 0h to Fh

USER_DATA_07[87:84] = 0h to Fh

USER_DATA_07[83:80] = 0h to Fh

USER_DATA_07[95:92] = 0h to Fh

USER_DATA_07[91:88] = 0h to Fh

USER_DATA_07[103:100] = 0h to Fh

USER_DATA_07[99:96] = 0h to Fh

0

15

A

DPA Hysteresis (2-3ph)

Set equal to 1/2 I_SUMripple with 2

phases operational

DPA Hysteresis (3-4ph)

Set equal to 1/2 I_SUMripple with 3

phases operational

DPA Hysteresis (4-5ph)

Set equal to 1/2 I_SUMripple with 4

phases operational

DPA Hysteresis (5-6ph)

Set equal to 1/2 I_SUMripple with 5

phases operational

DPA Hysteresis (6-7ph)

Set equal to 1/2 I_SUMripple with 6

phases operational

DPA Hysteresis (7-8ph)

Set equal to 1/2 I_SUMripple with 7

phases operational

DPA Hysteresis (8-9ph)

Set equal to 1/2 ISUM ripple with 8

phases operational

DPA Hysteresis (9-10ph)

Set equal to 1/2 ISUM ripple with 9

phases operational

DPA Hysteresis (10-11ph)

Set equal to 1/2 ISUM ripple with 10

phases operational

DPA Hysteresis (11-12ph)

Set equal to 1/2 ISUM ripple with 11

phases operational

I_HYST12

I_HYST-DPS

Dynamic phase shedding hysteresis

USER_DATA_07[15:14] = 00b

USER_DATA_07[15:14] = 01b

USER_DATA_07[15:14] = 10b

USER_DATA_07[15:14] = 11b

Avg. current, calculated

0

1

2

3

A

I_DPS2

I_DPS3

I_DPS4

I_DPS5

I_DPS6

I_DPS7

I_DPS8

I_DPS9

I_DPS10

I_DPS11

I_DPS12

Phase shed threshold (2-1ph)

Phase shed threshold (3-2ph)

Phase shed threshold (4-3ph)

Phase shed threshold (5-4ph)

Phase shed threshold (6-5ph)

Phase shed threshold (7-6ph)

Phase shed threshold (8-7ph)

Phase shed threshold (9-8ph)

Phase shed threshold (10-9ph)

Phase shed threshold (11-10ph)

Phase shed threshold (12-11ph)

I_DPA2– 1 × I_HYST-DPS

I_DPA3– 2 × I_HYST-DPS

I_DPA4– 3 × I_HYST-DPS

I_DPA5– 4 × I_HYST-DPS

I_DPA6– 5 × I_HYST-DPS

I_DPA7– 6 × I_HYST-DPS

I_DPA8– 7 × I_HYST-DPS

I_DPA9– 8 × I_HYST-DPS

I_DPA10– 9 × I_HYST-DPS

I_DPA11– 10 × I_HYST-DPS

I_DPA12– 11 × I_HYST-DPS

Dynamic phase shedding delay (N+1

ph to N ph) ⁽¹⁾

T_{DPS_DELAY}

115

120

125

µs

(1) Guaranteed by Design.

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6.4.8 Turbo Mode and Thermal Balance Management (TBM)

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, TJ = -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Turbo Mode and Thermal Management

N_turbo

Number of turbo phases

0

4

Current share gain for Turbo Phases

G_TURBO

USER_DATA_10[6:5] = 00b

100

%

(1)

USER_DATA_10[6:5] = 01b

USER_DATA_10[6:5] = 10b

USER_DATA_10[6:5] = 11b

USER_DATA_10[3:0] = 0000b

USER_DATA_10[3:0] = 0001b

USER_DATA_10[3:0] = 0010b

USER_DATA_10[3:0] = 0011b

USER_DATA_10[3:0] = 0100b

USER_DATA_10[3:0] = 0101b

USER_DATA_10[3:0] = 0110b

USER_DATA_10[3:0] = 0111b

USER_DATA_10[3:0] = 1000b

150

180

220

0.8

%

K_T

Thermal balance gain ⁽¹⁾

0.85

0.9

0.95

1

1.05

1.1

1.15

1.2

(1) Guaranteed by Design.

6.4.9 Overcurrent Limit (OCL)

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Overcurrent Limit Thresholds

I_OCL

Phase Valley OCL Thresholds

Programmable Range

17

130

A

(Program through

IOUT_OC_FAULT_LIMIT)

Programmable Resolution

17 A ≤ I_OCL≤ 80 A

3

5

Programmable Resolution

85 A ≤ I_OCL≤ 130 A

A

Threshold Accuracy

17 A ≤ I_OCL≤ 80 A

-3.05

-5.55

3.05

5.55

Threshold Accuracy

85 A ≤ I_OCL≤ 130 A

6.4.10 Telemetry

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Telemetry

Per-phase current filter time constant

t_{CS_FIL}

300

20

µs

(1)

t_{CS_UPDATE}

I_{CS_RNG}

Per-phase current update time ⁽¹⁾

Per-phase current reporting range

IMON average time ⁽¹⁾

µs

A

-10

120

t_{IMON_FIL}

290

24

µs

t_{IMON_UPDATE}IMON update time ⁽¹⁾

70 x

Nph

I_{MON_RNG}

IMON reporting range

A

A/ph

A

Summed of the per-phase currents

and the total current

I_{MON_ERROR}

Per-phase and total current error ⁽¹⁾

IMON Calibration Offset LSB ⁽¹⁾

1.0

I_{MON_CAL_OF_}

IOUT_CAL_OFFSET resolution

0.125

LSB

20

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{MON_CAL_OF_}

IMON Calibration Offset Range ⁽¹⁾

IOUT_CAL_OFFSET range

-4

3.75

A

RNG

I_{MON_CAL_GA_}

IMON Calibration Gain LSB ⁽¹⁾

IMON Calibration Gain Range ⁽¹⁾

IOUT_CAL_GAIN resolution

IOUT_CAL_GAIN range

0.2

%

LSB

I_{MON_CAL_GA_}

-10

10

RNG

I_{MON_LSB}

I_{MON_ACC}

IMON LSB via PMBus ⁽¹⁾

Digital IMON Accuracy

0.125

3.5

A

12-phase, I_OUT= 0 A

12-phase, I_OUT= 60 A

12-phase, I_OUT= 120 A

12-phase, I_OUT= 240 A

12-phase, I_OUT= 360 A

12-phase, I_OUT= 600 A

12-phase, I_OUT= 840 A

10-phase, I_OUT= 0 A

10-phase, I_OUT= 50 A

10-phase, I_OUT= 100 A

10-phase, I_OUT= 200 A

10-phase, I_OUT= 300 A

10-phase, I_OUT= 500 A

8-phase, I_OUT= 0 A

-3.5

-9

9

%

A

-4.5

-3

4.5

3

-2.25

-0.9

-0.64

-4

2.25

0.9

0.64

4

-8

8

%

A

-4

4

-2

2

-1.33

-0.8

-2.5

-8

1.33

0.8

2.5

8-phase, I_OUT= 45 A

8-phase, I_OUT= 90 A

8-phase, I_OUT= 135 A

8-phase, I_OUT= 180 A

8-phase, I_OUT= 225 A

8-phase, I_OUT= 270 A

8-phase, I_OUT= 450 A

6-phase, I_OUT= 0 A

8

%

A

-4

4

-2.67

-2

2.67

2

-1.6

-1.33

-0.8

-2.4

-9.41

-4.71

-3.14

-2.35

-1.88

-1.57

-0.94

-0.8

-9.76

-4.88

-3.25

-2.44

-1.95

-1.63

-0.98

-0.35

-11.67

1.6

1.33

0.8

2.4

6-phase, I_OUT= 25.5 A

6-phase, I_OUT= 51 A

6-phase, I_OUT= 76.5 A

6-phase, I_OUT= 102 A

6-phase, I_OUT= 127.5 A

6-phase, I_OUT= 153 A

6-phase, I_OUT= 255 A

2-phase, I_OUT= 0 A

9.41

4.71

3.14

2.35

1.88

1.57

0.94

0.8

%

A

2-phase, I_OUT= 8.2 A

2-phase, I_OUT= 16.4 A

2-phase, I_OUT= 24.6 A

2-phase, I_OUT= 32.8 A

2-phase, I_OUT= 41 A

2-phase, I_OUT= 49.2 A

2-phase, I_OUT= 82 A

1-phase, I_OUT= 0 A

9.76

4.88

3.25

2.44

1.95

1.63

0.98

0.35

11.67

%

A

1-phase, I_OUT= 3 A

%

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

-5.83

-3.89

-2.92

-2.33

-1.94

-1.17

-5

TYP

MAX

5.83

3.89

2.92

2.33

1.94

1.17

5

UNIT

%

1-phase, I_OUT= 6 A

1-phase, I_OUT= 9 A

1-phase, I_OUT= 12 A

1-phase, I_OUT= 15 A

1-phase, I_OUT= 18 A

1-phase, I_OUT= 30 A

V_VSP= 0.25 V to 0.75 V

V_VSP= 0.75 V to 1.5 V

V_VSP> 1.5 V

%

V_{READ_VOUT}READ_VOUT accuracy

mV

-10

10

-15.0

15.0

V_{READ_VOUT_}

READ_VOUT update rate ⁽¹⁾

200

2

µs

%

UPDATE

V_{READ_VIN}

READ_VIN accuracy

V_IN= 4.5 V to 17 V

-2

V_{READ_VIN_UP}

READ_VIN update rate ⁽¹⁾

150

µs

DATE

0.28 V to 1.8 V on TSEN pin (-40C to

150C)

Temp

READ_TEMPERATURE_1 accuracy

-2.5

2.5

C

READ_TEMPERATURE_1 update

rate ⁽¹⁾

Temp_UPDATE

V_TSENUVR

V_TSENUVF

V_TSENUVH

150

245

160

µs

Low voltage detection on TSEN pin

before soft-start and during operations

TSEN low voltage (rising edge)

TSEN low voltage (falling edge)

220

135

50

270

185

mV

Low voltage detection on TSEN pin

before soft-start and during operations

Low voltage detection on TSEN pin

before soft-start and during operations

TSEN low voltage (hysteresis) ⁽¹⁾

TSEN filter time constant ⁽¹⁾

t_TSEN

5

MHz

pF

C_TSEN

Maximum capacitance on TSEN pin ⁽¹⁾To get < 0.5us response time

220

10

R_INSHUNT

Input current shunt range

0.1

mΩ

Input amplifer gain options for different

GINSHUNT = 0h

G_INSHUNT

20

V/V

shunts (analog gain setting)

GINSHUNT = 1h

GINSHUNT = 2h

GINSHUNT = 3h

GINSHUNT = 4h

GINSHUNT = 5h

GINSHUNT = 6h

GINSHUNT = 7h

30

40

V/V

50

60

70

80

100

Maximum CSPIN-CSNIN voltage can

IIN x Shunt (mohm) x Analog Gain

be sensed ⁽¹⁾

V_{CSIN_MAX}

800

mV

t_{IIN_FIL}

IIN average time ⁽¹⁾

IIN update time ⁽¹⁾

IIN reporting range ⁽¹⁾

IIN = 5.0 A (1 mV),

440

24

µs

A

t_{IIN_UPDATE}

I_{IIN_RNG}

-5

-1

100

1

I_IN

READ_IIN accuracy

RSHUNT = 0.2 mΩ,

A

GINSHUNT = 20 and 100 V/V

IIN = 10.0 A (2 mV),

RSHUNT = 0.2 mΩ,

-1

1

GINSHUNT = 20 and 100 V/V

IIN = 20.0 A (4 mV),

RSHUNT = 0.2 mΩ,

-3.25

3.25

%

GINSHUNT = 20 and 100 V/V

22

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIN = 40.0 A (8 mV),

RSHUNT = 0.2 mΩ,

-3.25

3.25

%

GINSHUNT = 20 and 100 V/V

IIN = 70.0 A (14 mV),

RSHUNT = 0.2 mΩ,

-2

2

%

GINSHUNT = 20 and 100 V/V

I_{IN_CAL}

Calculated input current accuracy ⁽¹⁾

I_IN= 5A; 12Vin to 1.8Vout

I_IN= 10A

-10

-5

10

5

%

I_IN= 40A

-3.5

-3

3.5

3

IIN = 70A

V_IN= 12 V; VCSPIN-VCSNIN = 14 mV;

(70A @ 0.2 mohm shunt); Exclude

ripple;

V_{READ_PIN}

P_{OUT_ACC}

READ_PIN accuracy

-2.5

2.5

%

READ_POUT Accuracy

Per IOUT and VOUT

(1) Guaranteed by Design.

6.4.11 Phase-Locked Loop and Closed-Loop Frequency Control

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Switching Frequency

V_IN= 12 V, V_VSP= 1.0 V

f_SW× N_Φ≤ 8 MHz

f_SW(RNG)

f_SW(TOL)

Switching Frequency Range

300

–10

2000

10

kHz

%

V_IN= 12 V, V_VSP= 1.0 V

f_SW× N_Φ≤ 8 MHz

Switching Frequency Tolerance

Phase-Lock Loop and Synchronization

V_IL(SYNC)

V_IH(SYNC)

V_OL(SYNC)

V_OH(SYNC)

t_PW(SYNC)

D_SYNCOUT

f_SYNC

SYNC input logic low ⁽¹⁾

0.8

0.4

V

SYNC input logic high ⁽¹⁾

1.35

SYNC output logic low ⁽¹⁾

SYNC output logic high ⁽¹⁾

SYNC input minimum pulse width ⁽¹⁾

SYNC output duty cycle ⁽¹⁾

Synchronization frequency ⁽¹⁾

I_PIN= ± 0.5 mA

V

1.7

100

40

V

ns

%

50

60

200

2000

kHz

SYNC allowable frequency difference FREQUENCY_SWITCH from 300 kHz

Df_SYNC

–50

50

kHz

from free-running frequency ⁽¹⁾

Channel A Sync mode ⁽¹⁾

to 2 MHz

MFR_SPECIFIC_E4[5] = X

MFR_SPECIFIC_E4[8] = 0b

MFR_SPECIFIC_E4[14] = 0b

M_SYNCA

Disabled

MFR_SPECIFIC_E4[5] = 0b

MFR_SPECIFIC_E4[8] = 1b

MFR_SPECIFIC_E4[14] = 0b

Internal Clock, CLF Mode

External Clock, PLL Mode

Disabled

MFR_SPECIFIC_E4[5] = 1b

MFR_SPECIFIC_E4[8] = 0b

MFR_SPECIFIC_E4[14] = 1b

MFR_SPECIFIC_E4[6] = X

MFR_SPECIFIC_E4[9] = 0b

MFR_SPECIFIC_E4[15] = 0b

M_SYNCB

Channel B Sync mode ⁽¹⁾

MFR_SPECIFIC_E4[6] = 0b

MFR_SPECIFIC_E4[9] = 1b

MFR_SPECIFIC_E4[15] = 0b

Internal Clock, CLF Mode

MFR_SPECIFIC_E4[6] = 1b

MFR_SPECIFIC_E4[9] = 0b

MFR_SPECIFIC_E4[15] = 1b

External Clock, PLL Mode

0

PH_SYNCA

Channel A SYNC Phase Offset ⁽¹⁾

MFR_SPECIFIC_E4[23:20] = 0h

deg

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MFR_SPECIFIC_E4[23:20] = 1h

MFR_SPECIFIC_E4[23:20] = 2h

MFR_SPECIFIC_E4[23:20] = 3h

MFR_SPECIFIC_E4[23:20] = 4h

MFR_SPECIFIC_E4[23:20] = 5h

MFR_SPECIFIC_E4[23:20] = 6h

MFR_SPECIFIC_E4[23:20] = 7h

MFR_SPECIFIC_E4[23:20] = 8h

MFR_SPECIFIC_E4[23:20] = 9h

MFR_SPECIFIC_E4[23:20] = Ah

MFR_SPECIFIC_E4[23:20] = Bh

MFR_SPECIFIC_E4[31:28] = 0h

MFR_SPECIFIC_E4[31:28] = 1h

MFR_SPECIFIC_E4[31:28] = 2h

MFR_SPECIFIC_E4[31:28] = 3h

MFR_SPECIFIC_E4[31:28] = 4h

MFR_SPECIFIC_E4[31:28] = 5h

MFR_SPECIFIC_E4[31:28] = 6h

MFR_SPECIFIC_E4[31:28] = 7h

MFR_SPECIFIC_E4[31:28] = 8h

MFR_SPECIFIC_E4[31:28] = 9h

MFR_SPECIFIC_E4[31:28] = Ah

MFR_SPECIFIC_E4[31:28] = Bh

MIN

TYP

30

MAX

UNIT

deg

60

90

120

150

180

210

240

270

300

330

0

PH_SYNCB

Channel B SYNC Phase Offset ⁽¹⁾

30

60

90

120

150

180

210

240

270

300

330

(1) Guaranteed by Design.

6.4.12 Logic Interface

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.975

0.6

UNIT

Logic Interface Pins

V_AENL

Channel A ENABLE Logic Low

Channel A ENABLE Logic High

Channel A ENABLE Hysteresis ⁽¹⁾

Channel A ENABLE Deglitch ⁽¹⁾

V

V_AENH

1.525

0.4

V_AENHYS

t_AENDIG

V

0.275

µs

Channel A ENABLE Low to VRRDY

Low

No soft-stop; Only valid when using

AVR_EN pin.

t_AENVRRDYF

1.5

µs

I_AENH

Channel A I/O Leakage

Leakage current , V_{AVR_EN}= 1.1 V

25

µA

V

V_BENL

Channel B ENABLE Logic Low

Channel B ENABLE Logic High

Channel B ENABLE Hysteresis ⁽¹⁾

Channel B ENABLE Deglitch ⁽¹⁾

0.925

V_BENH

V_BENHYS

t_BENDIG

1.225

0.2

V

0.3

1.5

V

0.275

µs

Channel B ENABLE Low to VRRDY

Low ⁽¹⁾

No soft-stop; Only valid when using

BVR_EN pin.

t_BENVRRDYF

µs

I_BENH

Channel B I/O Leakage

PWMx Output Low-level

PWMx Output High-level

PWMx Tri-State

Leakage current , V_{BVR_EN}= 1.1 V

I_LOAD= ± 0.5 mA

25

µA

V

V_PWML

V_PWMH

V_{PWM_Tri}

0.11

I_LOAD= ± 0.5 mA; VCC = 2.97 V

I_LOAD= ± 100 µA

2.85

V

1.440

1.5

1.560

V

24

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_LOAD= 10 pF; I_LOAD= ± 100 µA; 10%

to 90% both edges

t_{P-S_H-L}

t_{P-S_TRI}

PWMx H-L Transition-time ⁽¹⁾

10

ns

C_LOAD= 10 pF; I_LOAD= ± 100 µA; 10%

or 90% to tri-state; both edges

PWMx Tri-State Transition ⁽¹⁾

20

ns

(1) Guaranteed by Design.

6.4.13 Current Sensing and Current Sharing

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current Sense and Current Sharing

I_ACSPx

ACSPx leakage current

V_ACSPx= 2.1 V

75

µA

%

I_{BAL_TOL}

Internal current share tolerance ⁽¹⁾

At 20.5A/ph operations

-4.5

2.8

4.5

Based on the filtered CSPx average

current

USER_DATA_11[47:46] = 00b

I_{SHARE_WRN_T}

Current Share Warning Threshold

5

7.2

A

H

(independently programmable for each

channel)

USER_DATA_11[47:46] = 01b

USER_DATA_11[47:46] = 10b

7.5

10

15

12.5

17.5

A

12.5

(1) Guaranteed by Design.

6.4.14 Pin Detection Thresholds

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low-Side Pinstrap Resistor Decode (3

LSB bits) ⁽¹⁾

R_DECODE

R_LOWER= 154 kΩ with 1% tolerance

111

Bin

R_LOWER= 115 kΩ with 1% tolerance

R_LOWER= 86.6 kΩ with 1% tolerance

R_LOWER= 64.9 kΩ with 1% tolerance

R_LOWER= 49.9 kΩ with 1% tolerance

R_LOWER= 37.4 kΩ with 1% tolerance

R_LOWER= 27.4 kΩ with 1% tolerance

R_LOWER= 20.0 kΩ with 1% tolerance

V_PIN= 22.5 mV

110

101

Bin

100

011

010

001

000

V_DECODEPin Voltage Decode (5 MSB bits) ⁽¹⁾

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

V_PIN= 67.5 mV

V_PIN= 112.5 mV

V_PIN= 157.5 mV

V_PIN= 202.5 mV

V_PIN= 247.5 mV

V_PIN= 292.5 mV

V_PIN= 337.5 mV

V_PIN= 382.5 mV

V_PIN= 427.5 mV

V_PIN= 472.5 mV

V_PIN= 517.5 mV

V_PIN= 562.5 mV

V_PIN= 607.5 mV

V_PIN= 652.5 mV

V_PIN= 697.5 mV

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

MAX

UNIT

Bin

V_PIN= 742.5 mV

V_PIN= 787.5 mV

V_PIN= 832.5 mV

V_PIN= 877.5 mV

V_PIN= 922.5 mV

V_PIN= 967.5 mV

V_PIN= 1012.5 mV

V_PIN= 1057.5 mV

V_PIN= 1102.5 mV

V_PIN= 1147.5 mV

V_PIN= 1192.5 mV

V_PIN= 1237.5 mV

V_PIN= 1282.5 mV

V_PIN= 1327.5 mV

V_PIN= 1372.5 mV

V_PIN= 1417.5 mV

(1) The same decoding scheme and thresholds apply to both the ADDR_CONFIG and VBOOT_CHA pins.

6.4.15 ADDR_CONFIG Pinstrap Decoding

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Phase Configuration (Channel A +

Channel B)

Pinstrap Mode

Decode 3 LSB = 000b

PH_CFG

12+0

Phases

Pinstrap Mode

Decode 3 LSB = 001b

11+0

10+2

9+2

8+2

7+2

6+2

5+2

Phases

Pinstrap Mode

Decode 3 LSB = 010b

Pinstrap Mode

Decode 3 LSB = 011b

Pinstrap Mode

Decode 3 LSB = 100b

Pinstrap Mode

Decode 3 LSB = 101b

Pinstrap Mode

Decode 3 LSB = 110b

Pinstrap Mode

Decode 3 LSB = 111b

Phases

Bin

NVM Mode (PIN_DETECT_OVERRIDE)

Pinstrap Mode

PHASE_CONFIG

PMB_ADD

PMBus Address (7 bit I²C Address)

88d + 5 MSB of decode

SLAVE_ADDRESS

R

NVM Mode (PIN_DETECT_OVERRIDE)

Bin

6.4.16 VBOOT_CHA Pinstrap Decoding

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pinstrap Mode

Decode = 0d

V_BOOTA

Boot voltage for Channel A

0

V

Pinstrap Mode

Decode = 1d to 253d

0.24 + (Decode × 0.01)

V

26

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pinstrap Mode

Decode = 254d

3.3

V

Pinstrap Mode

5

V

Decode = 255d⁽¹⁾

NVM Mode (PIN_DETECT_OVERRIDE)

VOUT_COMMAND

(1) Requires an external divider on the VSP and VSN pins. VOUT_SCALE_LOOP is automatically programmed to 0.5

6.4.17 Timing Specifications

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Timing Specifications

TON_DELAY range = 0.5 ms to 127.5

ms with

t_ENABLE

Enable delay time options ⁽¹⁾

0.5

127.5

ms

(independently programmable for each

channel)

TON_DELAY resolution

TON_DELAY accuracy

0.5

ms

%

-10

0.5

10

TOFF_DELAY range = 0.5 ms to 127.5

ms

t_DISABLE

Disable delay time options ⁽¹⁾

127.5

ms

(independently programmable for each

channel)

TOFF_DELAY resolution

TOFF_DELAY accuracy

0.5

ms

-10

10

%

PH_START

Operating Phases during Soft-Start ⁽¹⁾USER_DATA_07[5:4] = 00b

MIN(4, N_TOTAL

)

ph

(independently programmable for each

USER_DATA_07[5:4] = 01b

channel)

MIN(6, N_TOTAL

ph

USER_DATA_07[5:4] = 10b

USER_DATA_07[5:4] = 11b

MIN(8, N_TOTAL

N_TOTAL

ph

Programmable Range

Controller minimum OFF time range

t_{OFF_MIN}

40

135

ns

USER_DATA_02[23:20] = 0 to Fh

(independently programmable for each

Resolution

channel)

15

Accuracy (all settings)

-25

30

25

60

ns

t_{ON_MIN}

Controller minimum ON time ⁽¹⁾

USER_DATA_02[39:38] = 0 to 3h

Resolution

(independently programmable each

channel)

10

ns

Accuracy

-12

20

12

Programmable Range

USER_DATA_02[31:24]

t_{ON_BLANK}

Rising-edge blanking time range ⁽¹⁾

155

(independently programmable for each

channel)

Resolution

Accuracy

5

ns

-25

25

(1) Guaranteed by Design.

6.4.18 Faults and Converter Protection

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

32

TYP

MAX

UNIT

PROTECTION

Programmable Range ⁽²⁾

448

16

mV

Channel A Tracking OV Fault Threshold

V_OVTRKA( Offset with respect to output voltage

target including VDROOP )

Resolution

32

Accuracy (all settings)

-16

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

V

Programmable Range ⁽²⁾

32

448

Channel B Tracking OV Fault Threshold

V_OVTRKB( Offset with respect to output voltage

target including VDROOP )

Resolution

32

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-20

0.6

20

3.7

0.1

V

V_OVFIXAChannel A Fixed OV Fault Threshold

Accuracy (V_OVFIX< 3.6 V)

Accuracy (V_OVFIX≥ 3.6 V)

Programmable Range ⁽²⁾

Resolution

-50

-65

0.6

50

65

mV

V

3.7

V

V_OVFIXBChannel B Fixed OV Fault Threshold

Accuracy (V_OVFIX< 3.6 V)

Accuracy (V_OVFIX≥ 3.6 V)

-50

-65

50

65

mV

V

V_OVPB-APre-biased OVP Channel A threshold ⁽¹⁾

V_OVPB-BPre-biased OVP Channel B threshold ⁽¹⁾

3.7

V

Programmable Range ⁽²⁾

Resolution

16

448

mV

Channel A Tracking OV Warning

Threshold (Offset with respect to output

voltage target including VDROOP)

V_OVW-A

V_OVW-B

V_UVW-A

V_UVW-B

V_UVF-A

V_UVF-B

8

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-12

24

12

448

Channel B Tracking OV Warning

Threshold (Offset with respect to output

voltage target including VDROOP)

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-23

-16

23

-448

Channel A UV Warning Threshold ( Offset

with respect to output voltage target

including VDROOP )

8

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-11

-8

11

-448

Channel B UV Warning Threshold ( Offset

with respect to output voltage target

including VDROOP )

8

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-22

32

22

448

Channel A Tracking UV Fault Threshold

( Offset with respect to output voltage

target including VDROOP )

32

Accuracy (all settings)

Programmable Range ⁽²⁾

Resolution

-16

32

16

448

Channel B Tracking UV Fault Threshold

( Offset with respect to output voltage

target including VDROOP )

Accuracy (all settings)

-21

21

VOUT_UV_FAULT_RESPONSE[2:0] =

x00b

t_DLY(UVF)Deglitch Time for Triggering UV Fault ⁽¹⁾

4

8

µs

VOUT_UV_FAULT_RESPONSE[2:0] =

x01b

VOUT_UV_FAULT_RESPONSE[2:0] =

x10b

12

16

VOUT_UV_FAULT_RESPONSE[2:0] =

x11b

Programmable Range ⁽²⁾

1

1023

A

Resolution

1

Channel A Overcurrent Protection

Threshold

I_OCP-A

Accuracy (11 phase, I_OCP≤ 135 A)

Accuracy (11 phase, I_OCP> 135 A)

Programmable Range ⁽²⁾

Resolution

-7

-4

1

7

4

A

%

A

1023

A

Channel B Overcurrent Protection

Threshold

I_OCP-B

Accuracy (4 phase, I_OCP≤ 75 A)

Accuracy (4 phase, I_OCP> 75 A)

-3

3

A

%

28

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VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

A

Programmable Range ⁽²⁾

1

1023

Resolution

1

A

Channel A Overcurrent Warning

Threshold

I_OCW-A

Accuracy (11 phase, I_OCW≤ 135 A)

Accuracy (11 phase, I_OCW> 135 A)

Programmable Range ⁽²⁾

Resolution

-7

-4

1

7

4

A

%

A

1023

1

A

Channel B Overcurrent Warning

Threshold

I_OCW-B

Accuracy (4 phase, I_OCW≤ 75 A)

Accuracy (4 phase, I_OCW> 75 A)

Programmable Range

Resolution

-3

3

A

%

°C

V

90

160

T_OTF

Over-temperature Fault threshold

Over-temperature Warning threshold⁽¹⁾

Input over-voltage fault threshold

Input over-voltage warning threshold

Input under-voltage warning threshold

Input under-voltage fault threshold

1

10

Accuracy (all settings)

Programmable Range

Resolution

-3

3

90

160

T_OTW

V_IOVF

V_IOVW

V_IUVW

V_IUVF

t_IUVF

Accuracy (all settings)

Programmable Range

Resolution

-3

4

3

18

1

V

Accuracy

-2

4

2

%

V

Programmable Range

Resolution

18

1

V

Accuracy

-2

2

%

V

Programmable Range

Resolution

4.25

11.5

0.25

V

Accuracy (all settings)

Programmable Range

Resolution

-0.25

4.0

0.25

V

11.25

Accuracy (all settings)

-0.25

0.25

300

128

V

Input Under-Voltage Fault Response

Time ⁽¹⁾

Time from VIN < V_IUVFto converter

shutdown

VIN_UV_FAULT_RESPONSE = 80h

Shutdown immediately, do not restart

µs

Programmable Range

Resolution

4

A

I_IOCF

Input over-current fault threshold

4

Accuracy (all settings)

Programmable Range

Resolution

-3.5

4

3.5

A

128

A

I_IOCW

Input over-current warning threshold

A

Accuracy (all settings)

USER_DATA_11[15:14] = 00b

USER_DATA_11[15:14] = 01b

USER_DATA_11[15:14] = 10b

USER_DATA_11[15:14] = 11b

-4

4

A

5

10

25

50

ms

Hiccup Wait Time ⁽¹⁾

Applies only to HICCUP fault responses

t_HICCUP

ATSEN/BTSEN pin voltage causing

Power stage fault (TAO HIGH)

V_PSFLT

2.6

2.4

0.2

V

ATSEN/BTSEN pin voltage clearing

Power stage fault (TAO HIGH)

ATSEN/BTSEN pin voltage hysteresis for

Power stage fault (TAO HIGH)

(1) Guaranteed by Design.

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(2) Settings are programmed through PMBus commands as described in the Programming section of this document. The device internally

maps programmed settings to hardware supported values.

6.4.19 PMBus Interface

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J= -40 to 125 ℃ unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PMBus Interface and Timing

PMBus Free time between STOP and

START conditions ⁽¹⁾

t_PMB-BUF

0.5

0.26

0

µs

ns

ms

t_PMB-HD-Hold time after Repeated Start Condition

(1)

STA

t_PMB-SU-

Stop condition Setup time ⁽¹⁾

STO

t_PMB-HD-

SMB_DIO Hold Time ^{(1) (2)}

DAT

t_PMB-SU-

SMB_DIO Setup Time ⁽¹⁾

50

DAT

t_PMB-

SMB_CLK low timeout ^{(1) (3)}

25

35

TIMEOUT

t_PMB-LOWSMB_CLK low time ⁽¹⁾

0.5

µs

t_PMB-HIGHSMB_CLK high time ^{(1) (4)}

0.26

50

25

t_PMB-LOW-Maximum clock stretching time (slave)

ms

(1) (5)

SEXT

t_PMB-LOW-Maximum clock stretching time (master)

10

(1) (6)

MEXT

100 kHz Class

1000

300

120

1000

300

120

50

ns

SMB_DIO/SMB_CLK rise time,

t_R-PMB

400 kHz Class

1000 kHz Class

100 kHz Class

400 kHz Class

1000 kHz Class

( V_IL(MAX)-150 mV to V_IH(MIN)+150 mV) ⁽¹⁾

SMB_DIO/SMB_CLK fall time, ( V_IH(MIN)

t_F-PMB

+150 mV to V_IL(MAX)+ 150 mV) ⁽¹⁾

t_PMB-REJNoise spike suppression-time ^{(1) (7)}

I_LK-PMB-

Input leakage per PMBus segment ⁽¹⁾

-200

-10

200

10

µA

BUS

I_LK-PMB-

Input leakage for PMBus pins

C_PMB-BUSPMBus Bus Capacitance ⁽¹⁾

400

10

pF

C_PMB-PINPMBus Pin Capacitance ⁽¹⁾

V_{PULLUP_}

PMBus interface pull ups ⁽¹⁾

1.62

1.35

3.6

0.8

V

PMBus

V_{IL_PMBus}SMB_DIO, SMB_CLK Input logic low

V_{IH_PMBu}

SMB_DIO, SMB_CLK Input logic high

s

V_{HYST_PM}

Hysteresis voltage ⁽¹⁾

150

250

350

2

mV

Bus

PMB_CLKRPMBus clock frequency range ⁽¹⁾

PMBus clock ⁽⁸⁾

0.05

MHz

(1) Guaranteed by Design.

(2) A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the V_{IH, MIN}of the SMBCLK signal) to

bridge the undefined region of the falling edge of SMBCLK.

(3) Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds

the value of t_{TIMEOUT, MIN}. After the master in a transaction detects this condition, it must generate a stop condition within or after

the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able

to receive a new START condition no later than t_{TIMEOUT, MAX}. Typical device examples include the host controller, and embedded

controller, and most devices that can master the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind

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of device typically may reset its communications port after a start or a stop condition. A timeout condition can only be ensured if the

device that is forcing the timeout holds the SMBCLK low for t_{TIMEOUT, MAX}or longer

(4) t_{PMB-HIGH, MAX}provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is

free if it detects that the clock and data signals have been high for greater than t_{HIGH, MAX}

.

(5) t_PMB-LOW-SEXTis the cumulative time a given slave device is allowed to extend the clock cycles in one message from the initial START

to the STOP. It is possible that another slave device or the master extends the clock causing the combined clock low extend time to be

greater than tLOW:SEXT. Therefore, this parameter is measured with the slave device as the sole target of a full-speed master

(6) t_PMB-LOW-MEXTis the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined

from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device or another master extends the clock causing the

combined clock low time to be greater

(7) Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

(8) I2C High-Speed mode is not supported

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6.5 Typical Characteristics

Figure 6-1. Quiescent current vs. junction

temperature

Figure 6-2. VREF voltage vs. junction temperature

Figure 6-3. Pull-down resistance vs. junction

temperature

Figure 6-4. PWM output voltage vs. junction

temperature (0.5 mA bias)

Figure 6-5. AVR_EN / BVR_EN logic threshold vs.

junction temperature

Figure 6-6. AVSP, BVSP, AVSN, BVSN leakage vs.

junction temperature (1.0 V bias)

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7 Detailed Description

7.1 Overview

The TPS536C7B1 is a 12-phase step-down controller with two channels, built-in non-volatile memory (NVM), a

PMBus v1.3.1 interface, and is fully compatible with TI NexFET power stages.

7.2 Functional Block Diagram

DCLLA

COMPA

Tristate

Driver /

Logic

AVSP

AVSN

Differential

Amplifier

T_ON

1-Shot

VRAMPA

VCOMPA

VISUMA

APWM1

+

VDIFFA

VISUMA

VFBDRPA

VDACA

+

CLKA_ON

CLKB_ON

Loadline

Control

Programmable

Loop

Mode Control

and

Programmable

Phase Manager

BVSP

BVSN

Differential

Amplifier

VRAMPB

VCOMPB

VISUMB

+

VDIFFB

VISUMB

VFBDRPB

VDACB

+

Loadline

Control

Programmable

Loop

Tristate

Driver /

Logic

T_ON

1-Shot

APWM12 / BPWM1

DCLLB

COMPB

Phase Config

VISUMA

ACSP1

VISUMB

IL1

Current

Sensing

Amplifiers

AVR_EN

Analog

Mux

IL1

BVR_EN

ACSP12 / BCSP1

Fault Management,

Status Detection and

State Control

IL12

AVR_RDY

BVR_RDY

VR_FAULT#

Adaptive

On-Time Control

and

Current Sharing

Circuitry

V3P3

GND

FAULT

VRAMPA VRAMPB

Ramp

Generator

VDACA

VDACB

ADDR_CONFIG

VBOOT_CHA

I²C Interface and

Digital Logic

Pin Detection

Circuit

IIN

SMB_CLK

NVM

AFE, ADC, and DAC

SMB_ALERT#

SMB_DIO

VDACA

VDACB

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7.3 Power-up and initialization

7.3.1 First power-up

When power is applied to TPS536C7B1, an initialization procedure performs self-checks of internal memories,

performs pin detection, and loads the values stored in non-volatile memory to operating memory. This procedure

can take up to 20 ms to complete, during which time the device may not respond to PMBus commands.

Initialization takes place the first time power is applied to the VCC pin and does not repeat unless the device

is power cycled. Pin configuration is loaded during this time. Until initialization is complete, all pins remain high

impedance, except for the AVR_RDY and BVR_RDY pins which are pulled low by default.

Once initialization is complete, the device waits for an enable condition specified by the ON_OFF_CONFIG

command to begin power conversion. By default the device is configured to wait for the AVR_EN pin to be set

high to enable channel A, and the BVR_EN pin to be set high to enable channel B. Once an enable condition is

received, TPS536C7B1 checks that the powerstage input supply (VIN_CSNIN pin) is above the VIN_ON value,

and the powerstage driver is fully powered (e.g. that no TAO_LOW condition exists). This takes approximately

750 μs (up to 1.0 ms) to complete before the first PWM pulses are output by the controller. This process repeats

each time power conversion is enabled for any reason, including enable cycling or fault shutdown.

Continue

Waiting

Begin accepting

PMBus commands.

Initialize

+3.3 V Power

Applied to VCC

NVM and Trim bits,

Pinstrap Detection

Up to 20 ms

Wait for Enable

Condition per

ON_OFF_CONFIG,

or hiccup/hysteresis

fault recovery

Fault

Not

Ready

Yet

Power

Conversion

Continues

Check for faults, UVLO

and Powerstages ready,

begin enable sequence

Power Conversion

Output voltage begins

rising to VBOOT,

VR_RDY releases

Up to 1 ms

Fault Condition

Figure 7-1. Initialization process

7.3.2 Boot voltage configuration (VBOOT)

By default, the boot voltage for channel A is given by pin-detection on the VBOOT_CHA pin. Alternatively,

configure the device to use a value stored in non-volatile memory (NVM) for VOUT_COMMAND using

the PIN_DETECT_OVERRIDE command. See Pin-strap Detection and PIN_DETECT_OVERRIDE for more

information. The boot voltage for Channel B is given by the value stored in non-volatile memory for

VOUT_COMMAND always. Whenever power conversion is enabled, each channel boots to its VBOOT value,

regardless of whether the output voltage was changed after the last boot-up.

Use the VOUT_COMMAND PMBus command to change the output voltage on-the-fly. This is one

implementation of adaptive voltage scaling (AVS) or dynamic VID (DVID). Output voltage transitions occur at

the value slew rate specified by the VOUT_TRANSITION_RATE command.

7.3.3 Power Sequencing

There are no strict supply sequencing requirements for TPS536C7B1. VIN_CSNIN and CSP, the powerstage 5-

V supply, and the controller VCC (3.3-V) may be safely powered up independently of each other. TI recommends

that power conversion be commanded on only after all supplies are established and have had time to settle.

Refer to Power Supply Recommendations for more detailed information.

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7.4 Pin connections and bevahior

7.4.1 Supplies: VCC and VREF

The VCC pin supplies all analog and digital circuits internal to the device. Connect a 3.3-V supply voltage, and

local ceramic bypass capacitor with a minimum effective capacitance of 1.0 µF.

The VREF pin is the output of an internal LDO with a nominal voltage of 1.5 V. The VREF voltage provides a

common-mode voltage for the power stage IOUT pins, as well as internal analog circuits. Bypass the VREF pin

local to the controller, with a ceramic bypass capacitor with a minimum effective capacitance of 1.0 µF. Connect

VREF to the REFIN pins of the power stages.

7.4.2 Differential remote sensing and output voltage scaling: AVSP/AVSN, BVSP/BVSN

A differential remote sense amplifier enables the controller to compensate for I×R drop due to PCB copper, in

high current applications. Connect the AVSP/BVSP and AVSN/BVSN pins respectively to the output voltage at

the load point, through the network described in Figure 7-2. A connection to the output voltage, local to the

power stages, shown by R_{LCL_P}and R_{LCL_N}, maintains closed loop operation even if the load is uninstalled, or

the remote sense connection is opened. Route the differential remote sense lines as a tightly-coupled differential

pair, and maintain a wide clearance to any fast switching nets, such as power stage switch nodes or power

input voltage. Optionally, use a small filtering capacitor, shown as C_FILT, at the controller side to improve noise

immunity.

The output voltage set-point is generated by an internal precision reference DAC. The reference DAC is capable

of producing reference voltages up to 1.87 V. For output voltage set-points below 1.87 V, no scaling (internal or

external) is required, and the sensed output voltage is compared directly to the reference voltage.

For output voltage set-points between 1.87 V and 3.74 V, the controller applies internal scaling of the remote

sense amplifier, and no external sense divider is needed. Set the VOUT_MAX command greater than 1.87 V to

enable this internal scaling. For output voltage set-points greater than 3.74 V, apply an external sense divider

with R_{RMT_P}= R_DIV= 500 Ω, and set the VOUT_SCALE_LOOP command to 0.5 V/V. This enables output

voltage set-points up to 5.5 V. The overvoltage/undervoltage thresholds are referenced to the VSP/VSN pins

only and need to be scaled appropriately for applications with an external resistor divider. Refer to Table 7-1 for

more information.

TPS536C7B1 performs an open/short detection on the AVSP/AVSN and BVSP/BVSN pins at initialization to

determine if the voltage sense lines are open. The controller flags a fault condition and does not attempt to boot

if an open sense line is detected. Ground the VSP/VSN lines for unused channels to prevent false-triggering,

in applications which do not make use of both channels. As such, the local sense resistor connection may be

omitted, but is still recommended for debug and system bode plot measurement.

VOUT Local

R_{LCL_P}

R_{RMT_P}

AVSP/BVSP

VOUT+

VDROOP

Remote Sense and

Droop Amplifier

C_FILT

R_DIV

To Control Loop

R_{RMT_N}

AVSN/BVSN

VOUT-

R_{LCL_N}

GND Local

VDAC

Voltage

Reference

DAC

VOUT_COMMAND

×

VOUT_SCALE_LOOP

VOUT_MAX

Figure 7-2. Differential remote sensing

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Table 7-1. Component and command values

Component / Command

R_{LCL_P}

Value (Vout ≤ 1.87 V)

Value (1.87 V < Vout ≤ 3.74 V)

Value (3.74 V < Vout ≤ 5.5 V)

DNP

R_{RMT_P}

0 Ω

500 Ω

R_{RMT_N}

0 Ω

R_{LCL_N}

DNP

500 Ω

R_DIV

C_FILT

100 pF (optional)

1.0

100 pF (optional)

1.0

100 pF (optional)

0.5

VOUT_SCALE_LOOP

VOUT_MAX

VOUT_COMMAND

VOUT_MAX ≤ 1.87 V

VOUT_COMMAND ≤ 1.87 V

1.87 V < VOUT_MAX ≤ 3.74 V

VOUT_COMMAND ≤ 3.74 V

3.74 V < VOUT_MAX ≤ 5.5 V

VOUT_COMMAND ≤ 5.5 V

7.4.3 Input current sensing: VIN_CSNIN and CSPIN

The VIN_CSNIN and CSP pins are internally connected to a high-side current sense amplifier. Kelvin connect

these pins to the external sense element R_SENSEas shown in Figure 7-3, and route back to the controller as

a tightly coupled differential pair. R_SENSEmay be a precision current sense shunt resistor or an input inductor

DCR, with an associated temperature compensation network. TI recommends adding common-mode filtering

capacitors, shown as C_CMFILT, and a differential-mode filtering capacitor C_DMFILTto reduce measurement noise.

A typical value for these capacitors is 1.0 µF.

For designs that do not use input current sensing, connect VIN_CSNIN and CSPIN together, and to the

input voltage supply. The controller requires input voltage sense for proper on-time generation. Ensure the

VIN_CSNIN and CSPIN pins remain within ± 300 mV due to internal ESD protection structures on these pins.

To Power stage VIN

R_SENSE

Pins/pads

PVIN

TPS536xx

To On-Time

Generators

VIN_CSNIN

CSPIN

C_DMFILT

œ

READ_IIN

ADC

ꢀ

+

800mV

Max

G_INSHUNT

Digital Gain

G_IINMAX= 0 to 255

C_CMFILT

Analog Front-End Gain

20 to 100

IIN Offset

IIN_OFS = -8 A to +7.9375A

Figure 7-3. Input current sensing

Once properly calibrated, the READ_IIN command returns measured input current data in real time. Power

supply telemetry and calibration describes the process and equations for input current calibration.

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7.4.4 Pin-strap detection and PIN_DETECT_OVERRIDE

The ADDR_CONFIG pin provides limited resistor pin detection for the PMBus slave address, and phase

configuration. Connect a resistor divider to ADDR_CONFIG as shown in Figure 7-4. Refer to Table 7-2 to

select resistor values. The table shows series E96 value equivalents. Use 1% tolerance resistors for all values.

After pin detection completes, the decoded results are loaded into the SLAVE_ADDRESS and PHASE_CONFIG

commands. Phase firing order is automatically selected by pin detection. Disable phase number detection on the

ADDR_CONFIG pin detection using PIN_DETECT_OVERRIDE, to use a non-default firing order.

The VBOOT_CHA pin provides resistor pin detection for the channel A boot voltage. The channel B boot

voltage does not have pin detection and must be programmed in non-volatile memory. Connect a resistor divider

to VBOOT_CHA as shown in Figure 7-4. The table shows series E96 value equivalents. Use 1% tolerance

resistors for all values. After pin detection completes, the decoded result is loaded into the VOUT_COMMAND

command for PAGE 0.

For each each pin detection, during boot-up the device performs two measurements to determine an 8 bit binary

number, referred to as the pinstrap decode. The 3 LSB bits are determined by shorting the high-side resistor

and measuring the low-side resistor value. The 5 MSB bits are determined by measuring the pin voltage. The

decoded value is then mapped to the configuration values shown in the tables below.

Values not given by ADDR_CONFIG pinstrap decoding and VBOOT_CHA pinstrap decoding can still be

achieved using the PIN_DETECT_OVERRIDE command. This command instructs the device at power-up,

whether to follow the values given by pin detection, or use values stored in non-volatile memory to populate

the SLAVE_ADDRESS, PHASE_CONFIG and VOUT_COMMAND commands. Each parameter has a separate

control, so it is possible, for example, to pin detect PMBus address, while taking phase configuration from NVM.

TPS536xx

VREF

R_HB

R_HA

ADDR_CONFIG

VBOOT_CHA

R_LB

R_LA

Figure 7-4. Pin-strap pin connections

Example: Selecting a PMBus address not available by pin-strapping

1. Select the ADDR_CONFIG resistors R_HAand R_LAto ensure each device on the bus still has a unique

adddress at the first power-up. Each device still must be addressed uniquely, in order to configure the

PIN_DETECT_OVERRIDE command.

2. Write bit 2 in PIN_DETECT_OVERRIDE command to 0b, to disable pin detection for the PMBus Address on

the ADDR_CONFIG pin.

3. Write the SLAVE_ADDRESS command, to configure the new slave address, in 7-bit right-justified binary

format (e.g. 96d = 1100000b).

4. Issue a STORE_USER_ALL command to commit the configuration to non-volatile memory

5. At the next power cycle, the values stored in non-volatile memory are used, instead of those selected by the

ADDR_CONFIG resistors selected.

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SPACE

Table 7-2. ADDR_CONFIG pinstrap decoding

Phase Configuration

12 + 0

LSB = 000b

11 + 0

10 + 2

9 + 2

8 + 2

7 + 2

6 + 2

5 + 2

(Ch. A + Ch. B)

LSB = 001b

LSB = 010b

LSB = 011b

LSB = 100b

LSB = 101b

LSB = 110b

LSB = 111b

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

R_HA

R_LA

MSB

PMBus Address

(kΩ)

00000b

00001b

00010b

00011b

00100b

00101b

00110b

00111b

01000b

01001b

01010b

01011b

01100b

01101b

01110b

01111b

10000b

10001b

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

88d / B0h

89d / B2h

90d / B4h

91d / B6h

92d / B8h

93d / BAh

94d / BCh

95d / BEh

96d / C0h

97d / C2h

98d / C4h

99d / C6h

100d / C8h

101d / CAh

102d / CCh

103d / CEh

104d / D0h

105d / D2h

106d / D4h

107d / D6h

108d / D8h

109d / DAh

110d / DCh

111d / DEh

112d / E0h

113d / E2h

114d / E4h

115d / E6h

116d / E8h

117d / EAh

118d / ECh

119d / EEh

1300

422

249

169

127

102

82.5

68.1

59

20

1780

576

340

232

174

140

113

27.4

2430

787

464

316

237

191

154

130

110

37.4

3240

1050

619

422

316

255

205

174

147

49.9

4220

1370

806

549

412

332

267

226

191

64.9

5620

1820

1070

732

86.6

7500

2430

1430

976

115

9760

3240

1910

1300

976

154

549

732

442

576

787

357

475

634

95.3

80.6

301

392

536

255

332

453

Not recommended - reserved SMBus address

43.2

38.3

33.2

29.4

26.1

23.2

20.5

18.2

16.2

14.3

12.4

11.0

9.5

20

59

27.4

80.6

71.5

61.9

54.9

48.7

43.2

38.3

34.0

30.1

26.7

23.2

20.5

18.2

15.8

13.3

11.5

9.5

37.4

110

95.3

82.5

73.2

64.9

57.6

51.1

45.3

40.2

35.7

30.9

27.4

24.3

21.0

17.8

15.4

13.0

10.5

8.5

49.9

140

124

64.9

187

165

143

127

113

86.6

249

221

191

169

150

133

118

115

332

294

255

226

200

178

158

140

124

110

154

52.3

45.3

40.2

35.7

31.6

28.0

24.9

22.1

19.6

17.4

15.0

13.3

11.5

9.8

107

95.3

84.5

73.2

66.5

57.6

51.1

45.3

40.2

35.7

30.9

26.7

23.2

19.6

16.5

13.7

11.0

8.5

97.6

88.7

78.7

69.8

61.9

53.6

47.5

41.2

36.5

30.9

26.7

22.1

18.2

14.7

11.3

8.1

105

93.1

82.5

71.5

63.4

54.9

48.7

41.2

35.7

29.4

24.3

19.6

15.0

10.7

6.7

95.3

84.5

75.0

64.9

54.9

47.5

40.2

32.4

26.1

20.0

14.3

8.9

8.5

7.2

6.2

8.5

5.1

7.2

4.2

5.8

7.9

3.4

4.6

6.3

2.6

3.6

4.9

6.5

1.9

2.6

3.5

4.6

6.0

1.2

1.6

2.2

2.9

3.7

5.0

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SPACE

Table 7-3. VBOOT_CHA Pinstrap Decoding

R_LB= 20.0 kΩ

LSB = 000b

R_LB= 27.4 kΩ

LSB = 001b

R_LB= 37.4 kΩ

R_LB= 49.9 kΩ

R_LB= 64.9 kΩ

R_LB= 86.6 kΩ

R_LB= 115.0 kΩ

LSB = 110b

R_LB= 154.0 kΩ

LSB = 111b

LSB = 010b

LSB = 011b

LSB = 100b

LSB = 101b

V_BOOTA

R_HB(kΩ)

(V)

MSB

R_HB(kΩ)

(V)

0.3

00000b

00001b

00010b

00011b

00100b

00101b

00110b

00111b

01000b

01001b

01010b

01011b

01100b

01101b

01110b

01111b

10000b

10001b

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

Do Not Use

0.25

0.33

0.41

0.49

0.57

0.65

0.73

0.81

0.89

0.97

1.05

1.13

1.21

1.29

1.37

1.45

1.53

1.61

1.69

1.77

1.85

1.93

2.01

2.09

2.17

2.25

2.33

2.41

2.49

2.57

2.65

2.73

1780

576

340

232

174

140

113

0.26

0.34

0.42

0.5

2430

787

0.27

0.35

0.43

0.51

0.59

0.67

0.75

0.83

0.91

0.99

1.07

1.15

1.23

1.31

1.39

1.47

1.55

1.63

1.71

1.79

1.87

1.95

2.03

2.11

2.19

2.27

2.35

2.43

2.51

2.59

2.67

2.75

3240

1050

619

422

316

255

205

174

147

124

110

0.28

0.36

0.44

0.52

0.6

4220

1370

806

549

412

332

267

226

191

162

140

124

107

95.3

84.5

75

0.29

0.37

0.45

0.53

0.61

0.69

0.77

0.85

0.93

1.01

1.09

1.17

1.25

1.33

1.41

1.49

1.57

1.65

1.73

1.81

1.89

1.97

2.05

2.13

2.21

2.29

2.37

2.45

2.53

2.61

2.69

2.77

5620

1820

1070

732

7500

2430

1430

976

732

576

475

392

332

287

249

221

191

169

150

133

118

0.31

0.39

0.47

0.55

0.63

0.71

0.79

0.87

0.95

1.03

1.11

1.19

1.27

1.35

1.43

1.51

1.59

1.67

1.75

1.83

1.91

1.99

2.07

2.15

2.23

2.31

2.39

2.47

2.55

2.63

2.71

5 ⁽¹⁾

9760

3240

1910

1300

976

787

634

536

453

383

332

294

255

226

200

178

158

140

124

110

0.32

0.4

422

249

169

127

102

82.5

68.1

59

0.38

0.46

0.54

0.62

0.7

464

0.48

0.56

0.64

0.72

0.8

316

0.58

0.66

0.74

0.82

0.90

0.98

1.06

1.14

1.22

1.3

237

549

191

0.68

0.76

0.84

0.92

1

442

154

357

0.78

0.86

0.94

1.02

1.1

95.3

80.6

68.1

59

130

301

0.88

0.96

1.04

1.12

1.2

110

255

49.9

43.2

38.3

33.2

29.4

26.1

23.2

20.5

18.2

16.2

14.3

12.4

11

93.1

80.6

71.5

61.9

54.9

48.7

43.2

38.3

34

215

1.08

1.16

1.24

1.32

1.4

187

52.3

45.3

40.2

35.7

31.6

28

95.3

82.5

73.2

64.9

57.6

51.1

45.3

40.2

35.7

30.9

27.4

24.3

21

165

1.18

1.26

1.34

1.42

1.5

143

1.28

1.36

1.44

1.52

1.6

127

1.38

1.46

1.54

1.62

1.7

113

1.48

1.56

1.64

1.72

1.8

97.6

88.7

78.7

69.8

61.9

53.6

47.5

41.2

36.5

30.9

26.7

22.1

18.2

14.7

11.3

8.06

4.99

66.5

59

1.58

1.66

1.74

1.82

1.9

24.9

22.1

19.6

17.4

15

105

93.1

82.5

71.5

63.4

54.9

48.7

41.2

35.7

29.4

24.3

19.6

15

1.68

1.76

1.84

1.92

2

30.1

26.7

23.2

20.5

18.2

15.8

13.3

11.5

9.53

7.87

6.34

4.87

3.48

2.15

52.3

46.4

40.2

35.7

30.9

27.4

23.2

20

1.78

1.86

1.94

2.02

2.1

1.88

1.96

2.04

2.12

2.2

95.3

84.5

75

1.98

2.06

2.14

2.22

2.30

2.38

2.46

2.54

2.62

2.70

3.3 ⁽¹⁾

9.53

8.45

7.15

6.19

5.11

4.22

3.4

13.3

11.5

9.76

8.45

7.15

5.76

4.64

3.57

2.55

1.58

2.08

2.16

2.24

2.32

2.4

64.9

54.9

47.5

40.2

32.4

26.1

20

2.18

2.26

2.34

2.42

2.50

2.58

2.66

2.74

17.8

15.4

13

2.28

2.36

2.44

2.52

2.60

2.68

2.76

16.9

13.7

11

10.5

8.45

6.49

4.64

2.87

2.48

2.56

2.64

2.72

2.61

1.87

1.15

8.45

6.04

3.74

10.7

6.65

14.3

8.87

(1) Requires the use of an external output voltage divider.

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7.4.5 Enable and disable: AVR_EN and BVR_EN

The ON_OFF_CONFIG command controls the conditions which TPS536C7B1 requires to enable power

conversion. By default only the AVR_EN (active high) pin enables channel A, and only the BVR_EN pin (active

high) enables channel B. This command can program the controller ignore the VR_EN pins and require the

OPERATION command to be sent to enable power conversion, or even require a combination of the two.

When enabled, first the controller waits for a delay time given by TON_DELAY, then ramps the output voltage at

a controlled slew rate SR_BOOT. The device requires 750 μs typically (up to 1.0 ms), to begin ramping the output

voltage, after being enabled. Turn-on delay added by the TON_DELAY is in addition to this delay.

The ON_OFF_CONFIG command also controls the turn-off behavior. When configured for immediate-off, the

controller immediately tri-states all PWM pins assigned to that channel and stops transferring power immediately.

When configured for soft-off the controller first waits for the TOFF_DELAY time, then actively ramps down the

output voltage at a controlled slew rate.

VR_EN

SR_OFF

VOUT

SR_BOOT

Decay based

on load current

t_{EN_INIT}

TON_DELAY

TOFF_DELAY

Figure 7-5. Soft-start and immediate-off (decay)

Figure 7-6. Soft-start and soft-off

The TON_RISE and TOFF_FALL commands are used to calculate the turn-on and turn-off (in the case of

soft-off) slew rates. While these commands are numerically programmable from 0 to 31.75 ms, only a limited

set of slew rates are supported. During enable, the device calculates the target rising and falling slew rates

according to Equation 1 and Table 7-4, then selects the nearest available value from Table 7-4.

VOUT_COMMAND

SR

= LOOKUP

(1)

(2)

BOOT

TON_RISE

VOUT_COMMAND

TOFF_FALL

SR

= LOOKUP

OFF

Table 7-4. Supported SR_BOOTand SR_OFFslew rates

Supported slew rates (mV/μs)

0.093

0.097

0.101

0.105

0.111

0.117

0.124

0.131

0.140

0.151

1.163

0.175

0.192

0.313

0.625

0.938

1.250

1.563

1.875

2.188

2.50

5.00

10.00

15.00

20.00

25.00

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Table 7-4. Supported SR_BOOTand SR_OFFslew rates (continued)

Supported slew rates (mV/μs)

0.213

0.238

0.265

30.00

35.00

40.00

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Example: VOUT_COMMAND = 0.88 V, TON_RISE = 1.0 ms

The target slew rate is calculated as SR_BOOT= LOOKUP(880 mV/1000 μs) = 0.88 mV/μs. The nearest supported

value of 0.9375 mV/μs is selected.

The expected rise time is approximately (880 mV / 0.9375 mV/μs) ≈ 940 μs.

7.4.6 System feedback: AVR_RDY and BVR_RDY

The AVR_RDY and BVR_RDY pins are used to signal to the system, when each channel is in regulation. These

pins are open drain structures, and require external pull-up resistors. During boot-up, the VR_RDY pins are

released when the internal reference DAC reaches the boot voltage. Any condition which causes the channel to

stop converting power, causes its VR_RDY pin to pull low. This includes any fault protection-related shutdown, or

the channel simply being disabled. The VR_RDY pins do not assert to alert the host to any warning conditions or

faults configured to be ignored.

7.4.7 Catastrophic fault alert: VR_FAULT#

The VR_FAULT# pin is an open drain output which alerts the system to potentially catastrophic power supply

faults. The VR_FAULT# pin is an open drain structure. Connect an external pull-up resistor to this pin.

Only the most critical fault conditions assert the VR_FAULT# pin. Fault responses configured to be ignored do

not assert the VR_FAULT# pin. The VR_FAULT_CONFIG PMBus command provides some options to control

which fault conditions cause this pin to assert.

Fault conditions which assert the VR_FAULT# pin include:

•

Over-voltage fault (including pre-bias OVP, fixed OVP, and tracking OVP)

Powerstage fault (TAO_HIGH)

Input overcurrent fault

Output overcurrent fault (configurable)

Over-temperature fault (configurable)

Faults from channel A only, or channel A+B (configurable)

7.4.8 Output voltage reset: RESET#

By default, pin 19 functions as the channel B enable pin, BVR_EN. Use the command to assign pin 19 as a

hardware voltage reset signal, RESET#, as needed. When pin 19 is not assigned as BVR_EN, the AVR_EN pin

becomes a shared enable pin for both channels. RESET# is an active-low signal. Connect an external pull-up to

this pin to make its default state high (e.g. not in reset).

Asserting the RESET# pin low during regulation causes the output voltage of both channels to slew back to their

respective V_BOOTvalues, at the slew rate defined by . While RESET# is asserted low, new output voltage targets

from PMBus are ignored. Figure 7-7 describes the behavior of the RESET# pin.

VR_EN

RESET#

V_NEW

SR_VOTR

V_BOOT

Reset

After

V_BOOT

SR_BOOT

voltage

settled

New target

from PMBus

New target

from PMBus

Reset during

Voltage slew

Figure 7-7. RESET# behavior

The RESET# pin is not a global reset pin for the device. Asserting RESET# changes only the output voltage

target of both channels. RESET# does not cause any operating state change or re-initialization.

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7.4.9 Synchronization: SYNC

By default, pin 19 functions as the channel B enable pin, BVR_EN. Use the MULTIFUNCTION_PIN_CONFIG

command to assign pin 19 as a synchronization pin as needed. When pin 19 is not assigned as BVR_EN,

the AVR_EN pin becomes a shared enable pin for both channels. When there is no SYNC pin assigned,

configure the SYNC_CONFIG to operate based on internal timing, in order to maintain an accurate switching

frequency over the full range of operation. Any external clock applied to must have a 50% duty cycle,

and the FREQUENCY_SWITCH command must still be programmed as close as possible to the desired

switching frequency after any scaling. The input on the SYNC pin must be ±50 kHz from the configured

FREQUENCY_SWITCH value.

An internal phase-locked loop (PLL) adjusting the on-time of each phase enables edge synchronization. During

steady-state operation, when synchronization is used, the PWM pin assigned to order 0 is synchronized to

a clock on the SYNC pin. The DCAP+ control topology is inherently a variable frequency scheme. During

load transients, the pulse frequency of each channel modulates to maintain voltage regulation. Load transients

cause the PLL to lose phase lock, and slowly return to phase lock based on the PLL loop bandwidth. The

PLL bandwidth is much slower than the voltage regulation loop, and it can take many cycles for the PLL to

re-lock following a transient event. Figure 7-8 illustrates the DCAP+ response to a load transient using edge

synchronization.

I_OUT

PLL corrects phase error

Phase delay of

between PWM1 and SYNC

SYNC to PWM1

SYNC

CLK_ON

PLL

Locked

PLL

Locked

PLL

Locked

Not

Locked

PWM1

PWM2

Figure 7-8. Synchronization behavior (2 phase example, no phase shift)

The SYNC_CONFIG command configures various options related to synchronization. These include: enable/

disable of the PLL, sync direction (clock master or clock slave), input clock division ratio, phase shift, and

gain/scalar terms to increase/decrease the PLL loop bandwidth. Refer to the Technical Reference Manual for a

complete register map.

Figure 7-9 and Figure 7-10 illustrate two common methods of synchronizing multiple converters based on

TPS536C7B1. Use the programmable phase shift parameters to phase spread multiple converters, to improve

ripple cancellation and reduce beat frequencies on input supplies.

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TPS536xx

50% duty

SYNC

SYNC_DIR = IN

SYNC_DIR = OUT

SYNC_PHASE = 0°

SYNC_DIR = IN

SYNC_PHASE = 0°

SYNC_PHASE = 180°

Figure 7-10. Two clock slaves driven externally

Figure 7-9. Clock master driving a clock slave

7.4.10 Smart power stage connections: PWM, CSP and TSEN

Interface the controller to TI smart power stage devices, as shown in Figure 7-11.

Connect the PWM pins of the controller to the PWM pins of the power stage devices. The PWM pins are

three-state logic outputs of the controller. A PWM pin being logic-high commands the power stage device to turn

its high-side FET on, and its low-side FET off. A PWM pin being logic-low commands the power stage device to

turn its low-side FET on and its high-side FET off. TI power stage devices provide a weak drive on their PWM

pins, causing them to float to a mid-level value when the controller stops driving them. During enable, or dynamic

phase addition, the controller starts phases switching with a transition from tri-state to high. Similarly, during

disable or dynamic phase shedding, the controller disables phases with a transition from low-to-tri-state. Float

unused PWM pins on the controller.

Connect the IOUT pins of the powerstage devices to the CSP pins of the controller. Connect the VREF pin

of the controller to the REFIN pins of the powerstage devices. A local bypass capacitor C_VREF, is required

for the controller VREF pin. Optionally, add a local VREF bypass capacitor at the powerstage devices. VREF

provides common-mode voltage for the IOUT signal, which is a voltage representing the output current of each

powerstage with a nominal gain of 5 mV/A. Float unused CSP pins on the controller.

Connect the TAO/FAULT pins of all powerstages within a channel to each other, and to the corresponding TSEN

pin of the controller. For example, tie all TAO/FAULT pins of powerstages used on channel A together and to

the controller ATSEN pin. TI recommends adding a 2200 pF capacitor to the TSEN pins at the controller to

reduce temperature measurement noise. TI recommends keeping a place holder for a 1000 pF capacitor at

the powerstage side. Refer to the individual powerstage datasheet for more detailed recommendations. During

normal operation, the TSEN pins provide a voltage signal proportional to the temperature of the warmest

powerstage device according to Equation 3 . During a UVLO condition, the powerstages pull the shared TAO line

low to inform the controller they are not able to accept PWM input. When powerstages detect a fault condition

internally, they pull the shared TAO pin high to inform the controller a fault condition has occurred. If channel B is

not used, float the BTSEN pin.

V

− 600mV

TSEN

8mV

READ_TEMPERATURE_1 =

°C

(3)

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TPS536xx

CSD9xxx

APWM1

ACSP1

PWM

IOUT

Channel A

Phase 1

TAO/FAULT

REFIN

DNP

VREF

C_VREF

...

CSD9xxx

APWMx

ACSPx

PWM

Controller

IOUT

Channel A

Phase N

TAO/FAULT

REFIN

ATSEN

C_ATSEN

DNP

CSD9xxx

BPWMx

BCSPx

BTSEN

PWM

IOUT

Channel B

Phase 1

TAO/FAULT

C_BTSEN

DNP

REFIN

to other channel

B power stages

Figure 7-11. Power stage pin connections

7.4.11 PMBus pins: SMB_DIO, SMB_CLK, and SMB_ALERT#

The SMB_CLK, SMB_DIO, and SMB_ALERT# pins are used for PMBus communication, an open-drain

interface. TPS536C7B1 is compatible with both 1.8-V and 3.3-V logic levels as shown in to Part I of the PMBus

specification, revision v1.3.1. At least one external pull-up resistor is required for these pins. The 100 kHz, 400

kHz and 1 MHz modes of operation are supported. PMBus is a shared bus, where devices are assigned a

communication address. Select the PMBus slave address as described in Section 7.4.4. The controller device

stretches clock pulses during operation when more processing time is required. Clock stretching support in the

PMBus master is mandatory. See the Section 7.9 section for more information about PMBus functionality.

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7.5 Advanced power management functions

7.5.1 Adaptive voltage scaling or dynamic VID (DVID) through VOUT_COMMAND

Figure 7-12 shows a conceptual view of the TPS536C7B1 output voltage control, and dynamic behavior.

Update the VOUT_COMMAND value through PMBus to change the output voltage of each channel on-the-fly.

Optionally, use the OPERATION command to toggle the output voltage bewteen the VOUT_MARGIN_HIGH,

VOUT_MARGIN_LOW and VOUT_COMMAND values. This is described in more detail in Output voltage

margining.

The VOUT_MAX and VOUT_MIN commands define the maximum and minimum allowed voltage, through any

combination of offsets and voltage target commands. If commanded higher or lower than these limits, the output

voltage transitions to these limits and stops.

The soft-start and soft-off slew rates are calculated using the current output voltage target and TON_RISE and

TOFF_FALL command values. All output voltage transitions which occur during normal power conversion follow

the slew rate defined by VOUT_TRANSITION_RATE.

The VOUT_SCALE_LOOP parameter must be set properly when an external output voltage divider is being

used. This value is used internally to provide scaling for all output voltage related parameters.

Update the VOUT_TRIM value to apply a static offset to the output voltage target. This may be used to fine-tune

the output voltage in production, or null any board related offsets.

OPERATION[5:2]

VOUT_MAX

VOUT_MIN

VOUT_SCALE_LOOP

VOUT_COMMAND

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

MUX

V_TARGET

+

DAC

Code

Slew Rate

+

VOUT_TRIM

DAC

V_DAC

ꢀ

×

Control

Limiter

+

OFS_DACUP

OFS_DACDWN

OFS_WAKE

Dynamic

Offset

Control

DCLL

Dynamic

Load line

control

ACLL

DAC moving up,

down, softstart

VOUT_TRANSITION_RATE

Slew rate

(TON_RISE / VOUT_COMMAND)

(TOFF_FALL / VOUT_COMMAND)

MUX

DCLL_DACUP, DCLL_DACDWN,

ACLL_DACDWN, ACLL_DACUP

Soft-start, soft-stop, normal operation

Figure 7-12. Output voltage control conceptual view

TPS536C7B1 provides several options to fine-tune the controller response to high speed output voltage

transitions. For example, large output voltage steps upward cause an inrush current, required to charge the

output capacitors for that channel. This inrush current combined with the DC load line setting make the output

voltage appear to move more slowly than the commanded slew rate. Use the DVID_CONFIG command to

configure dynamic loadlines and offsets which apply only during output voltage transitions. Typically, set the DC

and AC load lines for upward moving transitions to a value equal or lower than the nominal. Similarly, typically,

set the DC and AC loadlines to a value larger than the nominal value for downward moving transitions. Refer to

the Technical Reference Manual for a register map of this command.

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DACUP_DLY

DACDWN_DLY

OFS_DACDWN

OFS_DACUP

V_DAC

DACUP_DCLL

DACUP_ACLL

DACDWN_DCLL

DACDWN_ACLL

OFS_DACDWN removed at

1/16 × VOUT_TRANSITION_RATE

V_TARGET

Figure 7-13. Dynamic load line and offset control

The DVID_CONFIG command also allows the user to configure dynamic offsets which are only applied during

output voltage transitions. The configured recovery delays determine when the load line and offset values return

to nominal settings, in terms of PWM (order 0) cycle counts. Figure 7-13 illustrates the dynamic load line, offset

and recovery delay behavior of the controller.

7.5.2 Output voltage margining

Output voltage margin testing allows power designers to test the response of their system to across output

voltage tolerance corners.

The MARGIN bits in the OPERATION command can be used to toggle the active channel between several

states:

Table 7-5. Supported MARGIN settings

MARGIN

bits

Description

Output voltage target

Voltage fault detection

0000b

0101b

0110b

1001b

1010b

Other

Margin none

VOUT_COMMAND

VOUT_MARGIN_LOW

VOUT_MARGIN_HIGH

Enabled

Disabled

Enabled

Disabled

Margin low (act on faults)

Margin low (ignore on faults)

Margin high (act on faults)

Margin high (ignore on faults)

Not supported/invalid data

Example procedure: voltage margin (ignore fault) testing

1. Write to the PAGE command to select the desired channel (E.g. 00h for channel A).

2. Write VOUT_COMMAND to the desired value during margin none operation.

3. Write VOUT_MARGIN_LOW to the desired value during margin low operation.

4. Write VOUT_MARGIN_HIGH to the desired value during margin high operation.

5. Write the ON_OFF_CONFIG command to ensure the device is configured to respect the OPERATION

command.

6. Toggle to margin none operation. Write OPERATION to 80h.

7. Toggle to margin low (ignore fault) operation. Write OPERATION to 94h.

8. Toggle to margin high (ignore fault) operation. Write OPERATION to A4h.

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7.5.3 Power supply telemetry and calibration

Table 7-6 summarizes the available telemetry functions through PMBus.

Table 7-6. Summary of telemetry functions

Shared/

Update Rate

and filter

time

Parameter

Output voltage

Output current

Sensed Signal(s)

Paged/

Phased

PMBus Command(s)

Range

constant

0 to 3.74 V

(VOUT_SCALE_LOOP=1.0)

0 to 5.5 V

24 µs update

+

330 µs time

const.

VSP-VSN

Paged

READ_VOUT

(VOUT_SCALE_LOOP=0.5)

24 µs update

+

290 µs time

const.

READ_IOUT (PHASE=FFh)

IOUT_CAL_GAIN

(-10.0 to 70.0 A) × N_ϕ+

Offset

CSP1 to CSP12

IOUT_CAL_OFFSET

20 µs update

+

300 µs time

const.

READ_IOUT

(PHASE=00h, 01h, ...)

IOUT_CAL_OFFSET

Paged,

Phased

Per-phase current

Output power

CSP1 to CSP12

Calculated

-10.0 to 70.0 A per phase

Paged

READ_POUT

Per READ_VOUT and READ_IOUT

(V_OUT× I_OUT

)

150 µs

update

+

650 µs time

const.

Power stage

temperature

ATSEN, BTSEN

READ_TEMPERATURE_1

-40 to 165 °C

150 µs

update

+

Input voltage

VIN_CSNIN

Shared

READ_VIN

0.0 to 18.7 V

660 µs time

const.

24 µs update

+

440 µs time

const.

READ_IIN

MFR_CALIBRATION_

CONFIG

Input current

Input power

CSPIN, VIN_CSNIN

Shared

-5.0 to 100.0 A

Calculated

(V_IN× I_IN)

READ_PIN

Per READ_VIN and READ_IIN

No sensor gain or offset calibration is required for output voltage, temperature or input voltage telemetry.

7.5.3.1 Output current calibration

Use the IOUT_CAL_GAIN to adjust the gain of the output current telemetry. One gain setting is provided which

applies to all phases in the channel. Use the IOUT_CAL_OFFSET to adjust the current measurement offset

for each phase. The offset for the total channel is calculated as a sum of the configured offsets for all phases.

During power supply characterization use the PHASE_CONFIG command to configure the controller for 1-phase

mode, to enable measurement of a single phase measurement offset. Refer to the example below.

The READ_IOUT command value is calculated according to Equation 4 and Equation 5.

1

active

READ_IOUT

=

× ∑

CSP − VREF + ∑

IOUT_CAL_OFFSET

i

(4)

TOTAL

i

IOUT_CAL_GAIN

phases

where

•

READ_IOUT_TOTALis the total output current telemetry value, accessible with PHASE=FFh

IOUT_CAL_GAIN is the output current gain setting (one per channel)

CSP_iis the voltage of the current sense signal from each power stage

VREF is the digitized value of the internal 1.5-V LDO

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•

IOUT_CAL_OFFSET_iis the output current offset setting for each phase

1

READ_IOUT

=

× CSP − VREF + IOUT_CAL_OFFSET

i

(5)

PHASE i

i

IOUT_CAL_GAIN

where

•

READ_IOUT_{PHASE i}is the per-phase current telemetry value, accessible with PHASE=00h for phase 1, 01h

for phase 2, etc ...

•

IOUT_CAL_GAIN is the output current gain setting (one per channel)

CSP_iis the voltage of the current sense signal for that phase

VREF is the digitized value of the internal 1.5-V LDO

IOUT_CAL_OFFSET_iis the output current offset setting for that phase

Example procedure: Per-Phase calibration of READ_IOUT

First select the correct IOUT_CAL_GAIN for the whole channel:

1. With all phases active, apply the first load current, I_OUT1, to the converter and wait for the READ_IOUT value

to stabilize. Read-back and record the value of READ_IOUT as I_MON1

.

2. With all phases active, apply the second load current, I_OUT2, to the converter and wait for the READ_IOUT

value to stabilize. Read-back and record the value of READ_IOUT as I_MON2

3. Calculate the new gain setting according to Equation 6.

4. Write the PAGE to the current channel, and the PHASE to FFh.

5. Write the newly calculated value to IOUT_CAL_GAIN.

6. Perform an NVM Store operation and power cycle.

.

I

− I

OUT2

OUT1

IOUT_CAL_GAIN

=

× IOUT_CAL_GAIN

current

(6)

new

I

MON2

MON1

Next, select the IOUT_CAL_OFFSET for each phase according to the procedure below:

1. Record the current values of PHASE_CONFIG and IOUT_CAL_OFFSET for each phase.

2. Adjust the TON_RISE temporarily to accomodate enabling power conversion with one phase only active, if

needed.

3. With power conversion disabled for both channels, update the PHASE_CONFIG command so that only the

first phase is active, and its assigned ORDER is 0.

4. Enable power conversion through the VR_EN pins or OPERATION as configured through

ON_OFF_CONFIG.

5. Apply a known load current, I_OUT1. Wait for the READ_IOUT to stabilize and record the value as I_MON1

6. Calculate the new IOUT_CAL_OFFSET per Equation 7, where i is the currently configured phase.

7. Store the newly calculated offset for the first phase value in memory temporarily.

8. Repeat steps 3-7 for each phase in the converter.

.

9. Disable power conversion.

10. Set the PHASE_CONFIG back to the original value.

11. Write the PAGE to the current channel, and the PHASE to 00h for the first phase.

12. Write the newly calculated IOUT_CAL_OFFSET value.

13. Repeat steps 11-12 for each phase. PHASE value 01h refers to the 2nd phase, 02h refers to the 3rd phase

and so on.

14. Re-set the TON_RISE to the desired value during normal operation, if needed.

15. Perform an NVM Store operation and power cycle.

IOUT_CAL_OFFSET

= I

− I

+ IOUT_CAL_OFFSET

(7)

new

OUT i

MON i current

7.5.3.2 Input current calibration (measured)

Use MFR_CALIBRATION_CONFIG command to adjust the gain and offset of the input current sensor. First, set

analog front-end gain such to keep the signal at the ADC to be less than 800 mV. Then set the digital gain to

fine-tune the total gain based on the selected input current shunt. Finally adjust the input current offset based

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on lab measurements. A detailed example of input current sensor calibration is shown in Input current sensing:

VIN_CSNIN and CSPIN.

The equation for input current sense measurements is shown in Equation 8.

G

IINMAX

READ_IIN = I × R

× G ×

INSHUNT

+ IIN_OFS

(8)

IN

SENSE

800 mV

where

•

I_INis the true input current in amperes

R_SENSEis the effective sense element gain in ohms

G_INSHUNTis the analog front-end gain

G_IINMAXis a digital-domain gain factor used for fine tuning

IIN_OFS is an offset factor applied to the resulting value in amperes

Estimate the maximum input current for the design using Equation 9.

V

× I

OUT(A) PEAK(A)

V

× I

OUT(B) IPEAK(B)

I

=

+

× K

MARGIN

(9)

IN(MAX)

V

× η

V

× η

IN

IPEAK(A)

IN IPEAK(B)

where

•

V_OUT(A)and V_OUT(B)are the output voltage for channels A and B respectively

I_PEAK(A)and I_PEAK(B)are the peak design currents for channels A and B respectively

V_INis the input voltage for the design

ɳ_IPEAK(A)and ɳ_IPEAK(B)are the full-load conversion efficiency for channels A and B respectively

K_MARGINis a factor of safety used for design margin

Select the analog front-end gain, G_IINSHUNT, to maximize the signal level at the ADC whie remaining within its full

scale range of 800 mV. Select the closest available value less than the result of Equation 10.

800 mV

G

≤

I

(10)

IINSHUNT

× R

IN(MAX)

SENSE

Finally select the digital gain factor, G_IINMAX, with a resolution of 0.5 per LSB, to fine-tune the current sense gain

using Equation 11.

800 mV

G

=

G

(11)

IINMAX

× R

IINSHUNT

SENSE

Example: 12V to 0.88 V 12+0 design at 400 A / 25 A, R_SENSE= 0.3 mΩ

Channel B is not used in this design. Estimate the maximum input current, according to the calculation below.

1.8V × 400A

12V × 95%

1.0V × 25A

× 1.25 = 82A

12V × 90%

I

=

+

IN(MAX)

Select the analog front-end gain, and digital gain factors as shown below. Set the IIN_OFS should to 0.0 A, and

tune the value based on design characterization measurements.

800mV

82A × 0.2mΩ

G

≤

G

= 40

IINSHUNT

800mV

40 × 0.2mΩ

=

≈ 100

IINMAX

Finally, the calibrated input current measurement is verified to be calibrated properly.

100

800mV

READ_IIN = I × 0.2mΩ × 40 ×

IN

≈ 1.0 × I

IN

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7.5.3.3 Input current calibration (calculated)

Applications which do not use measured current sensing can still report calculated input current based on the

output voltage, output current and input voltage of each channel. To use calculated input current reporting,

connect the VIN_CSNIN and CSPIN pins together, and to the input voltage. A connection to the input voltage

is still required for the control loop to set the correct on-time. Use the CALCIIN_RD setting in MISC_OPTIONS

to enable calculated input current reporting. The controller estimates the converter power efficiency for each

channel by comparing the actual on-time of the PWM pins, which get wider as the conversion loss increases

to maintain voltage and frequency regulation, to the idealized on-time assuming no power loss. Fine-tune the

gain of the calculated input current measurement through PMBus, using the MFR_CALIBRATION_CONFIG

command.

V

× I

OUT(A) OUT(A)

V

× I

OUT(B) OUT(B)

I

=

+

(16)

IN(CALC)

V

× η × CALCIIN_EFF_A V

× η × CALCIIN_EFF_B

IN

est(A)

IN

est(B)

where

•

V_OUT(A)is the output voltage telemetry value for channel A

IOUT_(A)is the output current telemetry value for channel A

V_INis the input current telemetry value (shared)

η_est(A)is the controller's estimated conversion efficiency on channel A

CALCIIN_EFF_A is the PMBus programmable gain factor to fine-tune the current gain for channel A

V_OUT(B)is the output voltage telemetry value for channel B

IOUT_(B)is the output current telemetry value for channel B

η_est(B)is the controller's estimated conversion efficiency on channel B

CALCIIN_EFF_B is the PMBus programmable gain factor to fine-tune the current gain for channel B

7.5.4 Flexible phase assignment

Use the PHASE_CONFIG command to assign each PWM pin to a logical phase number. By default, phase

configuration settings are derived from pinstrapping and not from non-volatile memory. Refer to Section 7.4.4, for

more information about enabling NVM phase configuration settings. Refer to the Technical Reference Manual for

a register map of the PHASE_CONFIG command. Each PWM pin has 4 available settings:

•

ENABLE: Controls whether the phase is active or remains at tristate always.

PAGE: Assigns each phase to channel A or channel B. This setting also determines which CSP pins are

incorporated in the I_SUMcontrol signals for each channel.

•

PHASE: Assigns each phase within a channel a PHASE setting at which it can be addressed. The PHASE

assignment is not backed by non-volatile memory, and each phase is assigned a derived PHASE setting at

power-on.

ORDER: Controls the order in which phases are fired with respect to each other. Figure 7-14 and Figure

7-15 illustrate the effect of different ordering assignments. Reconfigure the phase ordering to ensure adjacent

phases do not interfere with each other due to layout related coupling issues. If dynamic phase shedding is

used, phases add or drop according to their assigned ORDER value.

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CLK_ON

PWM1

ORDER=0

0

PWM1

ORDER=0

0

1

2

PWM2

ORDER=1

PWM2

ORDER=2

2

4

PWM3

ORDER=2

PWM3

ORDER=4

3

PWM4

ORDER=3

PWM4

ORDER=1

1

4

3

PWM5

ORDER=4

PWM5

ORDER=3

5

PWM6

ORDER=5

PWM6

ORDER=5

Figure 7-14. 0-1-2-3-4-5 fire order (6 phase

example)

Figure 7-15. 0-2-4-1-3-5 fire order (6 phase

example)

Observe the following rules when updating the phase configuration settings. The Fusion Digital Power Designer

GUI enforces these rules, but the controller itself does not:

•

Channel A may be assigned up to 12 phases. Channel B may be assigned up to 6 phases.

The ORDER assignments within a channel must be continuous, and start at 0. Do not skip phase order

assignments.

•

The PHASE assignments within a channel must be continuous, start at 0 counting upward from APWM1 for

channel A and downward from APWM12/BPWM1 for channel B.

Example: 8+2 phase configuration with non-standard fire order

1. Write the PIN_DETECT_OVERRIDE command to ensure the controller takes its phase configuration from

non-volatile memory at the next power-up.

2. Write the PHASE_CONFIG command as shown below.

3. Issue STORE_USER_ALL. At the next power-on, the phase configuration is restored from NVM.

Table 7-7. Example settings: 8+2, 0-2-4-6-1-3-5-7 ordering

Pin Name

APWM12/BPWM1

APWM11/BPWM2

APWM10/BPWM3

APWM9/BPWM4

APWM8/BPWM5

APWM7/BPWM6

APWM6

Bit Numbers

191:176

175:160

159:144

143:128

127:112

111:96

95:80

Phase Enable

PAGE

PHASE

ORDER

1

0

1

X

0

1

X

7

6

5

4

3

2

1

0

1

X

7

5

3

1

6

4

2

0

APWM5

79:64

APWM4

63:48

APWM3

47:32

APWM2

31:16

APWM1

15:0

7.5.5 Thermal balance management (TBM)

In any practical multiphase printed circuit board design, some power stages are physically located near to, or

between other phases. Power stages physically located between two other power stages experience mutual

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heating as a result of power dissipation from adjacent power stages. Hence, even though the controller device

regulates the DC current sharing of each phase, the temperature of each power stage may be different.

Optionally, adjust the per-phase current sharing ratio K_Tfor each phase using the ISHARE_CONFIG command.

This open-loop adjustment allows the designer to balance the temperature of each phase to compensate for

mutual heating and non-uniform ground copper for heat spreading. The per-phase current limit of each phase is

not affected by this setting. Refer to the Technical Reference Manual for a register map of ISHARE_CONFIG.

Thermal balancing is accomplished by scaling the gain of each phase current, as provided to the current sharing

amplifier, in the on-time generator circuit for each phase. Refer to Figure 7-23 for more information. Each phase

has an independently programmable gain K_T. Current share gain is assigned according to the logical phase

number (PHASE setting) for each phase. The current carried by each phase when thermal balancing is active,

can be calculated according to Equation 13.

First, calculate the effective thermal phase number, N_Tas shown in Equation 13. This value changes with

different numbers of operational phases, when phase shedding is enabled.

1

N =

+

+ … +

K

(17)

T

K

T1

T2

Tn

where

•

N_Tis the effective thermal phase number.

K_T1, K_T2, K_Tnare the individual thermal balance gains for phase 1, phase 2, ... phase n.

Then each phase carries a proportion of the total current, I_SUM, as shown in Equation 14.

I

SUM

I

=

N

(18)

PHASE i

× K

T

Ti

where

•

I_iis the phase current for the i-th phase in amperes

I_SUMis the total current carried by all phases in amperes

K_Tiis thermal balance gain assigned to the i-th phase

N_Tis the effective thermal phase number, calculated above

Then, the current sharing ratio, comparing one phase to another is given by Equation 15.

K

I

Tj

Ti

PHASE i

PHASE j

=

(19)

where

•

I_iand I_jare the phase current of the i-th and j-th phases in amperes

K_Tiand K_Tjare the thermal balance gains of the i-th and j-th phases

Example: Balancing phase temperature for 7-phase converter

Consider a 7-phase converter with the following thermal balance gains assigned:

Thermal Balance

Gain K_i

Thermal Balance

PHASE

VALUE

PHASE

VALUE

Gain K_i

Phase 1

Phase 2

Phase 3

Phase 4

K₁

K₂

K₃

K₄

0.8

0.9

1.0

Phase 5

Phase 6

Phase 7

K₅

1.0

0.9

0.8

K₆

K₇

Calculate N_Taccording to Equation 16.

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1

0.8

1

0.9

1

1.0

1

1.0

1

1.0

1

0.9

1

0.8

N =

+

≈ 7.722

(20)

T

Phases 1 and 7 have the same thermal balance gain, and carry the same proportion of the total current. Phases

2 and 6 have the same thermal balance gain and carry the same proportion of total current. Similarly, phases

3, 4, and 5 carry the same proportion of total current. Equation 17, Equation 18, and Equation 19 show the

expected phase currents as a fraction of the total current I_SUM

.

I

SUM

7.722 × 0.8

SUM

× K

I = I =

=

≈ I

× 0.162

× 0.144

(21)

(22)

(23)

1

7

SUM

N

T

1

I

SUM

I = I =

≈ I

2

6

N

× K

7.722 × 0.9

T

2

I

SUM

× K

SUM

I = I = I =

=

≈ I × 0.129

SUM

3

4

5

N

7.772 × 1.0

T

3

The ratios of two phase currents can be easily calculated as shown in Equation 20 and Equation 21.

I

K

2

1

T1

T2

0.9

0.8

=

≈ 1.125

≈ 0.9

(24)

(25)

I

K

4

6

T6

T4

0.9

1.0

7.5.6 Dynamic phase adding/shedding (DPA/DPS)

The dynamic phase shedding (DPS) feature allows the controller to dynamically select the number of operational

phases for each channel, based on the total output current. This increases the total converter efficiency by

reducing unnecessary switching losses when the output current is low enough to be supported by a fewer

number of phases, than are available in hardware. Use the PHASE_SHED_CONFIG command to configure

the phase adding/shedding thresholds. Refer to the Technical Reference Manual for a full listing of available

thresholds.

Set the DPS_EN bit to 0b to disable phase shedding operation. The MIN_PH setting determines the minimum

number of phases which are active during light-load operation.

Phase adding is detected based on the summed peak current of all phases in the analog domain. Phase

shedding is detected based on average current telemetry, with a forced delay of 120 μs. The phase add

thresholds are not affected by current measurement calibration, but the phase shed thresholds are.

Each phase has 3 settings available:

•

Phase add threshold (PH_ADDx) selects the nominal phase adding threshold. Set this value approximately

equal to the peak efficiency point per phase to optimize overall converter efficiency.

Phase add hysteresis (DPA_HYSTx) selects the phase add threshold hsyteresis. Nominally set this value to

one-half the value of the ripple current on the I_SUMcurrent for that number of phases.

Phase drop hysteresis (DPS_HYST) selects the phase drop hysteresis (per-phase average current). There

is one setting per channel.

The phase add/drop thresholds can be calculated according to the equations below. First determine the ripple

cancellation effect for each combination of phase numbers, for the chosen duty cycle using Equation 22. This

value affects the true add thresholds.

m

m + 1

N × D −

×

− D

i

ΔI

RIPPLE(ISUM)

N

i

K =

≈

(26)

i

ΔI

D × 1 − D

RIPPLE(PHASE)

where

•

K_iis the ripple cancellation ratio before the phase transition

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•

ΔI_ripple(ISUM)is the ripple in the summed current after cancellation

ΔI_{ripple(IPHASE)}is the ripple each individual phase

N_iis the number of phases currently active

D is the converter duty cycle, nominally Vout / Vin

m is the maximum integer which does not exceed N_i× D (can be zero)

Calculate the DC phase adding thresholds based on the chosen configuration using Equation 23. Phases are

added based on peak I_SUMcurrent, after being passed through a 1 μs filter. Typically, choose the DPA_HYST

settings to cancel out the current ripple term. Then the DC current adding threshold is equal to the PH_ADDx

value selected.

ΔI

RIPPLE(PHASE)

I

≈ PH_ADD

+ DPA_HYST

− K ×

(27)

DPA(i to i+1)

i+1

i+1 i

2

where

•

I_{DPA(i to i+1)}is the DC current at which the controller transitions from i to i+1 phases

PH_ADD_iis the selected phase add threshold for phase number i

DPA_HYST_iis the selected phase add hysteresis for phase number i

ΔI_{RIPPLE(PHASE)}is the ripple each individual phase

Calculate the DC phase drop thresholds based on the chosen configuration using Equation 24 phases are

added based on the output current telemetry value, with a deglitch filter of 120 μs.

I

≈ PH_ADD

− i × DPS_HYST

(28)

DPS(i+1 to i)

i+1

where

•

I_{DPS(i+1 to i)}is the DC current at which the controller transitions from i+1 to i phases

PH_ADD_i+1is the selected phase add threshold for phase number i+1

N_iis the number of phases currently active before the phase shed event

DPA_HYST_iis the selected phase shed hysteresis

Phase add/shed example: 600-kHz, 8-phase, 12-V to 0.8-V converter, with 120 nH inductor

Assume V_IN= 12 V, V_OUT= 0.88, f_SW= 600 kHz, L = 120 nH.

The example below explains how to calculate the phase adding and shedding thresholds for 2 to 3 phases. First

calculate the inductor ripple current in one phase. Set the DPA_HYST3 setting to approximately 1/2 the inductor

current ripple in one phase. Assuming the phase adding threshold for phase 3, PH_ADD3, parameter is set to

40.0 A, and the phase shed hysteresis, DPS_HYST is set to 2.0 A, the phase adding and shedding thresholds

are calculated as shown below.

V

× V

− V

IN

0.88V × 12V − 0.88V

OUT

V

OUT

× L × f

I

=

= 11.3A

12V × 120nH × 600kHz

RIPPLE(PHASE)

IN

SW

0.88V

12V

m = FLOOR 2 ×

= 0

m

m + 1

0.88V

12V

0

0 + 1

12phases

0.88V

12V

0.88V

12V

N × D −

×

− D

2phases ×

−

×

−

i

N

12phases

i

K ≈

≈

≈ 0.92

2

0.88V

12V

D × 1 − D

× 1 −

ΔI

RIPPLE(PHASE)

2

11.3A

2

I

≈ PH_ADD + DPA_HYST − K ×

≈ 40A + 6A − 0.92 ×

= 40.8A

DPA(2 to 3)

3

i

≈ PH_ADD − 2 × DPS_HYST = 40A − 2 × 2A = 36A

DPS(3 to 2)

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7.5.7 Turbo Mode

The turbo mode feature enables multiphase systems to boost their efficiency by separating phases which carry

the thermal steady state current of the load (normal phases) from those which only need to turn on to support

fast load transient events (turbo phases).

•

Normal phases carry the steady state current, and are operational all or most of the time. Normal phases

can use larger inductance values to enable converter operation at lower switching frequency, as well as

reduce inductor core loss.

•

Turbo phases carry the AC load transient current and are not intended to remain operational always.

Uselower inductance values for turbo phases to enable them to ramp up their phase current quickly as

they turn on during transient events. Assign a higher current sharing ratio to turbo phases using the

ISHARE_CONFIG command. Turbo phases are activated whenever USR2 is triggered, or whenever the

converter output current exceeds their respective phase adding threshold. Turbo phases are always added

last, and multiple turbo phases are added at the same time, regardless of their ordering assignment.

Turbo mode is only applicable to systems which use dynamic phase shedding. This feature is optional, and only

recommended in cases where the system provides enough margin for the turbo phase power stages to operate

within their safe operating area. The per-phase current report is not correct in turbo mode.

Use the PHASE_CONFIG command to assign phases as being either normal phases or turbo phases.

Example: 7 phases with 2 turbo phases

•

Use the PHASE_CONFIG command to assign phase order 3 and 6 as turbo phases. Assign turbo phases

out-of-phase with each other to avoid increasing the converter output ripple by a large amount due to loss of

interleaving benefits.

Use the ISHARE_CONFIG command to assign the "turbo gain" ratio as 2.0. This means the turbo phases will

carry 2.0x the current of normal phases when turned on. Ensure that the turbo phase power stages are still

operated within their safe operating area at worst case.

Nominally, assign the turbo phases an inductance value proportionally lower compared to normal phases.

In this case, normal phases use 150 nH inductance, and turbo phases use 75 nH. Without turbo phase, all

normal phases would require 120nH.

Use the PHASE_CONFIG command to set the dynamic phase adding thresholds for 5-6 phases and 6-7

phases high enough that they do not add during steady state current operation.

Use the FREQUENCY_SWITCH command to reduce the switching frequency, to reduce switching loss.

As shown in Figure 7-16 and Figure 7-17, the design still meets the transient requirement. The efficiency

improvement is approximately 0.3-0.5%.

•

Figure 7-16. Load step with Turbo Mode

Figure 7-17. Load removal with Turbo Mode

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7.6 Control Loop Theory of Operation

7.6.1 Adaptive voltage positioning and DC load line (droop)

TPS536C7B1 supports adaptive voltage positioning (AVP) through the VOUT_DROOP PMBus command. This

feature is also referred to as the DC load line (DCLL) for the control loop. Use a non-zero DC load line to reduce

output voltage set-point as a function of the load current, with a controlled slope. This feature is optional. Set the

DC load line to 0.0 mΩ in applications which do not use a load line.

The DC load line provides two main benefits:

•

Reducing the output voltage set-point, reduces the power consumption of the system, when the load current

is high.

•

Adaptive voltage positioning increases the allowable undershoot and overshoot during load transient events.

Figure 7-18 and Figure 7-19 compare example output voltage specifications for systems with zero load line

and non-zero load line. The nominal setting for the output voltage is chosen to be higher, to allow the entire

transient window as margin for transient overshoot and undershoot.

I_LOAD

V_MAX(AC)

V_MARG(OVER)

û V_OVER(SPEC)

û V_DROOP= VOUT_DROOP × I_LOAD

û V_UNDER(SPEC)

V_MARG(UNDER)

V_MIN(AC)

Figure 7-18. Load transient specification (zero load Figure 7-19. Load transient specification (non-zero

line) load line)

7.6.2 DCAP+ conceptual overview

Figure 7-20 below describes the theory of operation for multiphase DCAP+ control, in continuous conduction

mode (CCM).

The summed inductor currents, I_SUM, and output voltage deviation information, along with appropriate gain

and integration, are processed to form a control signal V_COMP. Neglecting the output voltage information and

integration, the V_COMPsignal is a scaled version of I_SUM. A compensating ramp signal, V_RAMP, has a slope

proportional to the number of phases, and switching frequency setting. When the V_RAMPand V_COMPsignals

intersect, the controller fires a new pulse.

Phase management logic distributes new pulses to the next phase in the firing order sequence. Each phase is

assigned a firing order, at which pulses are passed to that phase. A separate, slower loop adjusts the on-times

for each phase based on the output voltage setpoint, switching frequency setting, and current balance error.

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V_CORE

V_COMP

(includes I_SUM

V_RAMP

)

V_COMP

(includes I_SUM

V_RAMP

I_SUM

)

CLK_ON

PWM1

I_SUM

ZC

PWM2

CLK_ON

PWM1

PWM3

PWM4

Time

Figure 7-21. DCAP+ conceptual diagram (DCM)

Figure 7-20. DCAP+ conceptual diagram (FCCM)

7.6.3 Off-time control: loop compensation and transient tuning

Figure 7-22 shows a conceptual block diagram of the DCAP+ off-time control loop. Transient response tuning is

accomplished by changing the parameters which generate the V_COMPsignal. These parameters are accessible

using the COMPENSATION_CONFIG command. Refer to the Technical Reference Manual for a register map of

this command.

The V_COMPsignal is generated by the sum of three signal paths. Finally the V_COMPsignal is scaled by the AC

gain parameter, K_AC

.

•

Proportional path: An error amplifier subtracts the sensed output voltage from the output voltage target, set

by V_DAC. The gain of the proportional path is set by the AC load line (ACLL). Reducing the value of the AC

load line increases the proportional path gain, which gives faster transient response. Setting the AC load line

to a very low value can lead to low phase margin. The minimum recommended ACLL value is 0.125 m ohm.

Integral path: The difference between the sensed output voltage and the output voltage target, V_DAC, is

compared to the ideal droop (I_SUM× DCLL) value to create an error voltage, V_ERR. An integrator adjusts

the setpoint of V_COMP, to drive the output voltage error to zero. Integration provides high DC gain, giving

the power supply excellent output regulation and DC load line performance. The programmable integration

time constant, τ_INTchanges the settling time of of the output voltage folliowing a transient. Increasing the

integration time constant improves phase margin. The programmable integration path gain, K_INT, sets the

gain of the integral path.

•

Current feedback: The summed phase current, I_SUM, with a nominal gain of 5 mV/A, is used directly to

generate V_COMP, as well as in the integral path to set the DC load line. The gain of this path is not affected by

the IOUT_CAL_GAIN or IOUT_CAL_OFFSET calibration commands.

V_RAMP

Loop

Comparator

Proportional Path

Error Amplifier

+

1/ACLL

CLK_ON

+

V_ERR

Integral Path

K_INT

+

V_DAC

V_VSP- V_VSN

V_DROOP

+

K_DIV

-K_AC

N

ꢀ

DCLL

ꢀ

Þ

V_COMP

œ

t_INT

Current Feedback

5mΩ

I_SUM

Figure 7-22. Loop compensation conceptual block diagram

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7.6.4 On-time control: adaptive t_onand autobalance current sharing

The nominal on-time for each phase is determined by an adaptive one-shot circuit, which generates on-times

according to Equation 25. PWM on-times are adjusted very slowly compared to off-times, so the DCAP+

modulator behaves similar to a constant-on-time architecture.

Use the FREQUENCY_SWITCH command to set the nominal per-phase switching frequency.

V

+ K × I − I

ISHARE L AVG

× FREQUENCY_SWITCH

DAC

t

=

+ ΔPLL_CLF

(34)

ON

V

IN

where

•

t_ONis the on-time for the phase in seconds

V_DACis the output voltage set-point in volts

FREQUENCY_SWITCH is the commanded switching frequency in Hz

V_INis the sensed input voltage from the VIN_CSNIN pin

K_ISHAREis the gain of the current share loop

I_Lis the current carried by the phase

I_AVGis the average phase current for all phases

ΔPLL_CLF is the on-time adjustment from the closed loop frequency correction circuit

Current sharing is implemented by adapting the on-time for each phase, according to the difference between its

own phase current I_L, and the average of all phase currents I_AVG. When the phase current for any one phase

is greater than the average of all phase currents, the on-time of that phase is reduced accordingly. Similarly, if

the phase current of any one phase is less than the average of all phase currents, the on-time of that phase is

increased.

The on-time is also proportional to the sensed input voltage, which provides the controller with inherent input

voltage feed-forward.

Furthermore, a frequency control loop adjusts the on-times for each phase to drive the actual switching

frequency equal to the FREQUENCY_SWITCH setting. An internal clock counts the number of observed pulses

over a set interval, and compares the result to the calculated ideal number. If too many pulses are fired in the

sampling period, the switching frequency is too high, and the on-times are increased to reduce the steady-state

switching frequency. If too few pulses are fired during the sampling period, the switching frequency is too low

and the on-times are reduced to increase the steady-state frequency. The PWM pin assigned to ORDER=0 is

used for counting purposes, as it does not drop due to phase shedding.

g_m

FREQUENCY_SWITCH

+

VIN

CLK_ON

œ

discharge

Tristate

PWM

Logic

t_ON1

PWM1

+

VOUT_SCALE_LOOP

V_DAC

K_T1

×

+

I_L1

+

1 µs

Filter

+

ꢀ

œ

I_AVG

+

PWM

Frequency

Control

REFCLK

(one per channel)

Figure 7-23. On-time generation and auto-balance current sharing

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7.6.5 Load transient response

TPS536C7B1 achieves fast load transient performance using the inherently variable switching frequency

characteristics of DCAP+ control. Figure 7-24 illustrates the load insertion behavior, in which PWM pulses are

generated with faster frequency than the steady-state frequency, to provide more energy to the output voltage,

improving undershoot performance. Figure 7-25 illustrates the load release behavior, in which PWM pulses can

be delayed to avoid charging extra energy to the load until the output voltage reaches the peak overshoot.

When there is a sudden load increase, the output voltage immediately drops. The controller device reacts to this

drop by lowering the voltage on internal V_COMPsignal. This forces PWM pulses to fire more frequently, which

causes the inductor current to rapidly increase. As the converter output current reaches the new load current, the

device reaches a steady-state operating condition and the PWM switching resumes the steady-state frequency.

When there is a sudden load release, the output voltage immediately overshoots. The control loop reacts to this

rise by increasing the voltage of the internal V_COMPsignal. This rise forces the PWM pulses to be delayed until

the converter output current reaches the new load current. At that point, the switching resumes and steady-state

switching continues. In Figure 7-24 and Figure 7-25, the ripples on V_OUT, and V_COMPvoltages are not shown for

simplicity.

I_OUT

I_SUM

V_OUT

V_COMP

V_RAMP

CLK_ON

PWM1

PWM2

PWM3

PWM4

Figure 7-24. Load insertion response (4-phase example, 0-1-2-3 ordering)

I_OUT

I_SUM

V_OUT

V_COMP

V_RAMP

CLK_ON

PWM1

PWM2

PWM3

PWM4

Figure 7-25. Load release response (4-phase Example, 0-1-2-3 ordering)

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7.6.6 Forced minimum on-time, minimum off-time and leading-edge blanking time

Under normal linear operation, the PWM on- and off-times are generated by the control loop. To improve noise

immunity, the controller forces a minimum on-time whenever the PWM pins pulse high. The off-time for any

phase is limited by a forced minimum off-time. Although TI smart power stage devices have built-in protection

from glitches on the PWM pins also, this feature provides redundant protection against cross-conduction issues.

The controller also limits the time between sending pulses to any two adjacent phases. This is referred to as

the leading-edge blanking time, t_BLANK. Increase the leading edge blanking time to prevent over-compensation

(or "ring-back") by the controller during heavy load transient events. The minimum on-time, minimum off-time,

and leading edge blanking time are programmable by the NONLINEAR_CONFIG PMBus command. Refer to the

Technical Reference Manual for a register map of this command.

For multiphase designs, the maximum per-phase switching frequency during transients, is limited by the leading

edge blanking time parameters as shown in Equation 26. The controller also forces a minimum-off-time per

phase. The greater of the two limits the maximum frequency.

1

f

=

N

(35)

PHASE(max)

× t

Φ

BLANK

where

•

N_Φis the number of active phases

t_BLANKis the leading edge blanking time in seconds

7.6.7 Nonlinear: undershoot reduction (USR), overshoot reduction (OSR) and dynamic integration

Nonlinear features improve the controller response to severe repetitive load transient conditions.

When the controller is subjected to load transients at very high frequency, the output voltage may not be able to

completely settle before the next transient event occurs. As a result, particularly during overshoot events, when

the controller is firing pulses infrequently, the controller integration path can see error which does not completely

settle. Accumulation of large overshoot error can cause the controller response to following undershoot events

to be slower. To prevent excess accumulation of error during repetitive load transient events, the controller

implements dynamic integration. When the output voltage overshoots its target by a certain voltage, V_DINT, the

controller integration time constant can be changed to an alternate value, the dynamic integration time constant.

Use the COMPENSATION_CONFIG command to configure the dynamic integration time constant and threshold

voltage. Typically, set the dynamic integration constant to a longer time than the static integration time constant.

I_SUMslew rate limited by inductors

I_OUT

I_SUM

V_OUT

V_DAC

V_DROOP

I_SUM×R_DCLL

V_DROOP

V_USR2

V_USR1

V_ERR

V_DINT

V_OSR

Dynamic

integration

active

USR1 phases added

All phases added

Diode braking,

Pulse truncation

Figure 7-26. Dynamic integration, OSR, USR detection

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Systems which use the dynamic phase shedding feature, may still have sudden and severe load transient events

occur. The undershoot reduction (USR) feature allows the controller to add phases even before the output

current reaches the dynamic phase adding thresholds. This ensures the transient undershoot event is stopped

as quickly as possible. TPS536C7B1 has two levels of USR. The USR1 threshold is used to quickly enable

a configurable number of phases, USR1_PH. The USR2 threshold adds all enabled phases, assigned to that

channel. Use the NONLINEAR_CONFIG command to configure the USR1 and USR2 features.

The overshoot reduction (OSR) feature reduces output voltage overshoot during severe load transient events,

by turning off the low-side FETs of the powerstage devices (e.g. tri-stating the controller PWM pins), when an

overshoot event occurs. The inductor current of each phase must remain continuous, forcing the output current

through the body diode of each low-side FET. This dissipates excess energy more quickly than keeping the

powerstage low-side FET fully conducting, due to the forward voltage drop characteristics of the body diodes. As

a result, the transient overshoot is smaller when this technique is used, compared to simply turning on the low-

side FET of each powerstage. However, this results in excess heat which must be properly managed in systems

with highly repetitive transient conditions. Additionally, TPS536C7B1 can be configured to truncate PWM pulses,

to reduce the worst-case response time to overshoot events. The NONLINEAR_CONFIG command provides

four controls for overshoot reduction: an enable bit for diode braking, an enable bit for pulse truncation, the OSR

threshold, V_OSR, and the diode braking timeout, which limits the maximum amount of time during which diode

braking takes place, to manage excess heating. Refer to the Technical Reference Manual for a register map of

this command.

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7.7 Power supply fault protection

7.7.1 Host notification and status reporting

The supported status bits and registers are detailed in Figure 7-27. All of the fault conditions listed in Section

7.7.3 have associated status bits. Status bits and SMB_ALERT# may be cleared using the CLEAR_FAULTS

command, commanding the offending channel to disable (as specified in ON_OFF_CONFIG), or by power

cycling. Most commonly, issue CLEAR_FAULTS with the PAGE set to FFh, to clear faults for both channels.

(78h) STATUS_BYTE [paged] (and LSB of STATUS_WORD)

(79h) STATUS_WORD [paged]

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LSB

MSB

Bit 15: More info in STATUS_VOUT

Bit 14: More info in STATUS_IOUT

Bit 13: More info in STATUS_INPUT

Bit 12: More info in STATUS_MFR

Bit 11: VR_RDY pin is low

Bit 7: Device was busy and could not respond

Bit 6: Power conversion is disabled for any reason

Bit 5: Vout OV Fault

Bit 4: Iout OC Fault

Bit 3: Vin UV Fault

Bit 9: More info in STATUS_OTHER

Bit 2: More info in STATUS_TEMPERATURE

Bit 1: More info in STATUS_CML

Bit 0: More info in MSB

(7Ah) STATUS_VOUT [paged]

(7Bh) STATUS_IOUT [paged]

(7Ch) STATUS_INPUT [shared]

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Bit 7: Vout OV Fault (Fixed or Tracking). More

info in STATUS_EXTENDED

Bit 6: Vout OV Warn

Bit 7: Iout (Isum) OC Fault

Bit 5: Iout (Isum) OC Warn

Bit 3: Ishare Warn. More info in

STATUS_PHASES

Bit 7: Vin OV Fault

Bit 6: Vin OV Warn

Bit 5: Vin UV Warn

Bit 4: Vin UV Fault

Bit 5: Vout UV Warn

Bit 4: Vout UV Fault (Tracking)

Bit 3: Vout commanded outside

VOUT_MIN/VOUT_MAX window

Bit 2: TON_MAX Fault

Bit 3: Unit off due to low input voltage

Bit 2: Iin OC Fault

Bit 1: Iin OC Warn

Bit 0: Pin OP Warn

(7Fh) STATUS_OTHER [shared]

(7Dh) STATUS_TEMPERATURE [paged]

(7Eh) STATUS_CML [shared]

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Bit 7: Power stage OT Fault

Bit 6: Power stage OT Warn

Bit 0: Device was first to assert SMB_ALERT#

Bit 7: Invalid command

Bit 6: Invalid data

Bit 5: Packet error check failed

Bit 4: Memory failure

Bit 1: Communication error

Bit 0: Other communication error occurred

(DCh) STATUS_PHASES [paged][phased]

15 14 13 12 ...

If PHASE=FFh (address all phases)

(DDh) STATUS_EXTENDED [shared]

(80h) STATUS_MFR_SPECIFIC [paged]

2

1

0

55 54 53 52

...

2

1

0

7

6

5

4

3

2

1

0

Bit 7: Power-on self-check failed

Bit 55: CML Access error

Bit 54: Bad group command

Bit 53: Attempted group read

Bit 52: Unknown CML error

Bit 51: Transaction aborted

Bit 50: Lost arbitration

Bit 49: Block size was NACK

Bit 45: Too few bytes rx‘d

Bit 44: Too many bytes rx‘d

Bit 43: Block size too small

Bit 42: Block size too large

Bit 41: Write to protected cmd

Bit 39: VSP open Ch. B

Bit 38: VSP open Ch. A

Bit 37: VSN open Ch. B

Bit 36: VSN open Ch. A

Bit 28: SYNC/CLF fault

Bit 26: Update not allowed

Bit 25: BOOT pin detect failed

Bit 24: ADDR pin detect failed

Bit 19: Invalid phase config

Bit 18: Invalid config file

Bit 15: TAO low Ch. B

Bit 6: More info in STATUS_EXTENDED

Bit 4: More info in STATUS_PHASES

Bit 3: RESET# Vout occurred

Bit 0: Warn info available about Phase 1

Bit 1: Warn info available about Phase 2

Bit 0: Power stage fault (TAO High)

If PHASE=00h, 01h, … (individual phase)

Bit 7: Ishare (higher than avg) warning

Bit 6: Ishare (lower than avg) warning

Bit 1: Per-phase OCL warning

Bit 14: TAO low Ch. A

Bit 5: Pre-bias OVP Ch. B

Bit 4: Pre-bias OVP Ch. A

Bit 3: Tracking OVP Ch. B

Bit 2: Tracking OVP Ch. A

Bit 1: Fixed OVP Ch. B

Bit 0: Fixed OVP Ch. A

Figure 7-27. Status register support and decoding

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TPS536C7B1 supports a full set of PMBus status registers and the SMB_ALERT# notification protocol. Any

condition which causes a status bit to assert, also causes TPS536C7B1 to assert the SMB_ALERT# signal

(unless that bit is masked via SMBALERT_MASK). Use the alert response address (ARA) protocol to determine

the address of the device experiencing a fault condition in multi-slave systems. The SMB_ALERT# protocol is

optional, and the system designer may choose to implement fault management through other means. Figure

7-28 shows a flow diagram of using the ARA protocol.

SMB_ALERT#

Asserted

Issue ARA

SMBus ReceiveByte

to Address 12d

If fault re-occurs and is

not masked, ARA returns

the same address again.

Otherwise, it returns the

address of next device

with a fault

Return

(Confirm

SMB_ALERT# has

been cleared)

No

Data Received?

Ack/Nack

Yes

Receive address of

highest priority device

with an alert (lowest

numerical address)

Read (79h)

STATUS_WORD

from received

address at all Pages

More

Yes

Information in

other status

registers?

Read other status

registers

No

If applicable, write

(1Bh) SMBALERT_

MASK bits to mask

faults and issue (03h)

CLEAR_FAULTS

Manage and log fault

at system level

Figure 7-28. Flow diagram of SMB_ALERT# response protocol

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7.7.2 Fault type and response definitions

Paged fault conditions apply only to a single channel and are duplicated for channel A and channel B. Paged

fault conditions only cause one channel to shut down when triggered. For latch-off faults, the enable for that

channel must be toggled to re-enable power conversion. For example, if channel B experiences an overvoltage

fault, only channel B stops power conversion, and channel B must be commanded to disable power conversion,

and re-enable power conversion to continue normal operation.

Shared fault conditions apply to channels A and B simultaneously. Shared fault conditions cause both channels

A and B to shut down when triggered.

Warning conditions do not cause any interruption to power conversion. They are meant to inform the system

host of changing conditions so that it can react prior to a fault being triggered. Warnings do conditions set

associated PMBus status bits and trigger the SMB_ALERT# signal when not masked.

Fault conditions set to the ignore response are treated as warnings. Faults set to the ignore response do not

cause any interruption of power conversion but do still cause status bits and SMB_ALERT# to trigger.

Fault conditions set to the latch-off response cause power conversion to stop immediately. The channel must

be commanded to stop power conversion then restart to continue operation. Start-up from a latch-off fault

is identical to a normal power-up and the configured TON_DELAY is still observed. The RSTOSD option in

MISC_OPTIONS controls whether the boot voltage returns to its last programmed value, or boots to its VBOOT

value.

Fault conditions set to the hysteretic response cause power conversion to stop immediately. When the fault

condition no longer exists, the TPS536C7B1 attempts to restart immediately. The configured TON_DELAY is still

observed.

Fault conditions set to the hiccup response cause power condition to stop immediately. After a hiccup wait time,

25 ms by default, TPS536C7B1 attempts to re-enable power conversion. The configured TON_DELAY is still

observed. If the fault condition has disappeared, the start-up attempt succeeds and power conversion continues.

Otherwise, the process repeats indefinitely. The RSTOSD option in MISC_OPTIONS controls whether the boot

voltage returns to its last programmed value, or boots to its VBOOT value.

The TOFF_DELAY is not respected during any fault shutdown response.

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7.7.3 Fault behavior summary

Table 7-8. Fault detection and behavior

Shared /

Fault Name

Paged /

Phased

Condition

Latency

Enabled

Programmable Range

Response

Alerts ⁽¹⁾

Clearing ⁽²⁾

Output Voltage / Current / Power

Until

initialization

after 3.3V OK complete, then

disabled

VSP voltage

exceeded

threshold

Pre-Bias OV

Fault

Max 350 µs

Shared

3.7 V fixed by design

All PWM Low, Latch-Off

VR_FAULT#

3.3 V Power Cycle

3.3 V power cycle

if triggered while

power conversion

is disabled.

VSP voltage

exceeded fixed 1.0 µs

threshold

After

initialization

complete

VR_FAULT# if

not ignore

response

Ignore, Latch-Off, Hiccup

PWM Pulled Low

Fixed OV Fault Paged

0.6 V to 3.7 V

Otherwise,

clearable through

Enable cycle, or

CLEAR_FAULTS

VSP-VSN

voltage

VR_FAULT# if

not ignore

response

Tracking OV

Paged

During power

conversion

Offset from current VID+Droop, Ignore, Latch-Off, Hiccup

Enable cycle, or

CLEAR_FAULTS

exceeded VID 1.0 µs

+ Droop + OV

Offset

Fault

+32 to +448 mV Offset

PWM pulled low

Warning only

VSP-VSN

voltage

exceeded VID 2.0 µs

+ Droop + OV

Offset

Tracking OV

Paged

During power

conversion

Offset from current VID + Droop

+24 to +448 mV Offset

Enable cycle, or

CLEAR_FAULTS

n/a

Warn

VSP-VSN

voltage below

VID + Droop -

UV Offset

Tracking UV

Paged

During power

conversion

Offset from current VID + Droop

-24 to -448 mV Offset

Enable cycle, or

CLEAR_FAULTS

2.0 µs

n/a

Warn

VSP-VSN

Tracking UV

Paged

voltage below

1.0 µs

During power

conversion

Offset from current VID + Droop Ignore, Latch-Off, Hiccup

Enable cycle, or

CLEAR_FAULTS

Fault

VID + Droop-

-32 to -448 mV Offset

PWM Tri-State

UV Offset

VSP-VSN did

not rise to

threshold

quickly enough

during soft-

start

Max Turn-on

time

(TON_MAX)

During soft-

start only

Ignore, Latch-Off, Hiccup

PWM Tri-State

Enable cycle, or

CLEAR_FAULTS

Paged

500 µs

0 ms to 31.75 ms

n/a

Vout

commanded

Vout Min/Max

Warning

above

VOUT_MAX or

below

VOUT_MIN

During power

conversion

VOUT_MAX and

VOUT_MIN

DAC Voltage clamped to limit

Warning only

Enable cycle, or

CLEAR_FAULTS

Paged

N/A

Total current

exceeded

threshold

Over-current

Fault

During power

conversion

Ignore, Latch-Off, Hiccup

PWM Tri-State

VR_FAULT#

configurable

Enable cycle, or

CLEAR_FAULTS

175 µs

0 to 1023 A⁽³⁾

17 to 130 A⁽³⁾

Per-Phase

Over-current

Limit

Phase current

exceeded

threshold

Warning only,

PWM pulses skipped to limit

phase current

Paged,

Phased

During power

conversion

Enable cycle, or

CLEAR_FAULTS

Cycle-by-cycle

n/a

Phase current

above or below

average

current for all

phases by

Current Share Paged,

Warning Phased

During power

conversion

Enable cycle, or

CLEAR_FAULTS

175 µs

5 to 20 A per phase

Warning only

threshold

(1) Any fault response which causes a shutdown event de-asserts VR_RDY. All faults have associated PMBus status bits and

SMB_ALERT# response (unless masked by SMBALERT_MASK commands)

(2) Fault condition must have disappeared, otherwise fault re-triggers immediately

(3) IOUT_OC_FAULT_LIMIT[PAGE=x][PHASE=FFh] sets the per-page OC fault threshold, IOUT_OC_FAULT_LIMIT[PAGE=x]

[PHASE=Other] sets the per-phase OCL threshold

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Table 7-9. Fault detection and behavior (continued)

Shared /

Paged /

Phased

Fault Name

Condition

Latency

Enabled

Programmable Range

Response

Alerts ⁽¹⁾

Clearing ⁽²⁾

Power Stage Feedback

Power Stage

Temperature

exceeded

Over-

Temperature

Fault

After

initialization

complete

Ignore, Latch-Off, Hiccup

PWM Tri-State

VR_FAULT#

configurable

Enable cycle, or

CLEAR_FAULTS

Paged

950 µs

+90 to +160 °C

threshold

Power Stage

Temperature

exceeded

Over-

Temperature

Warning

After

initialization

complete

Enable cycle, or

CLEAR_FAULTS

Paged

950 µs

+90 to +160 °C

TAO > 2.5 V

Warning only

n/a

threshold

TAO pulled

high by power 1.0 µs

stage

After

initialization

complete

VR_FAULT# if

not ignore

response

Power Stage

Fault

Ignore, Latch-Off, Hiccup

PWM Tri-State

Enable cycle, or

CLEAR_FAULTS

Hysteresis

Power Stage

Not Ready

(TAO LOW)

After

initialization

complete

TAO pulled low

1.0 µs

TAO < 230 mV Falling (50mV

hysteresis)

Start-up is blocked if not yet

enabled, or rail is shutdown.

PWM tristated

Enable cycle, or

CLEAR_FAULTS

n/a

by power stage

Input Voltage / Current / Power

VIN_CSNIN

After

initialization

complete

Input Over-

voltage

Ignore, Latch-Off, Hiccup

PWM Tri-State

Enable cycle, or

CLEAR_FAULTS

Shared

950 µs

0 to 19 V

n/a

Voltage Fault

exceeded

threshold

VIN_CSNIN

voltage

exceeded

threshold

Input Over-

Voltage

Warning

After

initialization

complete

Enable cycle, or

CLEAR_FAULTS

0 to 19 V

Warning only

VIN > VIN_ON

first time and

either channel

enabled

Input Under-

Voltage

Warning

VIN_CSNIN

voltage below 950 µs

threshold

Enable cycle, or

CLEAR_FAULTS

4.0 to 11.25 V

4 to 128 A

8 to 2044 W

VIN > VIN_ON

first time and

either channel

enabled

VIN_CSNIN

voltage below 950 µs

threshold

Input Under-

Voltage Fault

Ignore, Latch-Off, Hiccup

PWM Tri-State

Enable cycle, or

CLEAR_FAULTS

CSPIN-

VR_FAULT# if

not ignore

response

Input Over-

VIN_CSNIN

During power

conversion

Ignore, Latch-Off, Hiccup

PWM Tri-State

Enable cycle, or

CLEAR_FAULTS

525 µs

Current Fault

current below

threshold

CSPIN-

Input Over-

Current

Warning

VIN_CSNIN

525 µs

During power

conversion

Enable cycle, or

CLEAR_FAULTS

Warning only

n/a

current below

threshold

Computed

Input Over-

input power

During power

conversion

Enable cycle, or

CLEAR_FAULTS

525 µs

Power Warning

above

threshold

Self-Checking

ADDR pin

open, low,

high, or non-

convergent

detection

Checked

Invalid ADDR

Pinstrap

Checked once

at initialization

Shared

during power- Per detection thresholds

on and enable

Latch-Off, PWM tristate

n/a

3.3 V Power Cycle

BOOT pin

open, low,

high, or non-

convergent

detection

Checked

Invalid BOOT

Pinstrap

Checked once

at initialization

during power- Per detection thresholds

on and enable

PMBus Interface

PMBus

Communicatio Shared

n Error

Per PMBus

communication initialization

frequency complete

After

Communicatio

n Error (See

STATUS_CML)

Enable cycle, or

CLEAR_FAULTS

See PMBus Specification

Warning only

n/a

(1) Any fault response which causes a shutdown event de-asserts VR_RDY. All faults have associated PMBus status bits and

SMB_ALERT# response (unless masked by SMBALERT_MASK commands)

(2) Fault condition must have disappeared, otherwise fault re-triggers immediately

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7.7.4 Detailed fault descriptions

7.7.4.1 Overvoltage fault (OVF) and warning (OVW)

TPS536C7B1 supports several forms of overvoltage protection. Figure 7-29 describes the overvoltage protection

scheme in more detail.

•

Pre-Bias OVF protects the converter while initialization runs. This protection is active t_INIT-PBOV, 350 μs

maximum after the VCC pin voltage is established, until initialization is complete. The threshold is hard-coded

to 3.7 V. In response to this condition, all PWM pins (regardless of channel assignment) pull low, regardless

of the overvoltage response setting. This fault cannot be cleared without a power cycle of the VCC pin.

The fixed overvoltage protection becomes active after t_INIT-LOGIC, up to 20 ms after the VCC pin voltage is

established. This fault detection cannot be disabled.

•

Fixed OVF is a programmable limit based on the VSP pin voltage, above which it is not safe to operate

the load device. Program the threshold through MFR_PROTECTION_CONFIG. This fault detection is active

regardless of power conversion. If triggered while power conversion is disabled, this fault is treated as

potentially catastrophic, and cannot be cleared without a power cycle of the VCC pin.

Tracking OVF is a fault limit, programmable as an offset from the current VOUT_COMMAND value. Program

this threshold through VOUT_OV_FAULT_LIMIT. When the VSP-VSN pin differential voltage exceeds this

limit during power conversion, the tracking overvoltage fault condition is detected. This fault detection is

disabled whenever power conversion is disabled.

Tracking OVW is a warning limit, programmable as an offset from the current VOUT_COMMAND value.

Program this threshold through VOUT_OV_WARN_LIMIT. When the VSP-VSN pin differential voltage

exceeds this limit during power conversion, the tracking overvoltage warning condition is detected. This is a

warning condition only, and does not cause any interruption to power conversion. The overvoltage warning

provides early feedback to they system host allowing it to make adjustments prior a fault triggering.

In response to the overvoltage warning condition, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_VOUT and asserts the SMB_ALERT# line if these bits are not masked.

In response to the overvoltage fault condition TPS536C7B1 responds according to the programmed

VOUT_OV_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins of the rail

which experienced a fault to pull low immediately. Additionally, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_VOUT and asserts the SMB_ALERT# line if these bits are not masked.

VCC

VR_EN

VR_RDY

V_OV-PREBIAS

t_INIT-LOGIC

t_INIT-PBOV

V_OV-FIXED

Fixed +Tracking OVP

V_OFS-OVFTRK

Fixed

OVP only

No Pre-Bias

OVP OVP only

Fixed

OVP only

V_OFS-UVFTRK

First PWM pulses

V_OFS-UVFTRK

V_OFS-UVWTRK

V_OUT

Figure 7-29. Overvoltage Protection

Program the tracking overvoltage fault threshold through the VOUT_OV_FAULT_LIMIT command as an absolute

voltage. When a new VOUT_OV_FAULT_LIMIT command is received the device calculates the tracking

overvoltage offset value internally according to Equation 27. The threshold voltages get scaled with the use

of an external voltage sensing divider and VOUT_SCALE_LOOP. TPS536C7B1 supports tracking overvoltage

fault offsets from +32 mV to +448 mV in 32 mV steps.

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Program the tracking overvoltage warning through the VOUT_OV_WARN_LIMIT command as an absolute

voltage. Similarly, when a new VOUT_OV_WARN_LIMIT command is received, the device calculates the

tracking overvoltage warning offset according to Equation 28. The threshold voltages get scaled with the use

of an external voltage sensing divider and VOUT_SCALE_LOOP. TPS536C7B1 supports tracking overvoltage

warning offsets from +24 mV to +448 mV in 8 mV steps.

Program the fixed overvoltage fault threshold through MFR_PROTECTION_CONFIG. TPS536C7B1 supports

values from 0.6 V to 3.7 V, in 100 mV steps.

VOUT_OV_FAULT_LIMIT − VOUT_COMMAND

V

=

(36)

(37)

OFS(OVF TRK)

VOUT_SCALE_LOOP

VOUT_OV_WARN_LIMIT − VOUT_COMMAND

=

OFS(OVW TRK)

VOUT_SCALE_LOOP

The over-voltage warning and fault trip thresholds include the load-line setting as shown in Equation 29 and

Equation 30.

V

= VOUT_COMMAND + V

− VOUT_DROOP × I

(38)

(39)

OVW(trip)

OVF(trip)

OFS(OVW TRK) OUT

= Min V

, VOUT_COMMAND + V

− VOUT_DROOP × I

OFS(OVF TRK) OUT

OVFIX

Updates to VOUT_COMMAND do not cause these the overvoltage offsets to be recalculated. After the output

voltage target has been changed, TPS536C7B1 reports the fault and warning thresholds by adding the

previously select offset value to the current VOUT_COMMAND.

Example: Programming the OVF and OVW offsets

Assume the current VOUT_COMMAND is 1.000 V, the VOUT_DROOP setting is equal to 0.5 mΩ, and the load

current is equal to 100 A.

•

Program the VOUT_OV_WARN_LIMIT to 1.128 V (1.0 V + 128 mV), to select the +128 mV tracking

overvoltage warning offset. The VOUT_DROOP is assumed to be zero for calculation purposes. However,

the over-voltage warning trip threshold does account for the load-line setting and is equal to 1.128 V - 0.5 mΩ

× I_OUT

.

•

Program the VOUT_OV_FAULT_LIMIT to 1.256 V (1.0 V + 256 mV) , to select the +256 mV tracking

overvoltage fault offset. The VOUT_DROOP is assumed to be zero for calculation purposes. However, the

over-voltage fault trip threshold does account for the load-line setting and is equal to 1.256 V - 0.5 mΩ × I_OUT

.

If the VOUT_COMMAND value is changed to is 1.100 V, the TPS536C7B1 reports VOUT_OV_WARN_LIMIT as

1.228 V (1.1 V + 128 mV), and VOUT_OV_FAULT_LIMIT as 1.356 V (1.1 V + 256 mV). The offset values are not

changed.

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7.7.4.2 Undervoltage fault (UVF) and warning (UVW)

Two undervoltage threshold limits are provided:

•

Tracking UVF is a fault limit, programmable as an offset from the current VOUT_COMMAND value. Program

this threshold through VOUT_UV_FAULT_LIMIT. When the VSP-VSN pin differential voltage falls below this

limit during power conversion, the tracking undervoltage fault condition is detected. This fault detection is

disabled whenever power conversion is disabled.

•

Tracking UVW is a warning limit, programmable as an offset from the current VOUT_COMMAND value.

Program this threshold through VOUT_UV_WARN_LIMIT. When the VSP-VSN pin differential voltage

exceeds this limit during power conversion, the tracking undervoltage warning condition is detected. This

is a warning condition only, and does not cause any interruption to power conversion. The undervoltage

warning provides early feedback to they system host allowing it to make adjustments prior a fault triggering.

In response to the undervoltage warning condition, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_VOUT and asserts the SMB_ALERT# line if these bits are not masked.

In response to the undervoltage fault condition TPS536C7B1 responds according to the programmed

VOUT_UV_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins of the

rail which experienced a fault to tristate immediately. TPS536C7B1 then sets the appropriate status bits in

STATUS_WORD and STATUS_VOUT and asserts the SMB_ALERT# line if these bits are not masked.

Program the tracking undervoltage fault threshold through the VOUT_UV_FAULT_LIMIT command as an

absolute voltage. When a new VOUT_UV_FAULT_LIMIT command is received, the device calculates the

tracking undervoltage offset value internally according to Equation 38. Threshold voltages get scaled with

the use of an external voltage sensing divider, and VOUT_SCALE_LOOP. TPS536C7B1 supports tracking

undervoltage fault offsets from -32 mV to -448 mV in 32 mV steps.

Program the tracking undervoltage warning through the VOUT_UV_WARN_LIMIT command as an absolute

voltage. When a new VOUT_UV_WARN_LIMIT command is received, the device calculates the tracking

undervoltage warning offset according to Equation 39. Threshold voltages get scaled with the use of an external

voltage sensing divider, and VOUT_SCALE_LOOP. TPS536C7B1 supports tracking undervoltage warning

offsets from -24 mV to -448 mV in 8 mV steps.

space

VOUT_COMMAND − VOUT_UV_WARN_LIMIT

V

=

(40)

(41)

OFS(UVW TRK)

VOUT_SCALE_LOOP

VOUT_COMMAND − VOUT_UV_FAULT_LIMIT

=

OFS(UVF TRK)

VOUT_SCALE_LOOP

The undervoltage warning and fault trip thresholds include the load-line setting as shown in Equation 33 and

Equation 34.

V

= VOUT_COMMAND − V

− VOUT_DROOP × I

OFS(UVW TRK) OUT

(42)

(43)

UVW(trip)

UVF(trip)

= VOUT_COMMAND − V

− VOUT_DROOP × I

OFS(UVF TRK)

OUT

Example: Programming the UVF and UVW thresholds

Assume the current VOUT_COMMAND is 1.000 V, the VOUT_DROOP setting is equal to 0.5 mΩ, and the load

current is equal to 100 A.

•

Program the VOUT_UV_WARN_LIMIT to 0.872 V (1.0 V - 128 mV), to select the -128 mV tracking

undervoltage warning offset. The VOUT_DROOP is assumed to be zero for calculation purposes. However,

the undervoltage warning trip threshold does account for the load-line setting and is equal to 0.872 V - 0.5

mΩ × I_OUT

.

•

Program the VOUT_UV_FAULT_LIMIT to 0.744 V (1.0 V - 256 mV), to select the -256 mV tracking

undervoltage fault offset. The VOUT_DROOP is assumed to be zero for calculation purposes. However,

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the undervoltage fault trip threshold does account for the load-line setting and is equal to 0.744 V - 0.5 mΩ ×

I_OUT

.

If the VOUT_COMMAND value is changed to is 1.100 V, the TPS536C7B1 reports VOUT_UV_WARN_LIMIT as

0.972 V (1.1 V - 128 mV), and VOUT_UV_FAULT_LIMIT as 0.844 V (1.1 V - 256 mV). The offset values are not

changed.

7.7.4.3 Maximum turn-on time exceeded (TON_MAX)

The TON_MAX_FAULT_LIMIT command sets a maximum allowable time during which the output voltage must

reach the regulation window during turn-on. The TON_MAX time is defined as the time between the first

switching pulses, and the sensed output voltage exceeding the the minimum allowed regulation point, defined as

V_TONMAX, in Equation 35. Program the TON_MAX_FAULT_LIMIT greater than the TON_RISE.

V

= VOUT_UV_FAULT_LIMIT − VOUT_DROOP × IOUT_OC_FAULT_LIMIT

(44)

TONMAX

Figure 7-30 illustrates the TON_MAX fault. TPS536C7B1 enables its undervoltage fault protection at the first

PWM pulses, during the output voltage rise time. Consequently, whenever the VOUT_UV_FAULT_RESPONSE

is not set to the ignore response, it triggers first and disables power conversion prior to the TON_MAX time.

VR_EN

V_OV-TRACK

TON_MAX

Shutdown

Tracking UV triggers

first if not Ignore

Response

V_UV-TRACK

V_TONMAX

V_DAC

V_OUT

TON_RISE

TON_MAX

Figure 7-30. TON_MAX fault

In response to the TON_MAX fault condition, TPS536C7B1 responds according to the programmed

TON_MAX_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins of the rail

which experienced the fault to tristate immediately. The TPS536C7B1 then sets the appropriate status bits in

STATUS_WORD and STATUS_VOUT and asserts the SMB_ALERT# line if these bits are not masked.

7.7.4.4 Output commanded out-of-bounds (VOUT_MIN_MAX)

The VOUT_MIN and VOUT_MAX commands set the minimum and maximum allowed output voltage targets.

TPS536C7B1 does not ramp the output voltage target for either channel outside these limits for any reason. This

includes being commanded to do so by VOUT_COMMAND, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW or

VOUT_TRIM.

Whenever the output voltage target is commanded outside the limits set by VOUT_MIN and VOUT_MAX,

TPS536C7B1 detects the VOUT_MIN_MAX warning condition. In response, TPS536C7B1 begins ramping the

output voltage target of that channel to the new target, and "clamps" to the VOUT_MIN or VOUT_MAX value. An

example is shown in Figure 7-31.

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V_OUT-MAX= 0.9 V

VOUT_TRANSITION_RATE

V_OUT-MIN= 0.7 V

VOUT_COMMAND

0.8 V

0.6 V

0.8 V

1.0 V

0.8 V

Figure 7-31. VOUT_MIN_MAX example

7.7.4.5 Overcurrent fault (OCF), warning (OCW), and per-phase overcurrent limit (OCL)

TPS536C7B1 provides three layers of overcurrent protection:

•

Overcurrent fault (OCF) is a programmable threshold which sets the maximum allowed total current (sum

of all phases) for a channel. Detection is based on output current telemetry. When the sensed output current

for a channel exceeds this limit, the output overcurrent fault is detected. Program this threshold using the

IOUT_OC_FAULT_LIMIT command with the PHASE set to FFh. TPS536C7B1 supports values of 0 to 1023 A

per channel.

•

Per-phase overcurrent limit (OCL) is a programmable cycle-by-cycle valley current limit for each individual

phase current, to protect against inductor saturation. TPS536C7B1 does not pass PWM pulses to phases

when their current is above the configured OCL threshold. Other than cycle-by-cycle current limit, no action

is taken when the per-phase OCL is engaged. Typically, in the case of a severe overload event, power

conversion is disabled when the output voltage reaches the VOUT_UV_FAULT_LIMIT. This is illustrated in

Figure 7-32. Program the OCL threshold using the IOUT_OC_FAULT_LIMIT command with the PHASE set to

00h. TPS536C7B1 supports values of 17 A to 130 A per phase.

•

Overcurrent warning (OCW) is a programmable warning threshold based on the total current (sum of all

phases) for a channel. Detection is based on output current telemetry. When the sensed output current for

a channel exceeds this limit, the output overcurrent warning is detected. Program this threshold using the

IOUT_OC_WARN_LIMIT. TPS536C7B1 supports values of 0 to 1023 A per channel.

Over-Load

Event

UVP

Shutdown

V_OUT

V_OUTfalls

because I_OUT> ꢀI_OCL

V_UV-TRK

I_OCL

I_PHASE1

I_PK= I_OCL+ ûI_RIPPLE

I_PHASE2

Pulses are blocked while I_PHASE> I_OCL

CLK_ON

PWM1

PWM2

Figure 7-32. Per-phase OCL (2 phase example)

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Typically, set the per-phase OCL threshold greater than total peak design current I_PK-CHANNELto allow margin for

transient events, as shown in Equation 36. TI recommends 30-50% design margin. Then peak current allowed

in any individual phase is given by Equation 37. Select output inductor components such that current saturation

levels are above this limit, including margin for threshold and current sensing accuracy.

I

OUT(peak)

1

2

I

= K

×

−

ΔI

RIPPLE

(45)

OCL(min)

MARGIN

N

Φ

where

•

I_OCL(min)is the per-phase overcurrent limit in amperes

I_OUT(PEAK)is the peak design current in amperes

N_ϕis the number of phases assigned to the channel

K_MARGINis a factor of safety for design margin

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I

= I

+ ΔI

(46)

PEAK(phase)

OCL RIPPLE

where

•

I_PEAK(phase)is the peak current observed in any individual phase

I_OCLis the per-phase overcurrent limit in amperes

ΔI_RIPPLEis the peak-to-peak inductor current ripple

In response to the overcurrent warning condition, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_IOUT and asserts the SMB_ALERT# line if these bits are not masked.

In response to the overcurrent fault condition, TPS536C7B1 responds according to the programmed

IOUT_OC_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins of the

rail which experienced a fault to tristate immediately. TPS536C7B1 then sets the appropriate status bits in

STATUS_WORD and STATUS_IOUT and asserts the SMB_ALERT# line if these bits are not masked.

7.7.4.6 Current share warning (ISHARE)

The TPS536C7B1 telemetry system continually monitors the average current in each phase, and compares it to

the average current of all phases assigned the channel. For each phase, whenever the condition described by

Equation 38 is satisfied, the current share warning condition is detected. Configure the current share warning

threshold through the MFR_PROTECTION_CONFIG command.

I

SUM

− I

≤ − I

or

I

−

≥ + I

SHAREW

(47)

PHASE

SHAREW

PHASE

N

Φ

where

•

I_PHASEis the current in each individual phase of a channel

I_SUMis the total current in that channel

N_ϕis the total number of phases assigned to that channel

I_SHAREWis the programmed ISHARE warning in amperes

In response to the current share warning condition, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_IOUT and asserts the SMB_ALERT# line if these bits are not masked.

7.7.4.7 Overtemperature fault protection (OTF) and warning (OTW)

TI smart power stages sense their internal die temperature and output temperature information as a voltage

signal through their TAO pins. The temperature sense output of the powerstage device includes an OR'ing

function such that the voltage signal present at the TSEN pin of the TPS536C7B1 represents that of the hottest

powerstage in the channel. The TPS536C7B1 digitizes its TSEN pins to provide temperature telemetry.

•

Overtemperature fault (OTF) is a programmable threshold which sets the maximum allowed temperature of

the powerstage devices attached to a channel. Detection is based on output temperature telemetry. When the

sensed temperature for a channel exceeds this limit, the overtemperature fault condition is detected. Program

this threshold using the OT_FAULT_LIMIT command. TPS536C7B1 supports values of 90 to 160 °C.

Overtemperature warning (OTW) is a programmable threshold which sets a warning based on the

temperature sense telemetry for a channel. Detection is based on temperature sense telemetry. When the

sensed temperature for a channel exceeds this limit, the overtemperature warning is detected. Program this

threshold using the OT_WARN_LIMIT. TPS536C7B1 supports values of 90 to 160 °C.

•

In response to the overtemperature warning condition, TPS536C7B1 sets the appropriate status bits in

STATUS_WORD and STATUS_TEMPERATURE and asserts the SMB_ALERT# line if these bits are not

masked.

In response to the overtemperature fault condition, TPS536C7B1 responds according to the programmed

OT_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins of the rail

which experienced a fault to tristate immediately. TPS536C7B1 then sets the appropriate status bits in

STATUS_WORD and STATUS_TEMPERATURE and asserts the SMB_ALERT# line if these bits are not

masked.

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7.7.4.8 Powerstage fault (TAO_HIGH) and powerstage not ready (TAO_LOW)

In addition to temperature sense information, the TPS536C7B1 and TI smart power stage devices use the TAO

lines to communicate fault information:

•

Powerstage fault (TAO_HIGH) is a fault condition detected when any of the connected powerstage devices

pulls its TAO line high (> 2.5 V). This occurs for any fault conditions detected inside the smart powerstage

itself. Refer to the individual powerstage datasheets for a complete list of conditions which cause the

powerstage fault. Program the controller response to a powerstage fault with MFR_PROTECTION_CONFIG.

Powerstage not ready (TAO_LOW) is a fault condition detected when the TAO line is low (160 mV falling,

245 mV rising) for any reason. At power-on, the TI smart power stages hold their TSEN/TAO lines low,

until their internal logic is valid, and their state is known (TAO_LOW condition). Once each device is in a

valid state, it's pull-down of the shared TSEN/TAO line is released, and the TAO/TSEN lines are driven by

the power-stage devices, based on temperature sense telemetry. The start-up of TPS536C7B1 is blocked

while the TAO_LOW condition exists, such that the controller does not attempt to begin conversion, until the

TAO/TSEN line is released by all power stages. During the initial power-on, no status bit or alerts are set if

the controller is commanded to enable with one of its TSEN/TAO pins low. This is done to accomodate power

sequences which have the power stage 5V rail being enabled after the controller 3.3V. The TAO_LOW fault

is a hysteretic-type response. When the TSEN/TAO pin is released, if the VR enable condition is still active,

power conversion starts immediately.

•

In response to the powerstage fault, the TPS536C7B1 responds according to the configured fault response

in MFR_PROTECTION_CONFIG. When not set to the ignore response, this causes the PWM pins for that

channel to tristate immediately. TPS536C7B1 then sets the appropriate status bits in STATUS_WORD and

STATUS_MFR_SPECIFIC and asserts the SMB_ALERT# line if these bits are not masked.

In response to the TAO_LOW condition, TPS536C7B1 tristates the PWM pins for that channel. TPS536C7B1

then sets the appropriate status bits in STATUS_WORD and STATUS_MFR_SPECIFIC and asserts the

SMB_ALERT# line if these bits are not masked. TAO_LOW is a hysteretic fault and cannot be configured

otherwise.

7.7.4.9 Input overvoltage fault (VIN_OVF) and warning (VIN_OVW)

TPS536C7B1 supports two layers of input overvoltage protection:

•

Input overvoltage fault (VIN_OVF) is a programmable threshold which sets the maximum allowed input

voltage, above which it is not safe to convert power. Detection is based on input voltage telemetry. When

the sensed input voltage exceeds this limit, the input overvoltage fault condition is detected. Program this

threshold using the VIN_OV_FAULT_LIMIT command. TPS536C7B1 supports values of 0 to 19 V.

Input overvoltage warning (VIN_OVW) is a programmable threshold which sets a warning based on the

input voltage sense telemetry. Detection is based on input voltage sense telemetry. When the sensed input

voltage for a channel exceeds this limit, the input overvoltage warning is detected. Program this threshold

using the VIN_OV_WARN_LIMIT command. TPS536C7B1 supports values of 0 to 19 V.

•

In response to the input overvoltage fault, the TPS536C7B1 responds according to the configured fault response

in VIN_OV_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins for both

channels to tristate immediately. TPS536C7B1 then sets the appropriate status bits in STATUS_WORD and

STATUS_INPUT and asserts the SMB_ALERT# line if these bits are not masked.

7.7.4.10 Input undervoltage fault (VIN_UVF), warning (VIN_UVW) and turn-on voltage (VIN_ON)

Three programmable parameters control the TPS536C7B1 input undervoltage protection. More detail is shown

in Figure 7-33.

•

Turn-on voltage (VIN_ON) is the input voltage at which TPS536C7B1 allows power conversion to be

enabled. Program this threshold through the VIN_ON command. The input undervoltage fault and warning

are masked until the turn-on voltage is exceeded the first time during power-up. TPS536C7B1 does not act

on commands to enable power conversion while the input voltage is below this limit. No action is taken when

the input voltage falls below this threshold during power conversion. Detection is based on input voltage

telemetry. TPS536C7B1 supports values from 4.25 V to 11.5 V.

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•

Input undervoltage fault (VIN_UVF) is the input voltage at which power conversion stops. Program this

threshold through the VIN_UV_FAULT_LIMIT command. This command is also forced equal to the turn-off

voltage (VIN_OFF). Detection is based on input voltage telemetry. When the sensed input voltage falls below

this limit, the input undervoltage fault condition is detected. This fault is masked until the sensed input voltage

exceeds the turn-on voltage VIN_ON for the first time. TPS536C7B1 supports values from 4.00 V to 11.25 V.

Input undervoltage warning (VIN_UVW) is a programmable threshold which sets a warning based on the

input voltage sense telemetry for a channel. Detection is based on input voltage sense telemetry. When the

sensed input voltage below this limit, the input undervoltage warning is detected. Program this threshold

using the VIN_UV_WARN_LIMIT. TPS536C7B1 supports values of 4.0 V to 11.25 V.

•

The input undervoltage fault is triggered when the sensed input voltage falls below the VIN_UV_FAULT_LIMIT

threshold, and considered to be cleared when the sensed input voltage exceeds the VIN_ON limit. The input

undervoltage fault is enabled only when either of the channels is enabled. Toggling the enable for both channels

at the same time with the input voltage above the VIN_UV_FAULT_LIMIT threshold clears the fault, and enables

power conversion to begin automatically after the input voltage exceeds the VIN_ON limit. In the case where

the enable for each channel is independent, commanding one channel to enable conversion does not clear the

input undervoltage condition and power conversion may not start automatically when the input voltage exceeds

the VIN_ON thresholds. TI recommends to enable power conversion only after the input voltage exceeds the

VIN_ON as shown in Figure 7-33.

VR_EN

V_IN-ON

V_IN-UVW

V_INOFF= V_IN-UVF

V_IN

0.0 V

VIN UVW is clearable

Power Conversion

OFF

ON

OFF

ON

Fault Status

VIN_UVW

VIN_UVF

VIN_UVW

None

Figure 7-33. Input undervoltage protection (VR_EN active high control)

7.7.4.11 Input overcurrent fault (IIN_OCF) and warning (IIN_OCW)

•

Input overcurrent fault (IIN_OCF) is a programmable threshold which sets the maximum allowed input

current for the converter. Detection is based on input current telemetry. When the sensed input current

exceeds this limit, the input overcurrent fault condition is detected. Program this threshold using the

IIN_OC_FAULT_LIMIT command. TPS536C7B1 supports values of 4 to 128A.

•

Input overcurrent warning (IIN_OCW) is a programmable threshold which sets a warning threshold for

the input current for the converter. Detection is based on input current telemetry. When the sensed input

current exceeds this limit, the input overcurrent warning condition is detected. Program this threshold using

the IIN_OC_WARN_LIMIT command. TPS536C7B1 supports values of 4 to 128A.

In response to the input overcurrent fault, the TPS536C7B1 responds according to the configured fault response

in IIN_OC_FAULT_RESPONSE. When not set to the ignore response, this causes the PWM pins for both

channels to tristate immediately. TPS536C7B1 then sets the appropriate status bits in STATUS_WORD and

STATUS_INPUT and asserts the SMB_ALERT# line if these bits are not masked.

7.7.4.12 Input overpower warning (PIN_OPW)

The PIN_OP_WARN_LIMIT command sets an input overpower warning limit for the converter. Detection is

based on the input power telemetry, which is derived by multiplying the input voltage and input current

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measurement values. When the input current telemetry measurements exceeds this limit, TPS536C7B1 detects

the input overpower warning condition. TPS536C7B1 supports values from 8 to 2044 W.

The input overpower warning does not interrupt power conversion. In response, TPS536C7B1 sets the

appropriate status bits in STATUS_WORD and STATUS_INPUT and asserts the SMB_ALERT# line if these

bits are not masked.

7.7.4.13 PMBus command, memory and logic errors (CML)

The STATUS_CML command provides information about communication errors which have occurred.

Communication errors are warnings and do not cause any interruption to power conversion.

•

Invalid command (IVC) occurs when the host attempts to access TPS536C7B1 at a command which it does

not support.

Invalid data (IVD) occurs when the host sends data to a supported command which is out of range or

unsupported.

Packet error check (PEC) error occurs when TPS536C7B1 receives a transaction with an invalid or

incorrect PEC byte.

•

Communication error (COMM) occurs when the SMBus timeout condition is detected.

Other (CML_OTHER) can occur due to multiple conditions (may not be an exhaustive list):

– Wrong transaction prototype - e.g. accessing a read word command as a read block

– Block command send with the incorrect number of bytes, or block count was not acknowledged

– Bus arbitration was lost

– Transaction aborted

7.8 Device Functional Modes

Power-on Reset (POR)

When the VCC in voltage is below approximately 2.5 V, the TPS536C7B1 enters power-on reset, and all internal

blocks return to their unpowered state. Raise the VCC voltage above the input UVLO threshold to exit the POR

state. Exiting POR requires up to 20 ms before power conversion can be enabled, during which the device

re-loads all NVM values and performs pinstrap detection.

Disabled state

The ON_OFF_CONFIG PMBus command specifies the combination of VR_EN pins and OPERATION command

input required to start power conversion. When the specified combination is not met (e.g. VR_EN is low, for

VR_EN only, active high configuration), power conversion is disabled. The PWM pins assigned to the channel

remain at tri-state, and the VR_RDY pin for the channel is pulled low. Once the enable conditions are met (e.g.

VR_EN pulled high for VR_EN only, active high configuration), the controller begins power conversion, after a

period of approximately 750 μs plus any added turn-on delay. The TPS536C7B1 device returns to the disabled

state after being disabled by the same means.

Turn-on and turn-off delay

The TON_DELAY and TOFF_DELAY commands allow the user to add additional turn-on or turn-off delay

between the time that enable/disable conditions are satisfied, and the TPS536C7B1 begins ramping the output

voltage. To ensure consistent behavior, TI recommends not to interrupt the turn-on or turn-off delays with

additional enable/disable requests.

Soft-start and soft-off shutdown

The soft-start period begins when the first PWM pulses are fired after a channel is enabled, and ends when the

internal loop DAC reaches the boot voltage. During this time, the controller is raising the output voltage at a slew

rate derived from to track the loop DAC, and tracking over/undervoltage protections are active.

TPS536C7B1 may be configured to actively ramp the output voltage down to zero after being disabled through

the ON_OFF_CONFIG command. During this time, the controller ramps down the loop DAC to zero at the slew

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rate derived from TOFF_FALL. This behavior is optional, and the default configuration is to have the channel

enter directly into the disabled state (immediate off).

Normal operation

The TPS536C7B1 is in the normal state when converting power. During this time, the device responds to new

output voltage target (DVID) commands through PMBus as configured through the OPERATION command.

Power conversion continues in Auto-DCM, FCCM dynamic phase shedding, or all phases FCCM, as configured

through the PMBus interface.

Fault shutdown (Latch-off)

Any time a fault which is configured with the latch-off response is triggered, the device stops power conversion

on the affected channel (or both if caused by a shared fault). The PWM pins remain at tri-state for all faults,

excepting over-voltage faults which cause the PWM pins to remain low. The VR_RDY pin remains low as

long as the converter is disabled. It remains in this state until commanded to re-enable as specified in

ON_OFF_CONFIG.

Fault shutdown (Hiccup)

Any time a fault which is configured with the hiccup response is triggered, the device stops power conversion

on the affected channel (or both if caused by a shared fault). The PWM pins remain at tri-state for all faults,

excepting over-voltage faults which cause the PWM pins to remain low. It remains in this state until a timer

expires, then attempt to re-enable itself, while respecting the configured TON_DELAY and TOFF_DELAY times.

The VR_RDY pin remains low as long as the converter is disabled, and re-asserts after a successful start-up

attempt.

POR Fault shutdown

Some fault conditions are considered catastrophic and cause the TPS536C7B1 to refuse any further enable

attempts. These include: memory errors, internal logic errors, invalid pinstrap, pre-bias overvoltage protection

conditions. The only way to recover from a POR fault is to re-cycle the VCC pin voltage below the POR

threshold.

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7.9 Programming

7.9.1 PMBus overview

TPS536C7B1 is designed to be compatible with the timing and physical layer electrical characteristics of the

Power Management Bus (PMBus) Specification, part I, revision 1.3.1 available at http://pmbus.org. The 100-kHz,

400-kHz, and 1000-kHz classes are supported. Input logic levels are designed to be compaitible with 1.8-V and

3.3-V logic. PMBus revision 1.3 is derived from the System Managmenet Bus (SMBus) revision 3.0, available at

http://smbus.org/. The communication mechanism is based on the inter-integrated circuit I²C protocol.

A master with clock stretching support is mandatory for communication with TPS536C7B1 through the PMBus

interface. TPS536C7B1 does support the packet error check (PEC) protocol. If the system host supplies clock

pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.

TPS536C7B1 can be configured to require PEC for each transaction in systems which require high reliability of

communication.

TPS536C7B1 supports the SMB_ALERT# response protocol. The SMB_ALERT# response protocol is a

mechanism by which a slave device can alert the master device that it is available for communication. The

master device processes this event and simultaneously accesses all slave devices on the bus (that support the

protocol) through the alert response address (ARA). Only the slave device that caused the alert acknowledges

this request. The host device performs a modified receive byte operation to ascertain the slave devices address.

At this point, the master device can use the PMBus status commands to query the slave device that caused the

alert. By default, these devices implement the auto alert response, a manufacturer specific improvement to the

SMB_ALERT# response protocol, intended to mitigate the issue of bus hogging. For more information on the

SMBus alert response protocol, see the System Management Bus (SMBus) specification.

7.9.2 PMBus transaction types

Support for the following SMBus transaction types is mandatory. The use of PEC is optional. Refer to the SMBus

specification and Technical Reference Manual for more detailed transaction diagrams.

SMBus Write Block and Read Block transaction types contain a repeated start condition, which may not be

compatible with all I²C master device IP.

•

Write Byte / Read Byte

Write Word / Read Word

Write Block / Read Block

Send Byte / Receive Byte

Block-Write-Block-Read Process Call (for SMBALERT_MASK commands)

7.9.3 PMBus data formats

TPS536C7B1 supports 3 data formats according to the PMBus specification. The data format for each command

is listed along with its address and supported values.

•

ULINEAR16 format uses a 16-bit unsigned integer. The default LSB size is 2^-10= 0.97656 mV

SLINEAR16 format uses a 16-bit number representing a decimal. This number has two fields: the 5 MSB

bits form an two's complement exponent, referred to as N, and the 11 LSB bits form a two's complement

mantissa, referred to as M. The decimal number is represented as D = M × 2^N

•

Unsigned binary format uses direct bit maps with each command being subdivided into multiple fields

that can have different meaning. Refer to the register maps in the Technical Reference Manual for these

commands.

TPS536C7B1 accepts writes to SLINEAR11 format commands with any desired exponent value. TI recommends

using the default exponent listed for each command for writes to ensure consistent NVM store and restore

behavior.

Telemetry commands in the SLINEAR11 format return data with variable exponent values according to the

absolute value of the retured value. As a rule TPS536C7B1 returns data in the SLINEAR11 format with the

smallest possible exponent, to provide the highest possible command resolution. As a result the host must be

able to support decoding of the SLINEAR11 format with any exponent value.

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7.9.3.1 Example PMBus number format conversions

Example: Decode SLINEAR11 number E804h

E804h = 11101 00000000100b

Exponent = 11101b. N = -3 (5-bit two's complement)

Mantissa = 00000000100b. M = 4 (11-bit two's complement)

The decimal number D = M × 2^N= 4 × 2^-3= 0.5

SPACE

Example: Encode 5.25 to SLINEAR11 with exponent -4

Exponent = -4 = 11100b (5-bit two's complement)

Mantissa = 5.25 / 2^N= 5.25 / 2^-4= 84d = 00001010100b (11-bit two's complement)

SLINEAR11 representation = 11100 00001010100b = E054h

SPACE

Example: Encode 1.00 V to ULINEAR16 with VOUT_MODE = 16h

VOUT_MODE = 16h (Linear Absolute). Exponent (PARAMETER) = 10110b = -10 (5-bit two's complement)

1.00 V = 1.00 / 2^-10= 1024d = 0400h

SPACE

Example: Decode 03E6h in ULINEAR16 with VOUT_MODE = 16h

VOUT_MODE = 16h (Linear Absolute). Exponent (PARAMETER) = 10110b = -10 (5-bit two's complement)

2^-10× 03D6h = 0.9746 V

7.9.3.2 Example system code for PMBus format conversion

Example code for handling the SLINEAR11 and ULINEAR16 formats at the system level is given below.

Example code in a syntax similar to the C programming language is provided for reference only. Error checking

code is not included. It is the responsibility of the system designer to verify and test all system code.

//Maps 5 bit linear exponent to LSB value (2^(twos complement of index))

const float LUT_linear_exponents[32] = {

1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0,256.0,512.0,1024.0,2048.0,4096.0,8192.0,

16384.0,32768.0,0.0000152587890625,0.000030517578125,0.00006103515625,

0.0001220703125,0.000244140625,0.00048828125,0.0009765625,0.001953125,0.00390625,

0.0078125,0.015625,0.03125,0.0625,0.125,0.25,0.5

};

Figure 7-34. Linear exponent to LSB converstion (look-up table approach)

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unsigned int float_to_slinear11(float number, signed int exponent)

{

signed int mantissa;

float lsb;

//Decode the exponent and generate twos complement form

if(exponent < 0) {

lsb = LUT_linear_exponents[(exponent+32)];

} else {

lsb = LUT_linear_exponents[exponent];

}

//Decode mantissa based on exponent and generate twos complement form

mantissa = (signed int)(number / lsb);

//If numbers are negative, de-sign-extend to 5/11 bit numbers

mantissa &= 0x07FF;

exponent &= 0x1F;

return (mantissa | (exponent << 11));

}

Figure 7-35. Floating point to SLINEAR11 conversion

float slinear11_to_float(unsigned int number)

{

unsigned int exponent;

int mantissa;

float lsb;

exponent = number >> 11;

mantissa = number & 0x07FF;

//Sign extend Mantissa to 32 bits (use your int size here)

if (mantissa > 0x03FF) {

mantissa |= 0xFFFFF800;

}

lsb = LUT_linear_exponents[exponent];

return ((float)mantissa)*lsb;

}

Figure 7-36. SLINEAR11 to floating point conversion

unsigned int float_to_ulinear16(float number, unsigned char vout_mode)

{

float lsb;

lsb = LUT_linear_exponents[(vout_mode & 0x1F)];

return (unsigned int)(number/lsb);

}

Figure 7-37. Floating point to ULINEAR16 conversion

float ulinear16_to_float(unsigned int number, unsigned char vout_mode)

{

float lsb;

lsb = LUT_linear_exponents[(vout_mode & 0x1F)];

return ((float)number)*lsb;

}

Figure 7-38. ULINEAR16 to floating point conversion

7.9.4 Raw non-volatile memory programming

TPS536C7B1 has 256 bytes of internal EEPROM non-volatile memory (NVM). Each PMBus command with

NVM backup is mapped into the NVM array. For example, if a command supports 16 possible values, there are 4

corresponding bits for that field. The NVM array is designed withstand being overwritten greater than 1,000 times

over the lifetime of the device.

The USER_NVM_INDEX and USER_NVM_EXECUTE commands provide access to read and write the raw data

bytes. These commands allow the entire configuration data for the device to be read/written with a minimum

number of transactions, to save programming time. The USER_NVM_EXECUTE command is a 32 byte block

which accesses blocks of raw NVM data. The USER_NVM_INDEX command is an auto-incrementing byte

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command which which selects which 32 bytes of memory are being accessed via the USER_NVM_EXECUTE

command.

The Fusion Digital Power Designer software provided for this device is capable of exporting raw configuration

data, as well as XML configuration files containing the value of each PMBus command.

Configuration validation

The first 9 bytes of data returned by USER_NVM_EXECUTE with index zero, are identifying information for

the configuration. Bytes 0 to 6 represent the IC_DEVICE_ID. Bytes 7-8 represent the IC_DEVICE_REV. Byte 9

represents the currently configured PMBus slave address.

During the NVM import process, the controller checks these 9 bytes versus its current configuration, and NACKs

theUSER_NVM_EXECUTE (index = 0) command if the data does not match.

Example: Configuration validation

•

Reading the USER_NVM_EXECUTE (index 0) from a configured device returns value 0x54 49 53 6C 70 00

00 04 60 … [NVM bytes 0 to 22]. This indicates the configuration data was generated from a device with

IC_DEVICE_ID 0x54 49 53 6C 70 00, IC_DEVICE_REV 00 04 and PMBus address 0x60.

Writing the USER_NVM_EXECUTE (index 0) with the value 0x54 49 53 6C 70 00 00 04 60 … [NVM bytes

0 to 22] to a new device causes it to check its IC_DEVICE_ID is equal to 0x54 49 53 6C 70 00, check its

IC_DEVICE_REV is equal to 00 04 and check its PMBus address 0x60. If any of these checks fail, the write

operation is rejected.

•

Writing the USER_NVM_EXECUTE (index 0) with the value 0xFF FF FF FF FF FF 00 04 60 … [NVM bytes

0 to 22] to a new device causes it skip the IC_DEVICE_ID check, but still check its IC_DEVICE_REV is equal

to 00 04 and check its PMBus address 0x60. If any of these checks fail, the write operation is rejected.

Writing the USER_NVM_EXECUTE (index 0) with the value 0xFF FF FF FF FF FF FF FF 60 … [NVM bytes

0 to 22] to a new device causes it skip the IC_DEVICE_ID check, skip its IC_DEVICE_REV check, but still

check its PMBus address 0x60. If any of these checks fail, the write operation is rejected.

Writing the USER_NVM_EXECUTE (index 0) with the value 0xFF FF FF FF FF FF FF FF FF … [NVM bytes

0 to 22] to a new device causes it skip the IC_DEVICE_ID check, skip its IC_DEVICE_REV check, and skip

its PMBus address check. No checks were performed, so the data is accepted.

Procedure: Read all configuration data

Follow the procedures below to read-back NVM data for TPS536C7B1 devices.

1. Configure the device as desired through PMBus commands, then issue STORE_USER_ALL. Power cycle

the device or issue RESTORE_USER_ALL with power conversion disabled to ensure operating memory and

non-volatile memory bytes are matching.

2. Write the USER_NVM_INDEX command to 00h.

3. Read back and record the USER_NVM_EXECUTE command (index = 0).

4. Read back and record the USER_NVM_EXECUTE command (index = 1).

5. Read back and record the USER_NVM_EXECUTE command (index = 2).

6. Read back and record the USER_NVM_EXECUTE command (index = 3).

7. Read back and record the USER_NVM_EXECUTE command (index = 4).

8. Read back and record the USER_NVM_EXECUTE command (index = 5).

9. Read back and record the USER_NVM_EXECUTE command (index = 6).

10. Read back and record the USER_NVM_EXECUTE command (index = 7).

11. Read back and record the USER_NVM_EXECUTE command (index = 8). The last 23 bytes of this

command are not used by the device. TI recommends replacing these bytes with 00h for consistency across

different configurations.

Procedure: Write all configuration data

Follow the procedures below to write NVM data for TPS536C7B1 devices.

1. Apply +3.3V to the VCC pin of TPS536C7B1

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2. Ensure power conversion is disabled for both channels.

3. Write the USER_NVM_INDEX command to 00h.

4. Write the previously recorded USER_NVM_EXECUTE (index = 0). In this example, disable the self-

validation checks by replacing the first 9 bytes with FFh.

5. Write the previously recorded USER_NVM_EXECUTE (index = 1).

6. Write the previously recorded USER_NVM_EXECUTE (index = 2).

7. Write the previously recorded USER_NVM_EXECUTE (index = 3).

8. Write the previously recorded USER_NVM_EXECUTE (index = 4).

9. Write the previously recorded USER_NVM_EXECUTE (index = 5).

10. Write the previously recorded USER_NVM_EXECUTE (index = 6).

11. Write the previously recorded USER_NVM_EXECUTE (index = 7).

12. Write the previously recorded USER_NVM_EXECUTE (index = 8). Replace the last 23 bytes with 00h. An

NVM store operation is automatically performed once the last block is successfully received.

13. Wait 100 ms for non-volatile memory programming to complete successfully. Ensure that the +3.3V power

supply to the device is not interrupted during this time to guarantee proper memory storage and retention.

14. Do not issue an NVM store operation at this point. This overwrites the NVM array with the data values in

operating memory.

15. Power cycle the device or issue RESTORE_USER_ALL to continue operation with the newly programmed

values. Multifunction pin configurations require a power cycle to take effect.

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Table 7-10. Supported Commands and NVM Defaults

Default

Hex⁽²⁾

Ch. A

Default

R/W

Access,

NVM

CMD

Default Behavior

Ch. A (PAGE = 0)

Default Behavior

Ch. B (PAGE = 1)

Command Name

Code

Hex⁽²⁾

Ch. B

00h

01h

02h

03h

PAGE

Commands address both Channel A and Channel B

FFh

R/W

OPERATION

ON_OFF_CONFIG

CLEAR_FAULTS

OPERATION Off, Margin None

AVR_EN pin only, Active High

Clears all faults related to channel A

OPERATION Off, Margin None

BVR_EN pin only, Active High

Clears all faults related to channel B

00h

17h

N/A

00h

17h

N/A

R/W, NVM

W

Commands address all phases in channel Commands address all phases in channel

04h

PHASE

FFh

R/W

A

B

05h

06h

10h

15h

16h

19h

1Bh

PAGE_PLUS_WRITE

PAGE_PLUS_READ

Utility to send PAGE along with a PMBus write transaciton

Utility to send PAGE along with a PMBus read transaciton

All commands are writeable

Per command

W

R

Per command

WRITE_PROTECT

00h

N/A

D0h

R/W, NVM

W

STORE_USER_ALL

Stores all current storable register settings into NVM as new defaults

Restores all storable register settings from NVM

1 MHz, PEC, SMB_ALERT Supported

RESTORE_USER_ALL

CAPABILITY

W

R

SMBALERT_MASK_WORD

SMBALERT_MASK_VOUT

SMBALERT_MASK_IOUT

SMBALERT_MASK_INPUT

No SMB_ALERT sources masked

LOW VIN bit is masked

No SMB_ALERT sources masked

00h

R/W

No SMB_ALERT sources masked

00h

R/W, NVM

08h

SMBALERT_MASK_

TEMPERATURE

1Bh

No SMB_ALERT sources masked

00h

R/W, NVM

1Bh

SMBALERT_MASK_CML

SMBALERT_MASK_MFR

No SMB_ALERT sources masked

VR SETTLED is masked

No SMB_ALERT sources masked

00h

26h

00h

06h

R/W, NVM

R

FIRST_TO_ALERT does not assert SMB_ALERT#

00h

ULINEAR16 Mode, Absolute,

Exponent = -10

ULINEAR16 Mode, Absolute,

20h

VOUT_MODE

16h

R

Exponent = -10

R/W,

NVM/

0.880 V

21h

VOUT_COMMAND

1.000 V

03 85h

00 00h

04 00h

From pin-detection by default

Pin Detect

(Ch A)

22h

24h

VOUT_TRIM

VOUT_MAX

+0.000 V

1.400 V

00 00h

05 9Ah

R/W, NVM

1.869 V (VBOOT_CHA pinstrp active by

default) NVM stored value is 1.200 V

07 7Ah /

04 CDh

25h

26h

27h

28h

29h

2Bh

33h

34h

35h

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

VOUT_TRANSITION_RATE

VOUT_DROOP

0.000 V

00 00h

E0 50h

C8 00h

E8 08h

00 00h

01 F4h

03h

00 00h

E0 50h

C80 0h

E8 08h

00 00h

01 F4h

03h

R/W

0.000 V

R/W

5.0 mV/µs

R/W, NVM

R/W

0.000 mΩ

VOUT_SCALE_LOOP

VOUT_MIN

1.000

0.000 V

FREQUENCY_SWITCH

POWER_MODE

500 kHz

DPS disabled, all phases FCCM

9.250 V

DPS disabled, all phases FCCM

VIN_ON

F0 25h

R/W, NVM

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Table 7-10. Supported Commands and NVM Defaults (continued)

Default

Hex⁽²⁾

Ch. A

Default

Hex⁽²⁾

Ch. B

R/W

Access,

NVM

CMD

Default Behavior

Ch. A (PAGE = 0)

Default Behavior

Ch. B (PAGE = 1)

Command Name

Code

38h

IOUT_CAL_GAIN

5.000 mΩ

CA 80h

E8 00h

R/W, NVM

+0.125 A (phase 10)

E8 01h

39h

IOUT_CAL_OFFSET

0.000 A (all phases)

0.000 A (other phases)

/ E8 00h

40h

41h

42h

43h

44h

45h

VOUT_OV_FAULT_LIMIT

VOUT_OV_FAULT_RESPONSE

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

VOUT_UV_FAULT_RESPONSE

1.072 V (VOUT_COMMAND + 192 mV)

Latch-off and do not restart

1.192 V (VOUT_COMMAND + 192 mV)

Latch-off and do not restart

04 4Ah⁽¹⁾04 C5h⁽¹⁾R/W, NVM

80h

R/W, NVM

1.040 V (VOUT_COMMAND + 160 mV)

0.704 V (VOUT_COMMAND - 176 mV)

0.688 V (VOUT_COMMAND - 192 mV)

Latch-off after 5.0 μs and do not restart

1.160 V (VOUT_COMMAND + 160 mV)

0.824 V (VOUT_COMMAND - 176 mV)

0.808 V (VOUT_COMMAND - 192 mV)

Latch-off after 5.0 μs and do not restart

04 29h⁽¹⁾

04 A4h⁽¹⁾R/W, NVM

02 D1h⁽¹⁾03 4Ch⁽¹⁾R/W, NVM

02 C0h⁽¹⁾03 3Bh⁽¹⁾R/W, NVM

40h

R/W, NVM

480 A total current

53 A phase current

80 A total current

10 E0h

00 35h

00 50h

00 35h

46h

IOUT_OC_FAULT_LIMIT

53 A phase current

47h

4Ah

4Fh

50h

51h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

60h

61h

62h

63h

64h

65h

6Bh

IOUT_OC_FAULT_RESPONSE

IOUT_OC_WARN_LIMIT

OT_FAULT_LIMIT

Latch-off and do not restart

60 A total current

120°C

C0h

01 B8h

00 78h

80h

C0h

00 3Ch

00 78h

80h

R/W, NVM

440 A total current

120°C

OT_FAULT_RESPONSE

OT_WARN_LIMIT

Latch-off and do not restart

110°C

00 6Eh

VIN_OV_FAULT_LIMIT

VIN_OV_FAULT_RESPONSE

VIN_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT

VIN_UV_FAULT_LIMIT

VIN_UV_FAULT_RESPONSE

IIN_OC_FAULT_LIMIT

IIN_OC_FAULT_RESPONSE

IIN_OC_WARN_LIMIT

TON_DELAY

15.0 V

00 0Fh

Latch-off and do not restart

80h

14.0 V

00 0Eh

F0 22h

F0 20h

80h

8.50 V

8.00 V

Latch-off and do not restart

52.0 A

00 34h

C0h

Latch-off and do not restart

44.0 A

00 2Ch

0.00 ms

F8 00h

F0 06h

F0 08h

80h

TON_RISE

1.5 ms (SR_BOOT= 0.625 mV/μs)

2.0 ms

1.5 ms (SR_BOOT= 0.625 mV/μs)

2.0 ms

F0 06h

F0 08h

80h

TON_MAX_FAULT_LIMIT

TON_MAX_FAULT_RESPONSE

TOFF_DELAY

Latch-off and do not restart

0.00 ms

Latch-off and do not restart

0.00 ms

F8 00h

F0 06h

F8 00h

F0 06h

TOFF_FALL

1.5 ms (SR_OFF= 0.625 mV/μs)

592.0 W

1.5 ms (SR_OFF= 0.625 mV/μs)

PIN_OP_WARN_LIMIT

09 28h

Current

Status

Current

Status

78h

79h

7Ah

STATUS_BYTE

STATUS_WORD

STATUS_VOUT

Current status channel A

Current status channel B

R

Current

Status

Current

Status

R/W

Current

Status

Current

Status

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Table 7-10. Supported Commands and NVM Defaults (continued)

Default

Hex⁽²⁾

Ch. A

Default

R/W

Access,

NVM

CMD

Default Behavior

Ch. A (PAGE = 0)

Default Behavior

Ch. B (PAGE = 1)

Command Name

Code

Hex⁽²⁾

Ch. B

Current

Status

Current

Status

7Bh

7Ch

7Dh

STATUS_IOUT

Current status channel A

Current status channel B

R/W

STATUS_INPUT

Current status

Current Status

Current

Status

Current

Status

STATUS_TEMPERATURE

Current status channel A

Current status channel B

Current

Status

Current

Status

7Eh

7Fh

80h

STATUS_CML

Current status

R/W

Current

status

Current

status

STATUS_OTHER

Current status

Current

Status

Current

Status

STATUS_MFR_SPECIFIC

Current status channel A

Current status channel B

88h

89h

READ_VIN

READ_IIN

Measured input voltage

Measured input current

Current Status

R

Current

Status

8Bh

8Ch

8Dh

96h

READ_VOUT

Measured output voltage channel A

Measured output current channel A

Measured output voltage channel B

Measured output current channel B

R

Status

Current

Status

Current

Status

READ_IOUT

Measured power stage temperature

channel A

Measured power stage temperature

channel B

Current

Status

Current

Status

READ_TEMPERATURE_1

READ_POUT

Current

Status

Current

Status

Calculated output power channel A

Calculated output power channel B

97h

98h

99h

9Ah

9Bh

9Dh

ADh

AEh

READ_PIN

Calculated input power

Current Status

R

PMBUS_REVISION

MFR_ID

Revision 1.3, Part I and Part II compatible

Manufacturer company identification

Manufacturer model identification

Manufacturer revision identification

Manufacturer date identification

TPS536C7B1

33h

02 00 00h

R/W, NVM

R

MFR_MODEL

MFR_REVISION

MFR_DATE

00 00 00h

IC_DEVICE_ID

IC_DEVICE_REV

54 49 53 6C 70 00h

00 04h

Revision 2

R

DC load line: 0.00 mΩ

AC load line: 0.20 mΩ

AC load line: 0.4375 mΩ

Integration time contsant: 7.0 μs

Dynamic integration contsant: 3.0 μs

Dynamic integration threshold: 120 mV

AC gain: 1.0

Integration time contsant: 1.0 μs

Dynamic integration contsant: 4.0 μs

Dynamic integration threshold: 60 mV

AC gain: 1.0

00 D0 0E

73 0D D0 72 1C D0 R/W, NVM

00 C8h 00 C8h

00 53 66

USER_DATA_01

B1h

(COMPENSATION_CONFIG)

Integration gain: 1.0

Ramp amplitude: 360 mV

Ramp amplitude: 200 mV

USR1 threshold: 120 mV

USR2 threshold: 50 mV

Min off time: 30 ns

USR1 threshold: 120 mV

USR2 threshold: 50 mV

Min off time: 30 ns

USER_DATA_02

31 1A 0F 31 1A 0F

06 DAh 07 DAh

B2h

R/W, NVM

(NONLINEAR_CONFIG)

Blanking time: 30 ns

OSR: Disabled

Blanking time: 35 ns

OSR: Disabled

USR1 phases: 4 phases

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Table 7-10. Supported Commands and NVM Defaults (continued)

Default

Hex⁽²⁾

Ch. A

Default

Hex⁽²⁾

Ch. B

R/W

Access,

NVM

CMD

Default Behavior

Ch. A (PAGE = 0)

Default Behavior

Ch. B (PAGE = 1)

Command Name

Code

00 80 02 81 04 82 06

USER_DATA_03

12+0 configuration, 0-2-4-6-8-10-1-3-5-7-9-11

From pin-detection by default

83 08 84 0A 85 01 86 R/W, NVM

03 87 05 88 07 89 09 Pin Detect

8A 0B 8Bh

B3h

(PHASE_CONFIG)

DCLL up: 0.00 mΩ

DCLL down: 0.00 mΩ

ACLL up: 0.50 mΩ

ACLL down: 0.50 mΩ

Boot offset: 90mV

DCLL up: 0.00 mΩ

DCLL down: 0.00 mΩ

USER_DATA_04

(DVID_CONFIG)

ACLL up: 0.75 mΩ

ACLL down: 0.50 mΩ

Boot offset: 40mV

03 60 08

03 20 0C

B4h

R/W, NVM

08 00 00h 08 00 00h

Dynamic offsets: 0 mV

30 08 44

44 44 44

30 08 44

44 44 44

USER_DATA_07

B7h

BAh

BBh

Phase shedding disabled

44 2F FF 48 2F FF R/W, NVM

FF FF FF FF FF FF

(PHASE_SHED_CONFIG)

FFh

USER_DATA_10

04h all

phases

04h all

phases

All phases = 1.0 K_T

RW, NVM

(ISHARE_CONFIG)

ISHARE warning: 50 mV

Fixed OVP channel A: 1.2 V

Fixed OVP channel B: 1.6 V

Powerstage fault response: Ignore

Hiccup wait time: 25 ms

USER_DATA_11

8C 99 00 00 00 55 00

00 00 00h

(MFR_PROTECTION_CONFIG)

88 00 00 00 50 00 00

USER_DATA_13

BDh

IIN shunt: 0.5 mΩ (analog gain: 20, digital gain = 80)

00 00 00 00 00 00 00 RW, NVM

00h

(MFR_CALIBRATION_CONFIG)

MFR_SPECIFIC_CD

Pin 43: BTSEN

Pin 19: BVR_EN

CDh

CEh

CFh

D1h

D2h

D3h

D4h

D5h

D6h

D7h

Default Settings

RW, NVM

RW

(MULTIFUNCTION_PIN_CONFIG_1)

MFR_SPECIFIC_CE

Pin 44: ATSEN

(MULTIFUNCTION_PIN_CONFIG 2)

MFR_SPECIFIC_CF

On-the-fly SMB_ALERT# Mask bits for bits in STATUS_EXTENDED

Peak logging function for output voltage telemetry

Peak logging function for output current telemetry

Peak logging function for temperature telemetry

Ouptut voltage telemetry in SLINEAR11 format

Peak logging function for input voltage telemetry

Peak logging function for input current telemetry

Peak logging function for input power telemetry

00 00 00 00 00 00 00h

(SMBALERT_MASK_EXTENDED)

MFR_SPECIFIC_D1

Current

status

Current

status

RW

(READ_VOUT_MIN_MAX)

MFR_SPECIFIC_D2

Current

status

Current

status

RW

(READ_IOUT_MIN_MAX)

MFR_SPECIFIC_D3

Current

status

Current

status

RW

(READ_TEMPERATURE_MIN_MAX)

MFR_SPECIFIC_D4

(READ_MFR_VOUT)

Current

status

Current

status

R

MFR_SPECIFIC_D5

Current status

RW

(READ_VIN_MIN_MAX)

MFR_SPECIFIC_D6

READ_IIN_MIN_MAX

Current status

RW

MFR_SPECIFIC_D7

RW

(READ_PIN_MIN_MAX)

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Table 7-10. Supported Commands and NVM Defaults (continued)

Default

Hex⁽²⁾

Ch. A

Default

R/W

Access,

NVM

CMD

Default Behavior

Ch. A (PAGE = 0)

Default Behavior

Ch. B (PAGE = 1)

Command Name

Code

Hex⁽²⁾

Ch. B

MFR_SPECIFIC_D8

D8h

Current

status

Current

status

Peak logging function for ouptut power telemetry

Returns all telemetry data for the current channel

Returns all status information for the current channel

RW

(READ_POUT_MIN_MAX)

MFR_SPECIFIC_DA

Current

status

Current

status

DAh

R

(READ_ALL)

MFR_SPECIFIC_DB

DBh

Current

status

Current

status

R

(STATUS_ALL)

MFR_SPECIFIC_DC

DCh

Returns status information for phase-wise faults OCL and ISHARE

Returns status information for Manufacturer specific bits

Current status

R

(STATUS_PHASES)

MFR_SPECIFIC_DD

DDh

Current status

00 0Eh

(STATUS_EXTENDED)

MFR_SPECIFIC_E3

E3h

VR_FAULT# asserts only due to faults on channel A. OC and OT fault assert

VR_FAULT#

RW, NVM

(VR_FAULT_CONFIG)

MFR_SPECIFIC_E4

E4h

Closed loop frequency enabled for both channels

FCCM mode, both channels, PEC not required.

Pin detect enabled for ADDR_CONFIG and VBOOT_CHA

00 12 0A 0A 00 00h

10 00 00 60 00h

13h

(SYNC_CONFIG)

MFR_SPECIFIC_ED

EDh

RW, NVM

R

(MISC_OPTIONS)

MFR_SPECIFIC_EE

EEh

(PIN_DETECT_OVERRIDE)

MFR_SPECIFIC_EF

EFh

00h

(SLAVE_ADDRESS)

Given by pin-detection by default

MFR_SPECIFIC_F0

F0h

CRC of NVM data bytes

Index = 0 (auto-incrementing)

Raw NVM data bytes

Curren status

Default Settings

00 00h

(NVM_CHECKSUM)

MFR_SPECIFIC_F5

F5h

RW

(USER_NVM_INDEX)

MFR_SPECIFIC_F6

F6h

RW, NVM

(USER_NVM_EXECUTE)

MFR_SPECIFIC_FA

FAh

NVM unlocked

(NVM_LOCK)

MFR_SPECIFIC_FB

FBh

No command groups write protected

00 00h

(MFR_WRITE_PROTECT)

(1) Tracking OV, UV offset value only is stored in NVM. Hex value is calculated based on VOUT_COMMAND in the ULINEAR16 format.

By default VOUT_COMMAND is restored based on pin detection, so the hex value of these commands differ from this table based on

the VBOOT_CHA pinstrap detection results.

(2) Block commands are documented LSB ... MSB, as displayed in Fusion Digital Power Designer.

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7.9.5 PMBus Command Descriptions

7.9.5.1 (00h) PAGE

Address:

00h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Paged / Phased:

Reset Value:

FFh

Updates Allowed:

Supported Values:

On-the-fly

00h: Channel A

01h: Channel B

FFh: Both channels

Description:

Selects which channel future PMBus commands address, in multi-channel devices.

7.9.5.2 (01h) OPERATION

Address:

01h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

00h

Updates Allowed:

Supported Values:

On-the-fly

00h: Immediate Off, Margin None

40h: Soft-Off, Margin None

80h: On, Margin None

98h: On, Margin Low, Act on Faults

A8h: On, Margin High, Act on Faults

94h: On, Margin Low, Ignore Faults

A4h: On, Margin High, Ignore Faults

Other possible values not shown. See the Technical Reference Manual

Description:

The OPERATION command is used to enable or disable power conversion, in conjunction input from the enable pins, according to the configuration

of the ON_OFF_CONFIG command.

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7.9.5.3 (02h) ON_OFF_CONFIG

Address:

02h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

03h: Always converting when power is present

16h: VR_EN pin only, Active High, Soft-Off

17h: VR_EN pin only, Active High, Immediate Off

1Bh: OPERATION command only

Other possible values not shown. See the Technical Reference Manual

Description:

The ON_OFF_CONFIG command configures the combination of enable pin input and serial bus commands needed to enable/disable power

conversion.

7.9.5.4 (03h) CLEAR_FAULTS

Address:

03h

Transaction Type:

Data Format:

Send Byte

Data-less

Yes / No

N/A

Paged / Phased:

Reset Value:

Updates Allowed:

Supported Values:

Description:

On-the-fly

N/A

CLEAR_FAULTS is used to clear any fault bits that have been set. This command simultaneously clears all bits in all status registers in the

selected PAGE. At the same time, the device releases its SMB_ALERT# signal output, if SMB_ALERT# is asserted. CLEAR_FAULTS is a write-only

command with no data.

7.9.5.5 (04h) PHASE

Address:

04h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

FFh

Updates Allowed:

Supported Values:

On-the-fly

FFh: Address all phases in the current PAGE

00h to 0Bh: Address individual phases. For example, 00h addresses Phase 1 (Order 0), and so on.

Description:

Selects which phase future PMBus commands address within the active PAGE.

7.9.5.6 (05h) PAGE_PLUS_WRITE

Address:

05h

Transaction Type:

Data Format:

Block Write

Unsigned Binary (variable block length)

Paged / Phased:

Reset Value:

No

N/A

Updates Allowed:

Supported Values:

Description:

On-the-fly

Per command description.

Utility to send PAGE along with a PMBus command write. See the Technical Reference Manual for more information.

7.9.5.7 (06h) PAGE_PLUS_READ

Address:

06h

Transaction Type:

Data Format:

Block-Write-Block-Read Process Call

Unsigned Binary (variable block size)

Paged / Phased:

Reset Value:

No / No

N/A

Updates Allowed:

Supported Values:

Description:

On-the-fly

Per command description.

Utility to send a PAGE and a PMBus read in the same transaction. See the Technical Reference Manual for more information.

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7.9.5.8 (10h) WRITE_PROTECT

Address:

10h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Write protection disabled (all writeable commands are accessible)

20h: Disable writes to all commands except WRITE_PROTECT, OPERATION, PAGE, ON_OFF_CONFIG, and VOUT_COMMAND.

40h: Disable writes to all commands except WRITE_PROTECT, OPERATION and PAGE

80h: Disable writes to all commands except WRITE_PROTECT

Description:

The WRITE_PROTECT command controls which commands are writeable by the PMBus host.

7.9.5.9 (15h) STORE_USER_ALL

Address:

15h

Transaction Type:

Data Format:

Send Byte

Data-less

Paged / Phased:

Reset Value:

No / No

N/A

Updates Allowed:

Supported Values:

Description:

Not recommended for on-the-fly-use, but not explicitly blocked

N/A

The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the Operating Memory to the matching locations in the

non-volatile User Store memory.

7.9.5.10 (16h) RESTORE_USER_ALL

Address:

16h

Transaction Type:

Data Format:

Send Byte / N/A

Data-less

Paged / Phased:

Reset Value:

No / No

N/A

Updates Allowed:

Supported Values:

Description:

Blocked During Regulation

N/A

The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the non-volatile User Store memory to the matching

locations in the Operating Memory.

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7.9.5.11 (19h) CAPABILITY

Address:

19h

Transaction Type:

Data Format:

Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

D0h

Updates Allowed:

Supported Values:

Description:

N/A

D0h: PEC, 1MHz, SMB_ALERT, Supported, Linear format.

This command provides a way for the host to determine the capabilities of this PMBus device.

7.9.5.12 (1Bh) SMBALERT_MASK_WORD

Address:

1Bh (with CMD byte = 79h)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_WORD (upper byte of STATUS_BYTE) command.

7.9.5.13 (1Bh) SMBALERT_MASK_VOUT

Address:

1Bh (with CMD byte = 7Ah)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_VOUT command.

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7.9.5.14 (1Bh) SMBALERT_MASK_IOUT

Address:

1Bh (with CMD byte = 7Bh)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_IOUT command.

7.9.5.15 (1Bh) SMBALERT_MASK_INPUT

Address:

1Bh (with CMD byte = 7Ch)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_INPUT command.

7.9.5.16 (1Bh) SMBALERT_MASK_TEMPERATURE

Address:

1Bh (with CMD byte = 7Dh)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_TEMPERATURE command.

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7.9.5.17 (1Bh) SMBALERT_MASK_CML

Address:

1Bh (with CMD byte = 7Eh)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_CML command.

7.9.5.18 (1Bh) SMBALERT_MASK_MFR

Address:

1Bh (with CMD byte = 80h)

Transaction Type:

Data Format:

Write Word / Block-Write-Block-Read Process Call

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

One mask bit for each supported status bit

SMBALERT_MASK bits for the STATUS_MFR command.

7.9.5.19 (20h) VOUT_MODE

Address:

20h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

Blocked during regulation

16h: Linear Mode, Absolute, Exponent = -10

Specifies the data format for all output voltage related commands.

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7.9.5.20 (21h) VOUT_COMMAND

Address:

21h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Channel A: NVM or Pinstrap depending on the setting of PIN_DETECT_OVERRIDE for VBOOT_CHA

Channel B: NVM only.

Updates Allowed:

Supported Values:

on-the-fly

0.000 to 1.87 V, VOUT_MAX ≤ 1.870 V

0.000 to 3.740 V, 1.870 < VOUT_MAX ≤ 3.740 V

0.000 to 5.500 V, VOUT_MAX > 3.74 V

LSB = 2^Nper VOUT_MODE

Description:

Updates the output voltage target for the controller when the OPERATION command is set to "Margin None."

7.9.5.21 (22h) VOUT_TRIM

Address:

22h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR16 (N = -10)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

on-the-fly

-125 mV to +124 mV

LSB = 2^Nper VOUT_MODE

Description:

Used to apply a fixed offset voltage to the output voltage command value.

7.9.5.22 (24h) VOUT_MAX

Address:

24h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

NVM

If VBOOT pinstrapping is used, VOUT_MAX is initialized to 1.87 V, or 5.5 V based on the selected option.

Updates Allowed:

Supported Values:

On-the-fly

0.000 V to 5.500 V

LSB = 2^Nper VOUT_MODE

Description:

Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations.

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7.9.5.23 (25h) VOUT_MARGIN_HIGH

Address:

25h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

0.000 V

Updates Allowed:

Supported Values:

On-the-fly

Same as VOUT_COMMAND.

LSB = 2^Nper VOUT_MODE

Description:

Loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to "Margin High."

7.9.5.24 (26h) VOUT_MARGIN_LOW

Address:

26h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

0.000 V

Updates Allowed:

Supported Values:

On-the-fly

Same as VOUT_COMMAND.

LSB = 2^Nper VOUT_MODE

Description:

Loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to "Margin Low."

7.9.5.25 (27h) VOUT_TRANSITION_RATE

Address:

27h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -4)

Yes / No

Paged / Phased:

Reset Value:

Yes

Updates Allowed:

Supported Values:

On-the-fly

0.3125 to 40 mV/μs

See the Technical Reference Manual for all supported values.

Description:

Sets the slew rate at which any output voltage changes during normal power conversion occur.

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7.9.5.26 (28h) VOUT_DROOP

Address:

28h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -7)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

0.0 to 1.0 mΩ with 7.8125 μΩ resolution

1.0 to 2.0 mΩ with 15.625 μΩ resolution

2.0 to 4.0 mΩ with 31.25 μΩ resolution

4.0 to 8.0 mΩ with 62.50 μΩ resolution

Description:

Sets the rate, in mV/A (mΩ) at which the output voltage decreases with increasing output current for use with adaptive voltage positioning. Also

referred to as the DC Load Line (DCLL).

7.9.5.27 (29h) VOUT_SCALE_LOOP

Address:

29h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -3)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

Blocked during regulation

1.000

0.500 (Recommended for output voltages greater than 3.74 V)

Description:

Sets the scaling factor between the output voltage and the input voltage to the controller VSP, VSN pins.

7.9.5.28 (2Bh) VOUT_MIN

Address:

2Bh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

NVM

Initialized to 0.00 V when VBOOT pinstrap is used.

Updates Allowed:

Supported Values:

On-the-fly

0.000 to 5.500 V

LSB = 2^Nper VOUT_MODE

Description:

Sets a lower limit on the output voltage the unit can command regardless of any other commands or combinations.

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7.9.5.29 (33h) FREQUENCY_SWITCH

Address:

33h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

300 to 2000 kHz, 50 kHz steps to 1800 kHz, 100 kHz steps after.

Sets the per-phase switching frequency for the controller.

7.9.5.30 (34h) POWER_MODE

Address:

34h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / No

00h or 03h depending if dynamic phase shedding is enabled

On-the-fly

Updates Allowed:

Supported Values:

00h: DPS enabled, Auto-DCM allowed on all phases

03h: DPS disabled, all phases FCCM

04h: DPS enabled, Auto-DCM allowd in 1 phase mode only

Description:

Change the power stage of the converter on-the-fly.

7.9.5.31 (35h) VIN_ON

Address:

35h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.25 to 11.50 V, in 0.25 V steps

Sets the value of the input voltage, in Volts, at which the unit starts power conversion.

7.9.5.32 (38h) IOUT_CAL_GAIN

Address:

38h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -7)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.500 to 5.493 mΩ in 7.8125 μΩ steps

Sets the ratio of the voltage at the current sense pins to the sensed current for the READ_IOUT command in miliohms.

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7.9.5.33 (39h) IOUT_CAL_OFFSET

Address:

39h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -3)

Paged / Phased:

Reset Value:

Yes / Yes

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

-4.000 to +3.750 A in 125 mA steps

Used to compensate for offset errors in the power stage for each individual phase, in amperes.

7.9.5.34 (40h) VOUT_OV_FAULT_LIMIT

Address:

40h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

(VOUT_COMMAND + 32 mV) to (VOUT_COMMAND + 448 mV) in 32 mV steps

LSB = 2^Nper VOUT_MODE

Description:

Sets the value of the tracking overvoltage fault limit. Refer to MFR_PROTECTION_CONFIG to set the fixed overvoltage fault limit.

7.9.5.35 (41h) VOUT_OV_FAULT_RESPONSE

Address:

41h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-Off immediately, require enable cycle to recover

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

Description:

Instructs the device on what action to take in response to an output overvoltage fault.

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7.9.5.36 (42h) VOUT_OV_WARN_LIMIT

Address:

42h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

(VOUT_COMMAND + 24 mV) to (VOUT_COMMAND + 448 mV) in 8 mV steps

LSB = 2^Nper VOUT_MODE

Description:

Sets the value of the output voltage at the sense or output pins that causes an output voltage high warning.

7.9.5.37 (43h) VOUT_UV_WARN_LIMIT

Address:

43h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

(VOUT_COMMAND - 24 mV) to (VOUT_COMMAND - 448 mV) in 8 mV steps

LSB = 2^Nper VOUT_MODE

Description:

Sets the value of the output voltage at the sense or output pins that causes an output voltage low warning.

7.9.5.38 (44h) VOUT_UV_FAULT_LIMIT

Address:

44h

Transaction Type:

Data Format:

Write Word / Read Word

ULINEAR16 per VOUT_MODE

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

(VOUT_COMMAND - 32 mV) to (VOUT_COMMAND - 448 mV) in 32 mV steps

LSB = 2^Nper VOUT_MODE

Description:

Sets the value of the tracking undervoltage fault limit.

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7.9.5.39 (45h) VOUT_UV_FAULT_RESPONSE

Address:

45h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-off immediately, require enable cycle to recover.

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

Other combinations are possible. See the Techinical Reference Manual.

Description:

Instructs the device on what action to take in response to an output undervoltage fault.

7.9.5.40 (46h) IOUT_OC_FAULT_LIMIT

Address:

46h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Yes / Yes

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

0 to 1023 A per-page OCP in 1 A steps

17 A to 130 A per-phase OCL (shared among all phases) in 3 A steps to 80 A, 5 A steps after

Description:

Sets the total page overcurrent protection threshold in amperes when written with PHASE = FFh.

Sets the per-phase overcurrent limit in amperes when written with PHASE ≠ FFh

7.9.5.41 (47h) IOUT_OC_FAULT_RESPONSE

Address:

47h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

C0h: Latch-off immediately, require enable cycle to recover.

F8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

Description:

Instructs the device on what action to take in response to an output overcurrent fault.

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7.9.5.42 (4Ah) IOUT_OC_WARN_LIMIT

Address:

4Ah

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0 to 1023 A in 1 A steps

Sets the value of the output current, in amperes, that causes the over-current detector to indicate an over-current warning condition.

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7.9.5.43 (4Fh) OT_FAULT_LIMIT

Address:

4Fh

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

90°C to 160°C in 10°C steps

Sets the value of the temperature limit, in degrees Celsius, that causes an over-temperature fault condition.

7.9.5.44 (50h) OT_FAULT_RESPONSE

Address:

50h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-off immediately, require enable cycle to recover

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

F8h: Hysteresis. Shutdown immediately and restart when the temperature falls.

Description:

Instructs the device on what action to take in response to an Over temperature Fault.

7.9.5.45 (51h) OT_WARN_LIMIT

Address:

51h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

90°C to 160°C in 10°C steps

Sets the value of the temperature limit, in degrees Celsius, that causes an over-temperature warning.

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7.9.5.46 (55h) VIN_OV_FAULT_LIMIT

Address:

55h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0.00 to 19.00 V in 1.0 V steps

Sets the value, in Volts, of the input voltage that causes an input overvoltage fault.

7.9.5.47 (56h) VIN_OV_FAULT_RESPONSE

Address:

56h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-off immediately, require enable cycle to recover

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

Description:

Instructs the device on what action to take in response to an input overvoltage fault.

7.9.5.48 (57h) VIN_OV_WARN_LIMIT

Address:

57h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0.00 to 19.00 V in 1.0 V steps

Sets the value, in Volts, of the input voltage that causes an input overvoltage warning.

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7.9.5.49 (58h) VIN_UV_WARN_LIMIT

Address:

58h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.00 to 11.25 V in 0.25 V steps

Sets the value, in Volts, of the input voltage that causes an input undervoltage warning.

7.9.5.50 (59h) VIN_UV_FAULT_LIMIT

Address:

59h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.00 to 11.25 V in 0.25 V steps

Sets the value, in Volts, of the input voltage that causes an input undervoltage fault.

7.9.5.51 (5Ah) VIN_UV_FAULT_RESPONSE

Address:

5Ah

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-off immediately, require enable cycle to recover

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time.

Description:

Instructs the device on what action to take in response to an input under-voltage fault.

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7.9.5.52 (5Bh) IIN_OC_FAULT_LIMIT

Address:

5Bh

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = 0)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.0 to 128.0 A in 4 A steps

Sets the value of the input current, in Amperes, that causes an Input Overcurrent Fault.

7.9.5.53 (5Ch) IIN_OC_FAULT_RESPONSE

Address:

5Ch

Transaction Type:

Data Format:

Write Word / Read Word

Unsigned Binary (1 byte)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

C0h: Latch-off immediately, require enable cycle to recover

F8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time

Description:

Instructs the device on what action to take in response to an input overcurrent fault.

7.9.5.54 (5Dh) IIN_OC_WARN_LIMIT

Address:

5Dh

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11(N = 0)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

4.0 to 128.0 A in 4 A steps

Sets the value of the input current, in Amperes, that causes an Input Overcurrent warning.

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7.9.5.55 (60h) TON_DELAY

Address:

60h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -1)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0.0 to 127.5 ms in 0.5 ms steps

Sets the time, in milliseconds, from when a start condition is received (as programmed by the ON_OFF_CONFIG command) until the output voltage

starts to rise.

7.9.5.56 (61h) TON_RISE

Address:

61h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

0.00 to 31.75 ms in 0.25 ms steps

This value used to calculate slew rate during boot only. Supported slew rates follow those of VOUT_TRANSITION_RATE.

Description:

Sets the desired rise time of the output voltage, which allows the device to calculate the slew rate setting during bootup.

7.9.5.57 (62h) TON_MAX_FAULT_LIMIT

Address:

62h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

0.00 ms: function disabled.

0.00 to 31.75 ms in 0.25 ms steps

Description:

Sets an upper limit, in milliseconds, on how long the unit can attempt to power up the output without reaching the undervoltage fault limit (including

droop).

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7.9.5.58 (63h) TON_MAX_FAULT_RESPONSE

Address:

63h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

00h: Ignore

80h: Latch-off immediately, require enable cycle to recover

B8h: Hiccup immediately, infinite retrials, shutdown and restart after wait time

Description:

Instructs the device on what action to take in response to TON_MAX fault.

7.9.5.59 (64h) TOFF_DELAY

Address:

64h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -1)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0.0 to 127.5 ms in 0.5 ms steps

Sets the time, in milliseconds, from when a stop condition is received (as programmed by the ON_OFF_CONFIG command) until the unit stops

transferring energy to the output.

7.9.5.60 (65h) TOFF_FALL

Address:

65h

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = -2)

Yes / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

0.00 to 31.75 ms in 0.25 ms steps

This value used to calculate slew rate during soft-off only. Supported slew rates follow those of VOUT_TRANSITION_RATE.

Description:

Sets the desired fall time of the output voltage, which allows the device to calculate the slew rate setting during soft-off.

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7.9.5.61 (6Bh) PIN_OP_WARN_LIMIT

Address:

6Bh

Transaction Type:

Data Format:

Write Word / Read Word

SLINEAR11 (N = +1)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-fly

8.0 to 2048 W

Non-uniform step size. See the Technical Reference Manual.

Description:

Sets the value of the input power, in watts, that causes a warning that the input power is high.

7.9.5.62 (78h) STATUS_BYTE

Address:

78h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

BUSY, OFF, VOUT_OV, IOUT_OC, VIN_UV, TEMP CML, OTHER

Returns one byte of information with a summary of the most critical faults.

7.9.5.63 (79h) STATUS_WORD

Address:

79h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Word / Read Word

Unsigned Binary (2 bytes)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

VOUT, IOUT, INPUT, MFR, PGOOD, plus the STATUS_BYTE

Returns two bytes of information with a summary of the most critical faults.

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7.9.5.64 (7Ah) STATUS_VOUT

Address:

7Ah

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

VOUT_OVF, VOUT_OVW, VOUT_UVW, VOUT_UVF, VOUT_MINMAX, TON_MAX

Returns one data byte with information about output voltage related faults and warnings.

7.9.5.65 (7Bh) STATUS_IOUT

Address:

7Bh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

IOUT_OCF, IOUT_OCW, CUR_SHAREF

Returns one data byte with information about output current related faults and warnings.

7.9.5.66 (7Ch) STATUS_INPUT

Address:

7Ch

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

VIN_OVF, VIN_OVW, VIN_UVW, VIN_UVF, LOW_VIN, IIN_OCF, IIN_OCW, PIN_OPW

Returns one data byte with information about input voltage/current related faults and warnings.

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7.9.5.67 (7Dh) STATUS_TEMPERATURE

Address:

7Dh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

OTF, OTW

Returns one data byte with information about temperature related faults and warnings.

7.9.5.68 (7Eh) STATUS_CML

Address:

7Eh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

IVC, IVD, PEC, MEM, COMM, CML_OTHER

Returns one data byte with information about communication related warnings.

7.9.5.69 (7Fh) STATUS_OTHER

Address:

7Eh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

No / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

FIRST_TO_ALERT

Returns one data byte with information about warnings not defined in the other standard status registers.

7.9.5.70 (80h) STATUS_MFR_SPECIFIC

Address:

80h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Yes / No

Current Status

Updates Allowed:

Supported Bits:

Description:

On-the-fly

POR, EXT, PSFLT

Returns one data byte with information about manufacturer-defined warnings and faults.

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7.9.5.71 (88h) READ_VIN

Address:

88h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Update Rate:

Supported Range:

Description:

150 μs update / 300 μs time filtering

0.000 V to 18.700 V

Returns the sensed input voltage in volts.

7.9.5.72 (89h) READ_IIN

Address:

89h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Update Rate:

Supported Range:

16 μs update / 120 μs time filtering

-5.0 to 100.0 A

(V_CSPIN-V_{VIN_CSN})× G_IINSHUNT= 800 mV max

Description:

Returns the sensed input current in amperes.

7.9.5.73 (8Bh) READ_VOUT

Address:

8Bh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

ULINEAR16

Yes / No

Current Status

Update Rate:

Supported Range:

200 μs update / 250 μs time filtering

0.00 to 3.74 V (VOUT_SCALE_LOOP = 1.0)

0.00 to 6.00 V (VOUT_SCALE_LOOP = 0.5)

Description:

Returns the sensed output voltage in volts.

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7.9.5.74 (8Ch) READ_IOUT

Address:

8Ch

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / Yes

Current Status

Update Rate:

Supported Range:

16 μs update / 80 μs time filtering

Per Channel:

(-10.0 to +70.0 A) × N_phases× (5.0 mΩ / IOUT_CAL_GAIN) + Σ(IOUT_CAL_OFFSET)_Phases

Per Phase:

(-10.0 to +70.0 A) × (5.0 mΩ / IOUT_CAL_GAIN) + (IOUT_CAL_OFFSET)_Phases

Description:

Returns the sensed output current in amperes.

Can be calibrated by IOUT_CAL_GAIN and IOUT_CAL_OFFSET.

Read with PHASE = FFh to read total page current.

Read with PHASE = 00h to read first phase (order 0) current, and so on.

7.9.5.75 (8Dh) READ_TEMPERATURE_1

Address:

8Dh

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Update Rate:

Supported Range:

Description:

TBD

-40.0°C to 150.0°C

Returns the sensed power stage temperature in degrees Celsius.

7.9.5.76 (96h) READ_POUT

Address:

96h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Update Rate:

Supported Range:

Description:

Per READ_VOUT and READ_IOUT

Returns the sensed output power in Watts.

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7.9.5.77 (97h) READ_PIN

Address:

97h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Update Rate:

Supported Range:

Description:

Per READ_VIN and READ_IIN

Returns the sensed input power in Watts.

7.9.5.78 (98h) PMBUS_REVISION

Address:

98h

Transaction Type:

Data Format:

Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

33h

Updates Allowed:

Supported Values:

Description:

N/A

33h: PMBus 1.3, Part I and II

Reads the revision of the PMBus to which the device is compatible.

7.9.5.79 (99h) MFR_ID

Address:

99h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (3 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-Fly

000000h to FFFFFFh

Arbitrary NVM for user tracking purposes.

Description:

3 bytes of arbitrarily writeable non-volatile memory intended for manufacturer identification.

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7.9.5.80 (9Ah) MFR_MODEL

Address:

9Ah

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (3 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-Fly

000000h to FFFFFFh

Arbitrary NVM for user tracking purposes.

Description:

3 bytes of arbitrarily writeable non-volatile memory intended for model identification.

7.9.5.81 (9Bh) MFR_REVISION

Address:

9Bh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (3 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-Fly

000000h to FFFFFFh

Arbitrary NVM for user tracking purposes.

Description:

3 bytes of arbitrarily writeable non-volatile memory intended for revision identification.

7.9.5.82 (9Dh) MFR_DATE

Address:

9Dh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (3 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

On-the-Fly

000000h to FFFFFFh

Arbitrary NVM for user tracking purposes.

Description:

3 bytes of arbitrarily writeable non-volatile memory intended for date tracking.

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7.9.5.83 (ADh) IC_DEVICE_ID

Address:

ADh

Transaction Type:

Data Format:

Read Block

Unsigned Binary (6 bytes)

No / No

Paged / Phased:

Reset Value:

5449536C7000h

Updates Allowed:

Supported Values:

Description:

N/A

5449536C7000h (TPS536C7B1)

Returns the part number of the device.

7.9.5.84 (AEh) IC_DEVICE_REV

Address:

AEh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (2 bytes)

No / No

Paged / Phased:

Reset Value:

Current Device Revision

N/A

Updates Allowed:

Supported Values:

Description:

Set by TI during device manufacturing.

Returns device revision.

7.9.5.85 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)

Address:

B1h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (8 bytes)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

See the Technical Reference Manual for a complete register map.

Configures the control loop compensation parameters including AC load line, integration time constant, dynamic integration, compensating ramp, AC

gain, integration gain.

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7.9.5.86 (B2h) USER_DATA_02 (NONLINEAR_CONFIG)

Address:

B2h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (5 bytes)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

See the Technical Reference Manual for a complete register map.

Configures the nonlinear controller parameters including minimum on time, minimum off time, leading edge blanking time, USR and OSR thresholds.

7.9.5.87 (B3h) USER_DATA_03 (PHASE_CONFIG)

Address:

B3h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (24 bytes)

Paged / Phased:

Reset Value:

No / No

NVM or Pinstrap

Updates Allowed:

Supported Values:

Description:

Blocked during regulation.

See the Technical Reference Manual for a complete register map.

Configures phase assignments: Assign phases to channels, phase number, and firing position.

7.9.5.88 (B4h) USER_DATA_04 (DVID_CONFIG)

Address:

B4h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (6 bytes)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

See the Technical Reference Manual for a complete register map.

Configures DVID options including dynamic AC and DC load lines.

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7.9.5.89 (B7h) USER_DATA_07 (PHASE_SHED_CONFIG)

Address:

B7h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (13 bytes)

Paged / Phased:

Reset Value:

Yes / No

NVM

Updates Allowed:

Supported Values:

Description:

on-the-fly

See the Technical Reference Manual for a complete register map.

Configures phase add/drop functionality and thresholds.

7.9.5.90 (BAh) USER_DATA_10 (ISHARE_CONFIG)

Address:

BAh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

Yes / Yes

NVM

Updates Allowed:

Supported Values:

Description:

on-the-fly

See the Technical Reference Manual for a complete register map.

Configures the current sharing ratios for each phase for thermal balance management.

7.9.5.91 (BBh) USER_DATA_11 (MFR_PROTECTION_CONFIG)

Address:

BBh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (10 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

on-the-fly

See the Technical Reference Manual for a complete register map.

Configures manufacturer-specific fault features such as the fixed overvoltage protection, hiccup wait time, and current share warning.

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7.9.5.92 (BDh) USER_DATA_13 (MFR_CALIBRATION_CONFIG)

Address:

BDh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (15 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

on-the-fly

See the Technical Reference Manual for a complete register map.

Configures telemetry calibration features including input current sensing gain/offset.

7.9.5.93 (CDh) MFR_SPECIFIC_CD (MULTIFUNCTION_PIN_CONFIG_1)

Address:

CDh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (32 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly (takes effect only after power on).

Do not modify.

Device configuration bits which are set by TI during manufacturing. Do not change from default settings.

7.9.5.94 (CEh) MFR_SPECIFIC_CE (MULTIFUNCTION_PIN_CONFIG_2)

Address:

CEh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (31 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly (takes effect only after power on).

Do not modify.

Device configuration bits which are set by TI during manufacturing. Do not change from default settings.

7.9.5.95 (CFh) SMBALERT_MASK_EXTENDED

Address:

CFh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (7 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the technical reference manual.

SMBALERT MASK bits for STATUS_EXTENDED bits

7.9.5.96 (D1h) READ_VOUT_MIN_MAX

Address:

D1h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_VOUT.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum output voltage values logged since last reset.

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7.9.5.97 (D2h) READ_IOUT_MIN_MAX

Address:

D2h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_IOUT.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum output current values logged since last reset.

7.9.5.98 (D3h) READ_TEMPERATURE_MIN_MAX

Address:

D3h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_TEMPERATURE_1.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum temperature values logged since last reset.

7.9.5.99 (D4h) READ_MFR_VOUT

Address:

D4h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Read Word

SLINEAR11 (variable exponent)

Yes / No

Current Status

Per READ_VOUT.

Update Rate:

Supported Range:

0.00 to 3.74 V (VOUT_SCALE_LOOP = 1.0)

0.00 to 6.00 V (VOUT_SCALE_LOOP = 0.5)

Description:

Returns the sensed output voltage in volts.

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7.9.5.100 (D5h) READ_VIN_MIN_MAX

Address:

D5h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_VIN.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum input voltage values logged since last reset.

7.9.5.101 (D6h) READ_IIN_MIN_MAX

Address:

D6h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_IIN.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum input current values logged since last reset.

7.9.5.102 (D7h) READ_PIN_MIN_MAX

Address:

D7h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_PIN.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum input power values logged since last reset.

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7.9.5.103 (D8h) READ_POUT_MIN_MAX

Address:

D8h

Transaction Type:

Data Format:

Paged / Phased:

Reset Value:

Write Block / Read Block

SLINEAR11 (2 MSB for min, 2 LSB for max)

Yes / No

Current Status

Update Rate:

Logging Control:

Same as READ_POUT.

0000 0004h: Pause logging (min and max)

0000 0020h: Resume logging (min and max)

0000 0100h: Reset logs (min and max)

Description:

Returns maximum and minimum output power values logged since last reset.

7.9.5.104 (DAh) READ_ALL

Address:

DAh

Transaction Type:

Data Format:

Read Block

Unsigned Binary (14 bytes)

Paged / Phased:

Reset Value:

Yes / No

0d

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the technical reference manual.

Read all supported telemetry values in a single block to reduce bus utilization.

7.9.5.105 (DBh) STATUS_ALL

Address:

DBh

Transaction Type:

Data Format:

Read Block

Unsigned Binary (18 bytes)

Paged / Phased:

Reset Value:

Yes / No

0d

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the technical reference manual.

Read all supported status registers in a single block to reduce bus utilization.

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7.9.5.106 (DCh) STATUS_PHASES

Address:

DCh

Transaction Type:

Data Format:

Write Word / Read Word

Unsigned Binary (2 bytes)

Paged / Phased:

Reset Value:

Yes / Yes

0d

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the technical reference manual.

Identify which phases have experienced a phased fault.

7.9.5.107 (DDh) STATUS_EXTENDED

Address:

DDh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (7 bytes)

Paged / Phased:

Reset Value:

Yes / Yes

0d

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the technical reference manual.

Report non-standard status information which is not captured in STATUS_X registers or STATUS_PHASES.

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7.9.5.108 (E3h) MFR_SPECIFIC_E3 (VR_FAULT_CONFIG)

Address:

E3h

Transaction Type:

Data Format:

Write Word / Read Word

Unsigned Binary (2 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

on-the-fly

Bit 0: Set to 1b to assert VR_FAULT# for channels A and B, 0 channel A only otherwise

Bit 1: Set to 1b to assert VRFAULT# for overcurrent faults, 0 otherwise

Bit 2: Set to 1b to assert VRFAULT# for overtemperature faults, 0 otherwise

Description:

Configure the behavior of the VR_FAULT# pin.

7.9.5.109 (E4h) SYNC_CONFIG

Address:

E4h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (6 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

Description:

Blocked during regulation.

Refer to the technical reference manual.

Configure phase synchronization and frequency control.

7.9.5.110 (EDh) MFR_SPECIFIC_ED (MISC_OPTIONS)

Address:

EDh

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (5 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

on-the-fly

See the Technical Reference Manual for a complete register map.

Configure miscellaneous options.

7.9.5.111 (EEh) MFR_SPECIFIC_EE (PIN_DETECT_OVERRIDE)

Address:

EEh

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 byte)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

on-the-fly (pin detection occurs on POR only).

Set bit 0 to 0b to derive channel A VBOOT from NVM

Set bit 1 to 0b to derive PMBus address from NVM.

Set bit 4 to 0b to derive phase configuration from NVM.

Description:

Configure whether the device follows pinstrapping or NVM settings for the parameters associated with the VBOOT_CHA and ADDR_CONFIG pins.

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7.9.5.112 (EFh) MFR_SPECIFIC_EF (SLAVE_ADDRESS)

Address:

EFh

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 bytes)

No / No

Paged / Phased:

Reset Value:

NVM or Pinstrap

Updates Allowed:

Supported Values:

Description:

on-the-fly, only takes effect at power-on.

00h to 7Fh (7 bit address right justified)

Configure the PMBus slave address, when the PIN_DETECT_OVERRIDE command is configured to ignore the ADDR_CONFIG pinstrap detection.

7.9.5.113 (F0h) MFR_SPECIFIC_F0 (NVM_CHECKSUM)

Address:

F0h

Transaction Type:

Data Format:

Read Word

Unsigned Binary (2 bytes)

Paged / Phased:

Reset Value:

No / No

Current Status

Updates Allowed:

Supported Values:

Description:

Only following NVM Store/Restore Operations

0000h to FFFFh

CRC16 of the internal NVM array. This can be used to verify proper NVM programming.

7.9.5.114 (F5h) MFR_SPECIFIC_F5 (USER_NVM_INDEX)

Address:

F5h

Transaction Type:

Data Format:

Write Byte / Read Byte

Unsigned Binary (1 bytes)

Paged / Phased:

Reset Value:

No / No

00h

Updates Allowed:

Supported Values:

Description:

On-the-fly (Auto-increments with USER_NVM_EXECUTE access)

00h to 08h

Used for batch-loading of NVM data via PMBus.

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7.9.5.115 (F6h) MFR_SPECIFIC_F6 (USER_NVM_EXECUTE)

Address:

F6h

Transaction Type:

Data Format:

Write Block / Read Block

Unsigned Binary (32 bytes)

No / No

Paged / Phased:

Reset Value:

Current NVM status

On-the-fly

Updates Allowed:

Supported Values:

Description:

All NVM bytes

With USER_NVM_INDEX = 0, this command writes/returns 9 bytes of identifying information, plus the first 23 bytes of NVM data

With USER_NVM_INDEX = 1 to 7, this command writes/returns the next 32 bytes of NVM data

With USER_NVM_INDEX = 8, this command writes the last NVM data bytes, and automatically performs an NVM Store operation.

Each time this command is accessed, USER_NVM_INDEX increments automatically.

7.9.5.116 (FAh) NVM_LOCK

Address:

FAh

Transaction Type:

Data Format:

Write Word / Read Word (when locked, this command does not read back the password value).

Unsigned Binary (2 bytes)

No / No

Paged / Phased:

Reset Value:

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

0000-FFFEh

NVM password. Used to lock or unlock WRITE_PROTECT and MFR_WRITE_PROTECT commands, which in turn provide write protection.

7.9.5.117 (FBh) MFR_SPECIFIC_WRITE_PROTECT

Address:

FBh

Transaction Type:

Data Format:

Write Word / Read Word

Unsigned Binary (2 bytes)

Paged / Phased:

Reset Value:

No / No

NVM

Updates Allowed:

Supported Values:

Description:

On-the-fly

Refer to the Technical Reference Manual for a bit map

Provides additional resolution to WRITE_PROTECT, allowing different groups of commands to be write protected. Access to this command is

controlled by NVM_LOCK.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Typical Application

8.1.1 Application

The TPS536C7B1 is a fully PMbus 1.3.1 compliant step-down controller with dual channels. All programmable

parameters can be configured by PMBus and stored in NVM as the new default value to minimize external

component count.

This design uses a 0.88-V / 400-A, 1-V / 50-A design as an example. Use the following design procedure to

select key components.

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8.1.1.2 Design Requirements

The key requirements for this design are summarized below.

Table 8-1. Design Parameters

SYMBOL

PARAMETER

Channel A

Channel B

N_Φ

V_IN

Phase Number

10

2

Operating input voltage

Input current

10.8 V to 13.2 V

0 to 80 A

I_IN

V_BOOT

I_CC(max)

I_CC(TDC)

I_CC(STEP)

R_LL

Boot voltage

0.88 V

400 A

1.00 V

50 A

Maximum output current

Maximum Thermal DC current

Step transient current

DC Load Line

350 A

45 A

225 A

12 A

0.0 mΩ

1.25 ms

100°C

0.0 mΩ

1.25 ms

100°C

5 mV/μs

500 kHz

TON_RISE

TOFF_FALL

T_MAX

Output voltage rise time

Output voltage fall time

Maximum temperature

DVID slew rate

SR_FAST

f_SW

5 mV/μs

500 kHz

Switching frequency

PMBus address

PMB_ADDR

96d / C0h

8.1.1.3 Detailed Design Procedure

The following steps illustrate the key components selection for the 0.88V / 400A, 1V / 50A ASIC application.

Inductor Selection

Smaller inductance yields better transient performance, but leads to higher ripple current and lower efficiency.

Higher inductance has the opposite effect. It is common practice to limit the ripple current to between 20%-40%

of maximum per-phase current for balanced performance. In this design example, 30% of the maximum per-

phase current is used for channel A.

I

CC(MAX)

400A

ΔI

=

× 30% =

× 0.3 = 12.0 A

10phases

(48)

(49)

RIPPLE(target)

N

Φ

V

×( V

× ΔI

− V

OUT

in(max)

OUT

× f

SW

0.88V ×( 13.2V − 0.88V

L

=

= 0.137μH

13.2V × 12A × 500kHz

target

V

in(max)

RIPPLE(target)

Considering the variation and derating of the inductance and a standard inductor value of 150nH with DCR 0.125

mΩ, is selected. Then use Equation 41 to re-calculate the actual output ripple.

V

× V

− V

OUT

in(max)

× f × L

actual

0.88V ×( 13.2V − 0.88V

I

=

= 10.9A

13.2V × 500kHz × 0.150μH

(50)

RIPPLE(actual)

V

in(max)

SW

With same design procedure for channel B, a standard inductor value of 150 nH with DCR 0.125 mΩ from ITG is

chosen.

Output Capacitor Selection

Generally, consider output ripple and output voltage deviation during load transient when selecting output

capacitors.

When available, follow the output capacitance recommendation for the load ASIC reference design. With

TPS536C7B1 device, it is possible to meet the load transient with lower output capacitance due to the

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high-speed nature of DCAP+ control. Table 8-2 is the output capacitance recommendation for the above rail

specification.

Table 8-2. Output Capacitor Recommendations

Capacitor location

Bulk capacitors near power stages

Top side

Channel A

Channel B

24x 470 μF / 2.5V / 3mΩ ESR

4x 470 μF / 2.5V / 3mΩ ESR

24x 220 μF / 4V / X5R/ 1206

18x 100 μF / 4V / X5R / 1206

4x 220 μF / 4V / X5R / 1206

3x 100 μF / 4V / X5R / 1206

Bottom side

24x 220 μF / 4V / X5R / 1206

18x 100 μF / 4V / X5R / 1206

4x 220 μF / 4V / X5R / 1206

3x 100 μF / 4V / X5R / 1206

Total output capacitance

24.4 mF

1874 μF

Select Per-Phase Valley Current Limit

Equation 42 shows the calculation of per-phase valley current limit based on maximum processor current, the

operating phase number and per-phase current ripple ΔI_{RIPPLE(actual)}

.

For the channel A,

I

ΔI

CC(max)

RIPPLE

2

400A

10phases

10.9A

2

I

= K

×

margin

−

= 1.25 ×

−

= 44.5A

(51)

OCL

N

Φ

Where K_marginis the maximum operating margin factor. Choose 125% margin to avoid triggering current limit

during load transient events. For this design, choose the 47A valley current limit for channel A.

I

= I

+ ΔI

= 47A + 10.9A = 57.9A

(52)

SAT(min)

OCL

RIPPLE

Equation 43 indicates the minimum saturation current for inductor. Using same design procedure, the valley

current limit for channel B is selected to be 26 A.

Set USR threshold to improve load transient performance

There are two levels of undershoot reduction (USR1, USR2) options. USR1 enables up to 3, 4, 5 or all normal

phases and USR2 enables all available phases. To select the proper value, start with each USR threshold set to

be disabled, and then systematically lower the threshold, enabling fast-phase-addition to meet the load transient

requirement.

For this design, phase shedding is disabled. USR1 and USR2 are selected to be disabled for both channel A and

channel B.

Input Current Sensing (Shunt/ Calculated Iin/ Inductor DCR)

TPS536C7B1 has three input current sensing options: shunt current sensing, calculated input current sensing

and inductor DCR current sensing. Either option may be chosen for precision input current reporting.

Shunt current sensing

In this design, the external shunt resistor 0.5 mΩ ± 1%, 3 W, 4026 package is selected. Once properly

calibrated, Input current reporting is within the tolerance target.

Calculated input current sensing

TPS536C7B1 includes an option to impute input current for situations in which the addition of a shunt or

input inductor is prohibitive. Connect pins 46 (VIN_CSNIN) and 47 (CSPIN) together, and place a minimum

1 μF effective capacitance bypass cap from pin 46 to GND, then connect pin 46 to input supply (12 V

nominally) before input inductor. Configure the calculated input current option through the NVM settings in

MFR_SPECIFIC_ED (MISC OPTIONS).

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Inductor DCR Current Sensing

This section describes the procedure to determine an inductor DCR thermal compensation network design.

Figure 8-6 shows a typical DCR sensing circuit. From Equation 44 and Equation 45, when the time constant of

the RC network is equal to the L/R time constant of the inductor, the capacitor voltage V_Cacross the C_SENSE

capacitor can be used to obtain the inductor current. However, inductor windings have a positive temperature

coefficient of approximately 3900 ppm/°C. So an NTC thermistor is used to cancel thermal variation from the

inductor DCR.

The design goal is for the DCR value to be invariant with the temperature. Therefore, the voltage across sense

capacitor would be only dependent on the inductor current over the temperature range of interest.

L

R_DCR

Vin

Vout

C

R

Vc

Figure 1

L

I_IN

R_DCR

12Vin

12Vin to power stage

R_NTC

R_SERIES

R_SEQU

R_{P_N}

R_PAR

C_SENSE

Vc

I_{IN_CSP}

I_{IN_CSN}

Figure 2

Figure 8-6. Input DCR Network

L

C

I

× R

DCR

=

EQ

(53)

(54)

SENSE

R

DCR

× R

= V

IN

DCR

The equivalent resistance of the R_SEQU, R_NTC, R_SERIESand R_PARvalues is given by R_EQin Equation 46. Use

Equation 46, Equation 47 and Equation 48 to derive the values of R_SEQU, R_NTC, R_SERIESand R_PAR

.

R

P_N

R

=

s

(55)

(56)

EQ

R

+ R

P_N

SEQU

R

×( R

NTC

+ R

PAR

SERIES

R

=

P_N

R

PAR

NTC

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I

× R

P_N

IN

DCR

+ R

V = V

× R

=

= β × I

IN

(57)

C

DCR

EQ

R

P_N

SEQU

Finally the value of β, given in Equation 49 represents the effective current sense gain after thermal

compensation. This value can be used as the sense element resistance to derive the PMBus settings as

described in Input current calibration (measured).

R

× R

P_N

DCR

+ R

β =

(58)

R

P_N

SEQU

For this design, select thermistor RNTC as 1 kΩ, 5%, 0603, B-constant is 3650k, P/N: NCP18XQ102J03B from

Murata. Select C_SENSEas 1 μF X7R or better dielectric (C0G preferred).

In order to solve the value of R_SEQU, R_SERIESand R_PAR, the β at three temperature points are set equal. set β =

0.15 mΩ equally at temperature 0 °C, 25 °C and 75 °C. With the calculation, three resistors value can be found

as R_SEQU= 332 Ω, R_SERIES= 432 Ω, R_PAR= 1.40 kΩ.

Figure 8-7. Inductor DCR sensing voltage over temperature

TI offers an application note and excel spreadsheet to streamline input DCR netowrk calculations. Contact your

local field/sales representative to get a copy of the document.

Loop compensation design

•

5 mΩ: Typical gain from power stage current sense

ACLL: Programmable AC load line, provides direct output voltage feedback.

DCLL: Programmable DC load line, provides adaptive voltage positioning

K_DIV: Fixed scalar with value of 0.5

τ_INT: Programmable integration time constant, adjustable from 1µs to 16 µs (scale = 1 µs)

K_INT: Programmable integration gain which can be adjustable from 0.5x, 1x, 1.5x, 2x

K_AC: Programmable AC gain which is adjustable from 0.5x, 1x, 1.5x, 2x

V_RAMP: Programmable ramp voltage which is adjustable from 80 mV to 320 mV(scale = 40 mV)

For this design, the optimal loop compensation values were derived by tuning. The final valuea are listed .

Table 8-3.

PARAMETER

DCLL

ACLL

τ_INT

Channel A

0.0 mΩ

0.2 mΩ

1 µs

Channel B

0.0 mΩ

0.5 mΩ

7 µs

K_INT

2.0

1.0

K_AC

1.0

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Table 8-3. (continued)

PARAMETER

Channel A

Channel B

V_RAMP

320 mV

200 mV

Select ADDR_CONFIG pin resistors

Based on the design requirements of PMBus address select the upper and lower ADDR_CONFIG pin resistors,

R_HAand R_LAaccording to #none##none##none#.

Table 8-4.

Phase configuration

PMBus address

R_HA

R_LA

10+2

96d / C0h

110 kΩ

37.4 kΩ

Select the boot voltage V_BOOTfor each channel

The boot voltage for channel A is determined by pinstrapping on the VBOOT_CHA pin. Based on

#none##none##none##none#, select R_HB= 20.0 kΩ and R_LB= 59.0 kΩ to select 0.88 V as the channel A

boot voltage.

The boot voltage for channel B is stored in NVM. Update the NVM value for VOUT_COMMAND to 1.0 V , and

store the value to non-volatile memory.

8.1.1.4 Application Performance Plots

Figure 8-9. Shutdown (immediate off) channel A

Figure 8-8. Soft-start channel A (0 ms TON_DELAY)

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Figure 8-11. Steady-state ripple channel A

Figure 8-10. Soft-stop channel A (0 ms

TOFF_DELAY)

Figure 8-12. Steady-state PWM jitter channel A

Figure 8-13. Load step response channel A

Figure 8-15. DVID up transition channel A

Figure 8-14. Load release response channel A

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Figure 8-17. Closed loop bode plot channel A

Figure 8-16. DVID down transition channel A

Figure 8-18. Soft-start Channel B (0 ms

TON_DELAY)

Figure 8-19. Shutdown (immediate off) channel B

Figure 8-21. Steady-state ripple channel B

Figure 8-20. Soft-stop channel B (0 ms

TOFF_DELAY)

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Figure 8-22. Steady-state PWM jitter channel B

Figure 8-23. DVID transition up channel B

Figure 8-25. Closed loop bode plot channel B

Figure 8-24. DVID transition down channel B

Figure 8-26. RESET# pin function

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9 Power Supply Recommendations

The TPS536C7B1 does not have strict power sequencing requirements. The VCC supply, power stage VDD

5V supply, VIN_CSNIN and CSPIN supplies may be safely powered up independently of each other, even if

the VCC supply voltage is off and low-impedance. Do not raise pull-up voltages for open-drain pins AVR_RDY,

BVR_RDY, SMB_ALRT#, SMB_DIO, VR_FAULT# before the VCC supply, or pull them to voltages above the

VCC voltage during operation. If system sequencing requirements mandate raising the pull-up voltages for these

pins prior to VCC being established, limit the pin current to 1.0 mA to avoid damage to the device.

The minimum pull-up resistor value for open drain pins AVR_RDY, BVR_RDY, SMB_ALRT#, SMB_DIO,

VR_FAULT# is limited by the allowable sinking current for the pin. The maximum pull-up resistor value is limited

by the off-state leakage current for the pin, and the logic level of any downstream device using the pin as an

input. Table 9-1 summarizes the allowable sinking current and off-state leakage for open drain IO pins.

Table 9-1. Open Drain Pin Current Capability

Maximum Current

Open-drain Pin

On-state Sinking

(mA)

Off-state leakage1

(μA)

AVR_RDY

25.0

20.0

1.0

4.0

BVR_RDY

SMB_ALRT#

SMB_DIO

VR_FAULT#

1. T_J= 125°C

For input pins ACSPx, BCSPx, AVR_EN, BVR_EN, SYNC, RESET#, which exceed the VCC pin value during

operation, during power-on or otherwise, include a series resistor of 10.0 kΩ or greater to limit the current into

the pin.

It is safe to power-on the VDD 5V supply to TI smart power stage devices prior to TPS536C7B1 VCC. TI smart

power stage devices do not source any unsafe voltages or currents into TPS536C7B1 ACSPx, BCSPx, ATSEN,

BTSEN, APWMx, BPWMx pins when the VCC pin is not powered.

TI smart power stages (CSD95xxx) provide hysteresis current on their PWM input pins to improve noise

immunity. This current is active when the power stage is powered by 5V VDD and enabled, regardless of the

status of VCC. When the VCC pin of TPS536C7B1 is unpowered, this hysteresis current flows through the PWM

pins, to ESD structures in the controller, causing the PWM pin voltage to float low, out of the tri-state window.

This can cause the power stage device to switch its low-side power MOSFET on. As a result, in any case where

the power stage VDD 5V power supply is enabled prior to VCC, supply, TI recommends to control the power

stage enable pin to be low until both supply voltages are established.

TPS536C7B1 voltage and current protections become active when the controller VCC supply is powered. TI

recommends the VCC voltage be powered first, prior to power stage 5V, or VIN_CSNIN/CSPIN voltages. In

general, TI recommends to assert the AVR_EN/BVR_EN pins last in the power sequence.

Other sequences are permissible, but may not be able to make use of the controller protection features. For

example, if a board assembly issue causes the power input supply (e.g. nominally 12V supply) to charge the

output voltage, the TPS536C7B1 over-voltage protection can protect the load device by forcing the PWM pins

low, causing the power stage devices to discharge the output voltage, but only if the VCC supply is established

by the time the power input voltage rises.

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10 Layout

Proper layout techniques are critical to power supply performance. The recommendations given in this document

are meant to minimize risk and give the highest possibility of first pass success. Other layout designs are

possible but may carry higher risk of performance issues. Contact your TI local field/sales representative for

in-depth guidance and layout reviews.

The driverless controller architecture makes it easy to separate noisy driver interface lines from sensitive

controller signals. Because the power stage is external to the device, all gate drive and switch node traces must

be local to the inductor and power stages.

Controller Layout Guidelines

•

Keep minimum 800 mil distance between the controller and the closest power stage

Ensure the controller and all power stages must share a common ground plane

Route CSPx /VREF differentially from controller to IOUT/REFIN pin of each power stages on a quiet inner

layer. Alternately, create a small VREF copper plane between controller and power stages, and embed the

CSPx traces inside VREF plane.

•

PWMx must be routed on a different quiet inner layer and not on the same layer next to CSPx/VREF

differential pairs.

Note

MOST IMPORTANT LAYOUT RECOMMENDATION: Must keep min 40mil clearance between 12Vin

copper/vias/traces and sensitive analog interface lines.

Power stage layout guidelines

•

Use the recommended land and via pattern for power stage footprint

Make layer 2 on the PCB stack a solid ground plane

Maximize the phase pitch between adjacent phases whenever possible to prevent any cross-coupling noise

between devices (9 mm or higher is preferred)

•

In cases where the phase pitch is tighter, adjust the controller phase firing order to minimize noise coupling

between devices.

•

The input voltage bypass capacitors require a minimum two vias per pad(for both Vin and GND)

Place additional GND vias along the sides of device as space allows

For multi-phase systems, ensure that the GND pour connects all phases.

Connect the VOS pin feedback point to the inner edge of the inductor output pad.

Place VDD and PVDD bypass capacitors directly next to pins on the same layer of the device.

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Layout example

Figure 10-1. Controller layout example

Figure 10-2. CSP signal routing example

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Figure 10-3. Power stage placement example

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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11.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

W

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS536C7B1RSLR

TPS536C7B1RSLT

VQFN

RSL

48

3000

250

330.0

180.0

16.4

6.3

1.1

12.0

16.0

Q2

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

38.0

TPS536C7B1RSLR

TPS536C7B1RSLT

VQFN

RSL

48

367.0

210.0

367.0

185.0

35.0

Submit Document Feedback 147

PACKAGE OUTLINE

VQFN - 1 mm max height

RSL0048B

PLASTIC QUAD FLATPACK- NO LEAD

A

6.1

5.9

B

PIN 1 INDEX AREA

6.1

5.9

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

4.4

13

24

44X 0.4

12

23

SYMM

49

4.5

4.3

4.4

1

36

0.25

0.15

48X

PIN 1 IDENTIFICATION

(OPTIONAL)

37

48

0.1

C A B

C

SYMM

0.5

0.3

0.05

48X

4219205/A 02/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RSL0048B

PLASTIC QUAD FLATPACK- NO LEAD

(5.8)

(

4.4)

SYMM

48

37

48X (0.6)

48X (0.2)

1

36

44X (0.4)

SYMM

(5.8)

10X (1.12)

49

6X (0.83)

(R0.05) TYP

12

25

13

6X (0.83)

24

(Ø0.2) VIA

10X (1.12)

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.05 MAX

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219205/A 02/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RSL0048B

PLASTIC QUAD FLATPACK- NO LEAD

(5.8)

SYMM

48

37

48X (0.6)

48X (0.2)

1

49

36

44X (0.4)

16X

(

0.92)

SYMM

8X (0.56)

(5.8)

8X (1.12)

(R0.05) TYP

12

25

13

8X (1.12)

24

METAL TYP

8X (0.56)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

70% PRINTED COVERAGE BY AREA

SCALE: 12X

4219205/A 02/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS536C7B1RSLR
厂家：	TEXAS INSTRUMENTS
描述：	双通道 D-CAP+™、PMBus（N+M ≤ 12 相）降压多相 PWM 控制器 \| RSL \| 48 \| -40 to 125 控制器
文件：	总154页 (文件大小：6547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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