TPS53915RVET [TI]
具有 PMBus 的 1.5V 至 18V、12A 同步 SWIFT™ 降压转换器 | RVE | 28 | -40 to 85;
| 型号： | TPS53915RVET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 PMBus 的 1.5V 至 18V、12A 同步 SWIFT™ 降压转换器 | RVE | 28 | -40 to 85 输入元件 开关 转换器 |
| 文件： | 总52页 (文件大小：36329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS53915
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
TPS53915 具有 PMBus™ 接口的 1.5V 至 18V（4.5V 至 25V 偏置）输
入、12A 同步降压 SWIFT™ 转换器
1 特性
2 应用范围
1
•
集成的 13.8mΩ 和 5.9mΩ 金属氧化物半导体场效
应晶体管 (MOSFET) 支持 12A 连续输出电流
•
•
•
•
服务器和云计算负载点 (POL) 产品
宽带、网络互联及光纤通信基础设施
输入输出 (I/O) 电源
•
可通过 PMBus™SWIFT™
–
–
–
–
–
–
来调节：电压裕量和调节
软启动时间
在 WEBENCH™ 设计中心中提供支持
3 说明
加电延迟
TPS53915 是一款具有自适应接通时间 D-CAP3 控制
模式的小尺寸，同步降压转换器。此器件使空间受限电
源系统易于使用，并且外部组件数量较少。
VDD 欠压闭锁 (UVLO) 电平
故障报告
开关频率
•
•
•
•
支持所有陶瓷输出电容
该器件 特有 高性能集成 MOSFET、精度为 0.5% 的
0.6V 电压基准和一个集成的升压开关。具有竞争力的
特性 包括：极低外部组件数量、快速负载瞬态响应、
自动跳跃模式操作、内部软启动控制，并且无需补偿。
此外，该器件还 具备 可编程性和故障报告特性，这些
特性通过 PMBus™实现，以简化电源设计。
基准电压 600mV（耐受幅度 ±0.5%）
输出电压范围：0.6V 至 5.5V
D-CAP3™控制模式，此模式具有快速负载阶跃响
应
•
•
针对轻负载时高效率的自动跳跃 Eco-mode™模式
针对严格输出纹波和电压要求的强制连续传导模式
(FCCM)
强制持续传导模式有助于满足数字信号处理器 (DSP)
和现场可编程门阵列 (FPGA) 性能实现所要求的严格电
压调节精度。TPS53915 采用 28 引脚 QFN 封装，并
且在 -40°C 至 85°C 的环境温度范围内额定运行。
•
•
8 个介于
200kHz 至 1MHz 之间的可选频率设置
3.5mm × 4.5mm， 28 引脚，四方扁平无引线
(QFN) 封装
器件信息(1)
器件型号
TPS53915
封装
封装尺寸（标称值）
VQFN-CLIP (28)
4.50mm x 3.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
效率与输出电流间的关系
100
PGOOD
VIN
90
80
23
22
21
20
19
18
17
16
15
24 VO
PGND 14
PGND 13
PGND 12
PGND 11
PGND 10
25 TRIP
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-skip
26 ALERT
27 SDA
28 SCL
TPS53915
70
60
V
VOUT = 0.6 V
VOUT = 1 V
V= 1.2 V
VOUT= 1.5 V
OUT
V
OUT
= 1.8 V
V
= 2.5 V
OUT
V
= 3.3 V
V
= 5 V
OUT
OUT
1
2
3
4
5
6
7
8
9
0
2
4
6
8
10
12
VOUT
Output Current (A)
C003
Thermal
Pad
VREG EN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSAS9
TPS53915
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
www.ti.com.cn
目录
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 23
7.5 Programming........................................................... 24
Application and Implementation ........................ 35
8.1 Application Information............................................ 35
8.2 Typical Application .................................................. 35
Power Supply Recommendations...................... 40
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 9
6.7 Thermal Performance ............................................. 15
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagrams ..................................... 17
8
9
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 41
11 器件和文档支持 ..................................................... 42
11.1 文档支持................................................................ 42
11.2 商标....................................................................... 42
11.3 静电放电警告......................................................... 42
11.4 术语表 ................................................................... 42
12 机械、封装和可订购信息....................................... 42
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2013) to Revision B
Page
•
已添加 引脚配置和功能部分，处理额定值表，特性 描述 部分，器件功能模式，应用和实施部分，电源相关建议部
分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................................ 1
Changes from Original (November 2013) to Revision A
Page
•
已将器件尺寸从 3,5mm × 4,5mm 更改为 3.5mm × 4.5mm .................................................................................................... 1
2
Copyright © 2013–2014, Texas Instruments Incorporated
TPS53915
www.ti.com.cn
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
5 Pin Configuration and Functions
28-PIN
QFN
(TOP VIEW)
28
27
26
25
24
1
2
3
4
5
6
7
8
9
23
22
21
20
19
18
17
16
15
ADDR
PGOOD
EN
FB
GND
MODE
VREG
VDD
NC
VBST
NC
TPS53915
SW
SW
VIN
SW
VIN
Thermal Pad
SW
VIN
10
11
12
13
14
Pin Functions(1)
PIN
I/O
DESCRIPTION
NAME
NO.
PMBus address configuration pin. Connect this pin into a resistor divider between VREG and GND to
program different address settings
ADDR
1
I
ALERT
EN
26
3
O
I
Alert output for the PMBus interface
The enable pin turns on the DC-DC switching converter.
VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND.
FB
23
I
This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane
with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the
thermal pad to PGND pins and PGND plane).
GND
22
G
The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also
selects the ramp coefficient of D-CAP3 mode.
MODE
NC
21
I
5
—
Not connected. These pins are floating internally.
18
10
11
12
13
14
PGND
G
These ground pins are connected to the return of the internal low-side MOSFET.
Open-drain power-good status signal which provides startup delay after the FB voltage falls within the
specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs.
PGOOD
2
O
I
SCL
SDA
28
27
Clock input for the PMBus interface
I/O Data I/O for the PMBus interface
(1) I = Input, O = Output, P = Supply, G = Ground
Copyright © 2013–2014, Texas Instruments Incorporated
3
TPS53915
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
www.ti.com.cn
Pin Functions(1) (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
6
7
SW
I/O SW is the output switching terminal of the power converter. Connect this pin to the output inductor.
8
9
TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at TA = 25°C, 3000 ppm/°C current is
I/O sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for
detailed OCP setting.
TRIP
25
VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor
from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.
VBST
VDD
4
P
19
15
16
17
20
24
P
P
Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.
VIN is the conversion power-supply input pins.
VIN
VREG
VO
O
I
VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.
VOUT voltage input to the controller.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–3
MAX
7.7
30
32
36
6
UNIT
EN
DC
SW
Transient < 10 ns
–5
VBST
VBST(3)
–0.3
–0.3
Input voltage range(2)
V
VBST when transient < 10 ns
38
28
30
6
VDD
–0.3
–0.3
–0.3
–0.3
–0.3
–40
VIN
ADDR, FB, MODE, SDA, SCL, VO
PGOOD
7.7
6
Output voltage range
V
ALERT, TRIP, VREG
Junction Temperature, TJ
Storage Temperature, Tstg
150
150
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Voltage values are with respect to the SW terminal.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2013–2014, Texas Instruments Incorporated
TPS53915
www.ti.com.cn
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–0.1
–3
MAX
7
UNIT
EN
SW
27
28
5.5
25
18
5.5
7
VBST
VBST(1)
–0.1
–0.1
4.5
Input voltage range
V
VDD
VIN
1.5
ADDR, FB, MODE, SDA, SCL, VO
PGOOD
–0.1
–0.1
–0.1
–40
Output voltage range
TA
V
ALERT, TRIP, VREG
Operating free-air temperature
5.5
85
°C
(1) Voltage values are with respect to the SW pin.
6.4 Thermal Information
TPS53915
RVE
THERMAL METRIC(1)
UNIT
28 PINS
37.5
θJA
Junction-to-ambient thermal resistance(2)
θJCtop
θJB
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
34.1
18.1
°C/W
ψJT
1.8
ψJB
18.1
θJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
6.5 Electrical Characteristics
over operating free-air temperature range, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C, No load
Power conversion enabled (no switching)
IVDD
VDD bias current
1350
850
1850
µA
TA = 25°C, No load
Power conversion disabled
IVDDSTBY
VDD standby current
VIN leakage current
1150
0.5
µA
µA
IVIN(leak)
VEN = 0 V
VREF OUTPUT
VVREF
Reference voltage
FB w/r/t GND, TA = 25°C
597
–0.6%
–0.7%
600
603
0.5%
0.5%
mV
FB w/r/t GND, TJ = 0°C to 85°C
FB w/r/t GND, TJ = –40°C to 85°C
VVREFTOL
Reference voltage tolerance
版权 © 2013–2014, Texas Instruments Incorporated
5
TPS53915
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
www.ti.com.cn
MAX UNIT
Electrical Characteristics (接下页)
over operating free-air temperature range, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
OUTPUT VOLTAGE
TEST CONDITIONS
MIN
TYP
IFB
FB input current
VFB = 600 mV
50
12
100
15
nA
IVODIS
VO discharge current
VVO = 0.5 V, Power Conversion Disabled
10
mA
INTERNAL DAC REFERENCE
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
VDACTOL1
VDACTOL2
VDACTOL3
DAC voltage tolerance 1
certain VOUT_ADJUSTMENT settings
only
–4.8
–4.8
–4.8
4.8
4.8
4.8
mV
mV
mV
(1)
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
certain VOUT_MARGIN settings only
DAC voltage tolerance 2
DAC voltage tolerance 3
(2)
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
VOUT_ADJUSTMENT=0Dh and
VOUT_MARGIN=70h for 5%
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
VOUT_ADJUSTMENT=13h and
VOUT_MARGIN=07h for -5%
VDACTOL4
DAC voltage tolerance 4
–4.8
4.8
mV
SMPS FREQUENCY
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 000
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 001
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 010
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 011
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 100
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 101
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 110
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 111
TA = 25°C(3)
250
300
400
500
600
750
850
1000
60
fSW
VO switching frequency
kHz
tON(min)
Minimum on-time
Minimum off-time
ns
ns
tOFF(min)
TA = 25°C
175
240
310
INTERNAL BOOTSTRAP SW
VF
Forward Voltage
VVREG–VBST, TA = 25°C, IF = 10 mA
TA = 25°C, VVBST = 33 V, VSW = 28 V
0.15
0.01
0.25
1.5
V
IVBST
VBST leakage current
µA
LOGIC THRESHOLD
VENH
EN enable threshold voltage
1.3
1.1
1.4
1.2
0.22
0
1.5
1.3
V
V
VENL
EN disable threshold voltage
EN hysteresis voltage
VENHYST
VENLEAK
SOFT-START
V
EN input leakage current
–1
1
µA
SST <1:0> = 00
SST <1:0> = 01
SST <1:0> = 10
SST <1:0> = 11
1
2
4
8
tSS
Soft-start time
ms
POWERGOOD COMPARATOR
PGOOD in from higher
PGOOD in from lower
PGOOD out to higher
PGOOD out to lower
104%
89%
108%
92%
111%
96%
VPGTH
PGOOD threshold
113%
80%
116%
84%
120%
87%
(1) Tested at these VOUT_ADJUSTMENT settings: -9.0%, -8.25%, -5.25%, -2.25%, 0.0%, 3.00%, 6.00%, 9.0%
(2) Tested at these VOUT_MARGIN settings: -11.62%, -10.74%, -7.06%, -3.15%, 0%, 3.7%, 7.74%, 12.05%
(3) Specified by design. Not production tested.
6
版权 © 2013–2014, Texas Instruments Incorporated
TPS53915
www.ti.com.cn
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
Electrical Characteristics (接下页)
over operating free-air temperature range, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Delay for PGOOD going in
PGD<2:0>=000
165
256
320
614
μs
μs
Delay for PGOOD going in
PGD<2:0>=001
409
0.819
1.638
3.276
6.553
13.104
105
512
1.024
2.048
4.096
8.192
16.38
131
Delay for PGOOD going in
PGD<2:0>=010
1.228
2.458
4.915
9.83
ms
ms
ms
ms
ms
ms
Delay for PGOOD going in
PGD<2:0>=011
tPGDLY
PGOOD delay time
Delay for PGOOD going in
PGD<2:0>=100
Delay for PGOOD going in
PGD<2:0>=101
Delay for PGOOD going in
PGD<2:0>=110
19.656
157
Delay for PGOOD going in
PGD<2:0>=111
Delay tolerance for PGOOD coming out
VPGOOD = 0.5 V
2
6
0
µs
mA
µA
IPG
PGOOD sink current
4
IPGLK
PGOOD leakage current
VPGOOD = 5.0 V
–1
1
POWER-ON DELAY
Delay from enable to switching
POD<2:0>=000
356
612
µs
µs
Delay from enable to switching
POD<2:0>=001
Delay from enable to switching
POD<2:0>=010
1.124
2.148
4.196
8.292
16.48
32.86
ms
ms
ms
ms
ms
ms
Delay from enable to switching
POD<2:0>=011
tPODLY
Power-on delay time
Delay from enable to switching
POD<2:0>=100
Delay from enable to switching
POD<2:0>=101
Delay from enable to switching
POD<2:0>=110
Delay from enable to switching
POD<2:0>=111
CURRENT DETECTION
RTRIP
TRIP pin resistance range
20
10.1
7.2
70
13.9
11.0
–8.5
–6
kΩ
RTRIP = 52.3 kΩ
RTRIP = 38 kΩ
RTRIP = 52.3 kΩ
RTRIP = 38 kΩ
12.0
9.1
IOCL
Current limit threshold, valley
A
–15.3
–12
–11.9
–9
Negative current limit threshold,
valley
IOCLN
A
VZC
Zero cross detection offset
0
mV
PROTECTIONS
Wake-up
3.25
3.00
4.15
3.95
3.34
3.12
4.25
4.05
3.41
3.19
4.35
4.15
VREG undervoltage-lockout
(UVLO) threshold voltage
VVREGUVLO
V
V
Shutdown
Wake-up (default)
Shutdown
VVDDUVLO
VDD UVLO threshold voltage
Overvoltage-protection (OVP)
threshold voltage
VOVP
OVP detect voltage
116%
120%
300
124%
tOVPDLY
OVP propagation delay
With 100-mV overdrive
ns
版权 © 2013–2014, Texas Instruments Incorporated
7
TPS53915
ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
www.ti.com.cn
Electrical Characteristics (接下页)
over operating free-air temperature range, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
68%
1
MAX UNIT
Undervoltage-protection (UVP)
threshold voltage
VUVP
UVP detect voltage
64%
71%
ms
tUVPDLY
UVP delay
UVP filter delay
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
140
40
TSDN
Thermal shutdown threshold(3)
°C
LDO VOLTAGE
VREG
LDO output voltage
VIN = 12 V, ILOAD = 10 mA
VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
VIN = 12 V, TA = 25°C
4.65
170
5
5.45
365
V
VDOVREG
ILDOMAX
LDO low droop drop-out voltage
LDO over-current limit
mV
mA
200
INTERNAL MOSFETS
RDS(on)H High-side MOSFET on-resistance
RDS(on)L Low-side MOSFET on-resistance
TA = 25°C
TA = 25°C
13.8
5.9
15.5
7.0
mΩ
mΩ
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS
SCL and SDA low-level input
VIL-PMBUS
0°C ≤ TJ ≤ 85°C
0.8
V
voltage(3)
SCL and SDA high-level input
voltage(3)
SCL and SDA hysteresis voltage(3) 0°C ≤ TJ ≤ 85°C
VIH-PMBUS
VHY-PMBUS
0°C ≤ TJ ≤ 85°C
2.1
V
240
mV
PMBus SDA and ALERT OUTPUT PULLDOWN
SDA and ALERT low-level output
VDDPMBus = 5.5 V, RPULLUP = 1.1 kΩ,
0°C ≤ TJ ≤ 85°C
VOL1-PMBUS
voltage(3)
0.4
0.4
V
V
SDA and ALERT low-level output
VDDPMBus = 3.6 V, RPULLUP = 0.7 kΩ,
0°C ≤ TJ ≤ 85°C
VOL2-PMBUS
voltage(3)
8
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6.6 Typical Characteristics
100
100
90
90
80
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-skip
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = FCCM
70
60
70
VOUT = 0.6 V
VOUT = 1 V
VOUT= 1.5 V
VOUT = 0.6 V
VOUT = 1 V
VOUT= 1.5 V
V= 1.2 V
V= 1.2 V
OUT
OUT
V
OUT
= 1.8 V
V
= 2.5 V
V
OUT
= 1.8 V
V
= 2.5 V
OUT
OUT
V
= 3.3 V
V
= 5 V
V
= 3.3 V
V
= 5 V
OUT
OUT
OUT
OUT
60
0
0
0
2
4
6
8
10
12
0
0
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C003
C004
图 1. Efficiency vs. Output Current
图 2. Efficiency vs. Output Current
100
90
80
70
60
50
100
90
80
70
60
50
fSW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-Skip
fSW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = FCCM
VOUT = 0.6 V
VOUT = 0.6 V
= 1.2 V
VOUT = 1 V
VOUT = 1 V
V
V
V
= 1.2 V
V
V
V
= 1.5 V
= 2.5 V
= 5 V
V
V
V
V
V
V
= 1.5 V
= 2.5 V
= 5 V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 1.8 V
= 1.8 V
OUT
OUT
= 3.3 V
= 3.3 V
OUT
OUT
2
4
6
8
10
12
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C005
C006
图 3. Efficiency vs. Output Current
图 4. Efficiency vs. Output Current
1.3
1.25
1.2
1.3
1.25
1.2
fSW = 500 KHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
fSW = 1 MHz
VDD = 5 V
ëhÜÇ = 1.2 ë
TA = 25°C
LOUT = 1 ꢀH
Mode = Auto-skip
Mode = Auto-skip
1.15
1.1
1.15
1.1
VIN=5V
VIN=5V
VIN = 12 V
VIN = 12 V
VIN = 18 V
VIN = 18 V
2
4
6
8
10
12
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C007
C008
图 5. Output Voltage vs. Output Current
图 6. Output Voltage vs. Output Current
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Typical Characteristics (接下页)
1.3
1.3
1.25
1.2
fSW = 500 KHz
VDD = 5 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VOUT = 1.2 V
fSW = 1 MHz
VDD = 5 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
ëhÜÇ = 1.2 ë
1.25
1.2
1.15
1.1
1.15
1.1
VIN=5V
VIN=5V
VIN = 12 V
VIN = 12 V
VIN = 18 V
VIN = 18 V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C009
C010
图 7. Output Voltage vs. Output Current
图 8. Output Voltage vs. Output Current
1200
1000
800
600
550
500
450
400
fSW = 500 kHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VIN = 12 V, VDD = 5 V, TA = 25°C
LOUT = 1 ꢀH, Mode = FCCM, VOUT = 1.2 V
F
fSW = 250 KHz
fSW=500KHz
fSW=1MHz
600
VIN=5V
400
VIN = 12 V
VIN = 18 V
200
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
Output Current (A)
Output Current (A)
C011
C012
图 9. Switching Frequency vs. Output Current
图 10. Switching Frequency vs. Output Current
100
85
70
55
40
25
100
85
70
55
40
25
VIN = VDD = 18 V
VOUT = 1.2 V
fSW = 1 MHz
LOUT = 1 µH
VIN = VDD = 18 V
VOUT = 5 V
fSW = 1 MHz
LOUT = 1 µH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Output Current (A)
Output Current (A)
C001
C002
图 11. Safe Operating Area, VOUT = 1.2 V
图 12. Safe Operating Area, VOUT = 5 V
10
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Typical Characteristics (接下页)
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
FCCM
= 0 A
Mode
IOUT
=
=
图 13. Auto-Skip Steady-State Operation
图 14. FCCM Steady-State Operation
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0.1 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
FCCM
= 0.1 A
Mode
IOUT
=
=
图 15. Auto-Skip Steady-State Operation
图 16. FCCM Steady-State Operation
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 6 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
FCCM
= 6 A
Mode
IOUT
=
=
图 17. Auto-Skip Steady-State Operation
图 18. FCCM Steady-State Operation
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Typical Characteristics (接下页)
VIN
VOUT
Fsw
Mode = Auto-skip
Idyn 0 A to 6 A
=
12
V
VIN
VOUT
Fsw
Mode
Idyn
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
=
FCCM
=
= 0 A to 6 A
图 19. Auto-Skip Mode Load Transient
图 20. FCCM Mode Load Transient
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2
V
=
1 MHz
=
1
MHz
FCCM
0 A
Mode
IOUT
=
=
=
图 21. Start-Up
图 22. Start-Up
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 6 A
=
12
V
VIN
VOUT
Fsw
=
12
V
=
1.2
V
=
1.2 V
=
1 MHz
=
1
MHz
FCCM
6 A
Mode
IOUT
=
=
=
图 23. Start-Up
图 24. Start-Up
12
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Typical Characteristics (接下页)
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
FCCM
= 0 A
Mode
IOUT
=
=
图 25. Shutdown Operation
图 26. Shutdown Operation
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 6 A
=
12
V
VIN
VOUT
Fsw
=
12
=
V
=
1.2
V
1.2 V
=
1
MHz
=
1
MHz
FCCM
= 6 A
Mode
IOUT
=
=
图 27. Shutdown Operation
图 28. Shutdown Operation
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0 A
=
12
V
=
1.2
V
=
500 KHz
=
VIN
VOUT
Fsw
Mode = Auto-skip
IOUT 0 A
=
12
V
=
1.2
V
=
1 MHz
=
Pre-bias
= 0.6 V
图 30. Overvoltage Protection
图 29. Pre-Bias Operation
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Typical Characteristics (接下页)
VIN
VOUT
Fsw
Mode
=
12
=
V
1.2
V
=
500 MHz
FCCM
=
图 32. I2C READ (Address=31d, Cmd=0x79): ACK 0x10C8.
图 31. Overcurrent Protection
IOC = 15 A
图 33. 1 MHz to 250 KHz
图 34. 31d_FFh_FFh
图 35. VOUT(adj) = 6%, VOMH = 12% to 0%
图 36. VOUT(adj) = 9%, VOMH = 0% to 12%
14
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Typical Characteristics (接下页)
图 37. 250 kHz to MHz
6.7 Thermal Performance
fSW = 500 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 12 A, COUT = 10 × 22 µF (1206, 6.3V, X5R), RBOOT = 0 Ω, SNB = 3 Ω + 470 pF
Inductor: LOUT = 1 µH, PCMC135T-1R0MF, 12.6 mm × 13.8 mm × 5 mm, 2.1 mΩ (typ)
图 38. SP1: 75.6℃ (TPS53915), SP2: 57.7℃ (Inductor)
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7 Detailed Description
7.1 Overview
The TPS53915 is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-output
voltage point-of-load applications with 12-A or lower output current in computing and similar digital consumer
applications. The TPS53915 features proprietary D-CAP3 mode control combined with adaptive on-time
architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters
in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from
1.5 V to 18 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses emulated current
information to control the modulation. An advantage of this control scheme is that it does not require a phase-
compensation network outside which makes the device easy-to-use and also allows low-external component
count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output
voltage while increasing switching frequency as needed during load-step transient.
16
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7.2 Functional Block Diagrams
PGOOD
+
+
0.6 V + 8/16%
0.6 V œ 32%
+
UV
+
Delay
Delay
OV
0.6 V œ 8/16%
0.6 V+20%
VREG
Internal Ramp
Control Logic
UVP / OVP
Logic
0.6 V
SS
+
+
PWM
OCP
VBST
VIN
VFB
10 µA
GND
LL
+
+
One-
Shot
TRIP
SW
XCON
+
ZC
Control
Logic
PGND
PGND
VO
SW
FCCM / SKIP
RC time
Constant
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
Light load
OVP/UVP
FCCM/SKIP
Soft-Start
MODE
Fault
Shut Down
LDO
VREG
+
VREGOK
3.34 V /
3.12 V
EN
VDD
+
+
Enable
VDDOK
THOK
4.3 V /
4.03 V
1.4 V / 1.2 V
+
140°C /
100°C
ALERT
SDA
PMBus
Communication
Block
ADDR
SCL
TPS53915
7.3 Feature Description
7.3.1 Powergood
The TPS53915 has powergood output that indicates high when switcher output is within the target. The power-
good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of
the target value, internal comparators detect the power-good state and the power-good signal becomes high
after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal
becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up
externally.
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Feature Description (接下页)
7.3.2 D-CAP3 Control and Mode Selection
RR
SW
To comparator
CR
VOUT
图 39. Internal RAMP Generation Circuit
The TPS53915 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use
feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The
amplitude of the ramp is determined by the R-C time-constant as shown in 图 39. At different switching
frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.
The default switching frequency (fSW) is pre-set at 400 kHz. The switching frequency can be changed via PMBus
function (see 表 13).
7.3.3 D-CAP3 Mode
From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified
as shown in 图 40.
VO
SW
CC1
RC1
VIN
CC2
RC2
Sample
and Hold
DRVH
PWM
Comparator
Lx
RFBH
Control
Logic
and
G
+
+
VRAMP
VOUT
FB
DRVL
Driver
RCO
+
VREF
RLOAD
COUT
RFBL
图 40. D-CAP3 Mode
The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR
output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or
voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation
network is to emulate the ripple component of the inductor current information and then combine it with the
voltage feedback signal to regulate the loop operation. For any control topologies supporting no external
compensation design, there is a minimum and/or maximum range of the output filter it can support. The output
filter used with the TPS53513 is a lowpass L-C circuit. This L-C filter has double pole that is described in 公式 1.
1
f =
P
2´ p´ L
´ C
OUT
OUT
(1)
18
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Feature Description (接下页)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS53513. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per
decade and increases the phase to 90 degree one decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of 公式 1 is located
close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides
adequate phase margin for the stability requirement.
表 1. Locating the Zero
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
250 and 300
400 and 500
600 and 750
850 and 1000
6
7
9
12
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the
application). Use 表 1 to help locate the internal zero based on the selected switching frequency. In general,
where reasonable (or smaller) output capacitance is desired, 公式 2 can be used to determine the necessary
output capacitance for stable operation.
1
f =
= f
Z
P
2´ p´ L
´ C
OUT
OUT
(2)
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and
AC bias are 80% and 50% respectively. The effective derating is the product of these two factors, which in this
case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
表 2 shows the recommended output filter range for an application design with the following specifications:
•
•
•
Input voltage, VIN = 12 V
Switching frequency, fSW = 600 kHz
Output current, IOUT = 8 A
The minimum output capacitance is verified by the small signal measurement conducted on the EVM using the
following two criteria:
•
•
Loop crossover frequency is less than one-half the switching frequency (300 kHz)
Phase margin at the loop crossover is greater than 50 degrees
For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high
output capacitance for this type of converter design, then verify the small signal response on the EVM using the
following one criteria:
•
Phase margin at the loop crossover is greater than 50 degrees
As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher.
However, small signal measurement (bode plot) should be done to confirm the design.
Select a MODE pin configuration as shown in 表 3 to double the R-C time constant option for the maximum
output capacitance design and application. Select a MODE pin configuration to use single R-C time constant
option for the normal (or smaller) output capacitance design and application.
The MODE pin also selects SKIP-mode or FCCM-mode operation.
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表 2. Recommended Component Values
COUT(min) CROSS- PHASE COUT(max) INTERNAL
VOUT RLOWER RUPPER
LOUT
(µH)
INDUCTOR
ΔI/ICC(max)
ICC(max)
(A)
(µF)
OVER
(kHz)
MARGIN
(°)
(µF)
RC SETTING
(µs)
(V)
(kΩ)
(kΩ)
(1)
(1)
3 × 100
9 × 22
4 × 22
3 × 22
2 × 22
247
48
70
62
53
84
57
63
57
59
51
58
40
80
40
80
40
80
40
80
40
80
0.36
0.6
0
33%
PIMB065T-R36MS
30 x 100
30 x 100
30 x 100
30 x 100
30 x 100
207
25
0.68
1.2
2.5
3.3
5.5
10
33%
34%
33%
28%
PIMB065T-R68MS
185
11
1.2
10
31.6
45.3
82.5
8
PIMB065T-1R2MS
185
9
1.5
PIMB065T-1R5MS
185
7
2.2
PIMB065T-2R2MS
(1) All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V.
For higher output voltage at or above 2.0 V, additional phase boost might be required in order to secure sufficient
phase margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time
topology based operation.
A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at
loop crossover.
表 3. Mode Selection and Internal RAMP RC Time Constant
SWITCHING
FREQUENCIES
fSW (kHz)
MODE
SELECTION
RMODE
(kΩ)
R-C TIME
CONSTANT (µs)
ACTION
60
50
275
and
and
and
325
425
625
850
275
425
625
850
275
425
625
850
275
425
625
850
275
425
625
850
525
750
0
40
30
and 1000
Skip Mode
Pull down to GND
120
100
80
and
and
and
325
525
750
150
20
150
0
60
and 1000
60
and
and
and
325
525
750
50
40
30
and 1000
Connect to
PGOOD
FCCM(1)
120
100
80
and
and
and
325
525
750
60
and 1000
120
100
80
and
and
and
325
525
750
FCCM
Connect to VREG
60
and 1000
(1) Device goes into Forced CCM (FCCM) after PGOOD becomes high.
20
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7.3.4 Sample and Hold Circuitry
CSP
Sampled_CSP
Buffer 2
C1
C2
Buffer 1
图 41. Sample and Hold Circuitry (Patent Pending)
The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,
which is an advance control scheme to boost output voltage accuracy higher on the TPS53915, is one of
features of the TPS53915. The sample and hold circuitry generates a new DC voltage of CSN instead of the
voltage which is produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the
TPS53915 more competitive.
CSP
CSN
CSP
CSN
CSN_NEW
(sample at valley of CSP)
CSN_NEW
(sample at valley of CSP)
图 42. Continuous Conduction Mode (CCM) With Sample
图 43. Discontinuous Conduction Mode (DCM) With
and Hold Circuitry
Sample and Hold Circuitry
CSP
CSN
CSP
CSN
图 44. Continuous Conduction Mode (CCM) Without
图 45. Discontinuous Conduction Mode (DCM) Without
Sample and Hold Circuitry
Sample and Hold Circuitry
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1.25
1.23
1.21
1.25
1.23
1.21
1.19
1.17
1.15
VIN = 12 V
1.19
VIN = 12 V
VDD = 5 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 ꢀH
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 ꢀH
Mode = Auto-skip
1.17
D-CAP3
D-CAP2
D-CAP3
D-CAP2
Mode = FCCM
1.15
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
Output Current (A)
Output Current (A)
C013
C014
图 46. Output Voltage vs Output Current
图 47. Output Voltage vs Output Current
7.3.5 Adaptive Zero-Crossing
The TPS53915 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current
detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function
also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode
conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.
7.3.6 Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
amost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.
7.3.7 Current Sense and Overcurrent Protection
The TPS53915 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53915 supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 μA typically at room temperature, and
the trip level is set to the OCL trip voltage VTRIP as shown in 公式 3.
VTRIP = RTRIP ´ITRIP
where
•
•
•
VTRIP is in mV
RTRIP is in kΩ
ITRIP is in µA
(3)
公式 4 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be used);
in order to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used.
The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly
connected to the drain terminal of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to
compensate the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node.
Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side
MOSFET.)
Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus,
the load current at the overcurrent threshold, IOCP, is calculated as shown in 公式 4.
I
V
- V
´ V
(
)
OUT OUT
V
IN
V
V
TRIP
1
IND(ripple)
IN
TRIP
I
=
+
=
+
´
OCP
2
2´L ´ f
8´R
8´R
DS(on)L
SW
(
)
(
)
DS(on)
where
22
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•
•
RDS(on) is the on-resistance of the low-side MOSFET
RTRIP is in kΩ
(4)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold and
shuts down.
7.3.8 Overvoltage and Undervoltage Protection
The TPS53915 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, the TPS53915 latches OFF both high-side and low-side
MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS53915 operates in this cycle until the output voltage is
pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is
latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin.
7.3.9 Out-Of-Bounds Operation (OOB)
The TPS53915 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly towards the setpoint. During the operation, the cycle-by-
cycle negative current limit is also activated to ensure the safe operation of the internal FETs.
7.3.10 UVLO Protection
The TPS53915 monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold
voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold
voltage, the controller turns back on. UVLO is a non-latch protection.
7.3.11 Thermal Shutdown
The TPS53915 monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C),
TPS53915 shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns
on. Thermal shutdown is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-Mode Light-Load Operation
While the MODE pin is pulled to GND directly or through a 150-kΩ resistor, the TPS53915 device automatically
reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the
operation in detail.
As the output current decreases from heavy-load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so
that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation I O(LL) (for example: the threshold between
continuous- and discontinuous-conduction mode) is calculated as shown in 公式 5.
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
OUT LL
( )
2´L ´ f
SW
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Device Functional Modes (接下页)
where
•
f SW is the PWM switching frequency
(5)
TI recommends only using ceramic capacitors for Auto-skip mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.
7.5 Programming
7.5.1 The PMBus General Descriptions
The TPS53915 has seven internal custom user-accessible 8-bit registers. The PMBus interface has been
designed for program flexibility, supporting a direct format for write operation. Read operations are supported for
both combined format and stop separated format. While there is no auto increment/decrement capability in the
TPS53915 PMBus logic, a tight software loop can be designed to randomly access the next register, regardless
of which register was accessed first. The START and STOP commands frame the data packet and the REPEAT
START condition is allowed when necessary.
The device can operate in either standard mode (100 kb/s) or fast mode (400 kb/s).
7.5.2 PMBus Slave Address Selection
The seven-bit slave address is 001A3A2A1A0x, where A3A2A1A0 is set by the ADDR pin on the device. Bit 0 is the
data direction bit, i.e., 001A3A2A1A00 is used for write operation and 001A3A2A1A01 is used for read operation.
7.5.3 PMBus Address Selection
The TPS53915 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed
as 001. The address selection process is defined by the resistor divider ratio from VREG pin to ADDR pin, and
the address detection circuit starts to work only after VDD input supply has risen above its UVLO threshold. The
table below lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical
temperature coefficient of ±100 ppm/°C are recommended. Higher performance resistors can be used if tighter
noise margin is required for more reliable address detection, as shown in 表 4.
表 4. PMBus Address Selection Settings
RESISTOR DIVIDER RATIO (Ω)
(RHIGH) (kΩ)
HIGH-SIDE
RESISTOR
(RLOW) (kΩ)
LOW-SIDE
RESISTOR
PMBus ADDRESS
(RLOW/RLOW+RHIGH
)
MIN
MAX
0011111
0011110
0011101
0011100
0011011
0011010
0011001
0011000
0010111
0010110
0010101
0010100
0010011
0010010
> 0.557
1
300
165
154
143
120
110
105
88.7
71.5
60.4
47.5
36.0
27.0
18.7
0.5100
0.4625
0.4182
0.3772
0.3361
0.2985
0.2641
0.2298
0.1955
0.1611
0.1268
0.0960
0.0684
0.4958
04482
0.4073
0.3662
0.3249
0.2905
0.2560
0.2215
0.1870
0.1524
0.1179
0.0900
0.0622
0.5247
0.4772
0.4294
0.3886
0.3476
0.3067
0.2725
0.2385
0.2044
0.1703
0.1363
0.1024
0.0752
160
180
200
200
220
249
249
240
249
249
249
255
255
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表 4. PMBus Address Selection Settings (接下页)
RESISTOR DIVIDER RATIO (Ω)
(RHIGH) (kΩ)
HIGH-SIDE
RESISTOR
(RLOW) (kΩ)
LOW-SIDE
RESISTOR
PMBus ADDRESS
(RLOW/RLOW+RHIGH
)
MIN
MAX
0010001
0010000
0.0404
0.0340
0.0480
270
300
11.5
1
< 0.013
7.5.4 Supported Formats
The supported formats are described in this section.
7.5.4.1 Direct Format: Write
The simplest format for a PMBus write is direct format. After the START condition [S], the slave chip address is
sent, followed by an eighth bit indicating a write. The TPS53915 then acknowledges that it is being addressed,
and the master responds with an 8-bit register address byte. The slave acknowledges and the master sends the
appropriate 8-bit data byte. Again the slave acknowledges and the master terminates the transfer with the STOP
condition [P].
7.5.4.2 Combined Format: Read
After the START condition [S], the slave chip address is sent, followed by an eighth bit indicating a write. The
TPS53915 then acknowledges that it is being addressed, and the master responds with an 8-bit register address
byte. The slave acknowledges and the master sends the repeated START condition [Sr]. Again the slave chip
address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge followed by
previously addressed 8 bit data byte. The master then sends a non-acknowledge (NACK) and finally terminates
the transfer with the STOP condition [P].
7.5.4.3 Stop-Separated Reads
Stop-separated read features are also available. This format allows a master to initialize the register address
pointer for a read and return to that slave at a later time to read the data. In this format the slave chip address
followed by a write bit are sent after a START [S] condition. The TPS53915 then acknowledges it is being
addressed, and the master responds with the 8-bit register address byte. The master then sends a STOP or
RESTART condition and may then address another slave. After performing other tasks, the master can send a
START or RESTART condition to the device with a read command. The device acknowledges this request and
returns the data from the register location that had been set up previously.
7.5.5 Supported PMBus Commands
The TPS53915 supports the PMBus commands shown in 表 5 only. Not all features of each PMBus command
are supported. The CLEAR_FAULTS, STORE_DEFAULT_ALL and RESTORE_DEFAULT_ALL commands have
no data bytes. The non-volatile memory (NVM) cells inside the TPS53915 can permanently store some registers.
表 5. Supported PMBus Commands
COMMAND
NOTES
OPERATION
Turn on or turn off switching converter only
ON/OFF configuration
ON_OFF_CONFIG
CLEAR_FAULTS
WRITE_PROTECT
STORE_DEFAULT_ALL
RESTORE_DEFAULT_ALL
STATUS_WORD
CUSTOM_REG
Clear all latched status flags
Control writing to the PMBus device
Store contents of user-accessible registers to non-volatile memory cells
Copy contents of non-volatile memory cells to user-accessible registers
PMBus read-only status and flag bits
MFR_SPECIFIC_00 (Custom Register 0): Custom register
MFR_SPECIFIC_01 (Custom Register 1): Power on and power good delay times
DELAY_CONTROL
MODE_SOFT_START_CONFIG MFR_SPECIFIC_02 (Custom Register 2): Mode and soft-start time
FREQUENCY_CONFIG
VOUT_ADJUSTMENT
MFR_SPECIFIC_03 (Custom Register 3): Switching frequency control
MFR_SPECIFIC_04 (Custom Register 4): Output voltage adjustment control
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表 5. Supported PMBus Commands (接下页)
COMMAND
NOTES
VOUT_MARGIN
UVLO_THRESHOLD
MFR_SPECIFIC_05 (Custom Register 5): Output voltage margin levels
MFR_SPECIFIC_06 (Custom Register 6): Turn-on input voltage UVLO threshold
7.5.5.1 Unsupported PMBus Commands
Do not send any unsupported commands to the TPS53915. Even though the device receives an unsupported
commands, it can acknowledge the unsupported commands and any related data bytes by properly sending the
ACK bits. However, the device ignores the unsupported commands and any related data bytes, which means
they do not affect the device operation in any way. Although the TPS53915 may acknowledge but ignore
unsupported commands and data bytes, it can however, set the CML bit in the STATUS_BYTE register and then
pull down the ALERT pin to notify the host. For this reason, unsupported commands and data bytes should not
be sent to TPS53915.
7.5.5.2 OPERATION [01h] (R/W Byte)
The TPS53915 supports only the functions of the OPERATION command shown in 表 6.
表 6. OPERATION Command Supported Functions
COMMAND
OPERATION<7>
OPERATION<6>
DEFINITION
ON_OFF
—
DESCRIPTION
NVM
—
0: turn off switching converter
1: turn on switching converter
not supported and don’t care
—
00xx: turn off output voltage margin function
0101: turn on output voltage margin low and ignore fault
0110: turn on output voltage margin low and act on fault
1001: turn on output voltage margin high and ignore fault
1010: turn on output voltage margin high and act on fault
OPERATION<5:2>
OPMARGIN<3:0>
—
OPERATION<1>
OPERATION<0>
—
—
not supported and don’t care
not supported and don’t care
—
—
7.5.5.3 ON_OFF_CONFIG [02h] (R/W Byte)
The TPS53915 supports only the functions of the ON_OFF_CONFIG command shown in 表 7.
表 7. ON_OFF_CONFIG Command Supported Functions
COMMAND
DEFINITION
DESCRIPTION
NVM
—
ON_OFF_CONFIG<7>
ON_OFF_CONFIG<6>
ON_OFF_CONFIG<5>
—
—
—
not supported and don’t care
not supported and don’t care
not supported and don’t care
not supported and always set to 1
—
—
ON_OFF_CONFIG<4> PU
—
0: ignore ON_OFF bit (OPERATION<7>)(1)
1: act on ON_OFF bit (OPERATION<7>)
ON_OFF_CONFIG<3> CMD
Yes
Yes
0: ignore EN pin
ON_OFF_CONFIG<2> CP
1: act on EN pin(1)
ON_OFF_CONFIG<1> PL
ON_OFF_CONFIG<0> SP
not supported and always set to 1
not supported and always set to 1
—
—
(1) TI default
Conditions required to enable the switcher:
•
•
If CMD is cleared and CP is set, then the switcher can be enabled only by the EN pin.
If CMD is set and CP is cleared, then the switcher can be enabled only by the ON_OFF bit (OPERATION<7>)
via PMBus.
•
If both CMD and CP are set, then the switcher can be enabled only when both the ON_OFF bit
(OPERATION<7>) and the EN pin are commanding to enable the device.
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•
If both CMD and CP are cleared, then the switcher is automatically enabled after the ADDR detection
sequence completes, regardless of EN pin and ON_OFF bit polarities.
7.5.5.4 WRITE_PROTECT [10h] (R/W Byte)
The WRITE PROTECT command is used to control writing to the PMBus device. The intent of this command is
to provide protection against accidental changes. This command has one data byte as described in 表 8.
表 8. WRITE_PROTECT Command Supported Functions
COMMAND
DEFINITION
DESCRIPTION
NVM
Disable all writes, except the
WRITE_PROTECT command.
10000000:
01000000:
—
Disable all writes, except the
WRITE_PROTECT and OPERATION
commands.
—
—
WRITE_PROTECT<7:0>
WP<7:0>
Disable all writes, except the
WRITE_PROTECT, OPERATION, and
ON_OFF_CONFIG commands.
00100000:
00000000:
Others:
Enable writes to all commands.
Fault data
—
—
7.5.6 CLEAR_FAULTS [03h] (Send Byte)
The CLEAR_FAULTS command is used to clear any fault bits in the STATUS_WORD and STATUS_BYTE
registers that have been set. This command clears all bits in all status registers. Simultaneously, the TPS53915
releases its ALERT signal output if the device is asserting the ALERT signal. If the FAULT condition is still
present when the bit is cleared, the fault bits shall immediately be set again, and the ALERT signal should also
be re-asserted.
The CLEAR_FAULTS does not cause a unit that has latched off for a FAULT condition to restart. Units that have
been shut down for a FAULT condition can be restarted with one of the following conditions.
•
The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to
turn off and then to turn back on.
•
VDD power is cycled for TPS53915
The CLEAR_FAULT command is used to clear the fault bits in the STATUS_WORD and STATUS_BYTE
commands, and to release the ALERT pin. It is recommended not to send CLEAR_FAULT command when there
is no fault to cause the ALERT pin to pull down.
7.5.7 STORE_DEFAULT_ALL [11h] (Send Byte)
The STORE_DEFAULT_ALL command instructs TPS53915 to copy the entire contents of the operating memory
to the corresponding locations in the NVM. The updated contents in the non-volitile memory (NVM)s become the
new default values. The STORE_DEFAULT_ALL command can be used while the device is operating. However,
the device may be unresponsive during the copy operation with unpredictable results. (see PMBus Power
System Management Protocol Specificaiton, Part II - Command Language, Revision, 1.2, 6 Sept. 2010.
www.powerSIG.org). It is recommended not to exceed 1000 write/erase cycles for non-volatile memory (NVM).
7.5.8 RESTORE_DEFAULT_ALL [12h] (Send Byte)
The RESTORE_DEFAULT_ALL command instructs TPS53915 to copy the entire contents of the NVMs to the
corresponding locations in the operating memory. The values in the operating memory are overwritten by the
value retrieved from the NVM. It is permitted to use the RESTORE_DEFAULT_ALL command while the device is
operating. However, the device may be unresponsive during the copy operation with unpredictable results.
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7.5.9 STATUS_WORD [79h] (Read Word)
The TPS53915 does not support all functions of the STATUS_WORD command. A list of supported functions
appears in 表 9. A status bit reflects the current state of the converter. Status bit becomes high when the
specified condition has occurred and goes low when the specified condition has disappeared. A flag bit is a
latched bit that becomes high when the specified condition has occurred and does not go back low when the
specified condition has disappeared. STATUS_BYTE command is a subset of the STATUS_WORD command,
or more specifically the lower byte of the STATUS_WORD.
表 9. STATUS_WORD Command Supported Functions
COMMAND
DEFINITION
DESCRIPTION
Low Byte: STATUS_BYTE [78h]
Low STATUS_WORD<7>
BUSY
OFF
not supported and always set to 0
0: raw status indicating device is providing power to output voltage
1: raw status indicating device is not providing power to output voltage
Low STATUS_WORD<6>
Low STATUS_WORD<5>
Low STATUS_WORD<4>
Low STATUS_WORD<3>
Low STATUS_WORD<2>
Low STATUS_WORD<1>
0: latched flag indicating no output voltage overvoltage fault has occurred
1: latched flag indicating an output voltage overvoltage fault has occurred
VOUT_OV
IOUT_OC
VIN_UV
TEMP
0: latched flag indicating no output current overcurrent fault has occurred
1: latched flag indicating an output current overcurrent fault has occurred
0: latched flag indicating input voltage is above the UVLO turn-on threshold
1: latched flag indicating input voltage is below the UVLO turn-on threshold
0: latched flag indicating no OT fault has occurred
1: latched flag indicating an OT fault has occurred
0: latched flag indicating no communication, memory or logic fault has occurred
1: latched flag indicating a communication, memory or logic fault has occurred
CML
Low STATUS_WORD<0>
OTHER
not supported and always set to 0
High Byte
0: latched flag indicating no output voltage fault or warning has occurred
1: latched flag indicating a output voltage fault or warning has occurred
High STATUS_WORD<7>
High STATUS_WORD<6>
VOUT
IOUT
0: latched flag indicating no output current fault or warning has occurred
1: latched flag indicating an output current fault or warning has occurred
0: latched flag indicating no input voltage fault or warning has occurred
1: latched flag indicating a input voltage fault or warning has occurred
High STATUS_WORD<5>
High STATUS_WORD<4>
High STATUS_WORD<3>
INPUT
MFR
not supported and always set to 0
0: raw status indicating PGOOD pin is at logic high
1: raw status indicating PGOOD pin is at logic low
PGOOD
High STATUS_WORD<2>
High STATUS_WORD<1>
High STATUS_WORD<0>
FANS
not supported and always set to 0
not supported and always set to 0
not supported and always set to 0
OTHER
UNKNOWN
The latched flags of faults can be removed or corrected only until one of the following conditions occurs:
•
•
The device receives a CLEAR_FAULTS command.
The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to
turn off and then to turn back on
•
VDD power is cycled for TPS53915
If the FAULT condition remains present when the bit is cleared, the fault bits are immediately set again, and the
ALERT signal is re-asserted.
TPS53915 supports the ALERT pin to notify the host of FAULT conditions. Therefore, the best practice for
monitoring the fault conditions from the host is to treat the ALERT pin as an interrupt source for triggering the
corresponding interrupt service routine. It is recommended not to keep polling the STATUS_WORD or
STATUS_BYTE registers from the host to reduce the firmware overhead of the host.
28
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7.5.10 CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
Custom register 0 provides the flexibility for users to store any desired non-volatile information. For example,
users can program this register to track versions of implementation or other soft identification information. The
details of each setting are listed in 表 10.
表 10. CUSTOM_REG (MFR_SPECIFIC_00) Settings
COMMAND
CUSTOM_REG<7>
CUSTOM_REG<6>
DEFINITION
DESCRIPTION
not supported and don’t care
NVM
—
—
—
not supported and don’t care
—
00000:(1) can be used to store any desired non-volatile
information.
CUSTOM_REG<5:0>
(1) TI Default
CUSTOMWORD <5:0>
Yes
7.5.11 DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
Custom register 1 provides software control over key timing parameters of the controller: Power-on delay (POD)
time and power-good delay (PGD) time. The details of each setting are listed in 表 11.
表 11. DELAY_CONTROL (MFR_SPECIFIC_01) Settings
COMMAND
DELAY_CONTROL<7>
DELAY_CONTROL<6>
DEFINITION
DESCRIPTION
NVM
—
—
—
not supported and don’t care
not supported and don’t care
—
000: 256 µs
001: 512 µs
010: 1.024 ms(1)
011: 2.048 ms
100: 4.096 ms
101: 8.192 ms
110: 16.384 ms
111: 131.072 ms
DELAY_CONTROL<5:3>
PGD<2:0>
Yes
000: 356 µs
001: 612 µs
010: 1.124 ms(1)
011: 2.148 ms
100: 4.196 ms
101: 8.292 ms
110: 16.484 ms
111: 32.868 ms
DELAY_CONTROL<2:0>
(1) TI Default
POD<2:0>
Yes
7.5.12 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
Custom register 2 provides software control over mode selection and soft-start time (tSS). The details of each
setting are listed in 表 12.
表 12. MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) Settings
COMMAND
MODE_SOFT_START_CONFIG<7>
MODE_SOFT_START_CONFIG<6>
MODE_SOFT_START_CONFIG<5>
MODE_SOFT_START_CONFIG<4>
DEFINITION
DESCRIPTION
not supported and don’t care
not supported and don’t care
not supported and don’t care
not supported and don’t care
NVM
—
—
—
—
—
—
—
—
00: 1 ms(1)
01: 2 ms
10: 4 ms
11: 8 ms
MODE_SOFT_START_CONFIG<3:2>
SST<1:0>
Yes
(1) TI Default
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表 12. MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) Settings (接下页)
COMMAND
DEFINITION
DESCRIPTION
0: hiccup after UV(1)
NVM
MODE_SOFT_START_CONFIG<1>
HICLOFF
Hiccup interval is (8.96 ms + soft-start time × 7)
1: latch-off after UV
Yes
0: DCM(1)
1: FCCM
MODE_SOFT_START_CONFIG<0>
CM
Yes
图 48 shows the soft-start timing diagram of TPS53915 with the programmable power-on delay time (tPOD), soft-
start time (tSST), and PGOOD delay time (tPGD). During the soft-start time, the controller remains in discontinuous
conduction mode (DCM), and then switches to forced continuous conduction mode (FCCM) at the end of soft-
start if CM bit (MODE_SOFT_START_CONFIG<0>) is set.
EN Pin and/or
ON_OFF bit
t
t
t
PGD
POD
SST
V
OUT
PGOOD
DCM or FCCM
(based on CM bit)
DCM
UDG-12070
Time
图 48. Programmable Soft-Start Timing
7.5.13 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
Custom register 3 provides software control over frequency setting (FS). The details of FS setting are listed in 表
13.
表 13. FREQUENCY_CONFIG (MFR_SPECIFIC_03) Settings
COMMAND
DEFINITION
DESCRIPTION
NVM
—
FREQUENCY_CONFIG<7>
FREQUENCY_CONFIG<6>
FREQUENCY_CONFIG<5>
FREQUENCY_CONFIG<4>
FREQUENCY_CONFIG<3>
—
—
—
—
—
not supported and don’t care
not supported and don’t care
not supported and don’t care
not supported and don’t care
not supported and don’t care
—
—
—
—
000: 250 kHz
001: 300 kHz
010: 400 kHz
(1)
011: 500 kHz
100: 600 kHz
101: 750 kHz
110: 850 kHz
111: 1 MHz
FREQUENCY_CONFIG<2:0>
FS<2:0>
Yes
(1) TI default.
7.5.14 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
Custom register 4 provides ouput voltage adjustment (VOA) in ±0.75% steps, with a total range of ±9%. When
fine adjustment is used together with the margin setting, the change in the output voltage is determined by the
multiplication of the two settings.
30
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表 14. VOUT_ADJUSTMENT (MFR_SPECIFIC_04) Settings
COMMAND
DEFINITION
DESCRIPTION
NVM
—
VOUT_ADJUSTMENT<7>
VOUT_ADJUSTMENT<6>
VOUT_ADJUSTMENT<5>
—
—
—
not supported and don’t care
not supported and don’t care
not supported and don’t care
—
—
111xx: +9.00%
11011: +8.25%
11010: +7.50%
11001: +6.75%
11000: +6.00%
10111: +5.25%
10110: +4.50%
10101: +3.75%
10100: +3.00%
10011: +2.25%
10010: +1.50%
10001: +0.75%
10000: +0%(1)
01111: –0%
VOUT_ADJUSTMENT<4:0>
VOA<4:0>
Yes
01110: –0.75%
01101: –1.50%
01100: –2.25%
01011: –3.00%
01010: –3.75%
01001: –4.50%
01000: –5.25%
00111: –6.00%
00110: –6.75%
00101: –7.50%
00100: –8.25%
000xx: –9.00%
(1) TI default.
7.5.15 Output Voltage Fine Adjustment Soft Slew Rate
To prevent sudden buildup of voltage across inductor, output voltage fine adjustment setting cannot change
output voltage instantaneously. The internal reference voltage must slew slowly to its final target, and SST<1:0>
is used to provide further programmability. The details of output voltage fine adjustment slew rate are shown in
表 15.
表 15. Output Voltage Fine Adjustment Soft Slew Rate Settings
COMMAND
DEFINITION
DESCRIPTION
NVM
00: 1 step per 4 µs(1)
01: 1 step per 8 µs
10: 1 step per 16 µs
11: 1 step per 32 µs
MODE_SOFT_START_CONF
IG<3:2>
SST<1:0>
Yes
(1) TI default.
7.5.16 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
Custom register 5 provides output voltage margin high (VOMH) and output voltage margin low (VOML) settings.
This register works in conjunction with PMBus OPERATION command to raise or lower the output voltage by a
specified amount. This register settings described in 表 16 are also used together with the fine adjustment setting
described in 表 14. For example, setting fine adjustment to +9% and margin to +12% changes the output by
+22.08%, whereas setting fine adjustment to –9% and margin to –9% change the output by –17.19%
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31
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NVM
表 16. VOUT_MARGIN (MFR_SPECIFIC_05) Settings
COMMAND
DEFINITION
DESCRIPTION
11xx: +12.0%
1011: +10.9%
1010: +9.9%
1001: +8.8%
1000: +7.7%
0111: +6.7%
0110: +5.7%
0101: +4.7%(1)
0100: +3.7%
0011: +2.8%
0010: +1.8%
0001: +0.9%
0000: +0%
VOUT_MARGIN<7:4>
VOMH<3:0>
Yes
0000: –0%
0001: –1.1%
0010: –2.1%
0011: –3.2%
0100: –4.2%
(1)
0101: –5.2%
0110: –6.2%
0111: –7.1%
1000: –8.1%
1001: –9.0%
1010: –9.9%
1011: –10.7%
11xx: –11.6%
VOUT_MARGIN<3:0>
VOML<3:0>
Yes
(1) TI default.
7.5.17 Output Voltage Margin Adjustment Soft-Slew Rate
Similar to the output voltage fine adjustment, margin adjustment also cannot change output voltage
instantaneously. The soft-slew rate of margin adjustment is also programmed by SST<1:0>. The details are listed
in 表 17.
表 17. Output Voltage Margin Adjustment Soft-Slew Rate Settings
COMMAND
DEFINITION
DESCRIPTION
NVM
00: 1 step per 4 µs(1)
01: 1 step per 8 µs
10: 1 step per 16 µs
11: 1 step per 32 µs
MODE_SOFT_START_CONFIG<3:2>
SST<1:0>
Yes
(1) TI default.
32
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图 49 shows the timing diagram of the output voltage adjustment via PMBus. After receiving the write command
of VOUT_ADJUSTMENT (MFR_SPECIFIC_04), the output voltage starts to be adjusted after tP delay time
(about 50 μs). The time duration tDAC for each DAC step change can be controlled by SST bits
(MODE_SOFT_START_CONFIG<3:2:> from 4 μs to 32 μs.
PMBus
Write
VOA<4:0>=10101b
Write
VOA<4:0>=01010b
tP
tP
VOUT
tDAC
UDG-12071
图 49. Output Voltage Adjustment via PMBus
The margining function is enabled by setting the OPERATION command, and the margining level is determined
by the VOUT_MARGIN (MFR_SPECIFIC_05) command. 图 50 and 图 51 illustrate the timing diagrams of the
output voltage margining via PMBus. 图 50 shows setting the margining level first, and then enabling margining
by writing OPERATION command. After the OPERATION margin high command enables the margin high setting
(VOMH<3:0>), the output voltage starts to be adjusted after tP delay time (about 50 μs). The time duration tDAC
for each DAC step change can be controlled by SST bits (MODE_SOFT_START_CONFIG<3:2>) from 4 μs to 32
μs.
As shown in 图 51, the margining function is enabled first by a write command of OPERATION. The output
voltage starts to be adjusted toward the default margin high level after tP delay. Because the margining function
has been enabled, the output voltage can be adjusted again by sending a different margin high level with a write
command of VOUT_MARGIN. The time duration tDAC for each DAC step change can be also controlled by SST
bits (MODE_SOFT_START_CONFIG<3:2>) from 4 μs to 32 μs.
PMBus
Write
VOMH<3:0>=0100b
Write
OPMARGIN<3:0>=1010b
tP
VOUT
tDAC
UDG-12072
图 50. Setting the Margining Level First
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Write
VOMH<3:0>=0001b
Write
OPMARGIN<3:0>=1010b
tP
tP
VOUT
tDAC
UDG-12073
图 51. Enabling Margining First
7.5.18 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
Custom register 6 provides some limited programmability of input supply UVLO threshold, as described in 表 18.
The default turn-on UVLO threshold is 4.25 V.
表 18. UVLO_THRESHOLD (MFR_SPECIFIC_06) Settings
COMMAND
DEFINITION
DESCRIPTION
not supported and don’t care
NVM
—
UVLO_THRESHOLD<7>
UVLO_THRESHOLD<6>
UVLO_THRESHOLD<5>
UVLO_THRESHOLD<4>
UVLO_THRESHOLD<3>
—
—
—
—
—
not supported and don’t care
not supported and don’t care
not supported and don’t care
not supported and don’t care
—
—
—
—
0xx: 10.2 V
100: not supported and should not be used
UVLO_THRESHOLD<2:0>
(1) TI default.
VDDINUVLO<2:0>
101: 4.25 V(1)
110: 6.0 V
111: 8.1 V
Yes
34
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53915 device is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-
output voltage point-of-load applications with 12-A or lower output current in computing and similar digital
consumer applications.
8.2 Typical Application
R1
PGOOD
6.65 kΩ
R2
C3
C4
2 kΩ
1 µF
1 µF
Thermal
Pad
VIN
R6
150 kΩ
CIN
2.2 nF
CIN
3 × 22 µF
23
22
21
20
19
18
17
16
15
24 VO
PGND 14
PGND 13
PGND 12
PGND 11
PGND 10
25 TRIP
ALERT
64.9 kΩ
26 ALERT
27 SDA
28 SCL
R8
TPS53915
SDA
SCL
1
2
3
4
5
6
7
8
9
PIMB065Tœ1R0MS-63
VOUT
R4
249 kΩ
R10
100 kΩ
1 µH
R7
0 Ω
C2
0.1 µF
R3
3 Ω
Thermal Pad
COUT
COUT
4 × 10 µF
6 × 22 µF
R5
105 kΩ
VREG
EN
C1
470 pF
图 52. Typical Application Circuit Diagram
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35
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Typical Application (接下页)
8.2.1 Design Requirements
This design uses the parameters listed in 表 19.
表 19. Design Example Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INPUT CHARACTERISTICS
VIN
Voltage range
5
12
2.5
1
18
V
A
IMAX
Maximum input current
No load input current
V IN = 5 V, I OUT = 8 A
V IN = 12 V, I OUT = 0 A with auto skip mode
mA
OUTPUT CHARACTERISTICS
VOUT
Output voltage
1.2
V
Line regulation, 0.2% 5 V ≤ V IN ≤ – 14 V with FCCM
0.2%
Output voltage regulation
Load regulation, 0.5% V IN = 12 V, 0 A ≤ I OUT ≤ 8 A with
FCCM
0.5%
10
mV
PP
VRIPPLE Output voltage ripple
V IN = 12 V, I OUT = 8 A with FCCM
ILOAD
IOVER
tSS
Output load current
Output over current
Soft-start time
0
8
A
11
1
ms
SYSTEM CHARACTERISTICS
fSW
Switching frequency
Peak efficiency
500
88.5%
88.9%
25
kHz
ºC
η
V IN = 12 V, V OUT = 1.2 V ,I OUT = 4 A
V IN = 12 V, V OUT = 1.2 V , I OUT = 8 A
Full load efficiency
Operating temperature
TA
8.2.2 Detailed Design Procedure
The external components selection is a simple process using D-CAP3 Mode. Select the external components
using the following steps.
8.2.2.1 Choose the Switching Frequency
The default switching frequency (fSW) is pre-set at 400 kHz. The switching frequency can be changed through
PMBus function MFR_SPECIFIC_03 (see 表 13).
8.2.2.2 Choose the Operation Mode
Select the operation mode using 表 3.
8.2.2.3 Choose the Inductor
Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output current.
Larger ripple current increases output ripple voltage, improves signal-to-noise ratio, and helps to stabilize
operation.
V
(
IN
max
(
- V
´ V
V
- V
max
´ V
OUT
OUT
)
)
OUT
(
IN
OUT
)
)
(
)
1
3
L =
´
=
´
I
´ f
V
I
´ f
V
IN(max)
SW
IN
max
(
OUT
SW
IND ripple
(
max
)
(
)
12V -1.2V ´1.2V
)
(
3
=
´
= 1.08mH
6´ 500kHz
12V
(6)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above peak
inductor current before saturation. The peak inductor current is estimated using 公式 7.
36
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TPS53915
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ZHCSBX1B –NOVEMBER 2013–REVISED DECEMBER 2014
V
(
IN
max
(
- V
´ V
OUT
OUT
)
)
12V -1.2V ´1.2V
)
)
(
V
10mA ´R
TRIP
1
1
TRIP
I
=
+
´
=
+
´
IND peak
(
)
8´R
L ´ f
V
8´5.9mW
1mH´500kHz
12V
SW
IN
max
DS on
( )
(
(7)
8.2.2.4 Choose the Output Capacitor
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has two components as shown in 公式 8. 公式 9 and 公式 10 define these components.
V
= V
+ V
RIPPLE
RIPPLE(C) RIPPLE(ESR)
(8)
IL ripple
(
)
VRIPPLE C
=
( )
8´ COUT ´ fSW
VRIPPLE ESR = IL ripple ´ESR
(9)
(
)
(
)
(10)
8.2.2.5 Determine the Value of R1 and R2
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in 公式 11. Connect R1
between the VFB pin and the output, and connect R2 between the VFB pin and GND. The recommended R2
value is from 1 kΩ to 20 kΩ. Determine R1 using 公式 11.
V
- 0.6
1.2V - 0.6
OUT
R1=
´R2 =
´10kW = 10kW
0.6
0.6
(11)
8.2.3 Application Curves
100
1.3
1.25
1.2
fSW = 1 MHz
VDD = 5 V
ëhÜÇ = 1.2 ë
TA = 25°C
LOUT = 1 ꢀH
Mode = Auto-skip
90
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = FCCM
70
60
1.15
1.1
V
VOUT = 0.6 V
VOUT = 1 V
VOUT= 1.5 V
VIN=5V
V= 1.2 V
OUT
VIN = 12 V
V
V
= 1.8 V
= 3.3 V
V
V
= 2.5 V
= 5 V
OUT
OUT
OUT
OUT
VIN = 18 V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C004
C008
图 53. Efficiency vs. Output Current
图 54. Output Voltage vs. Output Current
1.3
1.25
1.2
600
550
500
450
400
fSW = 500 KHz
fSW = 500 kHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VDD = 5 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VOUT = 1.2 V
1.15
1.1
VIN=5V
VIN=5V
VIN = 12 V
VIN = 12 V
VIN = 18 V
VIN = 18 V
0
2
4
6
8
10
12
1
2
3
4
5
6
7
8
9
10 11 12
Output Current (A)
Output Current (A)
C009
C012
图 55. Output Voltage vs. Output Current
图 56. Switching Frequency vs. Output Current
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PGOOD
PGOOD
V
OUT
V
OUT
50%
50%
50%
SW
SW
CTNL
CTNL
ILOAD = 6 A
ILOAD = 6 A
图 57. Start-Up Sequence
图 58. Shutdown Sequence
V
V
OUT
OUT
SW
SW
I
OUT
I
OUT
ILOAD from 0 A to 6 A
ILOAD from 6A to 0 A
图 59. Load Transient
图 60. Load Transient
V
OUT
V
OUT
SW
SW
I
OUT
ILOAD from 0 A to 6A to 0 A
ILOAD = 0 A
图 61. Full Cycle Load Transient
图 62. Output Voltage Ripple
38
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PGOOD
V
OUT
V
OUT
SW
EN
SW
ILOAD = 6 A
Preset VOUT = 0.5 V
图 63. Output Voltage Ripple
图 64. Pre-Bias Start-Up
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9 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 1.5-V and 18-V (4.5-V and 25-V biased)
Input. use only a well regulated supply. These devices are not designed for split-rail operation. The VIN and VDD
terminals must be the same potential for accurate high-side short circuit protection. Proper bypassing of input
supplies and internal regulators is also critical for noise performance, as is PCB layout and grounding scheme.
See the recommendations in the Layout section.
10 Layout
10.1 Layout Guidelines
Before beginning a design using the TPS53915, consider the following:
•
Place the power components (including input and output capacitors, the inductor, and the TPS53915) on the
solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and
connect at least one inner plane to ground.
•
All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and ADDR must be placed
away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as
ground planes and shield the feedback trace from power traces and components.
•
•
Pin 22 (GND pin) must be connected directly to the thermal pad. Connect the thermal pad to the PGND pins
and then to the GND plane.
Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input
AC-current loop.
•
•
Place the feedback resistor near the IC to minimize the VFB trace distance.
Place the frequency-setting resistor (ADDR), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE
close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
)
•
•
•
•
•
•
•
Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for
each decoupling capacitor and ensure the loop is as small as possible.
The PCB trace is defined as switch node, which connects the SW pins and high-voltage side of the inductor.
The switch node should be as short and wide as possible.
Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection
resistor. Do not combine these connections.
Place one more small capacitor (2.2 nF- 0402 size) between the VIN and PGND pins. This capacitor must be
placed as close to the IC as possible.
TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction.
The value of snubber design starts at 3 Ω + 470 pF.
Consider R,C,Cc network (Ripple injection network) component placement and place the AC coupling
capacitor, Cc, close to the device, and R and C close to the power stage.
See 图 65 for the layout recommendation.
40
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TPS53915
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10.2 Layout Example
VIN Shape
To inner GND plane
CIN
HF cap.
Cc
2
3
2
1
2
0
1
9
1
8
1
7
1
6
1
5
To VOUT Shape
VO
PGND
PGND
PGND
PGND
PGND
TRIP
ALERT
SDA
GND Shape
COUT
SCL
1
2
3
4
5
6
7
8
9
VOUT Shape
SW Shape
LOUT
To VREG Pin
Cap.
Res.
Trace on bottom layer
Trace of top layer
RCC On Bottom layer
Trace of bottom layer
Trace on inner layer
图 65. Layout Recommendation
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11 器件和文档支持
11.1 文档支持
相关文档如下：
•
应用报告《采用前馈电容优化内部补偿 DC-DC 转换器的瞬态响应》（文献编号：SLVA289）
11.2 商标
SWIFT, D-CAP3, Eco-mode, WEBENCH are trademarks of Texas Instruments.
PMBus is a trademark of SMIF, Inc.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
42
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
TPS53915RVER
TPS53915RVET
ACTIVE
VQFN-CLIP
VQFN-CLIP
RVE
28
28
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TPS53915
TPS53915
ACTIVE
RVE
RoHS-Exempt
& Green
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53915RVER
TPS53915RVET
VQFN-
CLIP
RVE
RVE
28
28
3000
250
330.0
12.4
3.8
4.8
1.18
8.0
12.0
Q1
VQFN-
CLIP
180.0
12.4
3.8
4.8
1.18
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53915RVER
TPS53915RVET
VQFN-CLIP
VQFN-CLIP
RVE
RVE
28
28
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVE0028A
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
4.6
4.4
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2.1 0.1
2X 1.6
(0.2) TYP
14
EXPOSED
THERMAL PAD
10
24X 0.4
9
15
2X
29
SYMM
3.2
3.1 0.1
23
1
0.25
28X
0.15
28
24
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
28X
0.05
0.5
0.3
4219151/A 07/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RVE0028A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.1)
SYMM
28
24
28X (0.6)
28X (0.2)
23
1
(1.3) TYP
SYMM
24X (0.4)
29
(4.3)
(3.1)
(R0.05)
TYP
9
15
(
0.2) TYP
VIA
10
14
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219151/A 07/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RVE0028A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.94)
(0.57) TYP
28
24
28X (0.6)
1
23
28X (0.2)
24X (0.4)
(0.775)
TYP
29
SYMM
(4.3)
(R0.05) TYP
4X (1.35)
9
15
METAL
TYP
10
14
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219151/A 07/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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