TPS5420-Q1 [TI]
2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT⢠CONVERTER; 2 -A宽输入范围降压SWIFTâ ?? ¢转换器
| 型号： | TPS5420-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT⢠CONVERTER |
| 文件： | 总22页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS5420-Q1
www.ti.com................................................................................................................................................... SLVS752B–NOVEMBER 2007–REVISED JUNE 2008
2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER
1
FEATURES
APPLICATIONS
•
•
•
Industrial and Car Audio Power Supplies
Battery Chargers, High-Power LED Supplies
12-V/24-V Distributed Power Systems
2
•
Qualified for Automotive Applications
•
•
Wide Input Voltage Range: 5.5 V to 36 V
Up to 2-A Continuous (3-A Peak) Output
Current
DESCRIPTION
•
•
•
•
•
•
High Efficiency up to 95% Enabled by 110-mΩ
Integrated MOSFET Switch
As a member of the SWIFT family of dc/dc regulators,
the TPS5420 is a high-output-current PWM converter
that integrates a low-resistance high-side N-channel
MOSFET. Included on the substrate with the listed
features is a high-performance voltage error amplifier
that provides tight voltage regulation accuracy under
transient conditions, an undervoltage-lockout circuit to
prevent start-up until the input voltage reaches 5.5 V,
an internally set slow-start circuit to limit inrush
Wide Output Voltage Range: Adjustable Down
to 1.22 V With 1.5% Initial Accuracy
Internal Compensation Minimizes External
Parts Count
Fixed 500-kHz Switching Frequency for Small
Filter Size
Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
currents, and
a voltage feed-forward circuit to
improve the transient response. Using the ENA pin,
shutdown supply current is reduced to 18 µA
typically. Other features include an active-high
enable, overcurrent limiting, overvoltage protection,
and thermal shutdown. To reduce design complexity
and external component count, the TPS5420
feedback loop is internally compensated.
System Protected by Over Current Limiting,
Over Voltage Protection, and Thermal
Shutdown
•
–40°C to 125°C Operating Junction
Temperature Range
•
•
Available in Small 8-Pin SOIC Package
The TPS5420 device is available in an easy-to-use
8-pin SOIC package. TI provides evaluation modules
and the SWIFT Designer software tool to aid in
quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
For SWIFT™ Documentation, Application
Notes and Design Software, See the TI Website
at www.ti.com/swift
Simplified Schematic
Efficiency vs Output Current
100
VIN
VOUT
VIN
PH
95
90
85
TPS5420
BOOT
NC
NC
80
VI = 12 V
75
70
ENA VSENSE
GND
65
60
55
50
0
0.5
1
1.5
2
2.5
3
I
- Output Current - A
O
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SWIFT is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS5420-Q1
SLVS752B–NOVEMBER 2007–REVISED JUNE 2008................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TJ
INPUT VOLTAGE
OUTPUT VOLTAGE
PACKAGE(2)
PART NUMBER
–40°C to 125°C
5.5 V to 36 V
Adjustable to 1.22 V
SOIC (D)
TPS5420QDRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VIN
–0.3 V to 40 V(3)
–0.3 V to 50 V
–0.6 V to 40 V(3)
–0.3 V to 7 V
–0.3 V to 3 V
10 V
BOOT
PH (steady-state)
VI
Input voltage range
EN
VSENSE
BOOT-PH
PH (transient < 10 ns)
–1.2 V
IO
Source current
PH
PH
Internally limited
10 µA
Ilkg
TJ
Leakage current
Operating virtual-junction temperature range
Storage temperature range
–40°C to 150°C
–65°C to 150°C
2000 V
Tstg
Human-Body Model (HBM)
Machine Model (MM)
ESD
Electrostatic discharge rating
150 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
DISSIPATION RATINGS(1) (2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
PACKAGE
(3)
8-pin D
75°C/W
(1) Maximum power dissipation may be limited by overcurrent protection.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
(3) Test board conditions:
a. 3 in × 3 in, two layers, thickness: 0.062 inch
b. 2-oz. copper traces located on the top and bottom of the PCB
RECOMMENDED OPERATING CONDITIONS
MIN
5.5
MAX
36
UNIT
V
VI
Input voltage range, VIN
TJ
Operating junction temperature
–40
125
°C
2
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 5.5 V to 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VSENSE = 2 V, Not switching, PH pin open
Shutdown, ENA = 0 V
3
4.4
50
mA
IQ
Quiescent current
18
µA
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage, UVLO
Hysteresis voltage, UVLO
5.3
5.5
V
330
mV
VOLTAGE REFERENCE
TJ = 25°C
1.202
1.196
1.221
1.221
1.239
1.245
Voltage reference accuracy
V
IO = 0 A to 2 A
OSCILLATOR
Internally set free-running frequency
Minimum controllable on time
Maximum duty cycle
400
500
150
600
200
kHz
ns
87%
89%
ENABLE (ENA PIN)
Start threshold voltage, ENA
Stop threshold voltage, ENA
Hysteresis voltage, ENA
Internal slow-start time (0 ~ 100%)
CURRENT LIMIT
1.3
10
V
V
0.5
5.4
450
8
mV
ms
Current limit
3
4
6.5
21
A
Current-limit hiccup time
THERMAL SHUTDOWN
Thermal shutdown trip point
Thermal shutdown hysteresis
OUTPUT MOSFET
13
16
ms
135
162
14
°C
°C
VIN = 5.5 V
150
110
rDS(on)
High-side power MOSFET switch
mΩ
VIN = 10 V to 36 V
230
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PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
BOOT
NC
PH
VIN
NC
GND
ENA
VSENSE
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
BOOT
NC
NO.
1
Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low ESR capacitor from BOOT pin to PH pin.
Not connected internally
2, 3
4
VSENSE
ENA
Feedback voltage for the regulator. Connect to output voltage divider.
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
Ground
5
GND
6
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality low-ESR ceramic
capacitor.
VIN
PH
7
8
Source of the high-side power MOSFET. Connected to external inductor and diode.
4
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TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
OPERATING QUIESCENT CURRENT
MINIMUM CONTROLLABLE ON TIME
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
530
520
3.5
180
170
V
= 12 V
I
3.25
510
160
150
500
490
480
3
140
130
120
2.75
2.5
470
460
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
− Junction Temperature − o
C
T
− Junction Temperature − o
C
T
− Junction Temperature − o
C
T
J
J
J
Figure 1.
Figure 2.
Figure 3.
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
INTERNAL SLOW START TIME
vs
JUNCTION TEMPERATURE
180
170
160
150
140
130
120
110
100
90
1.23
9
V
= 12 V
I
1.225
1.22
8.5
8
1.215
1.21
7.5
80
7
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
T
− Junction Temperature − o
C
T
− Junction Temperature − o
C
J
J
T
− Junction Temperature − o
C
J
Figure 4.
Figure 5.
Figure 6.
MINIMUM CONTROLLABLE DUTY
SHUTDOWN QUIESCENT CURRENT
RATIO
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
8
25
20
15
10
5
ENA = 0 V
T
= 125oC
J
J
7.5
T
= 27oC
7.5
7.25
T
= -40oC
J
7
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
− Junction Temperature − o
C
V
− Input Voltage − V
I
T
J
Figure 7.
Figure 8.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
VREF
SHDN
Boot
Regulator
1.221 V Bandgap
Reference
Slow Start
UVLO
BOOT
HICCUP
5 µA
SHDN
ENABLE
ENA
SHDN
VSENSE
Z1
Thermal
Protection
Error
Amplifier
SHDN
SHDN
Z2
Ramp
NC
VIN
Feed Forward
Gain = 25
Generator
NC
HICCUP
PWM
Comparator
SHDN
GND
Overcurrent
Protection
Oscillator
SHDN
SHDN
Gate Drive
Control
VSENSE
112.5% VREF
OVP
Gate
Driver
SHDN
PH
BOOT
VOUT
DETAILED DESCRIPTION
Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The
quiescent current of the TPS5420 in shutdown mode is typically 18 µA.
6
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The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open-drain or open-collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its
final value linearly. The internal slow start time is 8 ms typically.
Undervoltage Lockout (UVLO)
The TPS5420 incorporates a UVLO circuit to keep the device disabled when VIN (the input voltage) is below the
UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is
grouded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached,
the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO
stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01-µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
Output Feedback (VSENSE)
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
Internal Compensation
The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses
voltage-mode control, a type-3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See Internal Compensation Network in the Advanced
Information section for more details.
Voltage Feed Forward
The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e.:
VIN
Feed Forward Gain =
Ramp
pk-pk
(1)
The typical feed forward gain of TPS5420 is 25.
Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed-frequency PWM control method. First, the feedback voltage (VSENSE pin voltage)
is compared to the constant voltage reference by the high-gain error amplifier and compensation network to
produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this
way, the error voltage magnitude is converted to a pulse width that is the duty cycle. Finally, the PWM output is
fed into the gate drive circuit to control the on time of the high-side MOSFET.
Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain-to-source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle current
limiting.
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Sometimes, under serious overload conditions such as short-circuit, the overcurrent runaway may still occur
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e., hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow start circuit.
Overvoltage Protection (OVP)
The TPS5420 has an OVP circuit to minimize voltage overshoot when recovering from output fault conditions.
The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of
112.5% × VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET is forced
off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFET is enabled again.
Thermal Shutdown
The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low-ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this
is to extend the top-side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-µF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device
and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground
area under the device as shown in Figure 9.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout, and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may
need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the
output capacitor is not desired.
If using the grounding scheme shown in Figure 9, use a via connection to a different layer to route to the ENA
pin.
8
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PH
CATCH
DIODE
BOOT
CAPACITOR
INPUT
BULK
FILTER
INPUT
BYPASS
CAPACITOR
BOOT
NC
PH
VIN
OUTPUT
INDUCTOR
Vin
NC
GND
ENA
RESISTOR
DIVIDER
VSENSE
VOUT
OUTPUT
FILTER
CAPACITOR
TOPSIDE GROUND AREA
VIA to Ground Plane
Signal VIA
Route feedback
trace under the output
filter capacitor or on
the other layer.
Figure 9. Design Layout
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0.220
0.080
All dimensions in inches
Figure 10. TPS5420 Land Pattern
Application Circuits
Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output
current at a nominal output voltage of 5 V.
U1
L1
33 mH
C2
0.01 mF
TPS5420D
TP5
10 V - 35 V
7
5
2
5 V
VIN
VIN
1
8
4
BOOT
PH
VOUT
ENA
NC
ENA
C1
4.7 mF
C4
4.7 mF
+
D1
B340A
C3
100 mF
(See Note A)
R1
10 kW
3
6
NC
VSNS
GND
R2
3.24 kW
A. C3 = Tantalum AVX TPSD107M010R0080
Figure 11. Application Circuit, 10-V to 35-V Input to 5-V Output
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Design Procedure
The following design procedure can be used to select component values for the TPS5420. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To begin the design process, a few parameters must be determined. The designer must know the following:
•
•
•
•
•
•
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
Design Parameters
For this design example, use the following as the input parameters:
DESIGN PARAMETER(1)
Input voltage range
Output voltage
EXAMPLE VALUE
10 V to 36 V
5 V
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
300 mV
30 mV
2 A
500 kHz
(1) As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
Input Capacitors
The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor is 10 µF. A high-quality ceramic type X5R or X7R is
required. For some applications, a smaller-value decoupling capacitor may be used, if the input voltage and
current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple. For this design, two 4.7-µF capacitors, C1 and C4 are used to allow for smaller 1812 case size
to be used while maintaining a 50-V rating.
This input ripple voltage can be approximated by Equation 2 :
I
× 0.25
OUT(MAX)
+ I
(
× ESR
MAX
DV
=
)
OUT(MAX)
IN
C
× ƒSW
BULK
(2)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CI is the input capacitor value, and
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst-case conditions, this is approximated by
Equation 3:
I
OUT(MAX)
I
+
CIN
2
(3)
In this case, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors
are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual
measured input ripple voltage may be larger than the calculated value, due to the output impedance of the input
voltage source and parasitics associated with the layout.
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CAUTION:
The maximum ratings for voltage and current are not to be exceeded under any
circumstance.
Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within
approximately two inches from the input voltage source. The value for this capacitor is not critical, but it should
be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input
ripple voltage is acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
V
× V
(
– V
)
OUT
IN(MAX)
OUT
SW
L
=
MIN
V
× K
IND
× I
× F
× 0.8
IN(max)
OUT
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the
peak-to-peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch
current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For
designs using the TPS5420, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages are obtained when
paired with the proper output capacitor, the peak switch current is below the current limit set point, and low load
currents can be sourced before discontinuous operation.
For this design example, use KIND = 0.2, and the minimum inductor value is 31 µH. The next highest standard
value used in this design is 33 µH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current is found from Equation 5:
2
ǒV
OUTǓ
V
* V
IN(MAX)
L F
OUT
1
12
I2
I
+
)
ǒ
Ǔ
Ǹ
L(RMS)
OUT(MAX)
V
0.8
IN(MAX)
OUT
SW
(5)
and the peak inductor current is determined from Equation 6:
V
× V
(
– V
OUT
)
OUT
IN(MAX)
× L
I
= I
+
L(PK)
OUT(MAX)
1.6 × V
× F
OUT SW
IN(MAX)
(6)
For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen
inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 µH. It has a saturation current rating of
2.2 A and a RMS current rating of 2.7 A, which meet the requirements. Inductor values for use with the TPS5420
are in the range of 10 µH to 100 µH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual
value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between
the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to
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the design of the internal compensation, it is recommended to keep the closed-loop crossover frequency in the
range 3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this
design example, the intended closed-loop crossover frequency is between 2590 Hz and 24 kHz and below the
ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is related to the
LC corner frequency as:
2
f
LC
f
+
CO
85 V
OUT
(7)
and the desired output capacitor value for the output filter to:
1
f
C
+
OUT
3357 L
V
OUT
CO
OUT
(8)
For a desired crossover of 18 kHz and a 33-µH inductor, the calculated value for the output capacitor is 100 µF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
1
ESR
+
MAX
2p C
f
OUT
CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR listed in the capacitor data sheet results in an acceptable output ripple
voltage:
ESR
× V
× V
(
– V
IN(MAX) OUT
)
MAX
OUT
V
(MAX) =
PP
N
× V
× L
× F
SW
× 0.8
C
IN(MAX)
OUT
(10)
Where:
ΔVPP is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is
zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and
54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus
one-half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
V
× V
(
– V
)
OUT
IN(MAX) OUT
1
x
I
=
COUT(RMS)
√12
V
× L
– F
× 0.8 × N
IN(MAX)
OUT
SW C
(11)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
For this design example, a single 100-µF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is a AVX
TPSD107M010R0080, rated at 10 V with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This
capacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.1-µF ceramic
bypass capacitor may also used, but is not included in this design.
Other capacitor types can be used with the TPS5420, depending on the needs of the application.
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Output Voltage Setpoint
The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5420 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 µF.
Catch Diode
The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus one-half the
peak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode
parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating the
power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of
3 A, and a forward voltage drop of 0.5 V.
Additional Circuits
Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to
those given for the design example, with a larger value output inductor and a lower closed-loop crossover
frequency.
U1
TPS5420D
L1
27 mH
C2
0.01 mF
TP5
10 V - 21 V
7
VIN
5 V
VIN
ENA
NC
1
8
4
BOOT
VOUT
5
2
3
6
ENA
C1
10 mF
+
PH
C3
100 mF
(See Note A)
D1
B340A
R1
10 kW
NC
VSNS
GND
R2
3.24 kW
A. C3 = Tantalum AVX TPSD107M010R0080
Figure 12. 10-V to 21-V Input to 5-V Output Application Circuit
Circuit Using Ceramic Output Filter Capacitors
Figure 13 shows an application circuit using all ceramic capacitors for the input and output filters that generates a
3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design example,
except for the selection of the output filter capacitor values and the design of the additional compensation
components required to stabilize the circuit.
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U1
TPS5420D
L1
18 mH
C2
0.01 mF
VIN 10-24 V
7
3.3 V
VIN
VIN
1
8
4
VOUT
BOOT
PH
5
2
3
6
EN
ENA
NC
C1
4.7 mF
C3
47 mF
C4
47 mF
D1
MRBS340
NC
VSNS
GND
PwPd
9
R1
10 kW
C7
0.1 mF
C4
150 pF
R2
5.9 kW
C6
1800 pF
R3
549 W
Figure 13. Ceramic Output Filter Capacitors Circuit
Output Filter Component Selection
Using Equation 11, the minimum inductor value is 17.9 µH. A value of 18 µH is chosen for this design.
When using ceramic output filter capacitors, the recommended LC resonant frequency should be no more than
7 kHz. Since the output inductor is already selected at 18 µH, this limits the minimum output capacitor value to:
1
C
(MIN) ≥
O
(2π × 7000)2 × L
O
(13)
The minimum capacitor value is calculated to be 29 µF. For this circuit a larger value of capacitor yields better
transient response. Two 47-µF output capacitors are used for C3 and C4. It is important to note that the actual
capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to
3.3 V, minimizing this effect.
External Compensation Network
When using ceramic output capacitors, additional circuitry is required to stabilize the closed-loop system. For this
circuit, the external components are R3, C5, C6, and C7. To determine the value of these components, first
calculate the LC resonant frequency of the output filter:
1
F
=
LC
2π √ L × C (EFF)
O
O
(14)
For this example, the effective resonant frequency is calculated as 4109 Hz.
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The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
V
O
Fp1 = 500000 ×
F
LC
(15)
(16)
(17)
Fz1 = 0.7 × F
LC
Fz2 = 2.5 × F
LC
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated usingEquation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 426 Hz, Fz1 = 2708 Hz
and Fz2 = 8898 Hz, the values of R3, C6 and C7 are determined using Equation 18, Equation 19, and
Equation 20:
1
C7 =
2π × Fp1 × (R1 || R2)
(18)
1
R3 =
2π × Fz1 × C7
(19)
1
C6 =
2π × Fz2 × R1
(20)
For this design, using the closest standard values, C7 is 0.1 µF, R3 is 590 Ω, and C6 is 1800 pF. C5 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5420 or other wide voltage range SWIFT devices,
see Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors (TI literature number SLVA237).
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
ǒǒV
0.230Ǔ ) V Ǔ* ǒI
LǓ* V
D
V
+ 0.87
* I
R
OUTMAX
INMIN
OMAX
D
OMAX
(21)
Where:
VINMIN is the minimum input voltage.
IOMAX is the maximum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
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The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
ǒǒV
0.110Ǔ ) V Ǔ* ǒI
LǓ* V
D
V
+ 0.12
* I
R
OUTMIN
INMAX
OMIN
D
OMIN
(22)
Where:
VINMAX is the maximum input voltage.
IOMIN is the minimum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
checked to ensure proper functionality.
Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5420. These
designs are based on certain assumptions, and always select output capacitors within a limited range of ESR
values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the
TPS5420. Equation 23 gives the nominal frequency response of the internal voltage-mode type-3 compensation
network:
s
s
ǒ1 )
Ǔ ǒ
1 )
Ǔ
2p Fz1
2p Fz2
H(s) +
s
s
s
s
ǒ Ǔ ǒ
Ǔ ǒ
1 )
Ǔ ǒ
1 )
Ǔ
1 )
2p Fp0
2p Fp1
2p Fp2
2p Fp3
(23)
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon = IOUT2 × Rds(on) × VOUT/VIN
Switching Loss: Psw = VIN × IOUT × 0.01
Quiescent Current Loss: Pq = VIN × 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated Junction Temperature: TJ = TA + Rth × Ptot
Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth × Ptot
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PERFORMANCE GRAPHS
The performance graphs (Figure 14 through Figure 20) are applicable to the circuit in Figure 11, TA = 25°C
(unless otherwise specified)
0.3
0.3
100
V
= 10.8 V
I
0.2
0.2
V
= 12 V
95
90
I
I
= 2 A
V
= 15 V
O
I
0.1
0
0.1
0
I
= 0 A
O
85
V
= 18 V
V
= 19.8 V
-0.1
-0.1
I
I
I
= 1 A
O
80
75
-0.2
-0.3
-0.2
-0.3
2
2
V - Input Voltage - V
I
0
0.5
1
1.5
2.5
3
0
0.5
1
1.5
2.5
3
0
0.5
1
1.5
2
2.5
3
I
- Output Current - A
O
I
- Output Current - A
O
Figure 14. Efficiency
vs Output Current
Figure 15. Output Regulation
vs Output Current
Figure 16. Input Regulation
vs Input Voltage
VIN = 100 mV/Div (AC Coupled)
VOUT = 20 mV/Div (AC Coupled)
V
OUT = 50 mV/Div (AC Coupled)
PH = 5 V/Div
PH = 5 V/Div
IOUT = 500 mA/Div
t - Time = 200 μs/Div
t - Time - 1 ms / Div
t - Time - 1 ms / Div
Figure 17. Input Voltage Ripple
and PH Node, IO = 3 A
Figure 18. Output Voltage Ripple
and PH Node, IO = 3 A
Figure 19. Transient Response,
IO Step 0.5 to 1.5 A
VIN = 10 V/Div
ENA = 2 V/Div
VOUT = 2 V/Div
VOUT = 2 V/Div
t - Time = 5 ms/Div
t - Time = 5 ms/Div
Figure 20. Startup Waveform,
VIN and VOUT
Figure 21. Startup Waveform,
ENA and VOUT
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS5420QDRQ1
ACTIVE
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS5420-Q1 :
Catalog: TPS5420
Enhanced Product: TPS5420-EP
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 1
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