TPS54286 [TI]
2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET; 2 -A双非同步转换器，集成高边MOSFET
| 型号： | TPS54286 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET |
| 文件： | 总52页 (文件大小：1211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54283, TPS54286
www.ti.com
SLUS749C–JULY 2007–REVISED OCTOBER 2007
2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET
1
FEATURES
CONTENTS
23
•
4.5-V to 28-V Input Range
Device Ratings
2
3
•
Output Voltage Range 0.8 V to 90% of Input
Voltage
Electrical Characteristics
Device Information
Application Information
Design Examples
9
•
•
Output Current Up to 2 A
12
32
44
Two Fixed Switching Frequency Versions:
–
–
TPS54283: 300 kHz
TPS54286: 600 kHz
Additional References
•
Two Selectable Levels of Overcurrent
Protection (Output 2)
DESCRIPTION
•
•
•
•
0.8-V 1.5% Voltage Reference
2.1-ms Internal Soft Start
TPS54283 and TPS54286 are dual output
non-synchronous buck converters capable of
supporting 2-A output applications that operate from a
4.5-V to 28-V input supply voltage, and require output
voltages between 0.8 V and 90% of the input voltage.
Dual PWM Outputs 180° Out-of-Phase
Ratiometric or Sequential Startup Modes
Selectable by a Single Pin
With internally-determined operating frequency, soft
start time, and control loop compensation, these
converters provide many features with a minimum of
•
•
•
•
•
•
100-mΩ Internal High-Side MOSFETs
Current Mode Control
Internal Compensation (See Page 16)
Pulse-by-Pulse Overcurrent Protection
Thermal Shutdown Protection at 148°C
14-Pin PowerPAD™ HTSSOP package
external components. Channel
1
overcurrent
protection is set at 3 A, while Channel 2 overcurrent
protection level is selected by connecting a pin to
ground, to BP, or left floating. The setting levels are
used to allow for scaling of external components for
applications not needing the full load capability of
both outputs.
APPLICATIONS
•
•
•
•
Set Top Box
Digital TV
Power for DSP
Consumer Electronics
The outputs may be enabled independently, or may
be configured to allow either ratiometric or sequential
startup sequencing. Additionally, the two outputs may
also be powered from different sources.
V
IN
TPS54283
1
2
3
4
5
6
7
PVDD1 PVDD2 14
BOOT1 BOOT2 13
OUTPUT1
OUTPUT2
SW1
GND
EN1
EN2
FB1
SW2 12
BP 11
SEQ 10
ILIM2
FB2
9
8
GND
UDG-07006
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS54283, TPS54286
www.ti.com
SLUS749C–JULY 2007–REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PART NUMBER
TPS54283PWP
TPS54283PWPR
TPS54286PWP
TPS54286PWPR
OPERATING FREQUENCY (kHz)
PACKAGE
MEDIA
Tube
UNITS (Pieces)
90
2000
90
300
Tape and Reel
Tube
Plastic 14-Pin HTSSOP
600
Tape and Reel
2000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
30
UNIT
PVDD1, PVDD2, EN1, EN2
BOOT1, BOOT2
SW1, SW2
VSW+ 7
–2 to 30
–3 to 31
6.5
Input voltage range
SW1, SW2 transient (< 50ns)
BP
V
SEQ, ILIM2
–0.3 to 6.5
–0.3 to 3
7
FB1, FB2
SW1, SW2 output current
BP load current
A
35
mA
Tstg
TJ
Storage temperature
Operating temperature
Soldering temperature
–55 to +165
–40 to +150
+260
°C
(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the
Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended
periods of time may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
MAX
28
UNIT
V
VPVDD2 Input voltage
TJ
Operating junction temperature
–40
+125
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
2k
UNIT
Human body model
CDM
1.5k
250
V
Machine Model
PACKAGE DISSIPATION RATINGS(1)(2)(3)
THERMAL IMPEDANCE
JUNTION-TO-THERMAL PAD
TA = +25°C, NO AIR FLOW
TA = +85°C, NO AIR FLOW
PACKAGE
(°C/W)
POWER RATING (W)
POWER RATING (W)
Plastic 14-Pin HTSSOP (PWP)
2.07(4)
1.6
1.0
(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002A).
(2) TI device packages are modeled and tested for thermal performance using printed circuit board designs outlined in JEDEC standards
JESD 51-3 and JESD 51-7.
(3) For application information, see the Power Derating section.
(4) TJ-A = +40°C/W
2
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
–40°C ≤ TJ ≤ +125°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY (PVDD)
VPVDD1
Input voltage range
Shutdown
4.5
28
V
VPVDD2
IDDSDN
IDDQ
VEN1 = VEN2 = VPVDD2
VFB = 0.9V, Outputs off
70
150
3.0
µA
Quiescent, non-switching
Quiescent, while-switching
1.8
5
mA
SW node unloaded; Measured as BP sink
current
IDDSW
VUVLO
Minimum turn-on voltage
Hysteresis
PVDD2 only
3.8
0.9
4.1
4.4
V
VUVLO(hys)
400
mV
CBP = 10 µF, EN1 and EN2 go low
simultaneously
(1)(2)
tSTART
Time from startup to softstart begin
2
ms
ENABLE (EN)
VEN1
Enable threshold
1.2
50
6
1.5
12
V
VEN2
Hysteresis
mV
µA
µs
IEN1
IEN2
Enable pull-up current
Time from enable to soft-start begin
VEN1 = VEN2 = 0 V
(1)
tEN
Other EN pin = GND
10
BP REGULATOR (BP)
BP
Regulator voltage
8 V < PVDD2 < 28 V
5
5.25
400
5.6
V
PVDD2 = 4.5 V; switching, no external load on
BP
BPLDO
Dropout voltage
mV
(1)
IBP
Regulator external load
Regulator short circuit
2
mA
IBPS
4.5 V < PVDD2 < 28 V
10
20
30
OSCILLATOR
TPS54283
TPS54286
255
510
310
630
140
375
750
fSW
Switching frequency
Clock dead time
kHz
ns
(1)
tDEAD
ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF)
VFB1
0°C < TJ < +85°C
788
786
800
812
812
Feedback input voltage
VFB2
mV
nA
µS
–40°C < TJ < +125°C
IFB1
Feedback input bias current
IFB2
3
50
gM1(1)
Transconductance
gM2(1)
30
SOFT START (SS)
TSS1
Soft start time
TSS2
1.5
2.1
2.7
ms
A
OVERCURRENT PROTECTION
ICL1
Current limit channel 1
Current limit channel 2
2.4
1.15
2.4
3.0
1.50
3.0
3.6
1.75
3.6
VILIM2 = VBP
ICL2
VILIM2 = (floating)
VILIM2 = GND
1.15
1.50
1.75
VUV1
Low-level output threshold to declare a fault
Hiccup timeout
Measured at feedback pin.
670
10
mV
ms
ns
VUV2
(1)
THICCUP
(1)
tON1(oc)
Minimum overcurrent pulse width
90
150
(1)
tON2(oc)
(1) Ensured by design. Not production tested.
(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower
BP capacitor value. More information can be found in the Input UVLO and Startup section.
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
–40°C ≤ TJ ≤ +125°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BOOTSTRAP
RBOOT1
From BP to BOOT1 or BP to BOOT2,
IEXT = 50 mA
Bootstrap switch resistance
18
Ω
RBOOT2
OUTPUT STAGE (Channel 1 and Channel 2)
TJ = +25°C, VPVDD2 = 8 V
–40°C < TJ < +125°C, VPVDD2 = 8 V
ISWx peak current > 1 A(4)
VFB = 0.9 V
100
100
100
(3)
RDS(on)
MOSFET on resistance plus bond wire resistance
mΩ
180
200
0
(3)
tON(min)
DMIN
Minimum controllable pulse width
Minimum Duty Cycle
ns
%
TPS54283 fSW = 300 kHz
90
85
95
90
2
%
DMAX
Maximum Duty Cycle
TPS54286 fSW = 600 kHz
Outputs OFF
%
ISW
Switching node leakage current (sourcing)
12
µA
THERMAL SHUTDOWN
(3)
TSD
Shutdown temperature
Hysteresis
148
20
(3)
TSD(hys)
°C
(3) Ensured by design. Not production tested.
(4) See Figure 14 for characteristics for ISWx peak current < 1 A.
4
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (NON-SWITCHING)
SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
2.1
140
120
100
80
VBP = 5.25 V
VPVDDx = 28 V
2.0
1.9
VPVDDx = 12 V
1.8
1.7
60
40
V
PVDDx = 4.5 V
1.6
1.5
20
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 1.
Figure 2.
UNDERVOLTAGE LOCKOUT THRESHOLD
ENABLE THRESHOLDS
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
4.2
1.25
EN(Off)
4.1
4.0
1.23
1.21
UVLO(On)
3.9
3.8
EN(On)
UVLO(Off)
1.19
1.17
1.15
3.7
3.6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 3.
Figure 4.
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
SOFT START TIME
vs
JUNCTION TEMPERATURE
SWITCHING FREQUENCY (300 kHz)
vs
JUNCTION TEMPERATURE
3.5
3.0
2.5
2.0
1.5
350
V
BP = 5.25 V
VBP = 5.25 V
330
310
290
270
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 5.
Figure 6.
SWITCHING FREQUENCY (600 kHz)
FEEDBACK BIAS CURRENT
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
680
660
640
5
VBP = 5.25 V
3
1
620
600
580
-1
-3
-5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 7.
Figure 8.
6
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
FEEDBACK VOLTAGE
vs
JUNCTION TEMPERATURE
OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL)
vs
JUNCTION TEMPERATURE
808
803
3.4
3.2
3.0
V
PVDDx = 24 V
798
793
2.8
2.6
V
PVDDx = 12 V
V
PVDDx = 5 V
788
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 9.
Figure 10.
OVERCURRENT LIMIT (CH2 LOW LEVEL)
SWITCHING NODE LEAKAGE CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.8
5
V
PVDDx = 24 V
4
3
2
1
1.6
1.4
V
PVDDx = 12 V
V
PVDDx = 5 V
1.2
-50
-25
0
25
50 75
100
125
-50
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
T
- Junction Temperature - °C
J
Figure 11.
Figure 12.
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
OVERCURRENT LIMIT
vs
SUPPLY VOLTAGE
MINIMUM CONTROLLABLE PULSE WIDTH
vs
LOAD CURRENT
400
350
T (°C)
A
OCL = 3.0 A
–40
3.5
3.0
0
T
= –40°C
A
25
85
300
250
200
150
2.5
T
= 0°C
A
2.0
1.5
OCL = 1.5 A
T
= 25°C
100
50
A
T
= 85°C
1.0
A
4
8
12
16
20
24
28
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
- Supply Voltage - V
DD
I
- Load Current - A
L
Figure 13.
Figure 14.
8
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
DEVICE INFORMATION
PIN CONNECTIONS
HTSSOP (PWP)
(Top View)
PVDD1
BOOT1
SW1
GND
EN1
1
2
3
4
5
6
7
14 PVDD2
13 BOOT2
12 SW2
11 BP
Thermal Pad
(bottom side)
10 SEQ
EN2
9
8
ILIM2
FB2
FB1
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin
to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small
resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor.
BOOT1
2
I
Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin
to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small
resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor.
BOOT2
BP
13
11
5
I
-
I
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-µF
to 10-µF X7R or X5R preferred) ceramic capacitor.
Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft start of
Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to
GND to force "always ON" operation.
EN1
Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start of
Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to
GND to force "always ON" operation.
EN2
FB1
6
7
I
I
Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for
Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from
Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated
output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback
Loop and Inductor-Capacitor (L-C) Filter section for further information.
Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for
Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from
Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated
Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback
Loop and Inductor-Capacitor (L-C) Filter section for further information.
FB2
8
4
9
I
-
I
GND
ILIM2
Ground pin for the device. Connect directly to Thermal Pad.
Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical
load currents (Output 1 load current much greater than Output 2 load current) to optimize component
scaling of the lower current output while maintaining proper component derating in a overcurrent fault
condition. The discrete levels are available as shown in Table 2. Note: An internal 2-resistor divider
(150-kΩ each) connects BP to ILIM2 and to GND.
Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a
low ESR ceramic capacitor of 10-µF or greater.
PVDD1
PVDD2
1
I
I
The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2
pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed to
GND with a low ESR ceramic capacitor of 10-µF or greater. The UVLO function monitors PVDD2 and
enables the device when PVDD2 is greater than 4.1 V.
14
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 is
enabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startup
where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating,
then both outputs is disabled immediately, and the output voltages decays according to the load that is
present. For this sequence configuration, tie EN1 to ground.
If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start after
Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1
is allowed to go high after the outputs have been operating, then both outputs will be disabled
immediately, and the output voltages decays according to the load that is present. For this sequence
configuration, tie EN2 to ground.
SEQ
10
I
If left floating, Output 1 and Output 2 start ratio-metrically when both outputs are enabled at the same
time. They will soft start at a rate determined by their final output voltage and enter regulation at the
same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also
operate independently
NOTE: An internal two resistor (150-kΩ each) divider connects BP to SEQ and to GND. See Table 1
Sequencing States.
Source (switching) output for Output 1 PWM. A snubber is recommended to reduce ringing on this
node. See SW Node Ringing for further information.
SW1
3
O
Source (switching) output for Output 2 PWM. A snubber is recommended to reduce ringing on this
node. See SW Node Ringing for further information.
SW2
12
-
O
-
Thermal Pad
This pad must be tied externally to a ground plane and the GND pin.
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SLUS749C–JULY 2007–REVISED OCTOBER 2007
BLOCK DIAGRAM
2
1
BOOT1
PVDD1
BP
CLK1
Level
Shift
Current
f(I
) + DC(ofst)
Comparator
DRAIN1
S
Q
Q
+
R
R
GND
FB1
4
7
+
f(I
)
DRAIN1
Overcurrent Comp
3
SW1
+
0.8 V
REF
BP
R
f(I
)
COMP
f(I
)
SLOPE1
MAX1
Weak
Soft Start
SD1
CLK1
Pull-Down
MOSFET
C
1
Anti-Cross
Conduction
COMP
VDD2
f(I
)
SLOPE1
Ramp
Gen 1
TSD
CLK1
1.2 MHz
Oscilator
Divide
by 2/4
6 mA
6 mA
f(I
)
SLOPE2
Ramp
Gen 2
EN1
EN2
5
6
SD1
Internal
Control
SD2
CLK2
UVLO
150 kW
SEQ 10
BP
FB1
FB2
Output
Undervoltage
Detect
150 kW
CLK2
13 BOOT2
14 PVDD2
BP
Level
Shift
Current
Comparator
FET
f(I
) + DC(ofst)
DRAIN2
Switch
S
R
R
Q
Q
+
GND
FB2
4
8
+
f(I
)
DRAIN2
Overcurrent Comp
12 SW2
+
0.8 V
REF
BP
R
f(I
)
COMP
f(I
)
SLOPE2
MAX2
Weak
Soft Start
2
SD2
CLK2
Pull-Down
MOSFET
C
Anti-Cross
Conduction
COMP
5.25-V
BP 11
PVDD2
Regulator
150 kW
BP
Level
Select
ILIM2
9
150 kW
0.8 V
REF
References
I
(Set to one of two limits)
MAX2
UDG-07007
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APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The TPS54283 and TPS54286 are dual output non-synchronous converters. Each PWM channel contains an
internally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable,
and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference,
clock oscillator, and output voltage sequencing functions.
DESIGN HINT
The TPS5428x contains internal slope compensation and loop compensation
components; therefore, the external L-C filter must be selected appropriately so that
the resulting control loop meets criteria for stability. This approach differs from an
externally-compensated controller, where the L-C filter is generally selected first, and
the compensation network is found afterwards. (See Feedback Loop and L-C Filter
Selection section.)
NOTE:
Unless otherwise noted, the term TPS5428x applies to both the TPS54283 and
TPS54286. Also, unless otherwise noted, a label with a lowercase x appended implies
the term applies to both outputs of the two modulator channels. For example, the term
ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given
are typical. Refer to the Electrical Characteristics for minimum and maximum values.
Calculations should be performed with tolerance values taken into consideration.
Voltage Reference
The bandgap cell common to both outputs, trimmed to 800 mV.
Oscillator
The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are
internally configured to operate on alternating switch cycles (that is, 180° out of phase).
Input Undervoltage Lockout (UVLO) and Startup
When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and
all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises
above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup
sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with
a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start begins, depending on the
SEQ mode of operation and the EN1 and EN2 settings.
Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be
higher or lower than PVDD2. (See the Dual Supply Operation section.)
Enable and Timed Turn On of the Outputs
Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to
PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the
associated output is enabled and soft start is initiated.
If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is
shut down and minimal functions are active. The total standby current from both PVDD pins is approximately
70 µA at 12-V input supply.
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An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is
applied to PVDDx (see Figure 15). After power is applied to PVDD2, the voltage on the ENx pin slowly decays
towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup
sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to
PVDD2, then omit these two components and tie the ENx pin to GND directly.
If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6µA
or 200 kΩ. A suggested value is 51 kΩ. This resistor value allows the ENx voltage to decay below the 1.2-V
threshold while the 6-µA bias current flows.
The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation 1.
t
DELAY
C =
farads
æ
ç
è
ö
÷
ø
V
- 2´I
´R
ENx
IN
R ´ ln
V
-I
´R
TH ENx
(1)
where:
•
•
•
R and C are the timing components
VTH is the 1.2-V enable threshold voltage
IENx is the 6µA enable pin biasing current
Other enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing
section.)
PVDD2
6 mA
C
ENx
PVDDx
PVDDx
1.2-V
Threshold
+
1.2 V
R
ENx
TPS5428x
V
OUTx
0
t
t
+ t
DELAY
DELAY SS
T - Time
Figure 16. Startup Delay with R-C on Enable
Figure 15. Startup Delay Schematic
DESIGN HINT
If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to
GND. This configuration allows the outputs to start immediately on valid application of
PVDD2.
If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the
output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains
in the OFF state. (See the Bootstrap for N-Channel MOSFET section.)
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Output Voltage Sequencing
The TPS5428x allows single-pin programming of output voltage startup sequencing. During power-on, the state
of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behave
as described in Table 1.
Table 1. Sequence States
SEQ PIN STATE
MODE
EN1
EN2
Ignored by the device when VEN2
enable threshold voltage
<
Tie EN1 to < enable threshold voltage
for BP to be active when VEN2
enable threshold voltage
>
BP
Sequential, Output 2 then Output 1
Active
Tie EN1 to > enable threshold voltage
for low quiescent current (BP inactive)
when VEN2 > enable threshold voltage
Ignored by the device when VEN1
enable threshold voltage
<
Tie EN2 to < enable threshold voltage
for BP to be active when VEN1
enable threshold voltage
>
GND
Sequential, Output 1 then Output 2
Active
Tie EN2 to > enable threshold voltage
for low quiescent current (BP inactive)
when VEN1 > enable threshold voltage
Independent or Ratiometric, Output 1
and Output 2
Active. EN1 and EN2 must be tied
together for Ratiometric startup.
Active. EN1 and EN2 must be tied
together for Ratiometric startup.
(floating)
If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start approximately 400
µs after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2
is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the
output voltages decay according to the load that is present.
If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start approximately
400 µs after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If
EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately,
and the output voltages decay according to the load that is present.
SEQ = BP
Sequential
SEQ = GND
Sequential
CH2 then CH1
CH1 then CH2
5-V VOUT1
(2 V/div)
5-V VOUT1
(2 V/div)
3.3-V VOUT2
(2 V/div)
3.3-V VOUT2
(2 V/div)
T - Time - 1 ms/div
Figure 17. SEQ Pin TIed to BP
T - Time - 1 ms/div
Figure 18. SEQ Pin Tied to GND
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DESIGN HINT
An R-C network connected to the ENx pin may be used in addition to the SEQ pin in
sequential mode to delay the startup of the first output voltage. This approach may be
necessary in systems with a large number of output voltages and elaborate voltage
sequencing requirements. See Enable and Timed Turn On of the Outputs.
If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at
the same time. Output 1 and Output 2 soft start at a rate that is determined by the respective final output
voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently,
then the two outputs also operate independently.
5-V VOUT1
(2 V/div)
3.3-V VOUT2
(2 V/div)
T - Time - 1 ms/div
Figure 19. SEQ Pin Floating
Soft Start
Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of
two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total
ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft start interval, the
TPS5428x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the
output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the
internal 0.8 V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains
at the reference voltage.
NOTE:
To avoid a disturbance in the output voltage during the stepping of the digital soft
start, a minimum output capacitance of 50 µF is recommended. Also see Feedback
Loop and Inductor-Capacitor (L-C) Filter Selection Once the filter and compensation
components have been established, laboratory measurements of the physical design
should be performed to confirm converter stability.
During the soft start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six
PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the
Output Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected.
DESIGN HINT
If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low
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to support the desired regulation voltage by the time Soft Start has completed, then
the output UV circuit may trip and cause a hiccup in the output voltage. In this case,
use a timed delay startup from the ENx pin to delay the startup of the output until the
PVDDx voltage has the capability of supporting the desired regulation voltage. See
Operating Near Maximum Duty Cycleand Maximum Output Capacitance for related
information.
Output Voltage Regulation
Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse
width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider
connecting the output node, the FBx pin, and GND (see Figure 20). Assuming the value of the upper voltage
setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by
Equation 2.
VREF
R2 = R1´
VOUT - VREF
(2)
where
•
VREF is the internal 0.8-V reference voltage
TPS5428x
1
2
3
4
5
6
7
PVDD1 PVDD2 14
BOOT1 BOOT2 13
OUTPUT1
SW1
GND
EN1
EN2
FB1
SW2 12
BP 11
R1
SEQ 10
ILIM2
FB2
9
8
R2
UDG-07011
Figure 20. Feedback Network for Channel 1
DESIGN HINT
There is a leakage current of up to 12 µA out of the SW pin when a single output of
the TPS5428x is disabled. Keeping the series impedance of R1 + R2 less than 50 kΩ
prevents the output from floating above the referece voltage while the controller output
is in the OFF state.
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Feedback Loop and Inductor-Capacitor (L-C) Filter Selection
In the feedback signal path, the output voltage setting divider is followed by an internal gM-type error amplifier
with a typical transconductance of 30 µS. An internal series connected R-C circuit from the gM amplifier output to
ground serves as the compensation network for the converter. The signal from the error amplifier output is then
buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node.
Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to
drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 21.
NOTE:
Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow
pulse width operation, especially at load currents less than 1 A. See SW Node
Ringing for further information on reducing noise on the SWx node.
TPS5428x
BOOT
I
- I
COMP SLOPE
PWM to
Switch
x2
Error Amplifier
I
SLOPE
0.8 V
REF
+
I
+
COMP
FB
Offset
f(I
)
DRAIN
R
COMP
SW
11.5 kW
C
COMP
R
C
COMP
COMP
(kW)
700
700
(pF)
TPS54283
TPS54286
40
20
UDG-07012
Figure 21. Feedback Loop Equivalent Circuit
A more conventional small signal equivalent block diagram is shown in Figure 22. Here, the full closed loop
signal path is shown. Because the TPS5428x contains internal slope compensation and loop compensation
components, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria
for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally
selected first, and the compensation network is found afterwards. To find the appropriate L and C filter
combination, the Output-to-Vc signal path plots (see the next section) of gain and phase are used along with
other design criterial to aid in finding the combinations that best results in a stable feedback loop.
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VIN
VC
VOUT
+
+
VREF
Modulator
_
_
Filter
Current
Feedback
Network
Compensation
Network
Figure 22. Small Signal Equivalent Block Diagram
Inductor-Capacitor (L-C) Selection
The following figures plot the TPS5428x Output-to-Vc gain and phase versus frequency for various duty cycles
(10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple current levels. The loop
response curve selected to compensate the loop is based on the duty cycle of the application and the ripple
current in the inductor. Once the curve has been selected and the inductor value has been calculated, the output
capacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A brief
example follows the curves.
Note that the internal error amplifier compensation is optimized for output capacitors with an ESR zero frequency
between 20kHz and 60kHz. See the following sections for further details.
GAIN AND PHASE
vs
FREQUENCY
GAIN AND PHASE
vs
FREQUENCY
100
80
270
225
180
135
90
100
80
270
225
180
135
90
Duty Cycle %
Duty Cycle %
Gain Phase
Gain Phase
10
30
50
70
90
10
30
50
70
90
60
40
60
40
45
45
20
0
20
0
0
0
-45
-45
-20
-90
-20
-90
100
1 k
10 k
f - Frequency -Hz
100 k
1 M
100
1 k
10 k
100 k
1 M
Figure 23. TPS54283 at 200-mAp-p Ripple Current
Figure 24. TPS54283 at 400-mAp-p Ripple Current
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GAIN AND PHASE
vs
FREQUENCY
GAIN AND PHASE
vs
FREQUENCY
100
85
270
225
180
135
90
100
270
225
180
135
90
Duty Cycle %
Gain Phase
10
30
50
70
90
80
70
60
40
55
40
45
25
45
20
0
Duty Cycle %
Gain Phase
0
10
0
10
30
50
70
90
-45
-5
-45
-90
-20
-90
-20
100
1 k
10 k
f - Frequency -Hz
100 k
1 M
100
1 k
10 k
f - Frequency - Hz
100 k
1 M
Figure 25. TPS54283 at 600-mAp-p Ripple Current
Figure 26. TPS54286 at 200-mAp-p Ripple Current
GAIN AND PHASE
vs
FREQUENCY
GAIN AND PHASE
vs
FREQUENCY
100
85
270
100
80
270
225
180
135
90
225
180
135
90
70
60
40
55
40
45
25
45
20
0
Duty Cycle %
Gain Phase
Duty Cycle %
Gain Phase
0
10
10
0
10
30
50
70
90
30
50
-45
-5
-45
70
90
-90
-20
-20
-90
100
1 k
10 k
f - Frequency -Hz
100 k
1 M
100
1 k
10 k
f - Frequency - Hz
100 k
1 M
Figure 27. TPS54286 at 400-mAp-p Ripple Current
Figure 28. TPS54286 at 600-mAp-p Ripple Current
Maximum Output Capacitance
With internal pulse-by-pulse current limiting and a fixed soft start time, there is a maximum output capacitance
which may be used before startup problems begin to occur. If the output capacitance is large enough so that the
device enters a current limit protection mode during startup, then there is a possibility that the output will never
reach regulation. Instead, the TPS5428x will simply shut down and attempt a restart as if the output were short
circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is
given by Equation 3:
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R1
(1 +
) ´ TS
VREF
tSS
R2
R1
1
+
(1 +
I
CLx - VREF
)(1 -
)
COUTmax
=
R2
RLOAD
VREF
2 ´ VIN ´ L
(3)
Minimum Output Capacitance
Ensure the value of capacitance selected for closed loop stability is compatible with the requirements of Soft
Start.
Modifying The Feedback Loop
Within the limits of the internal compensation, there is flexibility in the selection of the inductor and output
capacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, thereby
increasing the required value of output capacitance. A smaller capacitor could also be used, increasing the
resonant frequency, and increasing the overall loop bandwidth—perhaps at the expense of adequate phase
margin.
The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between
20kHz and 60kHz. It is possible, with additional feedback compensation components, to use capacitors with
higher or lower ESR zero frequencies. For either case, the components C1 and R3 (ref. Figure 29 ) are added to
re-compensate the feedback loop for stability. In this configuration a low frequency pole is followed by a higher
frequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used, and the
desired closed loop frequency response.
TPS5428x
1
2
3
4
5
6
7
PVDD1 PVDD2 14
BOOT1 BOOT2 13
OUTPUT1
SW1
GND
EN1
EN2
FB1
SW2 12
BP 11
C2
R1
SEQ 10
C1
R3
ILIM2
FB2
9
8
R2
UDG-07013
Figure 29. Optional Loop Compensation Components
NOTE:
Once the filter and compensation components have been established, laboratory
measurements of the physical design should be performed to confirm converter
stability.
Using High-ESR Output Capacitors
If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to
instability. To compensate, a small R-C series connected network is placed in parallel with the lower voltage
setting divider resistor (Ref Figure 29). The values of the components are determined such that a pole is placed
at the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loop
stability.
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The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency to
the desired zero frequency.
R2
R3 =
æ
ç
ç
è
ö
æ
ö
fZERO(desired)
÷
÷
-1
ç
ç
è
÷
÷
ø
fESR(zero)
ø
(4)
where
•
•
fESR(zero) is the ESR zero frequency of the output capacitor
fZERO(desired) is the desired frequency of the zero added to the feedback. This frequency should be placed
between 20 kHz and 60 kHz to ensure good loop stability.
The value of the capacitor is calculated in Equation 5.
1
C1=
2p´R ´ f
EQ ESR(zero)
(5)
where:
•
REQ is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1
and R2) in series with R3.
1
R
= R3 +
EQ
æ
ç
è
ö
÷
ø
1
1
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
+
R1
R2
(6)
Using All Ceramic Output Capacitors
With low ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this
case, (Ref Figure 29) resistor R3 is set equal to 1/2 R2. This will lower the gain by 6dB, reduce the crossover
frequency, and improve phase margin.
The value of C1 is found by determining the frequency to place the low frequency pole. The minimum frequency
to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal soft
start. (Ref. Soft Start) The upper bound for the pole frequency is determined by the operating frequency of the
converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7. Keep
component tolerances in mind when selecting the desired pole frequency.
1
C1=
2p´R ´ f
EQ POLE(desired)
(7)
where:
•
fPOLE(desired)is the desired pole frequency between 1 kHz and 3 kHz (TPS54x83) or 1 kHz and 6 kHz
(TPS54x86).
•
REQ is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1
and R2) in series with R3.
1
R
= R3 +
EQ
æ
ç
è
ö
÷
ø
1
1
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
+
R1
R2
(8)
If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage setting divider
resistor (Ref. C2 in Equation 9).
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1
R1
R2´R3
C2 =
´ 1+
2p´ fC ´R1
æ
ö
(
)
ç
ç
è
÷
÷
ø
R2 + R3
(
)
(9)
where
•
fC is the unity gain crossover frequency (approximately 50 kHz for most designs following these guidelines)
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Example: TPS54286 Buck Converter Operating at 12-V Input, 3.3-V Output and 400-mAp-p Ripple Current
First, the steady state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the duty
cycle is approximated using Equation 10.
VOUT + VDIODE
3.3 + 0.5
d =
=
= 30%
V
IN + VDIODE
12 + 0.5
(10)
The filter inductor is then calculated; see Equation 11.
V
- V
OUT
12 - 3.3
1
IN
L =
´ d´ T =
´ 0.3´
= 10.9mH
S
DI
0.4
600000
L
(11)
A custom-designed inductor may be used for the application, or a standard value close to the calculated value
may be used. For this example, a standard 10-µH inductor is used. Using Figure 27, find the 30% duty cycle
curve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. This
curve is the resonant frequency that must be compensated. Any frequency wthin an octave of the peak may be
used in calculating the capacitor value. In this example, 6 kHz is used.
1
1
C =
=
= 70mF
2
)
2
)
L ´ 2´ p´ f
(
10´10-6 ´ 2´3.14´ 6000
(
RES
(12)
A 68-µF capacitor may be used as a bulk capacitor, with 10-µF of ceramic bypass capacitance in parallel. To
ensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should be
placed a decade above the resonant frequency.
1
1
RESR
<
=
» 40 mW
-6
2´ 3.14´10´ 6000´ 68´ 10
( )
2´ p´10´ fRES ´ C
(13)
The resulting loop gain and phase are shown in Figure 30. Based on measurement, loop crossover is 45 kHz
with a phase margin of 60 degrees.
GAIN AND PHASE
vs
FREQUENCY
80
70
60
50
40
180
135
90
Phase
45
0
30
20
10
0
-45
-90
Gain
-135
-10
-20
-180
100
1 k
10 k
f - Frequency - Hz
100 k
1 M
Figure 30. Example Loop Result
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Bootstrap for the N-Channel MOSFET
A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully
enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%,
allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and
BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the
MOSFET gate is derived from the voltage on this capacitor.
To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to
GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light
load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the
SW node toward ground and allow the bootstrap capacitor to charge.
Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It
must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge
requirement of the MOSFET being used.
DESIGN HINT
For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and
82 nF.
DESIGN HINT
For 5-V input applications, connect PVDDx to BP directly. This connection bypasses
the internal control circuit regulator and provides maximum voltage to the gate drive
circuitry. In this configuration, shutdown mode IDDSDN will be the same as quiescent
IDDQ.
Light Load Operation
There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous
converter is to operate in the discontinuous conduction mode (DCM) at an average load current less than
one-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of
input voltage, output voltage, inductor value, and operating frequency, as shown in Equation 14.
V
IN - VOUT
1
IDCM
=
´
´ d ´ TS
2
L
(14)
During discontinuous comduction mode operation the commanded pulse width may become narrower than the
capability of the converter to resolve. To maintain the output voltage within regulation, skipping of switching
pulses at light load conditions is a by-product of that mode. This condition may occur if the output capacitor is
charged to a value greater than the output regulation voltage, and there is insufficient load to discharge the
capacitor. A by-product of pulse skipping is an increase in the peak-to-peak output ripple voltage.
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Skipping
SW Waveform
SW Waveform
V
= 12 V
IN
V
= 5 V
OUT
V
OUT
Ripple
V
OUT
Ripple
Inductor
Current
Steady State
IN = 12 V
VOUT = 5 V
Inductor
Current
V
Figure 31. Steady State
Figure 32. Skipping
DESIGN HINT
If additional output capacitance is required to reduce the output voltage ripple during
DCM operation, be sure to recheck Feedback Loop and Inductor-Capacitor (L-C)
Filter Selection and Maximum Output Capacitance sections.
SW Node Ringing
A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to
decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than
30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design
techniques for reducing ringing and noise.
SW Node Snubber
Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and
capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an
R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range.
DESIGN HINT
A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω)
connected from SW to GND reduces the ringing on the SW node.
Bootstrap Resistor
A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, thereby
reducing the rising edge ringing of the SW node.
DESIGN HINT
A resistor with a value between 1Ω and 3Ω may be placed in series with the bootstrap
capacitor to reduce ringing on the SW node.
DESIGN HINT
Placeholders for these components should be placed on the initial prototype PCBs in
case they are needed.
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Output Overload Protection
In the event of an overcurrent during soft start on either output (such as starting into an output short),
pulse-by-pulse current limiting and PWM frequency division (see below) are in effect for that output until the
internal soft start timer ends. At the end of the soft start time, a UV condition is declared and a fault is declared.
During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to
GND) are turned ON. This process ensures that both outputs discharge to GND in the event that overcurrent is
on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting
to restart. "Frequency Division" means if an overcurrent pulse is detected, six clock cycles are skipped before a
next PWM pulse is initiated, effectively dividing the operating frequency by six and preventing excessive current
build up in the inductor.
In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is
in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that
follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault
condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON.
This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the
other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart.
The overcurrent threshold for Output 1 is set nominally at 3.0 A. The overcurrent level of Output 2 is determined
by the state of the ILIM2 pin. The ILIM setting of Output 2 is not latched in place and may be changed during
operation of the converter.
Table 2. Current Limit Threshold Adjustment for
Output 2
ILIM2 Connection
BP or GND
OCP Threshold for Output 2
1.5 A nominal setting
(floating)
3.0 A nominal setting
DESIGN HINT
The overcurrent protection threshold refers to the peak current in the internal switch.
Be sure to add one-half of the peak inductor ripple current to the dc load current in
determining how close the actual operating point is to the OCP threshold.
Operating Near Maximum Duty Cycle
If the TPS5428x operates at maximum duty cycle, and if the input voltage is insufficient to support the output
voltage (at full load or during a load current transient), then there is a possibility that the output voltage will fall
from regulation and trip the output UV comparator. If this should occur, the TPS5428x protection circuitry will
declare a fault and enter a shut down-and-restart cycle.
DESIGN HINT
Ensure that under ALL conditions of line and load regulation, there is sufficient duty
cycle to maintain output voltage regulation.
The operating duty cycle under continuous conduction (neglecting losses) is approximated using Equation 15.
VOUT + VDIODE
d =
V
+ VDIODE
IN
(15)
where
•
VDIODE is the voltage drop of the rectifier diode
Dual Supply Operation
It is possible to operate a TPS5428x from two supply voltages. If this application is desired, then the sequencing
of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level
requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies
energy to the output. In addition, Output 1 must be held in the disabled state (EN1 high) until there is sufficient
voltage on PVDD1 to support Output 1 in regulation. (See the Operating Near Maximum Duty Cycle section.)
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The preferred sequence of events is:
1. PVDD2 rises above the input UVLO voltage
2. PVDD1 rises with Output 1 disabled until PVDD1 rises above level to support Output 1 regulation.
With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.
DESIGN HINT
An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough
period of time to ensure that PVDD1 can support Output 1 load.
Cascading Supply Operation
It is possible to source PVDD1 from Output 2 as depicted in Figure 33 and Figure 34. This configuration may be
preferred if the input voltage is high, relative to the voltage on Output 1.
V
IN
TPS54283
1
2
3
4
5
6
7
PVDD1 PVDD2 14
BOOT1 BOOT2 13
OUTPUT1
OUTPUT2
SW1
GND
EN1
EN2
FB1
SW2 12
BP 11
SEQ 10
ILIM2
FB2
9
8
UDG-07015
Figure 33. Schematic Showing Cascading PVDD1 from Output 2
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PVDD2
Output2
PVDD1
Output1
T - Time
Figure 34. Waveforms Resulting from Cascading PVDD1 from Output 2
In this configuration, the following conditions must be maintained:
1. Output 2 must be of a voltage high enough to maintain regulation of Output 1 under all load conditions.
2. The sum of the current drawn by Output 2 load plus the current into PVDD1 must be less than the overload
protection current level of Output 2.
3. The method of output sequencing must be such that the voltage on Output 2 is sufficient to support Output 1
before Output 1 is enabled. This requrement may be accomplished by:
a. a delay of the enable function
b. selecting sequential sequencing of Output 1 starting after Output 2 is in regulation
Multiphase Operation
The TPS5428x is not designed to operate as
http://www.power.ti.com for appropriate device selection.
a two-phase single-output voltage converter. See
Bypass and FIltering
As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise
immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.
1. PVDD1 to GND: Use a 10-µF ceramic capacitor
2. PVDD2 to GND: Use a 10-µF ceramic capacitor
3. BP to GND: Use a 4.7-µF to 10-µF ceramic capacitor
Over-Temperature Protection and Junction Temperature Rise
The over-temperature thermal protection limits the maximum power to be dissipated at a given operating ambient
temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is
limited by the maximum allowable junction operating temperature. The device junction temperature is a function
of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature
should reach the thermal shutdown level, the TPS5428x shuts off both PWMs and remains in this state until the
die temperature drops below the hysteresis value, at which time the device restarts.
The first step to determine the device junction temperature is to calculate the power dissipation. The power
dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by
each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the
external rectifier diode. To find the conduction loss, first find the RMS current through the upper switch MOSFET.
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2
)
æ
ç
ö
÷
æ
ç
ç
è
ö
÷
÷
ø
DI
(
2
)
OUTPUTx
I
=
D ´
I
(
+
RMS(outputx)
OUTPUTx
ç
ç
è
÷
÷
ø
12
(16)
where
•
•
•
D is the duty cycle
IOUTPUTx is the DC output current
ΔIOUTPUTx is the peak ripple current in the inductor for Outputx
Notice the impact of the operating duty cycle on the result.
Multiplying the result by the RDS(on) of the MOSFET gives the conduction loss.
2
P
= I
´R
DS(on)
D(cond)
RMS(outputx)
(17)
(18)
The switching loss is approximated by:
2
(VIN) ´ CJ ´ fS
PD(SW)
=
2
where
•
•
where CJ is the parallel capacitance of the rectifier diode and snubber (if any)
fS is the switching frequency
The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal
regulator.
P = P
+ P
+ P
+ P
+ V ´Iq
D
D(cond)output1
D(SW)output1
D(cond)output2
D(SW)output2 IN
(19)
The temperature rise of the device junction depends on the thermal impedance from junction to the mounting pad
(See the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient. The
thermal impedance from the thermal pad to ambient depends on the PCB layout (PowerPAD interface to the
PCB, the exposed pad area) and airflow (if any). See the PCB Layout Guidelines, Additional References section.
The operating junction temperature is shown in Equation 20.
T = T + P ´ q + qTH(pad-amb)
TH(pkg)
(
)
J
A
D
(20)
Power Derating
The TPS5428x delivers full current at ambient temperatures up to +85°C if the thermal impedance from the
thermal pad to ambient is sufficiently low enough to maintain the junction temperature below the thermal
shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the
junction temperature at or below the thermal shutdown level. Figure 35 illustrates the power derating for elevated
ambient temperature under various airflow conditions. Note that these curves assume that the PowerPAD is
properly soldered to the recommended thermal pad. (See the References section for further information.)
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POWER DISSIPATION
vs
AMBIENT TEMPERATURE
1.8
1.6
LFM = 250
LFM = 500
1.4
1.2
LFM = 0
LFM = 150
1.0
0.8
0.6
0.4
LFM
0
150
250
500
0.2
0
0
20
40
60
80
100
120
140
T
- Ambient Temperature - °C
A
Figure 35. Power Derating Curves
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PowerPAD Package
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and
should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via
is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the
package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13
mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of
the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material
should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping
prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the
package. (See the Additional References section.)
PCB Layout Guidelines
The layout guidelines presented here are illustrated in the printed circuit board layout example given in Figure 36
and Figure 37.
•
The PowerPAD must be connected to a low current (signal) ground plane having a large copper surface area
to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer of
heat away from the IC.
•
•
•
Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace.
Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces.
Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor and
rectifier diode. Avoid using vias in this loop.
•
Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power
path as possible. Placement directly under the diode and the switch node is recommended.
•
•
Locate the bootstrap capacitor close to the BOOT pin to minimize the gate drive loop.
Locate voltage setting resistors and any feedback components over the ground plane and away from the
switch node and the rectifier diode to input capacitor ground connection.
•
•
•
Locate snubber components (if used) close to the rectifier diode with minimal loop area.
Locate the BP bypass capacitor very close to the IC; a minimal loop area is recommended.
Locate the output ceramic capacitor close to the inductor output terminal between the inductor and any
electrolytic capacitors, if used.
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L2
VOUT2
C14
D2
R8
C17
GND
C11
R9
C16
U1
VIN
C6
R2
C1
C10
D1
GND
GND
C5
C7
R3
VOUT1
L1
Figure 36. Top Layer Copper Layout and Component Placement
Figure 37. Bottom Layer Copper Layout
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DESIGN EXAMPLES
Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter
The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual
non-synchronous buck regulator using the TPS54283 converter. Design Example List of Materials and Table 4,
Definition of Symbols is found at the end of this section.
PARAMETER
NOTES AND CONDITIONS
MIN
NOM
MAX
UNIT
INPUT CHARACTERISTICS
VIN
IIN
Input voltage
6.9
12.0
1.6
12
13.2
2.0
20
V
A
Input current
VIN = nom, IOUT = max
VIN = nom, IOUT = 0 A
No load input current
mA
OUTPUT CHARACTERISTICS
VOUT1
VOUT2
Output voltage 1
Output voltage 2
Line regulation
Load regulation
VIN = nom, IOUT = nom
VIN = nom, IOUT = nom
VIN = min to max
4.8
3.2
5.0
3.3
5.2
3.4
1%
1%
V
IOUT = min to max
VOUT(ripple
Output voltage ripple
VIN = nom, IOUT = max
50
mVPP
)
IOUT1
IOUT2
Output current 1
Output current 2
VIN = min to max
VIN = min to max
0
0
2.0
2.0
Output overcurrent channel
1
A
IOCP1
IOCP2
VIN = nom, VOUT = VOUT1 = 5%
VIN = nom, VOUT = VOUT2 = 5%
ΔIOUT = 1 A @ 3 A/µs
2.4
2.4
3
3
3.5
3.5
Output overcurrent channel
2
Transient response ΔVOUT
from load transient
200
1
mV
ms
Transient response settling
time
SYSTEM CHARACTERISTICS
fSW
Switching frequency
Full load efficiency
250
0
310
370
60
kHz
η
85%
Operating temperature
range
TJ
25
°C
+
+
+
Figure 38. Design Example Schematic
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Design Procedure
Duty Cycle Estimation
The first step is to estimate the duty cycle of each switching FET.
V
+ V
FD
OUT
D
»
max
V
+ V
FD
IN(min)
(21)
(22)
V
+ V
FD
OUT
D
»
min
V
+ V
FD
IN(max)
Using an assumed forward drop of 0.5 V for a schottky rectifier diode, the Channel 1 duty cycle is approximately
40.1% (minimum) to 48.7% (maximum) while the Channel 2 duty cycle is approximately 27.7% (minimum) to
32.2% (maximum).
Inductor Selection
The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far
enough from the minimum overcurrent trip level to ensure reliable operation.
For both Channel 1 and Channel 2, the maximum inductor ripple current is 600 mA. The inductor size is
estimated in Equation 23.
V
- V
OUT
1
IN(max)
L
»
´ D
´
min
min
I
f
SW
LRIP(max)
(23)
The inductor values are
•
•
L1 = 18.3 µH
L2 = 15.3 µH
The next higher standard inductor value of 22 µH is used for both inductors.
The resulting ripple currents are :
V
- V
OUT
1
IN(max)
I
»
´D
´
RIPPLE
min
L
f
SW
(24)
Peak-to-peak ripple currents of 0.498 A and 0.416 A are estimated for Channel 1 and Channel 2 respectively.
The RMS current through an inductor is approximated by Equation 25.
2
1
2
)
I
=
I
(L(avg) )
+
I
(
RIPPLE
L rms
(
)
12
(25)
(26)
and is approximately 2.0 A for both channels.
The peak inductor current is found using:
1
IL peak » IOUT(max)
+
IRIPPLE
(
)
2
An inductor with a minimum RMS current rating of 2.0 A and minimum saturation current rating of 2.25 A is
required. A Coilcraft MSS1278-223ML 22-µH, 6.8-A inductor is selected.
Rectifier Diode Selection
A schottky diode is selected as a rectifier diode for its low forward voltage drop. Allowing 20% over VIN for
ringing on the switch node, the required minimum reverse break-down voltage of the rectifier diode is:
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V BR R min ³ 1.2´ V
IN
( ) (
)
(27)
The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used.
The average current in the rectifier diode is estimated by Equation 28.
I
» I
´ 1- D
( )
OUT max
D avg
(
)
(
)
(28)
For this design, 1.2-A (average) and 2.25 A (peak) is estimated for Channel 1 and 1.5-A (average) and 2.21-A
(peak) for Channel 2.
An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward
voltage drop of 0.4 V at 2 A.
The power dissipation in the diode is estimated by Equation 29.
PD max » VFM ´ID avg
)
(
)
(
(29)
For this design, the full load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2.
Output Capacitor Selection
The TPS54283's internal compensation limits the selection of the output capacitors. From Figure 24, the internal
compensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30.
1
COUT
=
2
)
4´ p2 ´ f
´L
(
RES
(30)
Solving for COUT using
•
•
fRES = 3 kHz
L = 22 µH
The resulting is COUT = 128 µF. The output ripple voltage of the converter is composed of the ripple voltage
across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the
maximum ESR allowable to meet the output ripple requirements the total ripple is partitioned, and the equation
manipulated to find the ESR.
VRIPPLE(tot) - VRIPPLE(cap) VRIPPLE(tot)
=
D
ESR(max)
=
-
IRIPPLE
IRIPPLE
fS ´ COUT
(31)
Based on 128 µF of capacitance, 300-kHz switching frequency and 50-mV ripple voltage plus rounding up the
ripple current to 0.5 A, and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a
maximum allowable ESR of 87 mΩ.
To meet the ripple voltage requirements, a low-cost 100-µF electrolytic capacitor with 400 mΩ ESR (C5, C17)
and two 10-µF ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-mΩ ESR are selected. From the
datasheets for the ceramic capacitors, the parallel combination provides an impedance of 28 mΩ @ 300 kHz for
14 mV of ripple.
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Voltage Setting
The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 kΩ and 50 kΩ to
maintain a balance between power dissipation and noise sensitivity. For this design, 20 kΩ is selected.
The lower resistors, R4 and R7 are found using the following equations.
V
´R2
- V
FB
R4 =
R7 =
V
OUT1
FB
(32)
(33)
V
´R9
- V
FB
V
OUT2
FB
•
•
•
•
R2 = R9 = 20 kΩ
VFB = 0.80 V
R4= 3.80 kΩ (3.83 kΩ standard value is used)
R7= 6.40 kΩ (6.34 kΩ standard value is used)
Compensation Capacitors
Checking the ESR zero of the output capacitors:
1
f
=
ESR(zero)
2´ p´ C´ESR
(34)
•
•
•
C = 100 µF
ESR = 400 mΩ
ESR(zero) = 3980 Hz
Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4
and R7 to compensate for the electrolytic capacitors' ESR and add a zero about 40 kHz.
R4
R5 =
æ
ç
ç
è
ö
æ
ö
fZERO(desired)
÷
÷
-1
ç
ç
è
÷
÷
ø
fESR(zero)
ø
(35)
•
•
•
•
•
•
fESR(zero) = 4 kHz
fESR(desired)= 40 kHz
R4 = 3.83 kΩ
R5 = 424 Ω(422Ω selected)
R7 = 6.34 kΩ
R8 = 702 Ω (698Ω selected)
1
R
= R5 +
EQ
æ
ç
è
ö
÷
ø
1
1
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
+
R2
R4
(36)
(37)
•
•
•
R2 = R9 = 20 kΩ
REQ1 = 3.63 kΩ
REQ2 = 5.51 kΩ
1
C8 =
2´ p´R ´ f
EQ ESR(zero)
•
•
C8 = 10.9 nF (10 nF selected)
C15 = 7.22 nF (6800 pF selected)
36
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Input Capacitor Selection
The TPS54283 datasheet recommends a minimum 10-µF ceramic input capacitor on each PVDD pin. These
capacitor must be capable of handling the RMS ripple current of the converter. The RMS current in the input
capacitors is estimated by Equation 38.
2
)
æ
ç
ö
÷
æ
ç
ç
è
ö
÷
÷
ø
DI
(
2
)
OUTPUTx
I
=
D ´
I
(
+
RMS(outputx)
OUTPUTx
ç
ç
è
÷
÷
ø
12
(38)
•
IRMS(CIN) = 0.43 A
One 1210 10-µF, 25 V, X5R ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for
each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to
ensure the capacitors maintains sufficient capacitance at the working voltage.
Boot Strap Capacitor
To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nF
boot strap capacitor is used.
ILIM
Current limit must be set above the peak inductor current IL(peak). Comparing IL(peak) to the available minimum
current limits, ILIM is left floating for the highest current limit level.
SEQ
The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied
together, the two supplies start-up ratiometrically. Alternatively, SEQ could be connected to BP or GND to
provide sequential start-up.
Power Dissipation
The power dissipation in the TPS54283 is composed of FET conduction losses, switching losses and internal
regulator losses. The RMS FET current is found using Equation 39.
2
æ
ç
ç
ö
÷
÷
DI
)
(
+
Outputx
(
)
2
)
IRMS(Outputx)
=
D´
I
(
OUTPUT
12
ç
ç
è
÷
÷
ø
(39)
(40)
This results in 1.05-A RMS for Channel 1 and 0.87-A RMS for Channel 2.
Conduction losses are estimated by:
2
P
= R
´ I
CON
(
DS on QSW rms
(
)
( )
)
Conduction losses of 198 mW and 136 mW are estimated for Channel 1 and Channel 2 respectively.
The switching losses are estimated in Equation 41.
2
V
(
»
´ C + C
´ f
)
OSS SW
(
)
DJ
IN max
(
)
P
SW
2
(41)
From the data sheet of the MBRS320, the junction capacitance is 658 pF. Since this is large compared to the
output capacitance of the TPS54x8x the FET capacitance is neglected, leaving switching losses of 17 mW for
each channel.
The regulator losses are estimated in Equation 42.
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PREG » IDD ´ V
+ IBP ´ V
- VBP
IN max
)
)
(
IN max
(
)
(
(42)
With no external load on BP (IBP=0) the regulator power dissipation is 66 mW.
Total power dissipation in the device is the sum of conduction and switching for both channels plus regulator
losses.
The total power dissipation is PDISS=0.198+0.136+0.017+0.017+.066 = 434 mW.
Design Example Test Results
The following results are from the TPS54283-001 EVM.
V
IN
= 12 V
SW 3.3 V
SW 5 V
t − Time − 40 ns/div
Figure 39. Switching Node Waveforms
100
90
80
70
60
50
40
30
20
100
V
= 9.6 V
IN
90
80
70
60
50
40
30
20
V
= 9.6 V
IN
V
= 12.0 V
IN
V
= 12.0 V
IN
V
= 13.2 V
IN
V
= 13.2 V
IN
V
= 5.0 V
(V)
V
= 3.3 V
(V)
OUT
V
OUT
V
IN
IN
9.6
9.6
12.0
13.2
12.0
13.2
10
0
10
0
0
0.3
0.6
I
0.9
1.2
1.5
1.8
2.1
0
0.3
0.6
0.9
- Load Current - A
LOAD
1.2
1.5
1.8
2.1
- Load Current - A
I
LOAD
Figure 40. 5.0-V Output Efficiency vs. Load Current
Figure 41. 3.3-V Output Efficiency vs. Load Current
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1.005
1.004
1.003
1.005
1.004
1.003
V
= 13.2 V
IN
1.002
1.001
1.002
1.001
All Input
Voltages
V
= 12.0 V
IN
1.000
0.999
1.000
0.999
V
= 5.0 V
(V)
OUT
V
0.998
0.997
0.998
0.997
V
= 9.6 V
IN
IN
9.6
12.0
13.2
0.996
0.996
0.995
0.995
0
0.4
0.8
1.2
1.6
2.0
0
0.4
0.8
1.2
1.6
2.0
I
- Load Current - A
I
OUT
- Load Current - A
OUT
Figure 42. 5.0-V Output Voltage vs. Load Current
Figure 43. 3.3-V Output Voltage vs. Load Current
80
60
40
20
0
180
135
90
45
0
-20
-40
-45
-90
Gain
Phase
5.0 V
3.3 V
-60
-80
-135
-180
1 k
10 k
f - Frequency -Hz
100 k
300 k
Figure 44. Example 1 Loop Response
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Table 3. Design Example List of Materials
REFERENCE
DESIGNATOR
QTY
VALUE
100 µF
DESCRIPTION
SIZE
PART NUMBER
MANUFACTURER
1
2
1
2
1
1
C1
Capacitor, Aluminum, 25V, ꢀ 20%
Capacitor, Ceramic, 25V, X5R 20%
Capacitor, Ceramic, 10V, X5R 20%
Capacitor, Ceramic, 25V, X7R, 20%
Capacitor, Ceramic, 25V, X7R, 20%
E-can
EEEFC1E101P
Panasonic
C10, C11
C12
10 µF
1210
0805
0603
0603
F-can
C3216X5R1E106M TDK
4.7 µF
470 pF
6.8 nF
100 µF
Std
Std
C14, C16
C15
Std
Std
Std
Std
C17, C5
Capacitor, Aluminum, 10V, 20%, FC
Series
EEEFC1A101P
Panasonic
4
1
2
2
2
C3, C4, C18, C19 10 µF
Capacitor, Ceramic, 6.3V, X5R 20%
Capacitor, Ceramic, 25V, X7R, 20%
Capacitor, Ceramic, 25V, X7R, 20%
Diode, Schottky, 3-A, 30-V
0805
0603
0603
SMC
C2012X5R0J106M
Std
TDK
C8
10 nF
Std
C9, C13
D1, D2
L1, L2
0.033 µF
MBRS320
22 µH
Std
Std
MBRS330T3
MSS1278-153ML
On Semi
Coilcraft
Inductor, Power, 6.8A, 0.038 Ω
0.484 x
0.484
2
1
2
1
1
1
1
R2, R9
R5
20 kΩ
422 Ω
10 Ω
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 5%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
0603
0603
0603
0603
0603
0603
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
TI
R6, R10
R8
698 Ω
3.83 kΩ
6.34 kΩ
R4
R7
U1
TPS54283 DC-DC Switching Converter
w/ FET
HTSSOP TPS54283PWP
-14
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Table 4. Definition of Symbols
CDJ
Average junction capacitance of the rectifier diode from 0V to VIN(max)
Average output capacitance of the switching MOSFET from 0V to VIN(max)
Output Capacitor
COSS
COUT
D(max)
D(min)
Maximum steady state operating duty cycle
Minimum steady state operating duty cycle
Maximum allowable output capacitor ESR
Switching frequency
ESR(max)
fSW
IBP
Output Current of BP regulator due to external loads
Switching quiescent current with no load on BP
Average diode conduction current
IDD
ID(avg)
ID(peak)
IIN(avg)
IIN(rms)
IL(avg)
Peak diode conduction current
Average input current
Root mean squared (RMS) input current
Average inductor current
IL(rms)
Root mean squared (RMS) inductor current
Peak current in inductor
IL(peak)
ILRIP(max)
L(min)
Maximum allowable inductor ripple current
Minimum inductor value to maintain desired ripple current
Maximum designed output current
IOUT(max)
IRMS(cin)
IRIPPLE
IQSW(rms)
PCON
Root mean squared (RMS) current through the input capacitor
Inductor peak to peak ripple current
Root mean squared current through the switching MOSFET
Power loss due to conduction through switching MOSFET
Maximum power dissipation in diode
PD(max)
RDS(on)
PSW
Drain to source resistance of the switching MOSFET when “ON”
Power loss due to switching
PREG
Power loss due to the internal regulator
Output Voltage of BP regulator
VBP
V(BR)R(min)
VFB
Minimum reverse breakdown voltage rating for rectifier diode
Regulated feedback voltage
VFD
Forward voltage drop across rectifier diode
Power stage input voltage
VIN
VOUT
Regulated output voltage
VRIPPLE(cap)
VRIPPLE(tot)
Peak to Peak ripple voltage due to ideal capacitor (ESR = 0ꢀ
)
Maximum allowable peak to peak output ripple voltage
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Additional Design Examples
Example 2: 24-V to 12-V and 24-V to 5-V
For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch
node and a 30 V schottky diode is selected. A higher resistance feedback network is chosen for the 12 V output
to reduce the feedback current.
+
+
Figure 45. 24-V to 12-V and 24-V to 5-V Using the TPS54283
V
= 24 V
= 2 A
IN
V
= 24 V
= 2 A
IN
I
OUT
I
OUT
V
V
OUT
OUT
(5 V/div)
(5 V/div)
T − Time − 10 ns / div
T − Time − 10 ns / div
Figure 46. Switch Node Ringing Without Snubber and
Boost Resistor
Figure 47. Switch Node Ringeing With Snubber and
Boost Resistor
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90
80
70
60
50
40
30
20
V
= 12 V
OUT
V
= 5 V
OUT
V
= 24 V
IN
V
(V)
OUT
5
12
10
0
0
0.5
1.0
1.5
2.0
2.5
I
- Load Current - A
OUT
Figure 48. Efficiency vs. Load Current
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Example 3: 5-V to 3.3V and 5-V to 1.2 V
For a low input voltage application, the TPS54286 is selected for reduced size and all ceramic output capacitors
are used. 22-µF input capacitors are selected to reduce input ripple and lead capacitors are placed in the
feedback to boost phase margin.
Figure 49. 5-V to 3.3V and 5-V to 1.2 V
80
60
180
135
90
100
90
80
70
60
50
40
30
20
V
= 1.2 V
OUT
40
V
= 3.3 V
OUT
20
45
V
= 1.2 V
OUT
0
0
-20
-40
-60
-80
-45
V
= 5.0 V
IN
-90
V
(V)
OUT
Gain
Phase
WIth Lead
1.2
3.3
-135
Without Lead
10
0
-180
1 k
10 k
f - Frequency -Hz
100 k
300 k
0
0.5
1.0
1.5
2.0
2.5
I
- Load Current - A
OUT
Figure 50. Efficiency vs. Load Current
Figure 51. Example 3 Loop Response
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ADDITIONAL REFERENCES
Related Devices
The following parts have characteristics similar to the TPS54283/6 and may be of interest.
Table 5. Devices Related to the TPS54283 and TPS54286
TI LITERATURE
DEVICE
DESCRIPTION
NUMBER
SLUS642
TPS40222
5-V Input, 1.6-A Non-Synchronous Buck Converter
TPS54383 /
TPS54386
SLUS774
3-A Dual Non-Synchronous Converter with Integrated High-Side MOSFET
References
These references, design tools and links to additional references, including design software, may be found at
http:www.power.ti.com
Table 6. References
TI LITERATURE
DESCRIPTION
NUMBER
SLMA002
SLMA004
SLUP206
SLVA057
SLUP173
PowerPAD Thermally Enhanced Package Application Report
PowerPAD™ Made Easy
Under The Hood Of Low Voltage DC/DC Converters. SEM1500 Topic 5, 2002 Seminar Series
Understanding Buck Power Stages in Switchmode Power Supplies
Designing Stable Control Loops. SEM 1400, 2001 Seminar Series
Package Outline and Recommended PCB Footprint
The following pages outline the mechanical dimensions of the 14-Pin PWP package and provide
recommendations for PCB layout.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2007
PACKAGING INFORMATION
Orderable Device
TPS54283PWP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
14
14
14
14
14
14
14
14
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS54283PWPG4
TPS54283PWPR
TPS54283PWPRG4
TPS54286PWP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS54286PWPG4
TPS54286PWPR
TPS54286PWPRG4
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS54283PWPR
TPS54286PWPR
PWP
PWP
14
14
SITE 60
SITE 60
7.0
7.0
5.6
5.6
1.6
1.6
8
8
12
12
Q1
Q1
330
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS54283PWPR
TPS54286PWPR
PWP
PWP
14
14
SITE 60
SITE 60
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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