TPS542A52 [TI]

具有遥感功能的 4V 至 18V 输入、电压模式、15A 同步 SWIFT™ 降压转换器;


型号：	TPS542A52
厂家：	TEXAS INSTRUMENTS
描述：	具有遥感功能的 4V 至 18V 输入、电压模式、15A 同步 SWIFT™ 降压转换器转换器
文件：	总37页 (文件大小：3313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS542A52

ZHCSM63B – SEPTEMBER 2020 – REVISED OCTOBER 2021

具有差分遥感功能的 TPS542A52 4V 至 18V 输入、15A

同步降压转换器

1 特性

2 应用

•

集成的 9.1mΩ 和 2.6mΩ MOSFET 可支持高达 15A

•

无线通信

的输出电流

模拟前端电源

测试和测量设备

医疗成像

•

0.5V 至 5.5V 输出电压范围

具有可选内部补偿的固定频率电压控制模式

7 种频率设置可选（400kHz 至 2.2MHz）

与外部时钟同步

3 说明

全差分遥感

TPS542A52 是一款具有差分遥感功能的高效同步降

压转换器。该器件提供具有引脚搭接、可选内部补偿的

固定频率电压控制模式，可降低系统成本和复杂性。

PWM 可通过 SYNC 引脚与外部时钟保持同步。其他

关键特性包括 PFM（可提高轻负载效率）、低关断静

态电流消耗、可调 UVLO（通过 EN 引脚实现）以及单

调启动至预偏置状态。TPS542A52 是一款无铅器件，

完全符合 RoHS 标准，无需豁免。

6 个可选过流限值、4 个软启动压摆率

单调启动至预偏置输出

EN 引脚，支持可调节的输入 UVLO

电源正常状态指示器

17µA 典型关断静态电流消耗

可选 FCCM 或 PFM，可实现出色轻负载效率

工作结温范围：–40°C 至 +150°C

4mm × 4.5mm VQFN 封装

器件信息

使用 TPS542A52 并借助 WEBENCH^®Power

Designer 创建定制设计方案

器件型号

TPS542A52

封装⁽¹⁾

封装尺寸（标称值）

VQFN (33)

4.50mm × 4.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100%

95%

90%

85%

80%

PVIN

V_IN

BOOT

AVIN

V_OUT

VREG

RSP

RSN

FSEL

COMP

SS/PFM

ILIM

PGD

SYNC

SREF

VSET

1.2MHz_12VIN

1.0MHz_12VIN

0.8MHz_12VIN

0.6MHz_12VIN

1.2MHz_5VIN

1.0MHz_5VIN

0.8MHz_5VIN

0.6MHz_5VIN

75%

70%

AGND

PGND

Output Current (A)

10 11 12 13 14 15

简化版原理图

1V_OUT条件下的典型效率

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBU2

TPS542A52

www.ti.com.cn

ZHCSM63B – SEPTEMBER 2020 – REVISED OCTOBER 2021

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................4

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................5

6.6 Typical Characteristics................................................8

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................14

7.4 Device Functional Modes..........................................20

8 Application and Implementation..................................21

8.1 Application Information............................................. 21

8.2 Typical Application.................................................... 21

9 Power Supply Recommendations................................26

10 Layout...........................................................................27

10.1 Layout Guidelines................................................... 27

10.2 Layout Example...................................................... 28

11 Device and Documentation Support..........................29

11.1 Device Support........................................................29

11.2 接收文档更新通知................................................... 29

11.3 支持资源..................................................................29

11.4 Trademarks............................................................. 29

11.5 Electrostatic Discharge Caution..............................29

11.6 术语表..................................................................... 29

12 Mechanical, Packaging, and Orderable

Information.................................................................... 30

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (October 2020) to Revision B (October 2021)

Page

•

Changed "V_VRSF" to "V_RSP" for I_Q– PFM Mode current test condition in the Electrical Characteristics ............ 5

Changed R_FSELtest condition values under Switching Frequency in the Electrical Characteristics ................. 5

Changed "K" to "k" under Switching Frequency in the Electrical Characteristics .............................................. 5

Changed R_ILIMtest condition values under Current Sense and Protection in the Electrical Characteristics .....5

Changed R_FSELvalues in 表 7-1 ......................................................................................................................15

Changed R_COMPvalues in 表 7-2 .....................................................................................................................15

Changed R_SS/PFMvalues in 表 7-5 ...................................................................................................................17

Changed R_ILIMvalues in 表 7-7 ....................................................................................................................... 18

Updated all figures in 节 8.2.1.4 to demonstrate new R_FSEL, R_COMP, R_SS/PFMand R_ILIMvalues......................25

Changes from Revision * (September 2020) to Revision A (October 2020)

Page

•

更新了图 3-1 ...................................................................................................................................................... 1

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ZHCSM63B – SEPTEMBER 2020 – REVISED OCTOBER 2021

5 Pin Configuration and Functions

ILIM

SS/PFM

28 SW

AGND

SYNC

RSN

PGND

RSP

AGND

图 5-1. RJM Package 33-Pin VQFN Top View

表 5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

AGND

8, 25

Ground of the internal analog and digital circuitry

Power input to the controller. Tie this pin to PVIN. It is best to use an RC filter from PVIN

such as 10-Ω and 100 nF to 1 μF.

AVIN

BOOT

COMP

Gate drive voltage for high-side FET. Connect a bootstrap capacitor between this pin and

SW.

A resistor to ground sets the compensation network. This pin can be grounded to select the

default compensation and reduce BOM count.

Enable pin. Float to enable, enable/disable with an external signal, or adjust the input

undervoltage lockout with a resistor divider.

A resistor to ground sets the switching frequency of the converter. This pin can be grounded

to select the default switching frequency to reduce BOM count.

FSEL

ILIM

A resistor to ground sets the overcurrent protection limit. This pin can be grounded to select

default settings and reduce BOM count.

PGD

Open-drain power good status

PGND

13-16, 29-33

18-20

Power ground. These pins are internally connected to the return of the internal low-side FET.

Power inputs to the power stage. Low impedance bypassing of these pins to PGND is

critical. At least 10 nF to 100 nF capacitor from PVIN to PGND is required.

PVIN

RSN

RSP

Remote sense ground return

Remote sense connection to V_OUT

No connect

N/A

No connect

SREF

1.2-V nominal system reference

A resistor to ground sets the soft-start slew rate and PFM mode. To reduce BOM count, this

pin can be grounded to use the default soft-start rate and enable PFM mode.

SS/PFM

SYNC

This pin is a clock input for synchronizing the oscillator.

26-28

Switch node output of the converter. Connect this pin to the output inductor to ground.

Bypass pin for the internal power stage LDO. It is recommended to use a 4.7-μF ceramic

capacitor.

VREG

VSET

I/O

Output voltage reference for the control loop. This must be the mid-point of a resistive

divider from SREF to AGND. Set this voltage to be 1/5 of the desired V_OUT

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–2

MAX

UNIT

PVIN, AVIN

PVIN - SW

BOOT

27.5

5.5

BOOT-SW

Input

EN, SYNC

FS, COMP, ILIM, SS/PFM, SREF, VSET

1.98

RSP

PGD

Output

SW transient (<10 ns)

VREG

–0.3

–40

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

T_J= -40℃ to 150℃ (unless otherwise noted)

MIN

NOM

MAX

UNIT

PVIN, AVIN

VOUT

IOUT

Input voltage

Output voltage

Output current

0.5

5.5

3.3

SYNC

FS, COMP, ILIM, SS/

PFM,SREF, VSET

1.8

T_J

Junction temperature

–40

150

°C

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6.4 Thermal Information

TPS542A52

THERMAL METRIC⁽¹⁾

RJM (VQFN)

33 PINS

54.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJA

Junction-to-ambient thermal resistance EVM PCB Layout

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

22.3

R_θJC(top)

R_θJB

23.3

17.7

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.7

Ψ_JB

17.5

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

T_J= -40℃ to 150℃ (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY (PVIN, AVIN PINS)

V_IN

PVIN and AVIN supply range

Shutdown current

PFM Mode current

EN < 0.4 V

I_Q

µA

V_IN= 12 V, V_OUT= 1 V, EN > 1.2 V, no

switching, V_RSP> 5*V_VSET

1800

ENABLE and UVLO (EN PIN)

V_ENEnable threshold: ON/OFF

Rising and falling

1.2

–0.6

–5

Enable threshold – 50 mV

Enable threshold + 50 mV

I_EN

Enable input current

µA

UVLO (AVIN, PVIN PINS)

UVLO rising threshold

3.75

3.50

3.85

3.6

AVIN, PVIN UVLO falling threshold

Hysteresis

3.7

0.25

INTERNAL REGULATOR, POWER STAGE (VREG PIN)

V_VREG

LDO output voltage

Output current limit

LDO output current = 0A

LDO output current = 30mA

V_VREG= 4.7V

4.3

4.7

4.96

220

120

170

f_sw= 2.2 MHz, output current = 15 A,

V_VREG= 4.7V

Nominal output current

UVLO rising yhreshold

UVLO falling threshold

UVLO hysteresis

2.8

2.6

0.2

V_REG(UVLO)

CONTROL REFERENCE VOLTAGE (SREF PIN)

Tolerance included in RSP/RSN

accuracy

V_SREF

SREF output voltage

1.2

ISREF

SREF current sourcing capability

Resistance > 6 kΩ

200

µA

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MAX UNIT

ZHCSM63B – SEPTEMBER 2020 – REVISED OCTOBER 2021

T_J= -40℃ to 150℃ (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS

MIN

TYP

OUTPUT VOLTAGE REGULATION ACCURACY

Total internal accuracy, measured at the

RSP and RSN pins = 5*VSET, VSET =

0.2V, –40 to 150°C

Output Voltage Accuracy; Vout = 1V

-15

-13

9.0

Total internal accuracy, measured at the

RSP and RSN pins = 5*VSET, VSET =

0.2V, –40 to 125°C

Output Voltage Accuracy; Vout =1V

Output Voltage Accuracy; Vout = 1V

Output Voltage Accuracy; Vout = 0.8V

Output Voltage Accuracy; Vout = 1.2V

Total internal accuracy, measured at the

RSP and RSN pins = 5*VSET, VSET =

0.2V, 0 to 105°C

-11.0

-15

Total internal accuracy, measured at the

RSP and RSN pins = 5*VSET, VSET =

0.16V, –40 to 150°C

Total internal accuracy, measured at the

RSP and RSN pins = 5*VSET, VSET =

0.24V, –40 to 150°C

-15

Total internal accuracy, measured at the

Output Voltage Accuracy; Vout = 5.5V ⁽¹⁾RSP and RSN pins = 5*VSET, VSET =

1.1V, –40 to 150°C

-30

REMOTE SENSE AMPLIFIER

Unity gain bandwidth ⁽¹⁾

Open loop gain ⁽¹⁾

MHz

Slew rate ⁽¹⁾

2.5

V/us

Input common mode range ⁽¹⁾

-0.05

1.1

Input offset voltage (RSA and EA

combined offset trim)

Vos

0.25

(1)

SWITCHING FREQUENCY

FSW_1MHz Switching frequency 1MHz

R_FSEL= 35.7 kΩ or Short

R_FSEL= 7.5 kΩ

900

-10

1000

1100

kHz

FSW_400kH

Switching frequency 400 kHz

FSW_600kH

Switching frequency 600 kHz

R_FSEL= 18.2 kΩ

R_FSEL= 26.1 kΩ

-10

FSW_800kH

Switching frequency 800 kHz

FSW_1.2MH

Switching frequency 1.2 MHz

R_FSEL= 47.5 kΩ

R_FSEL= 61.9 kΩ

R_FSEL= 78.7 kΩ

-9

-10

FSW_2MHz Switching frequency 2 MHz

FSW_2.2MH

Switching frequency 2.2 MHz

Minimum On-Time

Minimum Off-Time

SYNC

V_IH(SYNC)

V_IL(SYNC)

High-level input voltage

EN = High

EN = Low

1.35

Low-level input voltage

0.8

Sync input minimum pulse width

SYNC pin frequency range from f_SW

Δf_SYNC

–10%

1.35

15%

V_IH(SYNC)-

High-level input voltage to enter

programming mode when EN = 0V

PROG

POWER STAGE

R_ds(on)1

R_ds(on)2

Main high-side MOSFET on-resistance V_VREG= 4.7 V, T_J= 25°C

Main Low-side MOSFET on-resistance V_VREG= 4.7 V, T_J= 25°C

9.1

2.6

mΩ

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T_J= -40℃ to 150℃ (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS

VREG = 4.7V, T_J= 25°C

MIN

TYP

MAX UNIT

Dead-time between low-side off and

high-side on transition

Tdt(L-H)

Dead-time between high-side off and

low-side on transition

Tdt(H-L)

VREG = 4.7V, T_J= 25°C

CURRENT SENSE AND PROTECTION

IS1

OC limit HS FET

OC limit LS FET 6

OC limit LS FET 5

OC limit LS FET 4

OC limit LS FET 3

OC limit LS FET 2

OC limit LS FET 1

Negative OC limit LS FET

R_ILIM= 61.9 kΩ

R_ILIM= 47.5 kΩ

R_ILIM= 35.7 kΩ

R_ILIM= 26.1 kΩ

R_ILIM= 18.2 kΩ

R_ILIM= 7.5 kΩ

17.60

14.78

11.56

9.26

16.5

18.48

15.62

IS2

10.5

13.56

6.96

11.60

9.60

4.66

5.5

-8.5

IS2

Zero-cross detection comparator trip

point

135

SOFT-START COUNTER

SS setting 1: 2.0MHz CLK

V_VSET= 0.1 V to 0.28 V

0.45

0.9

1.8

3.6

SS setting 2: 1.0MHz CLK

SS setting 3: 0.5MHz CLK

SS setting 4: 0.25MHz CLK

t_SS

INTERNAL BOOTSTRAP SWITCH

Forward voltage

V_VREG(BOOT), I_F= 10 mA, T_A= 25^°C

0.16

500

0.3

OUTPUT VOLTAGE OVERSHOOT REDUCTION

POWER-ON DELAY

Power-on delay time

From EN to SS; V_IN> 4 V

POWER GOOD and OV/UV WARNING

OV warning level

RSP rising (fault)

105

100

110

105

115

109

93.5

OV warning level

V_RSP

RSP falling (reset)

5*V_VSET

UV warning level

RSP falling (fault)

UV warning level

PGD delay time

RSP rising (reset)

Delay from SS finish to PGD high

PGD FET On Resistance, I_PGOOD=5mA

500

5.8

µs

Ω

R_ds(on)PGDFET

4.1

9.1

OUTPUT OVERVOLTAGE PROTECTION (OVP)

OVP trip level

V_RSP

RSP rising (fault), V_VSET≤ 1.04 V

RSP falling

110

115

120

5*V_VSET

OVP reset level

OVP delay

100

OUPUT UNDERVOLTAGE PROTECTION (UVP)

5*V_SET

V_RSP

UVP detect voltage

UV delay

100

THERMAL SHUTDOWN

T_SDN

Shutdown temperature⁽¹⁾

Hysteresis⁽¹⁾

155

165

⁰C

(1) Specified by design. Not production tested.

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6.6 Typical Characteristics

Measured at 25°C unless otherwise specified

100%

95%

90%

85%

80%

75%

70%

65%

2.8

2.6

2.4

2.2

5V_IN

9V_IN

12V_IN

14V_IN

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

5V_IN

9V_IN

12V_IN

14V_IN

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_OUT= 1 V

f_SW= 1 MHz, FCCM

V_OUT= 1 V

f_SW= 1 MHz, FCCM

图 6-1. Efficiency vs Output Current

图 6-2. Power Loss vs Output Current

100%

5V_INFCCM

5V_INDCM

12V_INFCCM

12V_INDCM

2.8

2.6

2.4

2.2

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

5V_INFCCM

5V_INDCM

12V_INFCCM

12V_INDCM

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_OUT= 1 V

f_SW= 1 MHz, DCM versus FCCM

V_OUT= 1 V

f_SW= 1 MHz, DCM versus

FCCM

图 6-3. Efficiency vs Output Current

图 6-4. Power Loss vs Output Current

100%

9V_IN

12V_IN

14V_IN

4.5

95%

90%

85%

80%

75%

70%

3.5

2.5

1.5

9V_IN

12V_IN

14V_IN

0.5

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_OUT= 5 V

f_SW= 400 kHz, FCCM

V_OUT= 5 V

f_SW= 400 kHz, FCCM

图 6-5. Efficiency vs Output Current

图 6-6. Power Loss vs Output Current

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1.015

1.012

1.009

1.006

1.003

1.015

1.012

1.009

1.006

1.003

5V_IN25C

5V_IN-40C

5V_IN85C

5V_IN105C

12V_IN25C

12V_IN-40C

12V_IN85C

12V_IN105C

5V_IN25C

5V_IN-40C

5V_IN85C

5V_IN105C

12V_IN25C

12V_IN-40C

12V_IN85C

12V_IN105C

0.997

0.994

0.991

0.988

0.997

0.994

0.991

0.988

0.985

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_OUT= 1 V

f_SW= 1 MHz, FCCM

V_OUT= 1 V

f_SW= 1 MHz, DCM

图 6-7. Load Regulation

图 6-8. Line Regulation

5.05

5.04

5.03

5.02

5.01

110

105

100

4.99

4.98

4.97

4.96

Nat conv

100 LFM

200 LFM

400 LFM

9V_IN25C

9V_IN-40C

9V_IN85C

12V_IN25C

12V_IN-40C

12V_IN85C

4.95

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_IN= 12 V

V_OUT= 5 V

f_SW= 400 KHz,

FCCM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1 MHz

图 6-10. Ambient Temperature vs Output Current

图 6-9. Line Regulation

110

105

100

110

105

100

Nat conv

100 LFM

200 LFM

400 LFM

100 LFM

200 LFM

400 LFM

Output Current (A)

10 11 12 13 14 15

Output Current (A)

10 11 12 13 14 15

V_IN= 12 V

V_OUT= 5 V

f_SW= 600 kHz

V_IN= 5.5 V

V_OUT= 1 V

f_SW= 2.2 MHz

图 6-11. Ambient Temperature vs Output Current

图 6-12. Ambient Temperature vs Output Current

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V_IN= 5.5 V

V_OUT= 1 V

f_SW= 2.2 MHz

V_IN= 12 V

V_OUT= 1 V

f_SW= 1 MHz

图 6-14. Thermal Image at 14-A Output Current

图 6-13. Thermal Image at 15-A Output Current

V_IN= 12 V

V_OUT= 5 V

f_SW= 0.6 MHz

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-15. Thermal Image at 12-A Output Current

图 6-16. 100% Pre-biased Start-up by EN at 0-A

Output Current

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-17. 90% Pre-biased Start-up by EN at 0-A

图 6-18. 50% Pre-biased Start-up by EN at 0-A

Output Current

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V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-19. Start-up and Shutdown by EN at 0-A

图 6-20. Steady State at 0-A Output Current

Output Current

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-21. Steady State at 10-A Output Current

图 6-22. Switch Node Ringing and Dead-Time at

10-A Output Current

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-23. 20-A Overcurrent Protection by Chroma

图 6-24. Short Overcurrent Protection Hiccup by

Electronic Load

Chroma Electronic Load

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V_IN= 12 V

V_OUT= 1 V

f_SW= 1.2 MHz BOM

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-25. Overvoltage Protection, Negative OCP,

then Undervoltage Protection by Load Step Down

图 6-26. Load Transient 2 A to 12 A to 2 A at 20 A/

μs

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.0 MHz BOM

图 6-27. Load Transient in DCM to FCM 0.5 A to 10.5 A to 0.5 A at 1 A/μs

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7 Detailed Description

7.1 Overview

The TPS542A52 is a high-efficiency, single-channel, synchronous buck converter with integrated n-channel

MOSFETs. The device suits low-output voltage point-of-load applications with 15-A or lower current. The

TPS542A52 has a maximum operating junction temperature of 150°C making it suitable for high-ambient

temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V, and the output

voltage range is 0.5 V to 5.5 V. The device features a fixed-frequency, voltage-control mode with a switching

frequency range of 400 kHz to 2.2 MHz allowing for efficiency and size optimization when selecting output filter

components. The controller features selectable internal compensation that makes the device easy to use with

low external component count. The internal compensation networks support a wide range of output inductance

and capacitance, supporting all types of capacitors. The controller uses a digital PWM modulator that allows for

very narrow on-times with low jitter, making it ideal for high-frequency and high-step down ratio applications. The

switching frequency of the device can be synchronized to an external clock applied to the SYNC pin.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Enable and Adjustable Undervoltage Lockout

The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold

voltage (typically 1.2 V), the device starts operation. If the EN pin voltage is pulled below the threshold voltage,

the regulator stops switching and enters low power shutdown.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device.

The EN pin can also be externally driven high or low.

For adjustable input undervoltage lockout (UVLO), connect the EN pin to the middle point of an external resistor

divider. Once the EN pin voltage exceeds the threshold, an additional 5 µA of hystersis current is added to

facilitate UVLO hysteresis. 方程式 1 shows the calculation of resistor divider network.

VIN

I_H

I_P

R_HS

R_LS

V_EN

图 7-1. EN UVLO

V_START- V_STOP

R^HS=

R^LS=

I_H

R^HS∂ V_EN

V_STOP- V_EN+ RHS I +I

(

)

V_EN= 1.2V; I_P= 0.6mA; I_H= 5mA

(1)

7.3.2 Input and VREG Undervoltage Lockout Protection

The TPS542A52 provides fixed VIN and VREG UVLO thresholds and hysteresis. The typical VIN turnon

threshold is 3.85 V and hystersis is 0.25 V. The typical VREG turnon threshold is 2.8 and hysteresis is 0.2

V. There is no power-up sequence. Once all of the UVLO requirements have been met and the EN pin voltage

exceeds the enable threshold, the converter begins operation.

7.3.3 Voltage Reference and Setting the Output Voltage

The device has a 1.2-V reference that comes out on the SREF pin. To set the reference voltage of the converter,

connect the VSET pin to the mid-point of a resistor divider between SREF and AGND. TI recommends that the

total impedance of this divider network be > 6 kΩ. Do not connect anything other than a resistor divider network

to SREF.

There is an internal 5:1 resistor divider between the RSP and RSN feedback pins, so the VSET voltage must be

set to 1/5 of the desired output voltage. VSET can be programmed to any value between 0.1 and 1.1 V.

7.3.4 Remote Sense Function

RSP and RSN pins are used for remote sensing purposes. Always connect RSP to the positive sensing point of

the load, and always connect the RSN pin to the load return. There is an internal 5:1 divider in the device, so do

not connect an external feedback resistor divider. The converter loop gain measurement can tolerate 10 Ω to 50

Ω in series with RSP and output voltage.

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7.3.5 Switching Frequency

The internal oscillator of the device can be set to one of seven switching frequencies by a resistor to ground

on the FSEL pin. The FSEL pin can be shorted to ground to reduce BOM component count. When shorted to

ground, the default converter switching frequency is used.

表 7-1. Frequency

Resistor Selection

R_FSEL(kΩ)

Short

7.5

f_SW(kHz)

1000

400

18.2

600

26.1

800

35.7

1000

1200

2000

2200

47.5

61.9

78.7

The oscillator can also be synchronized to an external clock on the SYNC pin. The external clock frequency

must be within -10% and +15% of the programmed frequency of the converter. The SYNC pin has an internal

pulldown so it can be left floating externally.

When the converter operates at 2 MHz or 2.2 MHz, it is recommended to set the OCP at 13 A or lower and

without a snubber circuit. For operation with OCP at 16.5 A, a snubber circuit is required. The snubber circuit

components can start with a 470-pF cap and 2-Ω resistor. The component values will need to be tuned to

achieve optimal results.

7.3.6 Voltage Control Mode Internal Compensation

The TPS542A52 has 15 unique internal compensation settings to cover a wide range of output inductors and

capacitors. For each switching frequency option, there are four compensation options that can be chosen using

a single resistor to ground on the COMP pin.

表 7-2. Compensation Resistor Selection

R_COMP(kΩ)++

Short

7.5

COMPENSATION SETTING

COMP 2

COMP 1

18.2

COMP 2

26.1

COMP 3

35.7

COMP 4

47.5

COMP 1

61.9

COMP 2

78.7

COMP 3

102

COMP 4

Each compensation network consists of two zeros and one high frequency pole. 表 7-3 maps the compensation

settings to the first zero frequency at different output voltage range, second zero frequency, and high frequency

pole.

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POLE (kHz)

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表 7-3. Compensation Settings

ZERO 1

(kHz) for

VOUT = 0.5

V-1.1 V

COMPENS

ATION

SETTING

ZERO 1 (kHz) ZERO 1 (kHz) ZERO 1 (kHz)

for VOUT =

1.2 V-1.5 V

ZERO 1 (kHz)

for VOUT = for VOUT = 2.9 for VOUT = 4.1

FREQUEN

CY (kHz)

ZERO 2

(kHz)

1.6 V-2.8 V

V-4.0 V

V-5.5 V

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

COMP 1

COMP 2

COMP 3

COMP 4

2.2

3.6

7.2

2.2

2.7

4.5

10.5

2.2

3.6

7.2

13.5

2.2

4.5

9.0

18.8

2.7

4.5

10.5

23.5

4.5

2.1

1.8

1.6

1.2

2.0

4.1

1.2

1.5

2.5

5.9

1.2

2.0

4.1

7.6

1.2

2.5

5.1

10.6

1.5

2.5

5.9

13.3

2.5

5.1

10.6

21.2

2.5

5.1

10.6

21.2

5.5

7.3

400

600

3.4

3.0

2.7

14.5

28.4

5.5

159

312

7.0

6.1

5.4

2.1

1.8

1.6

2.6

2.3

2.0

11.0

18.1

45.2

7.3

121

199

497

4.3

3.8

3.4

10.1

2.1

8.8

7.9

1.8

1.6

3.4

3.0

2.7

14.5

28.4

55.6

9.0

159

312

612

800

7.0

6.0

5.4

11.4

1.9

10.1

1.7

2.1

4.3

3.8

3.4

18.1

37.1

72.3

11.0

18.1

45.2

90.4

18.1

37.1

72.3

144.7

18.1

37.1

72.3

144.7

199

408

796

121

199

497

995

199

408

796

1592

199

408

796

1592

1000

1200

2000

2200

8.7

7.6

6.7

18.2

2.6

15.9

2.3

14.1

2.0

4.3

3.8

3.4

10.1

22.7

4.3

8.8

7.9

19.9

3.8

17.7

3.4

8.7

7.6

6.7

18.8

37.7

4.5

18.2

36.4

4.3

15.9

31.8

3.8

14.1

28.3

3.4

8.7

7.6

6.7

18.8

37.7

18.2

36.4

15.9

31.8

14.1

28.3

表 7-4 shows the second zero frequency placement about two times based on a ratio (f_O/f_SW) of the LC

frequency (f_O) to the switching frequency and lists the values in 表 7-3. The second zero frequency does not

change with the output voltage. The high frequency pole is about 10 times of the second zero frequency to

attenuate the switching frequency noise and to have a safe gain margin.

The output filter LC frequency should be designed between the first and second zero frequencies. The ratio of

the LC frequency to the switching frequency in 表 7-4 is a guide to select the LC frequency f_O. For example, the

LC frequency for 1-MHz switching frequency is 10 kHz at 1% ratio. Given 1-V output voltage, COMP2 has the

first zero at 4.5 kHz to compensate the LC filter double poles. For the same LC filter and switching frequencies

of 3.3-V output voltage, COMP3 has the first zero at 6.7 kHz to compensate the LC filter double poles. The

compensation setting needs to consider for the output capacitor derating, especially ceramic capacitor and

inductor tolerance. It is recommended to verify the load transient and bode plot based upon the compensation

selection.

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表 7-4. Second Zero Frequency

COMPENSATION

SETTING

SECOND ZERO

FREQUENCY

f_O/f_SW

0.5%

COMP 1

COMP 2

COMP 3

COMP 4

~2X of 0.5% f_O/f_SW

~2X of 1% f_O/f_SW

~2X of 2% f_O/f_SW

~2X of 4% f_O/f_SW

7.3.7 Soft Start and Prebiased Output Start-up

The TPS542A52 uses a programmable soft-start rate to gradually ramp the output voltage reference to reduce

inrush currents. The device prevents current from being discharged from the output during start-up when a

pre-biased condition exists. No switching pulses occur until the internal soft-start reference exceeds the voltage

on the error amplifier input voltage (RSP and RSN pins). The TPS542A52 supports the output voltage with

pre-biasd up to 100%.

The soft-start clock in 表 7-5 can be programmed on the SS/PFM pin along with enabling/disabling PFM and

hiccup time. The soft-start timing in 表 7-6 can be programmed based upon the output voltage and soft-start

clock. There are four choices of soft-start time to select at different soft-start clock. For example of 1-V output

voltage, the soft-start time equals to 1.8 ms at 0.5-MHz SS CLK and 0.45 ms at 2.0-MHz SS CLK.

表 7-5. Soft-Start CLK and PFM Resistor Selection

and Hiccup Time

R_SS/PFM(kΩ)+

SS CLK

(MHz)

HICCUP

DURATION (ms)

PFM

Short

7.5

Disable

1.0

2.0

25.2

12.6

25.2

50.4

100.8

12.6

25.2

50.4

100.8

18.2

26.1

35.7

47.5

61.9

78.7

102

1.0

Enable

Disable

0.50

0.25

2.0

1.0

0.50

0.25

表 7-6. Soft-Start Timing versus Output Voltage

SS TIMING (ms) AT SS TIMING (ms) AT CLK:

SS TIMING (ms) AT

CLK: 0.25 MHz

VSET (V)

VOUT (V)

LSB SIZE (mV)

CLK: 2.0 MHz

1.0 MHz

CLK: 0.5 MHz

0.1

0.2

0.28

0.3

0.4

0.5

0.56

0.6

0.7

0.8

0.9

0.5

0.112

0.223

0.313

0.167

0.223

0.279

0.313

0.167

0.195

0.223

0.251

0.279

0.45

0.9

1.8

0.9

1.8

3.6

7.2

3.6

0.9

1.4

1.5

2.0

2.5

2.8

3.0

3.5

0.9

3.6

1.8

7.2

1.8

7.2

1.8

7.2

1.8

7.2

3.6

14.4

3.6

4.5

5.0

3.6

7.3.8 Power Good

The power good pin is an open-drain output and needs to pull up to a voltage supply if a designer uses this

feature. During normal converter operation, the device leaves this pin floating. Power good warnings occur if the

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output voltage is not within the OV or UV warning levels. Power Good (PGD) is forced low when a fault occurs,

when the converter is in soft start, and when the converter is in shutdown or programming mode. The PGD pin is

released to floating after the PGD delay time when all of the above conditions are met.

TI recommends connecting a pullup resistor to a voltage source that is 5.5 V or less, such as to the device

VREG pin.

7.3.9 Overvoltage and Undervoltage Protection

An output overvoltage (OV) fault is triggered if the output voltage, sensed by RSP/RSN, is greater than the OVP

trip level. When this condition is detected, the converter terminates the switching cycle and turns on the low-side

FET to discharge the output voltage. The low-side FET remains on until the low-side FET current reaches the

negative overcurrent limit. When the negative overcurrent limit is reached, the low set FET turns off for 2000

ns. After the 2000 ns delay, the low-side FET turns back on until the negative over-current limit is reached. This

process repeats until the output voltage is discharged below the undervoltage fault threshold (typically 80% set

V_OUT). The converter then enters hiccup for seven cycles of soft-start CLK frequency due to the output voltage

being below the UV threshold.

An output undervoltage fault is triggered if the output voltage, sensed by RSP/RSN, is less than UVP threshold.

When this condition is detected, power conversion is disabled, and the converter enters hiccup for seven cycles

of soft-start CLK frequency.

7.3.10 Overcurrent Protection

The device senses overcurrent (OC) in both the high-side and low-side power MOSFETs using cycle by cycle

detection. OC is detected in the low-side FET by sensing the voltage across the FET while it is on. After the

low-side FET turns on, there is a blanking time of approximately 70 ns to allow noise to settle before the OC

comparator begins sensing. Once an OC fault condition is detected, the device stops switching and enters

hiccup for seven cycles of soft-start CLK frequency. The overcurrent limit is set through a single resistor to

ground on the ILIM pin. The ILIM pin can be shorted to ground to reduce BOM component count. When shorted

to ground the default current limit is used. Current limits shown in 表 7-7 can be programmed on the ILIM pin.

表 7-7. Current Limit Resistor Selection

R_ILIM(kΩ)

Short

7.5

TYPICAL LIMIT (A)

5.5

18.2

26.1

10.5

35.7

47.5

16.5

61.9

The device also senses negative overcurrent in the low-side FET by sensing the voltage across the FET while it

is on. After the low-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator

begins sensing. Once a negative OC fault condition is detected the device stops switching and enters hiccup for

seven cycles of soft-start CLK frequency. The negative overcurrent threshold is fixed to a single value.

Overcurrent is detected in the high-side FET by sensing the voltage across the FET while it is on. After the

high-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins

sensing. Once an OC fault condition is detected, the device stops switching and enters hiccup for seven cycles

of soft-start CLK frequency. The high-side overcurrent threshold is fixed to a single value. For an application with

on-time less than 70 ns, the high-side FET over-current is not guaranteed to enable. In this case, the low-side

OC will dominate and protect the load while the output current ramps up gradually. With on-times less than 70 ns

and a hard short at the load, the controller loop will extend the on-time to respond to the output voltage drooping,

and as a result, both high-side and low-side OC protections will engage to protect the load.

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7.3.11 High-Side FET Throttling

When the high-side FET turns on or off, the ringing voltage across the FET depends on the output current,

loop inductance, and PCB parasitic inductance. To diminish the ringing voltage during turning on or off, the

TPS542A52 reduces the gate driver strength when TPS542A52 detects PVIN higher than 14 V with 0.5-V

hysteresis.

7.3.12 Overtemperature Protection

When the device senses a temperature above the thermal shutdown limit (typically 165°C), power conversion is

disabled. The converter remains disabled until the temperature cools down to the thermal recovery limit (typically

150°C). At this point the converter enters hiccup for seven cycles of soft-start CLK frequency.

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7.4 Device Functional Modes

7.4.1 Pulse-Frequency Modulation Eco-mode^™Light Load Operation

When the SS/PFM pin is terminated with a 35.7-kΩ or lower resistance, the TPS542A52 operates in pulse-

frequency modulation (PFM) for light load conditions to maintain high efficiency.

As the output current decreases from heavy-load conditions, the inductor current also decreases until the valley

of the inductor current reaches zero amps, which is the boundary between continuous-conduction mode (CCM)

and discontinuous-conduction mode (DCM). The synchronous MOSFET turns off when this zero inductor current

is detected. As the load current decreases further, the converter runs in DCM. In DCM operation, the on-time is

maintained to a level approximately the same as during CCM and the converter off-time is modulated to maintain

the proper output voltage. For the application of 5-V input voltage, it is not recommend to operate in PFM due to

the accuracy of the zero comparator which will be reduced because of the low input voltage.

7.4.2 Forced Continuous-Conduction Mode

When the SS/PFM pin is terminated with a 47.5-kΩ or higher resistance, the TPS542A52 operates in forced

continuous conduction mode (FCCM) for all load currents. During FCCM, the switching frequency is set by an

internal oscillator for which the frequency can either be selected by the FSEL pin or an external clock on the

SYNC pin.

7.4.3 Soft Start

The TPS542A52 operates in FCCM during soft start regardless of the setting selected by the SS/PFM pin. If

PFM is enabled by the SS/PFM pin, the PFM operation begins after PGD is asserted. The delay between soft

start finishing and PGD being asserted is typically 500 µs. During the start-up, the TPS542A52 has the low-side

current limit at 16.5 A when the OCP configures 20 A. However, if the OCP configures below 16.5 A such as 13

A, then the current limit during soft start sets to be at 13 A.

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8 Application and Implementation

Note

以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The TPS542A52 is a high-efficiency, single-channel, synchronous buck converter with integrated n-channel

MOSFETs. The device suits low-output voltage point-of-load applications with 15-A or lower current. The

TPS542A52 has a maximum operating junction temperature of 150°C, which makes it suitable for high-ambient

temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V, and the output

voltage range is 0.5 V to 5.5 V. The device features a fixed-frequency voltage-control mode with a switching

frequency range of 400 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter

components. The controller features selectable internal compensation making the device easy to use with a

low external-component count. The internal compensation networks are able to support a wide range of output

inductance and capacitance, supporting all types of capacitors. The controller utilizes a digital PWM modulator

that allows for very narrow on-times making it ideal for high-frequency and high-step down ratio applications. The

switching frequency of the device can be synchronized to an external clock applied to the SYNC pin.

8.2 Typical Application

8.2.1 Full Analog Configuration

A resistor to ground on the FSEL, COMP, SS/PFM, and ILIM pins configure the device. Any of these pins can be

grounded to use the default values and reduce component count.

PVIN

AVIN

V_IN

C_BST

BOOT

VREG

PGD

V_OUT

R_ENH

R_PGD

C_IN

RSP

RSN

C_OUT

C_VREG

R_ENL

FSEL

COMP

SS/PFM

ILIM

SYNC

SREF

VSET

R₁

R_SS/PFMR_COMP

R_ILIM

R_FSET

AGND

PGND

R₂

图 8-1. Full Analog Configuration

8.2.1.1 Design Requirements

For this design example, use the input parameters shown in 表 8-1.

表 8-1. Design Example Specifications

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

V_IN, Input Voltage

V_IN(ripple), Input Ripple Voltage

V_OUT, Output Voltage

0.2

V_PP, Ouput Ripple Voltage

V_OVER, Transient Response

Overshoot

I_STEP= 5 A at 1 A/μs

V_UNDER, Transient Response

Undershoot

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表 8-1. Design Example Specifications (continued)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

I_OUT, Output Current

I_OC, Over-Current Trip Point

F_SW, Switching Frequency

t_SS, Soft-start time

1.2

0.5

MHz

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS542A52 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Output Voltage Calculation

The output voltage equals five times of VSET. To set VSET voltage, a resistor divider network is required from

SREF (1.2 V). 方程式 2 shows the output voltage calculation. It is recommended to use R₁and R₂in the range

of 1 kΩ to 100 kΩ. For example, R₁equals 50 kΩ and R₂equals 10 kΩ for 1-V output voltage.

VOUT = 5ì VSET

VSET =

ì1.2

R¹+ R2

V^OUT= 5ì

ì1.2

R¹+ R2

8.2.1.2.3 Switching Frequency Selection

(2)

There is a trade off between higher and lower switching frequencies. Higher switching frequencies can produce

a smaller solution size using lower valued inductors and smaller output capacitors compared to a power supply

that switches at a lower frequency. However, the higher switching frequency causes extra switching losses,

which decrease efficiency and impacts thermal performance. In this design, a moderate switching frequency of

1.2 MHz achieves both a small solution size and a high efficiency operation is selected. The TPS542A52 offers

seven choices of switching frequency in 表 7-1. RFSET equals to 47.5 kΩ for 1.2-MHz switching frequency.

8.2.1.2.4 Inductor Selection

The inductor value is a compromise between having a good load step transient response, output ripple voltage,

and efficiency. A good practice is to select the inductor ripple current value between 15% to 50% of the

maximum output current. The output capacitor absorbs the inductor-ripple current. Therefore, selecting a high

inductor-ripple current impacts the selection of the output capacitor because the output capacitor must have

a ripple-current rating equal to or greater than the inductor-ripple current. Using 35% target ripple current, the

required inductor size can be calculated as shown in 方程式 3.

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1.0 V× 12 V-1.0 V

(

)

L =

= 218 nH

V^INì f^SWìI^OUTì0.35 12 V×1.2 MHzì10 A ì0.35

(3)

A standard inductor value of 220 nH is selected.

8.2.1.2.5 Input Capacitor Selection

The TPS542A52 requires a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a value of

at least 1 μF of effective capacitance on the PVIN pin, relative to PGND. The power stage input decoupling

capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching

currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a

result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be

greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the

maximum input current ripple to the device during full load. The input ripple current can be calculated by 方程式

(V^IN- VOUT)

I^CIN(rms)= I^OUT(max)ì ^VOUTì

= 2.8 Amps

VIN

(4)

The minimum input capacitance and ESR values for a given input voltage ripple specification, V_IN(ripple), are

shown in 方程式 5. The input ripple is composed of a capacitive portion, V_{IN(RIPPLE_CAP)}, and a resistive portion,

V_{IN(RIPPLE_ESR)}

I^OUT(max)ì 1-D ìD

(

)

C^IN(min)=

= 6.4 mF

V^{IN(RIPPLE _ CAP)}ì fSW

VIN(RIPPLE _ ESR)

ESR^CIN(max)=

= 8.5 mW

_{IOUT(max) +}IRIPPLE

where

ñ D is the duty cycle

(5)

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to

the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material

that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator

capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature.

The input capacitor must also be selected with the DC bias taken into account. For this example design, a

ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this

design, allow 0.1-V input ripple for V_{IN(RIPPLE_CAP)}, and 0.1-V input ripple for V_{IN(RIPPLE_ESR)}. Using 方程式 5, the

minimum input capacitance for this design is 6.4 µF, and the maximum ESR is 8.5 mΩ. In a real application, it is

recommended to use a combination of small capacitors such as 0.1-μF and larger value 10-μF or 22-μF ceramic

capacitors in parallel for the power stage.

8.2.1.2.6 Bootstrap Capacitor Selection

A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper

operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with

a voltage rating of 25 V or higher.

8.2.1.2.7 R-C Snubber and VIN Pin High-Frequency Bypass

Though it is possible to operate the TPS542A52 within absolute maximum ratings without voltage ringing

reduction techniques, some designs can require external components to further reduce ringing levels. This

example uses two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C

snubber between the SW area and GND.

The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimize the

outboard parasitic inductances in the power stage, which store energy during the high-side MOSFET on-time,

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and discharge once the high-side MOSFET is turned off. For this example two of 0.1-μF to 1-μF, 25-V, 0402-

sized high-frequency capacitors are used. The placement of these capacitors is critical to its effectiveness.

Additionally, an optional R-C snubber circuit is added to this example. To balance efficiency and spike levels,

a 220-pF capacitor and a 2-Ω resistor are chosen. In this example, a 0805-sized resistor is chosen, which is

rated for 0.125 W, nearly twice the estimated power dissipation. See the Seminar 900 Topic 2 - Snubber Circuits:

Theory, Design and Application application note for more information about snubber circuits.

8.2.1.2.8 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

affects three criteria:

•

Stability

Regulator response to a change in load current or load transient

Output voltage ripple

These three considerations are important when designing regulators that must operate where the electrical

conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these

three criteria.

8.2.1.2.9 Response to a Load Transient

The output capacitance must supply the load with the required current when current is not immediately provided

by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects

the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.

Use 方程式 6 and 方程式 7 to calculate the minimum output capacitance to meet the undershoot and overshoot

requirements. For this example, C_{OUT(min_under)}is 136-μF and 92-μF for C_{OUT(min_over)}. In a real application, the

value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. It is recommended to check the capacitor datasheet and account for the capacitance derating.

L ´ DI_LOAD(max)

DI_LOAD(max)´ 1- D ´ t

(

)

DV_LOAD(INSERT)

C_{OUT(min_under)}

2 ´ DV_LOAD(INSERT)´ (V -V_VOUT

)

(6)

(7)

L_OUT

LOAD(max)

(

)

2 ´ DV_{LOAD(release)}× V_OUT

C_{OUT(min_over)}

where

•

C_{OUT(min_under)}is the minimum output capacitance to meet the undershoot requirement

C_{OUT(min_over)}is the minimum output capacitance to meet the overshoot requirement

D is the duty cycle

L is the output inductance value (0.22 µH)

∆I_LOAD(max)is the maximum transient step (5 A)

V_OUTis the output voltage value (1 V)

t_SWis the switching period (0.833 µs)

V_INis the minimum input voltage for the design (12 V)

∆V_LOAD(insert)is the undershoot requirement (30 mV)

∆V_{LOAD(release)}is the overshoot requirement (30 mV)

8.2.1.2.10 Pin-Strap Setting

For overcurrent protection at 16.5 A, 47.5 kΩ is chosen from 表 7-7. For 0.5-ms soft start and FCCM operation,

47.5 kΩ is chosen from 表 7-5 and 表 7-6.

For converter stability and selecting the compensation network, 表 7-3 provides four compensation choices.

First, the power stage double pole filter frequency needs to be known. For this example, the output capacitor

bank selects as 4x100-μF ceramic capacitors in 0805 size to account the capacitor derating factors. Next, the LC

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filter frequency is calculated to 17 kHz. Finally, COMP3 becomes the best choice to select by using a 26.1-kΩ or

78.7-kΩ resistor on the COMP pin to GND.

8.2.1.3 Application Curves

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.2 MHz

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.2 MHz

图 8-3. Load Transient 5 A to 10 A to 5 A at 1 A/μs

图 8-2. 450 μs Start-up by EN at 0-A Output Current

V_IN= 12 V

V_OUT= 1 V

f_SW= 1.2 MHz

图 8-4. Bode Plot at 10-A Output Current

8.2.1.4 Typical Application Circuits

V_IN

PVIN

AVIN

0.1 µF

BOOT

0.68 µH

0.1 µF

VREG

PGD

V_OUT

3 x 10 µF

10 k

4.7 µF

RSP

RSN

5 x 100 µF

0.47 µF

2 x 22 µF

SYNC

FSEL

COMP

46.4 k

SS/PFM

ILIM

SREF

VSET

61.9 k

AGND

PGND

61.9 k

18.2 k

35.7 k

20 k

图 8-5. Typical Application Circuit for 1.8-V Output at 1.0 MHz

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V_IN

PVIN

AVIN

0.1 µF

BOOT

1.5 µH

0.1 µF

VREG

PGD

V_OUT

220 µF

4 x 10 µF

10 k

4.7 µF

RSP

RSN

0.47 µF

2 x 22 µF

Optional: 4 x 100 µF

SYNC

FSEL

COMP

28 k

SS/PFM

ILIM

SREF

VSET

61.9 k

AGND

PGND

61.9 k

26.1 k

20 k

图 8-6. Typical Application Circuit for 2.5-V Output at 0.8 MHz

V_IN

PVIN

0.1 µF

AVIN

VREG

PGD

BOOT

1.5 µH

0.1 µF

V_OUT

220 µF

4 x 10 µF

10 k

4.7 µF

RSP

RSN

0.47 µF

2 x 22 µF

Optional: 4 x 100 µF

SYNC

SCL

FSEL

COMP

SDA

16.5 k

SS/PFM

ILIM

SREF

VSET

61.9 k

AGND

PGND

61.9 k

26.1 k

20 k

图 8-7. Typical Application Circuit for 3.3-V Output at 0.8 MHz

V_IN

PVIN

0.1 µF

AVIN

VREG

PGD

BOOT

2.2 µH

0.1 µF

V_OUT

330 µF

4 x 10 µF

10 k

4.7 µF

RSP

RSN

0.47 µF

2 x 22 µF

SYNC

FSEL

COMP

10 k

SS/PFM

ILIM

SREF

VSET

47.5 k

AGND

PGND

61.9 k

26.1 k

18.2 k

49.9 k

图 8-8. Typical Application Circuit for 5-V Output at 0.6 MHz

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4 V and 18 V. This input supply

must be well regulated. Proper bypassing of input supplies (AVIN and PVIN) is critical for noise performance, as

is the PCB layout and grounding scheme. See the recommendations in 节 10.

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10 Layout

10.1 Layout Guidelines

1. The PVIN pins are the power inputs to the main half bridge and AVIN is the power input to the controller.

2. Connect AVIN and PVIN together on the PCB. It is important that these pins are at the same voltage

potential because the controller feedforward block uses this voltage information in the modulator to increase

transient performance. For AVIN, it is best to use RC filter from PVIN such as 10 Ω and 100 nF.

3. To minimize the power loop inductance for the half bridge, place the bypassing capacitors as close as

possible to the PVIN pins on the converter. When using a multilayer PCB (more than two layers), the power

loop inductance is minimized by having the return path to the input capacitor small and directly underneath

the first layer as shown below. Loop inductance is reduced due to flux cancellation as the return current is

directly underneath and flowing in the opposite direction.

4. Place the bias capacitor for VREG pin as close as possible to the pin as shown below.

5. The resistor divider network for SREF and VSET needs to placed as close as possible to the pins. Limit the

high frequency noise source coupling onto these components.

6. RSP and RSN signals are best to route parallel to the load sense location. It is recommended to limit high

frequency noise source coupling onto these traces.

7. PGND thermal vias: It is recommended to add vias under and outside the IC of PGND plane as shown

below.

8. AGND thermal vias: It is recommended to add at least 2 vias under the IC of AGND plane as shown below.

9. AGND plane can be routed as separate island in an internal layer. AGND can connect as a net tied to PGND

between the two thermal grounds under the IC as shown below.

10. Total PCB area can be routed in 17 mm by 14 mm as shown below. See the EVM userguide for more details.

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10.2 Layout Example

Total Area:

17mm x 14mm

PGND

PVIN

PGND

0402

AGND

0805

PVIN

0402

ILIM

SS/PFM

7mm x 7mm

VOUT

AGND

SYNC

RSN

RSP

PGND

AGND

0402

AGND

0402

VREG

AGND

PGND

图 10-1. Example PCB Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS542A52 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

11.4 Trademarks

Eco-mode^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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26-Aug-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS542A52RJMR

ACTIVE

VQFN-HR

RJM

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

542A52

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS542A52RJMR

VQFN-

RJM

3000

330.0

12.4

4.25

4.75

1.2

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN-HR RJM 33

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS542A52RJMR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

RJM0033A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.6

4.4

PIN 1 INDEX AREA

4.1

3.9

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

7X 0.175 0.05

PKG

0.95 0.1

(2X 0.375)

(0.127) TYP

21X 0.5

4X (0.2)

0.388 0.1

5X 1

PKG

2.05 0.1

3.5

8X 0.7 0.1

PIN 1 ID

0.3

0.2

0.1

(2X 0.375)

0.4

24X

C A B

24X

0.3

0.05

4223732/C 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RJM0033A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.55)

4X (0.2)

20X (0.55)

7X (0.175)

(1.925)

4X (0.575)

(0.95)

24X (0.25)

8X (0.7)

21X

(0.5)

PKG

(2.05)

0.000

0.2) VIA

(

(0.388)

5X (1)

(R0.05) TYP

(1.925)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223732/C 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RJM0033A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.55)

4X (0.2)

20X (0.55)

(1.925)

4X (0.575)

4X (0.237)

2X (1.75)

7X (0.175)

2X (0.94)

(0.56)

EXPOSED METAL

TYP

2X (0.83)

0.000

PKG

(0.62)

EXPOSED

METAL

2X (0.515)

(0.35)

17X

(0.5)

5X (1)

2X (1.744)

(1.925)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 8, 16, 17: 95%; PADS 25-33: 80%

SCALE:25X

4223732/C 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TPS542A52 [TI]

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TPS542A52RJMR

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TPS5430-Q1

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