TPS54313PWPRG4 [TI]

3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT); 3 V至6 V的输入， 3 -A输出同步降压具有集成FET的PWM切换器（ SWIFT ）


型号：	TPS54313PWPRG4
厂家：	TEXAS INSTRUMENTS
描述：	3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) 3 V至6 V的输入， 3 -A输出同步降压具有集成FET的PWM切换器（ SWIFT ）输出元件输入元件
文件：	总22页 (文件大小：747K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Typical Size

(6,3 mm x 6,4 mm)

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT™)

FEATURES

DESCRIPTION

60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink

Current

0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V Fixed

Output Voltage Devices With 1% Initial

Accuracy

Internally Compensated for Low Parts Count

Fast Transient Response

Wide PWM Frequency: Fixed 350 kHz, 550

kHz, or Adjustable 280 kHz to 700 kHz

Load Protected by Peak Current Limit and

Thermal Shutdown

Integrated Solution Reduces Board Area and

Total Cost

As members of the SWIFT family of dc/dc regulators, the

TPS54311, TPS54312, TPS54313, TPS54314,

TPS54315 and TPS54316 low-input-voltage high-output-

current synchronous-buck PWM converters integrate all

required active components. Included on the substrate

with the listed features are a true, high performance,

voltage error amplifier that provides high performance

under transient conditions; an undervoltage-lockout circuit

to prevent start-up until the input voltage reaches 3 V; an

internally and externally set slow-start circuit to limit

in-rush currents; and a power good output useful for

processor/logic reset, fault signaling, and supply

sequencing.

The TPS54311, TPS54312, TPS54313, TPS54314,

TPS54315 and TPS54316 devices are available in a

thermally enhanced 20-pin TSSOP (PWP) PowerPAD™

package, which eliminates bulky heatsinks. TI provides

evaluation modules and the SWIFTdesigner software tool

to aid in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

APPLICATIONS

Low-Voltage, High-Density Systems With

Power Distributed at 5 V or 3.3 V

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

Broadband, Networking and Optical

Communications Infrastructure

Portable Computing/Notebook PCs

EFFICIENCY

LOAD CURRENT

Simplified Schematic

Input

Output

VIN

TPS54316

BOOT

PGND

VBIAS

VSENSE

GND

= 25°C

V = 5 V

= 3.3 V

0.5

1.5

2.5

Load Current − A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGED DEVICES

PLASTIC HTSSOP

PACKAGED DEVICES

PLASTIC HTSSOP

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

(1)(2)

(PWP)

0.9 V

1.2 V

1.5 V

TPS54311PWP

TPS54312PWP

TPS54313PWP

1.8 V

2.5 V

3.3 V

TPS54314PWP

TPS54315PWP

TPS54316PWP

−40°C to 85°C

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54316PWPR). See application section of data

(2))

sheet for PowerPAD drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

TPS54310

−0.3 V to 7 V

−0.3 V to 6 V

−0.3 V to 4 V

−0.3 V to 17 V

−0.3 V to 7 V

−0.6 V to 10 V

Internally Limited

6 mA

VIN, SS/ENA, SYNC

Input voltage range, V

VSENSE

BOOT

VBIAS, PWRGD, COMP

Output voltage range, V

Source current, I

COMP, VBIAS

6 A

COMP

6 mA

Sink current

SS/ENA,PWRGD

AGND to PGND

10 mA

Voltage differential

0.3 V

Operating virtual junction temperature range, T

−40°C to 125°C

−65°C to 150°C

300°C

Storage temperature, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

UNIT

Input voltage range, V

Operating junction temperature, T

−40

125

°C

PACKAGE DISSIPATION RATINGS^{(1) (2)}

THERMAL IMPEDANCE

T = 25°C

POWER RATING

T = 70°C

POWER RATING

T = 85°C

POWER RATING

PACKAGE

JUNCTION-TO-AMBIENT

(3)

20-Pin PWP with solder

26.0°C/W

3.85 W

2.12 W

1.54 W

20-Pin PWP without solder

57.5°C/W

1.73 W

0.96 W

0.69 W

(1)

(2)

For more information on the PWP package, refer to TI technical brief (SLMA002).

Test board conditions:

1. 3” × 3”, 2 layers, Thickness: 0.062”

2. 1.5 oz copper traces located on the top of the PCB

3. 1.5 oz copper ground plane on the bottom of the PCB

4. Ten thermal vias (see recommended land pattern in application section of this data sheet)

Maximum power dissipation may be limited by overcurrent protection.

(3)

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS

T = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE, VIN

VIN input voltage range

f = 350 kHz,

FSEL = 0.8 V,

RT open

RT open,

6.2

8.4

9.6

f = 550 kHz,

FSEL ≥ 2.5 V,

12.8

1.4

Quiescent current

Phase pin open

Shutdown,

SS/ENA = 0 V

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.95

2.80

0.16

2.70

0.14

Rising and falling edge deglitch,

UVLO

2.5

µs

(1)

BIAS VOLTAGE

Output voltage, VBIAS

= 0

2.70

2.80

2.90

100

(VBIAS)

(2)

Output current, VBIAS

µA

OUTPUT VOLTAGE

T = 25°C,

VIN = 5 V

0.9

1.2

1.5

1.8

2.5

3.3

TPS54311

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

−40 ≤ T ≤ 125

−2.5%

2.5%

T = 25°C,

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

−40 ≤ T ≤ 125

T = 25°C,

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

−40 ≤ T ≤ 125

Output voltage

T = 25°C,

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

−40 ≤ T ≤ 125

T = 25°C,

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

−40 ≤ T ≤ 125

T = 25°C,

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

−40 ≤ T ≤ 125

REGULATION

Line regulation

(1) (3)

I = 1.5 A,

350 ≤ f ≤ 550 kHz, T = 85°C

0.21

%/V

%/A

Load regulation

OSCILLATOR

I = 0 A to 3 A,

350 ≤ f ≤ 550 kHz, T = 85°C

FSEL ≤ 0.8 V,

FSEL ≥ 2.5 V,

RT open

280

440

252

460

663

2.5

350

550

280

500

700

420

660

308

540

762

Internally set free-running frequency

range

kHz

(1)

RT = 180 kΩ (1% resistor to AGND)

RT = 100 kΩ (1% resistor to AGND)

Externally set free-running frequency

range

(1)

RT = 68 kΩ (1% resistor to AGND)

High-level threshold voltage at FSEL

Low-level threshold voltage at FSEL

0.8

(1)

Ramp valley

0.75

(1)

Ramp amplitude (peak-to-peak)

(1)

Minimum controllable on time

200

Maximum duty cycle

90%

(1)

(2)

(3)

Specified by design

Static resistive loads only

Specified by the circuit used in Figure 10.

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

T = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER

(1)

Error amplifier open loop voltage gain

(1)

Error amplifier unity gain bandwidth

MHz

PWM COMPARATOR

PWM comparator propagation delay time,

PWM comparator input to PH pin (ex-

cluding dead time)

(1)

10 mV overdrive

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA

0.82

1.20

0.03

2.5

3.3

4.5

5.6

3.3

4.7

6.1

1.40

(1)

Falling edge deglitch, SS/ENA

µs

TPS54311

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

2.6

3.5

4.4

2.6

3.6

4.7

4.1

5.4

6.7

4.1

5.6

7.6

(1)

Internal slow-start time

Charge current, SS/ENA

SS/ENA = 0 V

µA

Discharge current, SS/ENA

SS/ENA = 0.2 V,

V = 1.5 V

1.5

2.3

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage

VSENSE falling

ref

(1)

ref

Power good falling edge deglitch

Output saturation voltage, PWRGD

Leakage current, PWRGD

µs

= 2.5 mA

0.18

0.30

(sink)

V = 5.5 V

µA

CURRENT LIMIT

(1)

V = 3 V, output shorted

6.5

7.5

Current limit trip point

(1)

V = 6 V, output shorted

4.5

(1)

Current limit leading edge blanking time

Current limit total response time

100

200

(1)

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

135

150

165

°C

Thermal shutdown hysteresis

OUTPUT POWER MOSFETS

(2)

V = 6 V

Power MOSFET switches

mΩ

DS(on)

(2)

V = 3 V

136

(1)

(2)

Specified by design

Matched MOSFETs, low side r

production tested, high side r

specified by design

DS(on)

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

PIN ASSIGNMENTS

PWP PACKAGE

(TOP VIEW)

AGND

VSENSE

PWRGD

BOOT

FSEL

SS/ENA

VBIAS

VIN

PGND

NC − No internal connection

Terminal Functions

TERMINAL

DESCRIPTION

NAME

AGND

NO.

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and

FSEL pin. Make PowerPAD connection to AGND.

BOOT

Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

FSEL

Frequency select input. Provides logic input to select between two internally set switching frequencies.

No connection

PGND

11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the

input and output supply returns, and negative terminals of the input and output capacitors.

6−10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

PWRGD

Power good open drain output. Hi-Z when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when

ref

SS/ENA is low or internal shutdown signal active.

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f .

SS/ENA

Slow-start/enableinput/output. Dual function pin which provides logic input to enable/disable device operation and capacitor

input to externally set the start-up time.

VBIAS

VIN

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.

14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

VSENSE

Error amplifier inverting input. Connect directly to output voltage sense point.

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

VBIAS

AGND

VBIAS

VIN

Enable

Comparator

5 µA

SS/ENA

REG

Falling

Edge

Deglitch

SHUTDOWN

VIN

ILIM

Comparator

1.2 V

VIN

Thermal

Shutdown

145°C

Hysteresis: 0.03 V

Leading

Edge

Blanking

2.5 µs

VIN UVLO

Comparator

Falling

and

Rising

Edge

100 ns

VIN

BOOT

2.95 V

Deglitch

Hysteresis: 0.16 V

2.5 µs

SS_DIS

SHUTDOWN

OUT

Internal/External

Slow-Start

(Internal Slow-Start Time =

3.3 ms to 6.6 ms)

−

Adaptive Dead-Time

and

Control Logic

2 kΩ

PWM

Comparator

40 kΩ

Error

Amplifier

VIN

25 ns Adaptive

Deadtime

Feed-Forward

Compensation

OSC

PGND

Power good

Comparator

Reference/

DAC

Falling

Edge

PWRGD

VSENSE

0.90 V

ref

Deglitch

TPS5431x

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

FSEL

VSENSE

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

TYPICAL CHARACTERISTICS

INTERNALLY SET OSCILLATOR

DRAIN-SOURCE ON-STATE RESISTANCE DRAIN-SOURCE ON-STATE RESISTANCE

FREQUENCY

JUNCTION TEMPERATURE

120

100

750

V = 3.3 V

V = 5 V

= 3 A

650

FSEL ≥ 2.5 V

550

450

FSEL ≤ 0.8 V

350

250

−40

125

−40

125

−40

125

− Junction Temperature − °C

Figure 1

Figure 2

Figure 3

EXTERNALLY SET OSCILLATOR

FREQUENCY

OUTPUT VOLTAGE REGULATION

VOLTAGE REFERENCE

JUNCTION TEMPERATURE

INPUT VOLTAGE

JUNCTION TEMPERATURE

0.8950

0.8930

0.8910

0.8890

800

0.895

= 85°C

RT = 68 k

700

600

500

400

0.893

0.891

RT = 100 k

f = 350 kHz

0.889

RT = 180 k

0.8870

0.8850

0.887

0.885

300

200

−40

125

−40

125

− Input Voltage − V

− Junction Temperature − °C

Figure 4

Figure 5

Figure 6

INTERNAL SLOW-START TIME

JUNCTION TEMPERATURE

DEVICE POWER LOSSES

ERROR AMPLIFIER

OPEN LOOP RESPONSE

LOAD CURRENT

3.80

3.65

3.50

3.35

3.20

3.05

−20

140

2.25

R = 10 kΩ,

− 125°C,

= 160 pF,

120

= 700 kHz

= 25°C

−40

−60

−80

1.75

100

1.5

V = 3.3 V

Phase

1.25

−100

−120

0.75

0.5

V = 5 V

Gain

−140

−160

2.90

2.75

−180

−200

0.25

−20

−40

125

100 1 k 10 k 100 k 1 M 10 M

− Junction Temperature − °C

− Load Current − A

f − Frequency − Hz

Figure 8

Figure 9

Figure 7

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical

TPS54314 application. The TPS54314 (U1) can provide

up to 3 A of output current at a nominal output voltage of

1.8 V. For proper thermal performance, the PowerPAD

underneath the TPS54314 integrated circuit needs to be

soldered to the printed circuit board.

GND

10 kΩ

TPS54314PWP

AGND

71.5 kΩ

VSENSE

FSEL

SS/ENA

VBIAS

VIN

PWRGD

BOOT

PWRGD

0.047 µF

10 µF

0.1 µF

VIN

5.2 µH

VIN

PGND

GND

470 µF

4 V

C11

1000 pF

PwrPAD

Optional

Figure 10. TPS54314 Schematic

The output filter components work with the internal

compensation network to provide a stable closed loop

response for the converter.

INPUT VOLTAGE

The input to the circuit is a nominal 5 VDC, applied at J1.

The optional input filter (C2) is a 220-µF POSCAP

capacitor, with a maximum allowable ripple current of 3 A.

C8 is the decoupling capacitor for the TPS54314 and must

be located as close to the device as possible.

PCB LAYOUT

Figure 11 shows a generalized PCB layout guide for the

TPS54311−16.

FEEDBACK CIRCUIT

The VIN pins should be connected together on the printed

circuit board (PCB) and bypassed with a low ESR ceramic

bypass capacitor. Care should be taken to minimize the

loop area formed by the bypass capacitor connections, the

VIN pins, and the TPS54311−16 ground pins. The

minimum recommended bypass capacitance is 10-µF

ceramic with a X5R or X7R dielectric and the optimum

placement is closest to the VIN pins and the PGND pins.

The output voltage of the converter is fed directly into the

VSENSE pin of the TPS54314. The TPS54314 is

internally compensated to provide stability of the output

under varying line and load conditions.

OPERATING FREQUENCY

In the application circuit, a 700 kHz operating frequency is

selected by leaving FSEL open and connecting a 71.5 kΩ

resistor between the RT pin and AGND. Different

operating frequencies may be selected by varying the

value of R3 using equation 1:

The TPS54311−16 has two internal grounds (analog and

power). Inside the TPS54311−16, the analog ground ties

to all of the noise sensitive signals, while the power ground

ties to the noisier power signals. Noise injected between

the two grounds can degrade the performance of the

TPS54311−16, particularly at higher output currents.

Ground noise on an analog ground plane can also cause

problems with some of the control and bias signals. For

these reasons, separate analog and power ground traces

are recommended. There should be an area of ground one

the top layer directly under the IC, with an exposed area for

connection to the PowerPAD. Use vias to connect this

ground area to any internal ground planes. Use additional

vias at the ground side of the input and output filter

capacitors as well. The AGND and PGND pins should be

tied to the PCB ground by connecting them to the ground

area under the device as shown. The only components

500 kHz

Switching Frequency

R +

100 kW

(1)

Alternately, preset operating frequencies of 350 kHz or

550 kHz my be selected by leaving RT open and

connecting the FSEL pin to AGND or VIN respectively.

OUTPUT FILTER

The output filter is composed of a 5.2-µH inductor and

470-µF capacitor. The inductor is a low dc resistance

(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor

used is a 4-V POSCAP with a maximum ESR of 40 mΩ.

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

that should tie directly to the power ground plane are the

input capacitors, the output capacitors, the input voltage

decoupling capacitor, and the PGND pins of the

TPS54311−16. Use a separate wide trace for the analog

ground signal path. This analog ground should be used for

the timing resistor RT, slow-start capacitor and bias

capacitor grounds. Connect this trace directly to AGND

(pin 1).

Connect the output filter capacitor(s) as shown between

the VOUT trace and PGND. It is important to keep the loop

formed by the PH pins, Lout, Cout and PGND as small as

practical.

Connect the output of the circuit directly to the VSENSE

pin. Do not place this trace too close to the PH trace. Do

to the size of the IC package and the device pinout, they

will have to be routed somewhat close, but maintain as

much separation as possible while still keeping the layout

compact.

The PH pins should be tied together and routed to the

output inductor. Since the PH connection is the switching

node, inductor should be located very close to the PH pins

and the area of the PCB conductor minimized to prevent

excessive capacitive coupling.

Connect the bias capacitor from the VBIAS pin to analog

ground using the isolated analog ground trace. If a

slow-start capacitor or RT resistor is used, or if the SYNC

pin is used to select 350-kHz operating frequency, connect

them to this trace as well.

Connect the boot capacitor between the phase node and

the BOOT pin as shown. Keep the boot capacitor close to

the IC and minimize the conductor trace lengths.

ANALOG GROUND TRACE

FREQUENCY SET RESISTOR

AGND

VSENSE

FSEL

SS/ENA

VBIAS

VIN

SLOW START

CAPACITOR

PWRGD

BOOT

BIAS CAPACITOR

EXPOSED

POWERPAD

AREA

BOOT

CAPACITOR

Vin

VIN

VOUT

VIN

PGND

OUTPUT INDUCTOR

INPUT

BULK

FILTER

BYPASS

CAPACITOR

OUTPUT

FILTER

CAPACITOR

TOPSIDE GROUND AREA

VIA to Ground Plane

Figure 11. TPS54311 − 16 PCB Layout

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

any area available should be used when 3 A or greater

operation is desired. Connection from the exposed area of

the PowerPAD to the analog ground plane layer should be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Six vias should be in the

PowerPAD area with four additional vias located under the

device package. The size of the vias under the package,

but not in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the ten recommended

that enhance thermal performance should be included in

areas not under the device package.

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

For operation at full rated load current, the analog ground

plane must provide adequate heat dissipating area. A 3

inch by 3 inch plane of 1 ounce copper is recommended,

though not mandatory, depending on ambient temperature

and airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

6 PL ∅ 0.0130

4 PL ∅ 0.0180

Minimum Recommended Thermal Vias: 6 × .013 dia.

Inside Powerpad Area 4 × .018 dia. Under Device as Shown.

Additional .018 dia. Vias May be Used if Top Side Analog

Ground Area is Extended.

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0227

0.0600

0.0400

0.2560

0.2454

0.1010

0.0400

0.0600

0.0256

0.1700

0.1340

0.0620

0.0400

Minimum Recommended Exposed

Copper Area For Powerpad. 5mm

Stencils may Require 10 Percent

Larger Area

Minimum Recommended Top

Side Analog Ground Area

Figure 12. Recommended Land Pattern for 20-Pin PWP PowerPAD

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

PERFORMANCE GRAPHS

OUTPUT VOLTAGE

EFFICIENCY

LOAD CURRENT

1.9

LOOP RESPONSE

180

135

100

Efficiency at 700 kHz

Phase

5 V

1.85

3.3 V

Gain

3.3 V

1.8

5 V

1.75

1.7

−45

−90

−15

−30

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

− Load Current − A

Load Current − A

Figure 13

Figure 15

Figure 14

LOAD TRANSIENT RESPONSE

START-UP WAVEFORMS

OUTPUT RIPPLE VOLTAGE

V 2 V/div

50 mV/div

(AC)

10 mV/div

2 V/div

2 A/div

V = 5 V

= 3 A

5 V/div

PWRGD

V = 5 V

400 ns/div

Time − 2 ms/div

Time − 100 µs/div

Time − 10 µs/div

Figure 18

Figure 16

Figure 17

AMBIENT TEMPERATURE

LOAD CURRENT

125

115

105

†

Safe operating area is applicable to the test

board conditions listed in the Dissipation Rating

Table section of this data sheet.

†

Safe Operating Area

− Load Current − A

Figure 19

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

www.ti.com

The actual slow-start is likely to be less than the above

approximation due to the brief ramp-up at the internal rate.

DETAILED DESCRIPTION

Under Voltage Lock Out (UVLO)

VBIAS Regulator (VBIAS)

The TPS54311 − 16 incorporates an under voltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs

rising and falling edge deglitch circuit reduce the likelihood

of shutting the device down due to noise on VIN.

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommended because their values are more stable over

temperature. The bypass capacitor should be placed close

to the VBIAS pin and returned to AGND. External loading

on VBIAS is allowed, with the caution that internal circuits

require a minimum VBIAS of 2.70 V, and external loads on

VBIAS with ac or digital switching noise may degrade

performance. The VBIAS pin may be useful as a reference

voltage for external circuits.

Slow-Start/Enable (SS/ENA)

The slow-start/enable pin provides two functions; first, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.

Voltage Reference

The voltage reference system produces a precise V_ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precision regulation of the TPS54311 − 16, since it cancels

offset errors in the scale and error amplifier circuits.

OUTPUT

VOLTAGE

DEVICE

SLOW-START

Oscillator and PWM Ramp

TPS54311

0.9 V

3.3 ms

4.5 ms

5.6 ms

3.3 ms

4.7 ms

6.1 ms

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the FSEL pin as a static

digital input. If a different frequency of operation is required

for the application, the oscillator frequency can be

externally adjusted from 280 kHz to 700 kHz by connecting

a resistor to the RT pin to ground and floating the FSEL pin.

The switching frequency is approximated by the following

equation, where R is the resistance from RT to AGND:

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and

AGND. Adding a capacitor to the SS/ENA pin has two

effects on start-up. First, a delay occurs between release

of the SS/ENA pin and start up of the output. The delay is

proportional to the slow-start capacitor value and lasts until

the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

100 kW

SWITCHING FREQUENCY +

500 kHz

(4)

Table 1. Summary of the Frequency Selection

Configurations

SWITCHING

FREQUENCY

FSEL PIN

RT PIN

350 kHz, internally

set

Float or AGND

Float

550 kHz, internally

set

≥ 2.5 V

1.2 V

5 mA

+ C

(SS)

(2)

Externally set 280

kHz to 700 kHz

Float

R = 68 k to 180 k

Second, as the output becomes active, a brief ramp-up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

Error Amplifier

The high performance, wide bandwidth, voltage error

amplifier is gain limited to provide internal compensation

of the control loop. The user is given limited flexibility in

choosing output L and C filter components. Inductance

0.7 V

5 mA

+ C

(SS)

(3)

TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

www.ti.com

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

values of 4.7 µH to 10 µH are typical and available from

several vendors. The resulting designs exhibit good noise

and ripple characteristics, along with exceptional transient

response. Transient recovery times are typically in the

range of 10 to 20 µs.

turn-on times of the MOSFET drivers. The high-side driver

does not turn on until the gate drive voltage to the low-side

FET is below 2 V. The low-side driver does not turn on until

the voltage at the gate of the high-side MOSFETs is below

2 V. The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is supplied

from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

PWM Control

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately reset and set the PWM latch. Once

the PWM latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse duration.

During this period, the PWM ramp discharges rapidly to its

valley voltage. When the ramp begins to charge back up,

the low-side FET turns off and high-side FET turns on. As

the PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

Overcurrent Protection

The cycle by cycle current limiting is achieved by sensing

the current flowing through the high-side MOSFET and

differential amplifier and comparing it to the preset

overcurrent threshold. The high-side MOSFET is turned

off within 200 ns of reaching the current limit threshold. A

100-ns leading edge blanking circuit prevents false

tripping of the current limit. Current limit detection occurs

only when current flows from VIN to PH when sourcing

current to the output filter. Load protection during current

sink operation is provided by thermal shutdown.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

latch is never reset and the high-side FET remains on until

the oscillator pulse signals the control logic to turn the

high-side FET off and the low-side FET on. The device

operates at its maximum duty cycle until the output voltage

rises to the regulation set-point, setting VSENSE to

Thermal Shutdown

The device uses the thermal shutdown to turn off the power

MOSFETs and disable the controller if the junction

temperature exceeds 150°C. The device is released from

shutdown when the junction temperature decreases to

10°C below the thermal shutdown trip point and starts up

under control of the slow-start circuit. Thermal shutdown

provides protection when an overload condition is

sustained for several milliseconds. With a persistent fault

condition, the device cycles continuously; starting up by

control of the soft-start circuit, heating up due to the fault,

and then shutting down upon reaching the thermal

shutdown point.

approximately the same voltage as V . If the error

ref

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54311 − 16 is capable of sinking current

continuously until the output reaches the regulation

set-point.

Power Good (PWRGD)

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and

low-side FET turns on to decrease the energy in the output

inductor and consequently the output current. This

process is repeated each cycle in which the current limit

comparator is tripped.

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold, or SS/ENA is low, or

thermal shutdown is asserted. When VIN = UVLO

threshold, SS/ENA = enable threshold, and VSENSE >

Dead-Time Control and MOSFET Drivers

90% of V , the open drain output of the PWRGD pin is

ref

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

high. A hysteresis voltage equal to 3% of V and a 35-µs

falling edge deglitch circuit prevent tripping of the power

good comparator due to high frequency noise.

ref

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS54311PWP

TPS54311PWPG4

TPS54312PWP

ACTIVE

HTSSOP

PWP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

TPS54312PWPG4

TPS54312PWPR

TPS54312PWPRG4

TPS54313PWP

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS54313PWPG4

TPS54313PWPR

TPS54313PWPRG4

TPS54314PWP

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS54314PWPG4

TPS54314PWPR

TPS54314PWPRG4

TPS54315PWP

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS54315PWPG4

TPS54315PWPR

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS54315PWPRG4

TPS54316PWP

HTSSOP

PWP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TPS54316PWPG4

TPS54316PWPR

TPS54316PWPRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54311, TPS54312, TPS54313, TPS54314, TPS54315, TPS54316 :

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Automotive: TPS54312-Q1, TPS54314-Q1, TPS54315-Q1, TPS54316-Q1

•

Enhanced Product: TPS54311-EP, TPS54312-EP, TPS54313-EP, TPS54314-EP, TPS54315-EP, TPS54316-EP

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54312PWPR

TPS54313PWPR

TPS54314PWPR

TPS54315PWPR

TPS54316PWPR

HTSSOP PWP

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS54312PWPR

TPS54313PWPR

TPS54314PWPR

TPS54315PWPR

TPS54316PWPR

HTSSOP

PWP

2000

367.0

38.0

Pack Materials-Page 2

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TPS54313PWPRG4 [TI]

相关型号：

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