TPS54313PWP_技术文档

Typical Size

(6,3 mm x 6,4 mm)

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT)

FEATURES

DESCRIPTION

D

60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink

Current

0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V Fixed

Output Voltage Devices With 1% Initial

Accuracy

Internally Compensated for Low Parts Count

Fast Transient Response

Wide PWM Frequency: Fixed 350 kHz, 550

kHz, or Adjustable 280 kHz to 700 kHz

Load Protected by Peak Current Limit and

Thermal Shutdown

Integrated Solution Reduces Board Area and

Total Cost

As members of the SWIFT family of dc/dc regulators, the

TPS54311, TPS54312, TPS54313, TPS54314,

TPS54315 and TPS54316 low-input-voltage high-output-

current synchronous-buck PWM converters integrate all

required active components. Included on the substrate

with the listed features are a true, high performance,

voltage error amplifier that provides high performance

under transient conditions; an undervoltage-lockout circuit

to prevent start-up until the input voltage reaches 3 V; an

internally and externally set slow-start circuit to limit

in-rush currents; and a power good output useful for

processor/logic reset, fault signaling, and supply

sequencing.

D

The TPS54311, TPS54312, TPS54313, TPS54314,

TPS54315 and TPS54316 devices are available in a

thermally enhanced 20-pin TSSOP (PWP) PowerPAD

package, which eliminates bulky heatsinks. TI provides

evaluation modules and the SWIFTdesigner software tool

to aid in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

APPLICATIONS

D

Low-Voltage, High-Density Systems With

Power Distributed at 5 V or 3.3 V

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

D

Broadband, Networking and Optical

Communications Infrastructure

Portable Computing/Notebook PCs

EFFICIENCY

vs

LOAD CURRENT

SimplifiedSchematic

96

94

92

90

88

86

84

Input

Output

VIN

PH

TPS54316

BOOT

PGND

VBIAS

VSENSE

GND

T

A

= 25°C

V

= 5 V

82

80

I

= 3.3 V

O

0

0.5

1

1.5

2

2.5

3

Load Current – A

Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of TexasInstruments.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Copyright  2002 – 2003, Texas Instruments Incorporated

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring

storageor handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OUTPUT

VOLTAGE

PACKAGED DEVICES

PLASTICHTSSOP(PWP)

OUTPUT

VOLTAGE

PACKAGED DEVICES

PLASTICHTSSOP(PWP)

T

A

T

A

(1)

0.9 V

TPS54311PWP

TPS54312PWP

TPS54313PWP

1.8 V

2.5 V

3.3 V

TPS54314PWP

TPS54315PWP

TPS54316PWP

1.2 V

–40°C to 85°C

1.5 V

(1)

ThePWP package is also available taped and reeled. Add an R suffixtothedevicetype(i.e., TPS54316PWPR). Seeapplicationsectionofdata

sheet for PowerPAD drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

overoperating free-air temperature range unless otherwise noted

(1)

TPS54310

–0.3 V to 7 V

–0.3 V to 6 V

–0.3 V to 4 V

–0.3 V to 17 V

–0.3 V to 7 V

–0.6 V to 10 V

InternallyLimited

6 mA

VIN, SS/ENA, SYNC

RT

Input voltage range, V

I

VSENSE

BOOT

VBIAS, PWRGD, COMP

Output voltage range, V

O

PH

Source current, I

Sink current

O

COMP, VBIAS

PH

6 A

COMP

6 mA

SS/ENA,PWRGD

AGND to PGND

10 mA

Voltagedifferential

0.3 V

Operating virtual junction temperature range, T

–40°C to 125°C

–65°C to 150°C

300°C

J

Storagetemperature,T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice. Thesearestressratingsonly,and

functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

6

UNIT

V

Inputvoltage range, V

3

I

Operatingjunctiontemperature, T

–40

125

°C

J

(1) (2)

PACKAGE DISSIPATION RATINGS

THERMALIMPEDANCE

JUNCTION-TO-AMBIENT

T

= 25°C

T

= 70°C

T = 85°C

A

POWER RATING

A

PACKAGE

POWER RATING

(3)

20-Pin PWP with solder

26.0°C/W

57.5°C/W

3.85 W

2.12 W

1.54 W

20-Pin PWP without solder

1.73 W

0.96 W

0.69 W

(1)

(2)

For more information on the PWP package, refer to TI technical brief (SLMA002).

Test board conditions:

1. 3” × 3”, 2 layers, Thickness: 0.062”

2. 1.5 oz copper traces located on the top of the PCB

3. 1.5 oz copper ground plane on the bottom of the PCB

4. Ten thermal vias (see recommended land pattern in application section of this data sheet)

Maximum power dissipation may be limited by overcurrent protection.

(3)

2

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

ELECTRICAL CHARACTERISTICS

T = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE, VIN

VIN input voltage range

3

6

V

f = 350 kHz,

FSEL = 0.8 V,

RT open

RT open,

6.2

8.4

1

9.6

s

f = 550 kHz,

FSEL ≥ 2.5 V,

s

12.8

1.4

Quiescentcurrent

mA

Phase pin open

Shutdown,

SS/ENA = 0 V

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.95

2.80

0.16

3

V

2.70

0.14

Rising and falling edge deglitch,

UVLO

2.5

µs

(1)

BIAS VOLTAGE

Output voltage, VBIAS

(2)

I

= 0

2.70

2.80

2.90

100

V

(VBIAS)

Output current, VBIAS

OUTPUT VOLTAGE

µA

T = 25°C,

VIN = 5 V

0.9

1.2

1.5

1.8

2.5

3.3

V

J

TPS54311

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

–40 ≤ T ≤ 125 –2.5%

2.5%

J

T = 25°C,

J

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

–40 ≤ T ≤ 125

–2.5%

J

T = 25°C,

J

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

–40 ≤ T ≤ 125

J

V

O

Outputvoltage

T = 25°C,

J

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

–40 ≤ T ≤ 125

J

T = 25°C,

J

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

VIN = 5 V

–40 ≤ T ≤ 125

J

T = 25°C,

J

3 ≤ VIN ≤ 6 V,

0 ≤ IL ≤ 3 A,

–40 ≤ T ≤ 125

J

REGULATION

Lineregulation

(1) (3)

I

L

I

L

= 1.5 A,

350 ≤ f ≤ 550 kHz, T = 85°C

0.21

%/V

%/A

s

J

Load regulation

OSCILLATOR

= 0 A to 3 A,

350 ≤ f ≤ 550 kHz, T = 85°C

s

J

FSEL ≤ 0.8 V,

FSEL ≥ 2.5 V,

RT open

280

440

252

460

663

2.5

350

550

280

500

700

420

660

308

540

762

Internallysetfree-runningfrequency

range

kHz

(1)

RT = 180 kΩ (1% resistor to AGND)

Externally set free-running frequency

range

RT = 100 kΩ (1% resistor to AGND)

(1)

RT = 68 kΩ (1% resistor to AGND)

High-level threshold voltage at FSEL

Low-level threshold voltage at FSEL

V

0.8

(1)

Ramp valley

Rampamplitude(peak-to-peak)

0.75

1

V

(1)

V

Minimumcontrollableontime

Maximum duty cycle

200

ns

90%

(1)

(2)

(3)

Specified by design

Static resistive loads only

Specified by the circuit used in Figure 10.

3

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

T = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER

(1)

Error amplifier open loop voltage gain

(1)

Error amplifier unity gain bandwidth

26

5

dB

3

MHz

PWM COMPARATOR

PWMcomparatorpropagationdelaytime,

PWM comparator input to PH pin (ex-

cluding dead time)

(1)

10 mV overdrive

70

85

ns

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA

0.82

1.20

0.03

2.5

3.3

4.5

5.6

3.3

4.7

6.1

5

1.40

V

(1)

Falling edge deglitch, SS/ENA

µs

TPS54311

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

2.6

3.5

4.4

2.6

3.6

4.7

3

4.1

5.4

6.7

4.1

5.6

7.6

8

(1)

Internal slow-start time

ms

Charge current, SS/ENA

SS/ENA = 0 V

µA

Discharge current, SS/ENA

SS/ENA = 0.2 V,

V = 1.5 V

I

1.5

2.3

4

mA

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage

VSENSEfalling

90

3

%V

ref

(1)

ref

Power good falling edge deglitch

Output saturation voltage, PWRGD

Leakage current, PWRGD

35

µs

I

= 2.5 mA

0.18

0.30

1

V

(sink)

V = 5.5 V

µA

I

CURRENT LIMIT

(1)

V = 3 V, output shorted

4

6.5

7.5

I

Current limit trip point

A

V = 6 V, output shorted

I

4.5

(1)

Current limit leading edge blanking time

Current limit total response time

100

200

ns

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

135

150

10

165

°C

Thermalshutdownhysteresis

OUTPUT POWER MOSFETS

(2)

V = 6 V

59

85

88

I

r

Power MOSFET switches

mΩ

DS(on)

V = 3 V

I

136

(1)

(2)

Specified by design

MatchedMOSFETs, low side r

production tested, high side r

DS(on)

specified by design

DS(on)

4

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

PIN ASSIGNMENTS

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

AGND

VSENSE

NC

PWRGD

BOOT

PH

RT

19

18

17

16

15

14

13

12

11

FSEL

SS/ENA

VBIAS

VIN

PGND

PH

NC – No internal connection

Terminal Functions

TERMINAL

DESCRIPTION

NAME

AGND

NO.

1

Analogground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and

FSEL pin. Make PowerPAD connection to AGND.

BOOT

5

Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-sideFET driver.

FSEL

NC

19

3

Frequency select input. Provides logic input to select between two internally set switching frequencies.

Noconnection

PGND

11–13 Powerground.Highcurrentreturnforthelow-sidedriverandpowerMOSFET.ConnectPGNDwithlargecopperareastothe

inputand output supply returns, and negative terminals of the input and output capacitors.

PH

6–10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

PWRGD

4

Power good open drain output. Hi-Z when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when

ref

SS/ENA is low or internal shutdown signal active.

RT

20

18

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f .

s

SS/ENA

Slow-start/enableinput/output.Dualfunctionpinwhichprovideslogicinputtoenable/disabledeviceoperationandcapacitor

inputto externally set the start-up time.

VBIAS

VIN

17

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.

14–16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect directly to output voltage sense point.

5

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

VBIAS

AGND

VBIAS

VIN

Enable

Comparator

5 µA

SS/ENA

REG

Falling

Edge

Deglitch

SHUTDOWN

VIN

ILIM

Comparator

1.2 V

VIN

Thermal

Shutdown

145°C

Hysteresis: 0.03 V

Leading

Edge

Blanking

2.5 µs

VIN UVLO

Comparator

Falling

and

Rising

Edge

100 ns

VIN

BOOT

2.95 V

Deglitch

Hysteresis: 0.16 V

2.5 µs

SS_DIS

SHUTDOWN

L

OUT

V

O

PH

Internal/External

Slow-Start

(Internal Slow-Start Time =

3.3 ms to 6.6 ms)

+

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

–

2 kΩ

PWM

Comparator

40 kΩ

Error

Amplifier

VIN

25 ns Adaptive

Deadtime

V

I

Feed-Forward

V

I

OSC

PGND

Compensation

Power good

Comparator

Reference/

DAC

Falling

Edge

PWRGD

VSENSE

0.90 V

ref

Deglitch

TPS5431x

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

FSEL

VSENSE

RT

6

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

TYPICAL CHARACTERISTICS

INTERNALLY SET OSCILLATOR

FREQUENCY

DRAIN-SOURCE ON-STATE RESISTANCE DRAIN-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

120

100

80

100

80

60

40

20

0

750

650

550

450

V

= 3.3 V

V = 5 V

I

= 3 A

O

I

= 3 A

O

FSEL ≥ 2.5 V

60

FSEL ≤ 0.8 V

40

350

250

20

0

–40

0

25

85

125

–40

0

25

85

125

–40

0

25

85

125

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 1

Figure 2

Figure 3

EXTERNALLY SET OSCILLATOR

FREQUENCY

OUTPUT VOLTAGE REGULATION

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

0.8950

0.8930

0.8910

0.8890

800

0.895

T

A

= 85°C

RT = 68 k

700

600

500

400

0.893

0.891

RT = 100 k

f = 350 kHz

0.889

RT = 180 k

0.8870

0.8850

0.887

0.885

300

200

–40

0

25

85

125

3

4

5

6

–40

0

25

85

125

V – Input Voltage – V

I

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 4

Figure 5

Figure 6

INTERNAL SLOW-START TIME

vs

JUNCTION TEMPERATURE

DEVICE POWER LOSSES

vs

ERROR AMPLIFIER

OPEN LOOP RESPONSE

LOAD CURRENT

3.80

3.65

3.50

3.35

3.20

3.05

0

–20

140

2.25

2

R = 10 kΩ,

L

T

f

– 125°C,

J

C

L

= 160 pF,

120

= 700 kHz

s

T

A

= 25°C

–40

–60

–80

1.75

100

80

60

40

20

0

1.5

V

= 3.3 V

I

Phase

1.25

–100

–120

1

0.75

0.5

V

= 5 V

Gain

I

–140

–160

2.90

2.75

–180

–200

0.25

0

–20

–40

0

25

85

125

0

10

100 1 k 10 k 100 k 1 M 10 M

0

1

2

3

4

T

J

– Junction Temperature – °C

I

– Load Current – A

f – Frequency – Hz

L

Figure 8

Figure 9

Figure 7

7

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical

TPS54314 application. The TPS54314 (U1) can provide

up to 3 A of output current at a nominal output voltage of

1.8 V. For proper thermal performance, the PowerPAD

underneath the TPS54314 integrated circuit needs to be

soldered to the printed circuit board.

J1

2

V

I

+

U1

1

C2

1

GND

R1

10 kΩ

TPS54314PWP

R7

1

20

19

18

AGND

RT

2

3

4

5

6

7

8

71.5 kΩ

VSENSE

FSEL

NC

SS/ENA

VBIAS

VIN

17

16

15

PWRGD

BOOT

PWRGD

L1

C7

0.047 µF

C8

10 µF

C3

0.1 µF

PH

VIN

14

13

12

11

5.2 µH

J3

VIN

1

2

V

O

PGND

9

GND

PH

+

C9

470 µF

4 V

10

C11

1000 pF

PwrPAD

1

Optional

Figure 10. TPS54314 Schematic

The output filter components work with the internal

compensation network to provide a stable closed loop

response for the converter.

INPUT VOLTAGE

The input to the circuit is a nominal 5 VDC, applied at J1.

The optional input filter (C2) is a 220-µF POSCAP

capacitor, with a maximum allowable ripple current of 3 A.

C8isthedecouplingcapacitorfortheTPS54314andmust

be located as close to the device as possible.

GROUNDING AND PowerPAD LAYOUT

TheTPS54311–16 have two internal grounds (analog and

power). Inside the TPS54311–16, the analog ground ties

toallofthenoisesensitivesignals, whilethepowerground

ties to the noisier power signals. The PowerPAD must be

connected directly to AGND. Noise injected between the

two grounds can degrade the performance of the

TPS54311–16, particularly at higher output currents.

However, ground noise on an analog ground plane can

also cause problems with some of the control and bias

signals. For these reasons, separate analog and power

ground planes are recommended. These two planes

should tie together directly at the IC to reduce noise

between the two grounds. The only components that

should tie directly to the power ground plane are the input

capacitor, the output capacitor, the input voltage

decoupling capacitor, and the PGND pins of the

TPS54311–16. The layout of the TPS54314 evaluation

module is representative of a recommended layout for a

4-layer board. Documentation for the TPS54314

evaluationmodule can be found on the TexasInstruments

web site under the TPS54314 product folder and in the

application note, TI literature number SLVA111.

FEEDBACK CIRCUIT

The output voltage of the converter is fed directly into the

VSENSE pin of the TPS54314. The TPS54314 is

internally compensated to provide stability of the output

under varying line and load conditions.

OPERATING FREQUENCY

In the application circuit, a 700 kHz operating frequency is

selected by leaving FSEL open and connecting a 71.5 kΩ

resistor between the RT pin and AGND. Different

operating frequencies may be selected by varying the

value of R3 using equation 1:

500 kHz

Switching Frequency

R +

100 kW

(1)

Alternately, preset operating frequencies of 350 kHz or

550 kHz my be selected by leaving RT open and

connecting the FSEL pin to AGND or VIN respectively.

OUTPUT FILTER

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

The output filter is composed of a 5.2-µH inductor and

470-µF capacitor. The inductor is a low dc resistance

(16-mΩ) type, Sumida CDRH104R–5R2. The capacitor

used is a 4-V POSCAP with a maximum ESR of 40 mΩ.

For operation at full rated load current, the analog ground

plane must provide adequate heat dissipating area. A 3

inch by 3 inch plane of 1 ounce copper is recommended,

8

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

thoughnotmandatory,dependingonambienttemperature

andairflow. Most applicationshavelargerareasofinternal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

any area available should be used when 3 A or greater

operationis desired. Connection from theexposedareaof

the PowerPAD to the analog ground plane layer should be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Six vias should be in the

PowerPAD areawithfouradditionalviaslocatedunderthe

device package. The size of the vias under the package,

butnot in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the ten recommended

that enhance thermal performance should be included in

areas not under the device package.

6 PL ∅ 0.0130

4 PL ∅ 0.0180

Minimum Recommended Thermal Vias: 6 × .013 dia.

Inside Powerpad Area 4 × .018 dia. Under Device as Shown.

Additional .018 dia. Vias May be Used if Top Side Analog

Ground Area is Extended.

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0227

0.0600

0.0400

0.2560

0.2454

0.1010

0.0400

0.0600

0.0256

0.1700

0.1340

Minimum Recommended Exposed

Copper Area For Powerpad. 5mm

0.0620

0.0400

Minimum Recommended Top

Side Analog Ground Area

Stencils may Require 10 Percent

Larger Area

Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD

9

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

PERFORMANCE GRAPHS

OUTPUT VOLTAGE

EFFICIENCY

vs

LOAD CURRENT

vs

LOAD CURRENT

1.9

LOOP RESPONSE

60

45

180

135

100

Efficiency at 700 kHz

Phase

90

80

70

5 V

I

1.85

90

45

30

15

3.3 V

I

Gain

3.3 V

1.8

I

0

5 V

0

I

1.75

1.7

–45

–90

–15

–30

60

50

100

1 k

10 k

100 k

1 M

0

1

2

3

4

5

0

1

2

3

4

5

f – Frequency – Hz

I

– Load Current – A

L

Load Current – A

Figure 12

Figure 14

Figure 13

LOAD TRANSIENT RESPONSE

START-UP WAVEFORMS

OUTPUT RIPPLE VOLTAGE

V

2 V/div

I

V

50 mV/div

O

V

(AC)

O

10 mV/div

V

2 V/div

O

I

2 A/div

O

V

I

= 5 V

= 3 A

I

O

V

5 V/div

PWRGD

V

= 5 V

400 ns/div

I

Time – 2 ms/div

Time – 100 µs/div

Time – 10 µs/div

Figure 17

Figure 15

Figure 16

AMBIENTTEMPERATURE

vs

LOAD CURRENT

125

115

105

95

†

Safe operating area is applicable to the test

boardconditions listed intheDissipationRating

Table section of this data sheet.

85

75

65

55

†

Safe Operating Area

45

35

25

0

1

2

3

4

I

– Load Current – A

L

Figure 18

10

TPS54311, TPS54312

TPS54313,TPS54314

www.ti.com

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

The actual slow-start is likely to be less than the above

approximationdue to the brief ramp-up attheinternalrate.

DETAILED DESCRIPTION

Under Voltage Lock Out (UVLO)

VBIAS Regulator (VBIAS)

TheTPS54311–16incorporatesanundervoltagelockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

thresholdvoltageof2.95V.OncetheUVLOstartthreshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs

risingandfallingedgedeglitchcircuitreducethelikelihood

of shutting the device down due to noise on VIN.

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommendedbecause their values are more stable over

temperature.Thebypasscapacitorshouldbeplacedclose

to the VBIAS pin and returned to AGND. External loading

on VBIAS is allowed, with the caution that internal circuits

requirea minimum VBIAS of 2.70 V, and external loads on

VBIAS with ac or digital switching noise may degrade

performance.The VBIAS pin may be useful as a reference

voltage for external circuits.

Slow-Start/Enable (SS/ENA)

The slow-start/enable pin provides two functions; first, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceedsthe enable threshold, device start up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.

Voltage Reference

The voltage reference system produces a precise V

ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precisionregulationoftheTPS54311–16, sinceitcancels

offset errors in the scale and error amplifier circuits.

OUTPUT

VOLTAGE

DEVICE

SLOW-START

Oscillator and PWM Ramp

TPS54311

0.9 V

3.3 ms

4.5 ms

5.6 ms

3.3 ms

4.7 ms

6.1 ms

The oscillator frequency can be set to internally fixed

valuesof350kHzor550kHzusingtheFSELpinasastatic

digitalinput. Ifadifferentfrequencyofoperationisrequired

for the application, the oscillator frequency can be

externallyadjustedfrom280kHzto700kHzbyconnecting

aresistortotheRTpintogroundandfloatingtheFSELpin.

The switching frequency is approximated by the following

equation, where R is the resistance from RT to AGND:

TPS54312

TPS54313

TPS54314

TPS54315

TPS54316

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and

AGND. Adding a capacitor to the SS/ENA pin has two

effects on start-up. First, a delay occurs between release

of the SS/ENA pin and start up of the output. The delay is

proportionaltotheslow-startcapacitorvalueandlastsuntil

the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

100 kW

SWITCHING FREQUENCY +

500 kHz

R

(4)

Table 1. Summary of the Frequency Selection

Configurations

SWITCHING

FREQUENCY

FSEL PIN

RT PIN

350 kHz, internally

set

Float or AGND

Float

550 kHz, internally

set

≥ 2.5 V

1.2 V

5 mA

t

+ C

d

(SS)

(2)

Externally set 280

kHz to 700 kHz

Float

R = 68 k to 180 k

Second, as the output becomes active, a brief ramp-up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

Error Amplifier

The high performance, wide bandwidth, voltage error

amplifier is gain limited to provide internal compensation

of the control loop. The user is given limited flexibility in

choosing output L and C filter components. Inductance

0.7 V

5 mA

t

+ C

(SS)

(3)

11

TPS54311, TPS54312

TPS54313,TPS54314

TPS54315,TPS54316

SLVS416A – FEBRUARY 2002 – JULY 2003

www.ti.com

values of 4.7 µH to 10 µH are typical and available from

several vendors. The resulting designs exhibit good noise

andripplecharacteristics, alongwithexceptionaltransient

response. Transient recovery times are typically in the

range of 10 to 20 µs.

turn-ontimes of the MOSFET drivers. Thehigh-sidedriver

does not turn on until the gate drive voltage to the low-side

FET is below 2 V. The low-side driver does not turn on until

the voltage at the gate of the high-side MOSFETs is below

2 V. The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is supplied

from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

PWM Control

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWMlatch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately reset and set the PWM latch. Once

the PWM latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse duration.

During this period, the PWMrampdischargesrapidlytoits

valley voltage. When the ramp begins to charge back up,

the low-side FET turns off and high-side FET turns on. As

the PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

Overcurrent Protection

The cycle by cycle current limiting is achieved by sensing

the current flowing through the high-side MOSFET and

differential amplifier and comparing it to the preset

overcurrent threshold. The high-side MOSFET is turned

off within 200 ns of reaching the current limit threshold. A

100-ns leading edge blanking circuit prevents false

tripping of the current limit. Current limit detection occurs

only when current flows from VIN to PH when sourcing

current to the output filter. Load protection during current

sink operation is provided by thermal shutdown.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

latch is never reset and the high-side FET remains onuntil

the oscillator pulse signals the control logic to turn the

high-side FET off and the low-side FET on. The device

operatesatitsmaximumdutycycleuntiltheoutputvoltage

rises to the regulation set-point, setting VSENSE to

Thermal Shutdown

Thedeviceusesthethermalshutdowntoturnoffthepower

MOSFETs and disable the controller if the junction

temperatureexceeds 150°C. The device is released from

shutdown when the junction temperature decreases to

10°C below the thermal shutdown trip point and starts up

under control of the slow-start circuit. Thermal shutdown

provides protection when an overload condition is

sustained for several milliseconds. With a persistent fault

condition, the device cycles continuously; starting up by

control of the soft-start circuit, heating up due to the fault,

and then shutting down upon reaching the thermal

shutdown point.

approximately the same voltage as V . If the error

ref

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54311 – 16 is capable of sinking current

continuously until the output reaches the regulation

set-point.

Power Good (PWRGD)

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and

low-sideFETturnsontodecreasetheenergyintheoutput

inductor and consequently the output current. This

process is repeated each cycle in which the current limit

comparator is tripped.

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold, or SS/ENA is low, or

thermal shutdown is asserted. When VIN = UVLO

threshold, SS/ENA = enable threshold, and VSENSE >

Dead-Time Control and MOSFET Drivers

90% of V , the open drain output of the PWRGD pin is

ref

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

high. A hysteresis voltage equal to 3% of V and a 35-µs

falling edge deglitch circuit prevent tripping of the power

good comparator due to high frequency noise.

ref

12

THERMAL PAD MECHANICAL DATA

PWP (R-PDSO-G20)

PowerPAD™ PLASTIC SMALL-OUTLINE

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型号：	TPS54313PWP
厂家：	TEXAS INSTRUMENTS
描述：	3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs 3 V至6 V的输入， 3 -A输出同步降压PWM具有集成FET SWITCHER 输出元件输入元件
文件：	总15页 (文件大小：550K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS54313PWP [TI]

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