TPS54340 [TI]
42 V Input, 3.5 A, Step Down DC-DC Converter with Eco-mode; 42 V输入， 3.5 A降压DC -DC转换器具有Eco-Mode
| 型号： | TPS54340 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 42 V Input, 3.5 A, Step Down DC-DC Converter with Eco-mode |
| 文件： | 总43页 (文件大小：1949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54340
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SLVSBK0A –OCTOBER 2012–REVISED FEBRUARY 2013
42 V Input, 3.5 A, Step Down DC-DC Converter with Eco-mode™
Check for Samples: TPS54340
1
FEATURES
2
•
4.5 V to 42 V (45 V Abs Max) Input Range
•
•
•
•
Adjustable UVLO Voltage and Hysteresis
•
3.5 A Continuous Current, 4.5 A Minimum Peak
Inductor Current Limit
Internal Soft-Start
Accurate Cycle-by-Cycle Current Limit
•
•
•
Current Mode Control DC-DC Converter
Thermal, Overvoltage, and Frequency
Foldback Protection
92-mΩ High-Side MOSFET
High Efficiency at Light Loads with Pulse
Skipping Eco-mode™
•
•
•
•
0.8 V 1% Internal Voltage Reference
8-Pin HSOIC with PowerPAD™ Package
–40°C to 150°C TJ Operating Range
Supported by WEBENCH™ Software Tool
•
Low Dropout at Light Loads with Integrated
BOOT Recharge FET
•
•
•
•
146 μA Operating Quiescent Current
1 μA Shutdown Current
APPLICATIONS
100 kHz to 2.5 MHz Fixed Switching Frequency
Synchronizes to External Clock
•
12 V, 24 V and 48 V Industrial, Automotive and
Communications Power Systems
DESCRIPTION
The TPS54340 is a 42 V, 3.5 A, step down regulator with an integrated high side MOSFET. The device survives
load dump pulses up to 45 V per ISO 7637. Current mode control provides simple external compensation and
flexible component selection. A low ripple pulse skip mode reduces the no load supply current to 146 μA.
Shutdown supply current is reduced to 1 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can be increased using the enable pin. The output voltage start
up ramp is internally controlled to provide a controlled start up and eliminate overshoot.
A wide switching frequency range allows either efficiency or external component size to be optimized. Frequency
foldback and thermal shutdown protects internal and external components during an overload condition.
The TPS54340 is available in an 8-pin thermally enhanced HSOIC PowerPAD™ package.
SIMPLIFIED SCHEMATIC
EFFICIENCY vs LOAD CURRENT
100
90
V
VIN
IN
80
70
60
50
40
30
20
10
0
TPS54340
EN
BOOT
V
= 12V
IN
V
OUT
fsw = 600 kHz
SW
RT/CLK
COMP
R1
V
V
= 3.3V
= 5V
OUT
OUT
FB
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
R3
I
- Output Current - A
GND
O
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Eco-mode, PowerPAD, WEBENCH are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS54340
SLVSBK0A –OCTOBER 2012–REVISED FEBRUARY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
8 Pin HSOIC
TPS54340DDA
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com..
DEVICE INFORMATION
PIN CONFIGURATION
HSOIC PACKAGE
(TOP VIEW)
BOOT
VIN
1
2
3
4
8
7
6
5
SW
GND
COMP
FB
Thermal
Pad
9
EN
RT/CLK
PIN FUNCTIONS
PIN
NAME
I/O
DESCRIPTION
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
BOOT
1
O
VIN
EN
2
3
I
I
Input supply voltage with 4.5 V to 42 V operating range.
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the operating mode returns to resistor frequency programming.
RT/CLK
4
I
FB
5
6
I
Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
COMP
O
GND
SW
7
8
9
–
I
Ground
The source of the internal high-side power MOSFET and switching node of the converter.
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
Thermal Pad
–
2
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FUNCTIONAL BLOCK DIAGRAM
EN
VIN
Shutdown
Thermal
Shutdown
UVLO
Enable
OV
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Current
Sense
Skip
Error
Amplifier
PWM
FB
Comparator
BOOT
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft-Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012A 0192789
RT/CLK
GND
POWERPAD
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
MAX
VIN
EN
45
8.4
BOOT
53
Input voltage
FB
V
–0.3
–0.3
–0.3
3
COMP
3
RT/CLK
BOOT-SW
3.6
8
Output voltage
SW
–0.6
–2
45
45
V
SW, 10-ns Transient
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)
Operating junction temperature
2
kV
V
500
–40 to 150
–65 to 150
°C
°C
Storage temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54340
THERMAL METRIC(1)(2)
UNITS
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
Junction-to-board thermal resistance
42.0
5.9
ψJT
ψJB
23.4
45.8
3.6
°C/W
θJCtop
θJCbot
θJB
23.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
4
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
4.5
4.1
42
V
V
Internal undervoltage lockout threshold
Rising
4.3
4.48
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
1.3
3.5
μA
Operating: nonswitching supply current
FB = 0.83 V, TA = 25°C
146
175
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold +50 mV
1.1
1.2
–4.6
–1.2
–3.4
540
1.3
V
Input current
μA
Enable threshold –50 mV
–0.58
–2.2
-1.8
-4.5
Hysteresis current
Enable to COMP active
INTERNAL SOFT-START TIME
Soft-Start Time
μA
VIN = 12 V , TA = 25°C
µs
fSW = 500 kHz, 10% to 90%
fSW = 2.5 MHz, 10% to 90%
2.1
ms
ms
Soft-Start Time
0.42
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
190
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
VIN = 12 V, TA = 25°C
92
mΩ
Minimum controllable on time
ERROR AMPLIFIER
Input current
135
ns
50
nA
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
VFB = 0.8 V
350
μMhos
Error amplifier transconductance (gM) during
soft-start
77
μMhos
Error amplifier dc gain
Min unity gain bandwidth
10,000
2500
±30
V/V
kHz
μA
Error amplifier source/sink
COMP to SW current transconductance
CURRENT LIMIT
V(COMP) = 1 V, 100 mV overdrive
12
A/V
All VIN and temperatures, Open Loop(1)
All temperatures, VIN = 12 V, Open Loop(1)
VIN = 12 V, TA = 25°C, Open Loop(1)
4.5
4.5
5.2
5.5
5.5
5.5
60
6.8
6.25
5.85
Current limit threshold
A
Current limit threshold delay
THERMAL SHUTDOWN
ns
Thermal shutdown
176
12
°C
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
100
450
160
2500
550
kHz
kHz
kHz
ns
fSW
Switching frequency
RT = 200 kΩ
500
Switching frequency range using CLK mode
Minimum CLK input pulse width
RT/CLK high threshold
2300
15
1.55
1.2
1.7
V
RT/CLK low threshold
0.5
V
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
Measured at 500 kHz
55
78
ns
PLL lock in time
μs
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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TYPICAL CHARACTERISTICS
ON RESISTANCE vs JUNCTION TEMPERATURE
VOLTAGE REFERENCE vs JUNCTION TEMPERATURE
0.25
0.2
0.15
0.1
0.05
0
0.814
VIN = 12 V
BOOT-SW = 3 V
BOOT-SW = 6 V
0.809
0.804
0.799
0.794
0.789
0.784
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G001
G002
Figure 1.
Figure 2.
SWITCH CURRENT LIMIT vs JUNCTION TEMPERATURE
SWITCH CURRENT LIMIT vs INPUT VOLTAGE
6.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
6.5
VIN = 12 V
TJ = −40°C
TJ = 25°C
TJ = 150°C
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
4.5
0
−50
−25
0
25
50
75
100
125
150
5
10
15
20
25
30
35
40
45
TJ − Junction Temperature (°C)
G003
VIN − Input Voltage (V)
G004
Figure 3.
Figure 4.
SWITCHING FREQUENCY vs RT/CLK RESISTANCE
HIGH FREQUENCY RANGE
SWITCHING FREQUENCY vs JUNCTION TEMPERATURE
550
500
ƒSW (kHz) = 92417 × RT (kΩ)−0.991
RT (kΩ) = 101756 × fSW (kHz)−1.008
RT = 200 kΩ, VIN = 12 V
540
450
400
350
300
250
200
150
100
50
530
520
510
500
490
480
470
460
450
0
200
−50
−25
0
25
50
75
100
125
150
300
400
500
600
700
800
900 1000
TJ − Junction Temperature (°C)
RT/CLK − Resistance (kΩ)
G005
G006
Figure 5.
Figure 6.
6
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY vs RT/CLK RESISTANCE
LOW FREQUENCY RANGE
EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE
500
2500
2000
1500
1000
500
VIN = 12 V
450
400
350
300
250
200
0
0
50
100
150
200
−50
−25
0
25
50
75
100
125
150
RT/CLK − Resistance (kΩ)
TJ − Junction Temperature (°C)
G007
G008
Figure 7.
Figure 8.
EA TRANSCONDUCTANCE DURING SOFT-START vs
JUNCTION TEMPERATURE
EN PIN VOLTAGE vs JUNCTION TEMPERATURE
120
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
VIN = 12 V
VIN = 12 V
110
100
90
80
70
60
50
40
30
20
1.19
1.18
1.17
1.16
1.15
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G009
G010
Figure 9.
Figure 10.
EN PIN CURRENT vs JUNCTION TEMPERATURE
EN PIN CURRENT vs JUNCTION TEMPERATURE
−0.5
−0.7
−0.9
−1.1
−1.3
−1.5
−1.7
−1.9
−2.1
−2.3
−2.5
−4
−4.1
−4.2
−4.3
−4.4
−4.5
−4.6
−4.7
−4.8
−4.9
−5
VIN = 5 V,IEN = Threshold+50mV
VIN = 12 V,IEN = Threshold+50mV
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
Tj − Junction Temperature (°C)
100
125
150
TJ − Junction Temperature (°C)
G011
G012
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
EN PIN CURRENT HYSTERESIS vs JUNCTION
TEMPERATURE
SWITCHING FREQUENCY vs FB
−2.5
−2.7
−2.9
−3.1
−3.3
−3.5
−3.7
−3.9
−4.1
−4.3
−4.5
100
75
50
25
0
VFB Falling
VFB Rising
VIN = 12 V
−50
−25
0
25
50
75
100
125
150
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TJ − Junction Temperature (°C)
VFB (V)
G112
G013
Figure 13.
Figure 14.
SHUTDOWN SUPPLY CURRENT vs JUNCTION
TEMPERATURE
SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (VIN
)
3
2.5
2
3
VIN = 12 V
TJ = 25°C
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
−50
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
TJ − Junction Temperature (°C)
G014
VIN − Input Voltage (V)
G016
Figure 15.
Figure 16.
VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE
VIN SUPPLY CURRENT vs INPUT VOLTAGE
210
210
190
170
150
130
110
90
VIN = 12 V
TJ = 25°C
190
170
150
130
110
90
70
−50
70
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
TJ − Junction Temperature (°C)
G016
VIN − Input Voltage (V)
G018
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
BOOT-SW UVLO vs JUNCTION TEMPERATURE
INPUT VOLTAGE UVLO vs JUNCTION TEMPERATURE
2.6
2.5
2.4
2.3
2.2
2.1
2
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
4.4
4.3
4.2
4.1
4
3.9
UVLO Start Switching
UVLO Stop Switching
1.9
1.8
3.8
3.7
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
Tj − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G018
G019
Figure 19.
Figure 20.
SOFT-START TIME vs SWITCHING FREQUENCY
10
V
T
= 12V,
IN
= 25oC
9
8
7
6
5
J
4
3
2
1
0
100 300 500 700 900 110013001500 17001900 2100 2300 2500
Switching Frequency (KHz)
G021
Figure 21.
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OVERVIEW
The TPS54340 is a 42 V, 3.5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop
(PLL) connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external
clock signal.
The TPS54340 has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust the
input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current
source enables operation when the EN pin is floating. The operating current is 146 μA under no load condition
(not switching). When the device is disabled, the supply current is 1 μA.
The integrated 92mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 3.5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54340 reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54340 includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-
rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54340 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an
error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
at the COMP pin controls the high side power switch current. When the high side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will
increase and decrease as the output current increases and decreases. The device implements current limiting by
clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
Slope Compensation Output Current
The TPS54340 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
Pulse Skip Eco-mode
The TPS54340 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
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DETAILED DESCRIPTION (continued)
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since
the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling
output voltage by increasing the COMP pin voltage. The high side MOSFET is enabled and switching resumes
when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the
regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54340 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 33 enters Eco-mode at about TBD mA output current. As the load current approaches
zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.
Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54340 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high
side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54340 will
operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1V. When the voltage from
BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output
voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
The start and stop voltage for a typical 5 V output application is shown in Figure 22 where the Vin voltage is
plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
spacer
5.6
5.5
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
4.8
Voltage
4.7
4.6
Start
0.35 0.4
Stop
0.45 0.5
0
0.05
0.1
0.15 0.2
0.25 0.3
Load Current - A
Figure 22. 5V Start/Stop Voltage
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DETAILED DESCRIPTION (continued)
Error Amplifier
The TPS54340 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-
start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. It is recommended to use 1% tolerance or better divider resistors.
Select the low side resistor RLS for the desired divider current and use Equation 1 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator
will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
Vout - 0.8V
æ
ö
RHS = RLS
´
ç
÷
0.8 V
è
ø
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54340 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54340 is disabled when the VIN pin voltage falls below 4 V or when the EN
pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables operation
of the TPS54340 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4
μA Ihys current is removed. This addional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 2 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 3 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (e.g., 4.5 V) and withstand high input voltages
(e.g., 40 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8.4 V during the
high input voltage condition. It is recommended to use a zener diode to clamp the pin voltage below the absolute
maximum rating.
VIN
TPS54340
i1 ihys
R
UVLO1
EN
Optional
VEN
R
UVLO2
Figure 23. Adjustable Undervoltage Lockout (UVLO)
V
- V
STOP
START
R
=
UVLO1
I
HYS
(2)
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DETAILED DESCRIPTION (continued)
V
ENA
R
=
UVLO2
V
- V
ENA
START
+ I
1
R
UVLO1
(3)
Internal Soft-Start
The TPS54340 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value
in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 4
1024
t
(ms) =
SS
f
(kHz)
SW
(4)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets. The
soft-start also resets in thermal shutdown.
Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54340 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 5 or Equation 6 or the curves in Figure 5 and Figure 6. To reduce the solution size one
would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage and minimum controllable on time should be considered. The minimum controllable on
time is typically 135 ns which limits the maximum operating frequency in applications with high input to output
step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in the next section.
92417
f sw (kHz)0.991
RT (kW) =
(5)
101756
RT (kW)1.008
f sw (kHz) =
(6)
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DETAILED DESCRIPTION (continued)
Selecting the Switching Frequency
The TPS54340 implements peak current mode control in which the COMP pin voltage controls the peak current
of the high side MOSFET. A signal proportional to the high side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is
turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the
peak switch current limit. The TPS54340 provides an accurate current limit threshold with a typical current limit
delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 24.
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = V /L x tCLdelay
IN
tCLdelay
tON
Figure 24. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls
from 0.8 V to 0 V. The TPS54340 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 8 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
Equation 7 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
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DETAILED DESCRIPTION (continued)
æ
ç
ö
÷
IO ´Rdc + VOUT + Vd
1
fSW maxskip
=
´
(
)
ç
÷
tON
VIN -IO ´RDS on + Vd
( )
è
ø
(7)
(8)
æ
ö
÷
ICL ´Rdc + VOUT sc + Vd
fDIV
( )
ç
fSW(shift)
=
´
ç
÷
tON
VIN -ICL ´RDS on + Vd
( )
è
ø
IO
Output current
ICL
Current limit
Rdc
VIN
VOUT
inductor resistance
maximum input voltage
output voltage
VOUTSC
Vd
output voltage during short
diode voltage drop
RDS(on)
tON
switch on resistance
controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 25. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and
have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit
should be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground
when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is
connected in parallel with an ac coupling capacitor to a termination resistor (e.g., 50 Ω) as shown in Figure 25.
The two resistors in series provide the default frequency setting resistance when the signal source is turned off.
The sum of the resistance should set the switching frequency close to the external CLK frequency. It is
recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin.
The first time the RT/CLK is pulled above the PLL threshold the TPS54340 switches from the RT resistor free-
running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency
can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor
mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then
increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 volts. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
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DETAILED DESCRIPTION (continued)
TPS54340
PLL
TPS54340
RT/CLK
RT
RT/CLK
RT
PLL
Hi-Z
Clock
Source
Clock
Source
Figure 25. Synchronizing to a System Clock
16
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DETAILED DESCRIPTION (continued)
SW
SW
EXT
EXT
IL
IL
Figure 26. Plot of Synchronizing in CCM
Figure 27. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 28. Plot of Synchronizing in Eco-Mode
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DETAILED DESCRIPTION (continued)
Overvoltage Protection
The TPS54340 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable
time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit
threshold. When the overload condition is removed, the regulator output rises and the error amplifier output
transitions to the normal operating level. In some applications, the power supply output voltage can increase
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high side MOSFET resumes normal operation.
Thermal Shutdown
The TPS54340 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by the internal soft-start circuitry.
Small Signal Model for Loop Response
Figure 29 shows an equivalent model for the TPS54340 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of
3350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro
and capacitor Co model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
V
O
Power Stage
gm 12 A/V
ps
a
b
R
R1
ESR
R
COMP
L
c
FB
C
OUT
0.8 V
CO
RO
R3
C1
gm
ea
C2
R2
350 mA/V
Figure 29. Small Signal Model for Loop Response
18
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DETAILED DESCRIPTION (continued)
Simple Small Signal Model for Peak Current Mode Control
Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54340 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 9 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP pin voltage (node c in Figure 29) is the power stage transconductance,
gmPS. The gmPS for the TPS54340 is 12 A/V. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 10.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 11). The combined effect is highlighted by the dashed line in the right half of
Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 12).
V
O
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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DETAILED DESCRIPTION (continued)
æ
ç
è
ö
÷
ø
s
1+
1+
2p´ fZ
VOUT
= Adc ´
VC
æ
ç
è
ö
÷
ø
s
2p´ fP
(9)
Adc = gmps ´ RL
(10)
1
f
=
P
C
´R ´ 2p
L
OUT
(11)
(12)
1
f
=
Z
C
´R
´ 2p
OUT
ESR
Small Signal Model for Frequency Compensation
The TPS54340 uses a transconductance amplifier for the error amplifier and supports three of the commonly-
used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 13 and Equation 14 relate the frequency response of the amplifier to the small
signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 31. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 13 through Equation 22 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
V
O
R1
FB
Type 2A
Type 2B
Type 1
gm
ea
R
COMP
Vref
C2
R3
C1
R3
R2
C2
C
O
O
C1
Figure 31. Types of Frequency Compensation
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DETAILED DESCRIPTION (continued)
Aol
A0
P1
Z1
P2
A1
BW
Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
Ro =
(13)
(14)
gmea
CO
=
2p ´ BW (Hz)
æ
ç
è
ö
÷
ø
s
1+
2p´ fZ1
EA = A0´
æ
ç
è
ö æ
ö
÷
ø
s
s
1+
´ 1+
÷ ç
2p´ fP1
2p´ fP2
ø è
(15)
(16)
(17)
R2
A0 = gmea ´ Ro ´
R1 + R2
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
1
P1=
2p´Ro´ C1
(18)
1
Z1=
2p´R3´ C1
(19)
(20)
1
P2 =
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
(21)
(22)
1
P2 =
type 1
2p ´ RO ´ (C2 + CO
)
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APPLICATION INFORMATION
Design Guide — Step-By-Step Design Procedure
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. For this example, we will start with the following known parameters:
Output Voltage
3.3 V
Transient Response 0.875 A to 2.625 A load step
Maximum Output Current
Input Voltage
ΔVOUT = 4 %
3.5 A
12 V nom. 6 V to 42 V
0.5% of VOUT
5.75 V
Output Voltage Ripple
Start Input Voltage (rising VIN)
Stop Input Voltage (falling VIN)
4.5 V
Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 7 and Equation 8 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 7. To ensure overcurrent runaway is not a concern during short circuits use
Equation 8 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92
mΩ, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 5 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 33. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
3.5 A x 21 mW + 3.3 V + 0.7 V
42 V - 3.5 A x 92 mW + 0.7 V
æ
ö
fSW(maxskip)
=
´
= 712 kHz
ç
÷
135ns
è
ø
(23)
(24)
(25)
8
4.7 A x 21 mW + 0.1 V + 0.7 V
42 V - 4.7 A x 92 mW + 0.7 V
æ
ö
fSW(shift)
=
´
= 1260 kHz
ç
÷
135 ns
è
ø
92417
600 (kHz)0.991
RT (kW) =
= 163 kW
22
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L1
5.6uH
VOUT
0.1uF
C4
3.3V, 3.5A
C6
U1
TPS54340DDA
D1
100uF
R5
31.6k
B560C
1
2
3
4
8
7
6
5
BOOT
SW
GND
COMP
FB
6V to 42V
VIN
VIN
EN
C1
C2
GND
FB
R1
365k
FB
RT/CLK
2.2uF
2.2uF
R4
11.5k
9
C8
R6
10.2k
R2
86.6k
R3
162k
47pF
GND
C5
GND
5600pF
GND
GND
Figure 33. 3.3 V Output TPS54340 Design Example.
Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 26.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 28 and Equation 29. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54340 which is nominally 5.5 A.
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V
- VOUT
IN max
(
VOUT
)
42 V - 3.3 V
3.5 A x 0.3
3.3 V
LO min
=
´
=
´
= 4.8 mH
(
)
IOUT ´KIND
V
´ fSW
42 V ´ 600 kHz
IN max
(
)
(26)
spacer
IRIPPLE
V
OUT ´(V
- VOUT )
IN max
(
)
3.3 V x (42 V - 3.3 V)
=
=
= 0.905 A
V
´LO ´ fSW
42 V x 5.6 mH x 600 kHz
IN max
(
)
(27)
spacer
2
æ
ö
2
V
´ V
- V
OUT
(
OUT
)
æ
ç
ç
è
ö
÷
÷
ø
IN max
(
3.3 V ´ 42 V - 3.3 V
)
(
)
1
ç
ç
÷
1
2
2
I
=
I
(
+
´
=
3.5 A
(
+
´
= 3.5 A
)
)
OUT
÷
L rms
(
)
12
V
´L ´ f
12
42 V ´ 5.6 mH ´ 600 kHz
O
SW
IN max
(
)
ç
÷
è
ø
(28)
spacer
IL peak = IOUT
IRIPPLE
0.905 A
2
+
= 3.5 A +
= 3.95 A
(
)
2
(29)
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 30 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A - 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 34. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 31 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and VI is the initial voltage. For this example, the worst case load step
will be from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum
in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 31 yields a minimum
capacitance of 38.6 μF.
Equation 32 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 32 yields 11.4 μF.
Equation 33 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 33 indicates the ESR should be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
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Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 100
μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, well above the minimum
required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 34 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 34 yields 261 mA.
2´ DI
2 ´ 1.75 A
OUT
C
>
=
= 44.9 mF
OUT
f
´ DV
600 kHz x 0.13 V
SW
OUT
(30)
2
(OH ) (OL )
2
2.625 A2 - 0.875 A2
I
-
I
(
)
(
)
= 38.6 mF
COUT > LO
x
= 5.6 mH x
2
2
3.432 V2 - 3.3 V2
V
-
V
I
( ) ( )
(
)
f
(
)
(31)
1
1
1
1
C
>
´
=
x
= 11.4 mF
OUT
8´ f
8 x 600 kHz
16.5 mV
0.905 A
æ
ç
è
ö
÷
ø
æ
ö
V
SW
ORIPPLE
ç
è
÷
ø
I
RIPPLE
16.5 mV
0.905 A
(32)
(33)
V
ORIPPLE
R
<
=
= 18 mW
ESR
I
RIPPLE
V
´ V
- V
OUT
IN max
OUT
(
)
=
3.3 V ´ 42 V - 3.3 V
(
)
(
)
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
I
=
= 261 mA
COUT(rms)
12 ´ V
´L ´ f
O
SW
IN max
(
)
(34)
Catch Diode
The TPS54340 requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 volts
at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 35 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 35, the total loss in the diode is
2.42 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
)
V
(
- V
´ I
´ Vf d
OUT
)
IN max
OUT
C
´ f
´
V
IN
+ Vf d
IN max
(
(
)
j
SW
P =
+
=
D
V
2
(
)
2
42 V - 3.3 V ´ 3.5 A x 0.7 V
(
)
300 pF x 600 kHz x (42 V + 0.7 V)
+
= 2.42 W
(35)
25
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Input Capacitor
The TPS54340 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54340. The input ripple current can be calculated using Equation 36.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, two 2.2 μF, 100 V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 37. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒsw = 600 kHz,
yields an input voltage ripple of 331 mV and a rms input ripple current of 1.74 A.
V
- V
OUT
)
= 3.5 A
(
IN min
(
6 V - 3.3 V
)
V
(
)
3.3 V
6 V
OUT
I
= I
x
x
´
= 1.74 A
OUT
CI rms
(
)
V
V
6 V
IN min
(
IN min
(
)
)
(36)
(37)
I
´ 0.25
3.5 A ´ 0.25
OUT
DV
=
=
= 331 mV
IN
C
´ f
4.4 mF ´ 600 kHz
IN
SW
Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
1 to 4.7
1
EIA Size
VOLTAGE
100 V
50 V
DIALECTRIC
COMMENTS
1210
GRM32 series
Murata
100 V
50 V
1206
2220
2225
1812
1210
1210
1812
GRM31 series
VJ X7R series
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
50 V
100 V
50 V
Vishay
TDK
100 V
100 V
50 V
X7R
C series C4532
C series C3225
100 V
50 V
50 V
100 V
50 V
AVX
X7R dielectric series
1 to 4.7
1 to 2.2
100 V
Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or higher
voltage rating.
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Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54340. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and
ground connected to the EN pin. Equation 2 and Equation 3 calculate the resistance values necessary. For the
example application, a 365 kΩ between Vin and EN (RUVLO1) and a 86.6 kΩ between EN and ground (RUVLO2
)
are required to produce the 8 V and 6.25 V start and stop voltages.
V
- V
STOP
5.75 V - 4.5 V
START
R
=
=
= 368 kW
UVLO1
I
3.4 mA
HYS
(38)
V
1.2 V
5.75 V - 1.2 V
ENA
R
=
=
= 87.8 kW
UVLO2
V
- V
ENA
START
+1.2 mA
+ I
1
365 kW
R
UVLO1
(39)
Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 1, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
VOUT - 0.8 V
3.3 V - 0.8 V
æ
ö
RHS = RLS
x
= 10.2 kW x
= 31.9 kW
ç
÷
0.8 V
0.8 V
è
ø
(40)
Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 41 and
Equation 42. For COUT, use a derated value of 70 μF. Use equations Equation 43 and Equation 44 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 42 is the geometric mean of the modulator pole and the ESR zero and Equation 44 is the mean of
modulator pole and the switching frequency. Equation 43 yields 33.1 kHz and Equation 44 gives 26.9 kHz. Use
the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT max
(
)
3.5 A
fP mod
=
=
2´ p´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
= 2411 Hz
(
)
(41)
1
1
f
=
=
= 455 kHz
Z mod
(
)
2´ p´R
´ C
2 ´ p ´ 5 mW ´ 70 mF
ESR
OUT
(42)
(43)
f
=
f
f
=
2411 Hz x 455 kHz = 33.1 kHz
co
p(mod) x z(mod)
f
600 kHz
SW
f
=
f
=
2411 Hz x
= 26.9 kHz
co
p(mod) x
2
2
(44)
27
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To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
æ
ç
è
ö
÷
ø
æ 2´ p´ f ´ C
ö
÷
ø
V
OUT
æ
ç
è
ö
÷
ø
2´ p´ 26.9 kHz ´ 70 mF
12 A / V
3.3 V
æ
ö
co
OUT
R4 =
x
=
x
= 11.6 kW
ç
ç
÷
gmps
V
x gmea
0.8 V x 350 mA / V
è
ø
è
REF
(45)
1
1
C5 =
=
= 5740 pF
2´ p´R4 x f
2´ p´11.5 kW x 2411 Hz
p(mod)
(46)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 47 and Equation 48 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x R
ESR
70 mF x 5 mW
OUT
C8 =
=
= 30.4 pF
R4
11.5 kW
(47)
(48)
1
1
C8 =
=
= 46.1 pF
R4 x f sw x p
11.5 kW x 600 kHz x p
Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 μA with no load.
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APPLICATION CURVES
V
IN
C4: I
OUT
C4
C3: V
OUT
ac coupled
C3
VOUT -3.3 V offset
Time = 4 ms/div
Time = 100 ms/div
Figure 34. Load Transient
Figure 35. Line Transient (8 V to 40 V)
C1: V
IN
C1: V
IN
C1
C3
C3: EN
C1
C3: EN
C2: V
C2: V
OUT
C3
C2
OUT
C2
Time = 2 ms/div
Time = 2 ms/div
Figure 36. Start-up With VIN
Figure 37. Start-up With EN
C1: SW
C1: SW
C1
C4
C1
C4: I
C4: I
L
L
I
= 100 mA
I
= 3.5 A
OUT
OUT
C2: V
ac coupled
OUT
C2
C4
C2
C2: V
ac coupled
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 38. Output Ripple CCM
Figure 39. Output Ripple DCM
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C1: SW
C1: SW
C1
C1
C4: I
L
C4: I
L
C4
I
= 3.5 A
OUT
C2: V
OUT
ac coupled
C3: V
IN
ac coupled
C2
C2
C4
No Load
Time = 2 ms/div
Time = 2 ms/div
Figure 40. Output Ripple PSM
Figure 41. Input Ripple CCM
C1: SW
C1: SW
C1
C4
C4: I
L
C4
C3
C4: I
I
= 100 mA
L
OUT
C3: V
ac coupled
IN
C3
C3: V
OUT
ac coupled
V
V
= 5.5 V
= 5 V
IN
No Load
EN Floating
OUT
Time = 2 ms/div
Time = 20 ms/div
Figure 42. Input Ripple DCM
Figure 43. Low Dropout Operation
I
= 100 mA
I
= 1 A
OUT
EN Floating
OUT
EN Floating
V
V
V
IN
IN
V
OUT
OUT
Time = 40 ms/div
Time = 40 ms/div
Figure 44. Low Dropout Operation
Figure 45. Low Dropout Operation
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100
90
100
90
V
= 3.3V, fsw = 600 kHz
OUT
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
V
= 3.3V, fsw = 600 kHz
OUT
6Vin
12Vin
6Vin
36Vin
42Vin
36Vin
42Vin
12Vin
24Vin
24Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.001
0.01
0.1
1
I
- Output Current - A
I - Output Current - A
O
O
Figure 46. Efficiency vs Load Current
Figure 47. Light Load Efficiency
100
90
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= 5V, fsw = 600 kHz
V
= 5V, fsw = 600 kHz
OUT
OUT
6Vin
12Vin
6Vin
36Vin
42Vin
36Vin
42Vin
12Vin
24Vin
24Vin
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.001
0.01
0.1
1
I
- Output Current - A
I - Output Current - A
O
O
Figure 48. Efficiency vs Load Current
Figure 49. Light Load Efficiency
1
180
60
40
V
= 12V, V
= 3.3V,
OUT
IN
0.8
Phase
fsw = 600 kHz
120
60
0
0.6
0.4
0.2
0
20
Gain
0
-0.2
0.4
-0.6
-0.8
-1
6- 0
-20
V
= 12V,
IN
-120
-180
-40
-60
V
= 3.3V,
OUT
I
= 3.5A
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10
100
1000
10000
100000
1000000
I
- Output Current - A
Frequency - Hz
O
Figure 50. Overall Loop Frequency Response
Figure 51. Regulation vs Load Current
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0.3
V
= 3.3V, I
= 3.5A
OUT
OUT
fsw = 600 kHz
0.2
0.1
0
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
V
- Input Voltage - V
IN
Figure 52. Regulation vs Input Voltage
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Power Dissipation Estimate
The following formulas show how to estimate the TPS54340 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æ
ç
è
ö
÷
ø
V
3.3 V
12 V
2
2
OUT
P
= I
´R
´
= 3.5 A ´ 92 mW ´
= 0.31 W
(
)
COND
OUT
DS on
( )
V
IN
(49)
(50)
(51)
(52)
spacer
P
= V ´ f
´I
´ t
= 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
rise
SW
IN
SW
OUT
spacer
P
= V ´ Q ´ f
= 12 V ´ 3nC´ 600 kHz = 0.022 W
SW
GD
IN
G
spacer
P
= V ´ I = 12 V ´ 146 mA = 0.0018 W
IN Q
Q
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
P
= P
+ P
+ P + P = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
TOT
COND
SW GD Q
(53)
(54)
For given TA,
T = T + R ´P
TOT
J
A
TH
For given TJMAX = 150°C
TA max = TJ max - RTH ´PTOT
(
)
(
)
(55)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
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33
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TPS54340
SLVSBK0A –OCTOBER 2012–REVISED FEBRUARY 2013
www.ti.com
Layout
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 53 for a PCB layout
example. The GND pin should be tied directly to the power pad under the IC and the power pad.
The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The
SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection
is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area
of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top
side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT
resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional
external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
Vout
Output
Capacitor
Output
Inductor
Topside
Ground
Route Boot Capacitor
Catch
Area
Trace on another layer to
provide wide path for
topside ground
Diode
Input
Bypass
Capacitor
BOOT
VIN
SW
GND
COMP
FB
Vin
EN
UVLO
RT/CLK
Compensation
Network
Adjust
Resistor
Divider
Resistors
Frequency
Thermal VIA
Signal VIA
Set Resistor
Figure 53. PCB Layout Example
Estimated Circuit Area
Boxing in the components in the design of Figure 33 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
34
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Product Folder Links: TPS54340
TPS54340
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SLVSBK0A –OCTOBER 2012–REVISED FEBRUARY 2013
VIN
+
Cin
Cboot
SW
Lo
R1
GND
BOOT
VIN
Cd
+
GND
Co
R2
TPS54340 FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero Cpole
RT
Figure 54. TPS54340 Inverting Power Supply from SLVA317 Application Note
VOPOS
+
Copos
VIN
+
Cin
Cboot
SW
GND
BOOT
VIN
GND
Lo
Cd
R1
R2
+
Coneg
TPS54340
VONEG
FB
EN
COMP
Rcomp
RT/CLK
Czero Cpole
RT
Figure 55. TPS54340 Split Rail Power Supply Based on SLVA369 Application Note
Copyright © 2012–2013, Texas Instruments Incorporated
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TPS54340
SLVSBK0A –OCTOBER 2012–REVISED FEBRUARY 2013
www.ti.com
REVISION HISTORY
Changes from Original (October 2012) to Revision A
Page
•
•
Changed Figure 11 From: IEN (µV) To: IEN (µA) .................................................................................................................... 7
Changed Figure 12 From: IEN (µV) To: IEN (µA) .................................................................................................................... 7
36
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Product Folder Links: TPS54340
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2013
PACKAGING INFORMATION
Orderable Device
TPS54340DDA
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE SO PowerPAD
DDA
8
8
75
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 150 54340
-40 to 150 54340
TPS54340DDAR
ACTIVE SO PowerPAD
DDA
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54340DDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS54340DDAR
8
2500
Pack Materials-Page 2
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