TPS54354PWP_技术文档

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SLVS519 − MAY 2004

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FEATURES

DESCRIPTION

D

100 mΩ, 4.5-A Peak MOSFET Switch for High

Efficiency at 3-A Continuous Output Current

Uses External Lowside MOSFET or Diode

Fixed Output Versions −

1.2V/1.5V/1.8V/2.5V/3.3V/5.0V

Internally Compensated for Low Parts Count

Synchronizes to External Clock

1805 Out of Phase Synchronization

Wide PWM Frequency − Fixed 250 kHz,

500 kHz or Adjustable 250 kHz to 700 kHz

Internal Slow Start

Load Protected by Peak Current Limit and

Thermal Shutdown

Adjustable Undervoltage Lockout

The TPS5435x is a medium output current synchronous

buck PWM converter with an integrated high side

MOSFET and a gate driver for an optional low side

external MOSFET. Features include a high performance

voltage error amplifier that enables maximum

performance under transient conditions. The TPS5435x

has an under-voltage-lockout circuit to prevent start-up

until the input voltage reaches a preset value; an internal

slow-start circuit to limit in-rush currents; and a power good

output to indicate valid output conditions. The

synchronization feature is configurable as either an input

or an output for easy 180° out of phase synchronization.

D

The TPS5435x devices are available in a thermally

enhanced 16-pin TSSOP (PWP) PowerPAD package.

TI provides evaluation modules and the SWIFT Designer

software tool to aid in quickly achieving high-performance

power supply designs to meet aggressive equipment

development cycles.

D

16-Pin TSSOP PowerPADE Package

APPLICATIONS

D

Industrial & Commercial Low Power Systems

LCD Monitors and TVs

Computer Peripherals

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors

EFFICIENCY

vs

OUTPUT CURRENT

100

V

= 6 V

I

95

90

85

80

75

70

65

60

V

= 12 V

I

SIMPLIFIED SCHEMATIC

Input

Voltage

TPS54356

V = 12 V

I

O

SYNC

VIN

V

= 3.3 V

= 500 kHz

55

50

f

s

PWRGD

ENA

0

1

2

3

4

BOOT

PH

I

− Output Current − A

O

BIAS

Output

Voltage

LSG

PGND

VSENSE

PWRPAD

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of Texas Instruments.

ꢁꢖ ꢍ ꢛꢑ ꢔ ꢀꢏ ꢍꢐ ꢛ ꢒꢀꢒ ꢠꢡ ꢢꢣ ꢤ ꢟꢥ ꢦꢠꢣꢡ ꢠꢧ ꢨꢩ ꢤ ꢤ ꢪꢡꢦ ꢥꢧ ꢣꢢ ꢫꢩꢬ ꢭꢠꢨ ꢥꢦꢠ ꢣꢡ ꢮꢥ ꢦꢪꢊ ꢁꢤ ꢣꢮꢩ ꢨꢦꢧ

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ꢁꢤ ꢣ ꢮꢩꢨ ꢦ ꢠꢣ ꢡ ꢫꢤ ꢣ ꢨ ꢪ ꢧ ꢧ ꢠꢡ ꢳ ꢮꢣ ꢪ ꢧ ꢡꢣꢦ ꢡꢪ ꢨꢪ ꢧꢧ ꢥꢤ ꢠꢭ ꢲ ꢠꢡꢨ ꢭꢩꢮ ꢪ ꢦꢪ ꢧꢦꢠ ꢡꢳ ꢣꢢ ꢥꢭ ꢭ ꢫꢥ ꢤ ꢥꢟ ꢪꢦꢪ ꢤ ꢧꢊ

Copyright  2004, Texas Instruments Incorporated

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SLVS519 − MAY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

TPS54352PWP

TPS54353PWP

TPS54354PWP

TPS54355PWP

TPS54356PWP

TPS54357PWP

A

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

5.0 V

Plastic HTSSOP (PWP)

−40°C to 85°C

(1)

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS5435xPWPR).

(1)

PACKAGE DISSIPATION RATINGS

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T

= 25°C

T

= 70°C

T = 85°C

A

POWER RATING

A

PACKAGE

POWER RATING

16-Pin PWP with solder(2)

16-Pin PWP without solder

42.1°C/W

2.36

0.66

1.31

0.36

0.95

0.26

151.9°C/W

(1)

(2)

See Figure 46 for power dissipation curves.

Test Board Conditions

1. Thickness: 0.062”

2. 3” x 3”

3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering

4. Copper areas located on the top and bottom of the PCB for soldering

5. Power and ground planes, 1 oz. copper (0.036 mm thick)

6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch

7. Thermal isolation of power plane

For more information, refer to TI technical brief SLMA002.

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SLVS519 − MAY 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

VIN

−0.3 V to 21.5 V

−0.3 V to 8.0 V

−0.3 V to 4.0 V

VI(PH) + 8.0 V

−0.3 to 8.5 V

−0.3 to 4.0 V

−0.3 to 6.0 V

−0.3 to 4.0 V

−1.5 V to 22 V

VSENSE

UVLO

Input voltage range, V

I

SYNC

ENA

BOOT

VBIAS

LSG

SYNC

RT

Output voltage range, V

O

PWRGD

COMP

PH

Internally Limited (A)

10 mA

LSG (Steady State Current)

COMP, VBIAS

SYNC

Source current, I

O

3 mA

5 mA

LSG (Steady State Current)

PH (Steady State Current)

COMP

100 mA

500 mA

Sink current, I

S

3 mA

ENA, PWRGD

AGND to PGND

10 mA

Voltage differential

0.3 V

Operating virtual junction temperature range, T

−40°C to +150°C

−65°C to +150°C

260°C

J

Storage temperature, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN MAX

UNIT

V

Human body model

CDM

600

1.5

kV

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

20

UNIT

TPS54352−6

TPS54357

4.5

6.65

−40

Input voltage range, V

V

I

20

Operating junction temperature, T

125

°C

J

3

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SLVS519 − MAY 2004

ELECTRICAL CHARACTERISTICS

T = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

Operating current, PH pin open,

No external low side MOSFET, RT = Hi-Z

5

mA

I

Q

Quiescent current

Shutdown, ENA = 0 V

1

4.32

6.4

TPS54352−6

TPS54357

4.49

6.65

Start threshold voltage

Stop threshold voltage

Hysteresis

V

TPS54352−6

TPS54357

3.69

5.45

3.97

5.80

350

600

VIN

TPS54352−6

TPS54357

mV

OUTPUT VOLTAGE

T = 25°C, I = 100 mA to 3 A

1.88

1.176

1.485

1.47

1.2 1.212

1.2 1.224

1.5 1.515

J

O

TPS54352

TPS54353

TPS54354

TPS54355

TPS54356

TPS54357

I

O

= 100 mA to 3 A

T = 25°C, I = 100 mA to 3 A

J

O

I

O

= 100 mA to 3 A

1.5

1.53

T = 25°C, I = 100 mA to 3 A

1.782

1.764

2.475

2.45

1.8 1.818

1.8 1.836

2.5 2.525

J

O

I

O

= 100 mA to 3 A

V

O

Output voltage

V

T = 25°C, I = 100 mA to 3 A

J

O

I

O

= 100 mA to 3 A

2.5

2.55

T = 25°C, VIN = 5.5 V to 20 V, I = 100 mA to 3 A 3.267

J

3.3 3.333

3.3 3.366

O

VIN = 5.5 V to 20 V, I = 100 mA to 3 A

3.234

4.95

4.90

O

T = 25°C, VIN = 7.5 V to 20 V, I = 100 mA to 3 A

J

5.0

5.05

5.10

O

VIN = 7.5 V to 20 V, I = 100 mA to 3 A

O

UNDER VOLTAGE LOCK OUT (UVLO PIN)

Start threshold voltage

1.20

1.10

100

1.24

V

Stop threshold voltage

Hysteresis

1.02

UVLO

mV

BIAS VOLTAGE (VBIAS PIN)

VBIAS Output voltage

OSCILLATOR (RT PIN)

Internally set PWM switching frequency

I

= 1 mA, VIN ≥ 12 V

7.5

4.4

7.8

8.0

4.5

VBIAS

V

= 1 mA, VIN = 4.5 V

4.47

VBIAS

RT Grounded

RT Open

200

400

425

250

500

300

600

575

kHz

Externally set PWM switching frequency RT = 100 kΩ (1% resistor to AGND)

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SLVS519 − MAY 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

T = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN)

(1)

200

500

10

ns

SYNC out low-to-high rise time (10%/90%)

25 pF to ground

(1)

5

SYNC out high-to-low fall time (90%/10%)

Delay from rising edge to rising edge of PH

pins, see Figure 19

(1)

180

°

Falling edge delay time

(1)

100

360

ns

V

Minimum input pulse width

RT = 100 kΩ

(1)

Delay (falling edge SYNC to rising edge PH)

SYNC out high level voltage

RT = 100 kΩ

2.5

50-kΩ Resistor to ground, no pullup resistor

0.6

V

SYNC out low level voltage

0.8

V

SYNC in low level threshold

2.3

10%

770

V

SYNC in high level threshold

Percentage of programmed frequency

−10%

225

(1)

SYNC in frequency range

kHz

V/V

ns

FEED− FORWARD MODULATOR (INTERNAL SIGNAL)

Modulator gain

VIN = 12 V, T = 25°C

8

J

Modulator gain variation

−25%

80%

25%

(1)

Minimum controllable ON time

(1)

180

Maximum duty factor

VSENSE PIN

Input bias current, VSENSE pin

ENABLE (ENA PIN)

VIN = 4.5 V

86%

1

µA

Disable low level input voltage

0.5

V

(1)

f = 250 kHz, RT = ground

3.20

1.60

4.00

2.00

4.60

2.30

4.40

2.20

5.90

2.90

5.40

2.70

5

s

TPS54352

TPS54353

TPS54354

TPS54355

TPS54356

TPS54357

(1)

f = 500 kHz, RT = Hi−Z

s

f = 250 kHz, RT = ground

s

(1)

f = 500 kHz, RT = Hi−Z

s

f = 250 kHz, RT = ground

s

(1)

f = 500 kHz, RT = Hi−Z

s

Internal slow-start time

(10% to 90%)

ms

f = 250 kHz, RT = ground

s

(1)

f = 500 kHz, RT = Hi−Z

s

f = 250 kHz, RT = ground

s

(1)

f = 500 kHz, RT = Hi−Z

s

f = 250 kHz, RT = ground

s

(1)

f = 500 kHz, RT = Hi−Z

s

Pullup current source

Pulldown MOSFET

1.8

10

µA

I = 1 mA

I(ENA)

0.1

V

POWER GOOD (PWRGD PIN)

Power good threshold

Rising voltage

f = 250 kHz

97%

4

s

(1)

Rising edge delay

ms

f = 500 kHz

s

2

Output saturation voltage

Open drain leakage current

I

= 1 mA, VIN > 4.5 V

0.05

0.76

V

sink

I

= 100 µA, VIN = 0 V

PWRGD

(1)

Voltage on PWRGD = 6 V

3

µA

Ensured by design, not production tested.

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SLVS519 − MAY 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

T = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT LIMIT

Current limit

VIN = 12 V

3.3

4.5

6.5

A

(1)

Current limit hiccup time

f = 500 kHz

s

4.5

ms

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

165

7

_C

(1)

Thermal shutdown hysteresis

LOW SIDE MOSFET DRIVER (LSG PIN)

(1)

15

60

7.5

5

ns

Turn on rise time, (10%/90%)

VIN = 4.5 V, Capacitive load = 1000 pF

VIN = 12 V

(1)

Deadtime

VIN = 4.5 V sink/source

VIN = 12 V sink/source

Ω

Driver ON resistance

OUTPUT POWER MOSFETS (PH PIN)

0.5

1.13

1.08

150

100

V

Phase node voltage when disabled

DC conditions and no load, ENA = 0 V

VIN = 4.5 V, Idc = 100 mA

1.42

1.38

300

200

Voltage drop, low side FET and diode

VIN = 12 V, Idc = 100 mA

VIN = 4.5 V, BOOT−PH = 4.5 V, I = 0.5 A

O

(2)

r

mΩ

High side power MOSFET switch

DS(ON)

VIN = 12 V, BOOT−PH = 8 V, I = 0.5 A

O

(1)

(2)

Ensured by design, not production tested.

Resistance from VIN to PH pins.

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SLVS519 − MAY 2004

PIN ASSIGNMENTS

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

VIN

UVLO

PWRGD

RT

SYNC

ENA

COMP

BOOT

PH

15

14

13

12

11

10

9

LSG

THERMAL

PAD

VBIAS

PGND

AGND

VSENSE

NOTE:

If there is not a Pin 1 indicator, turn device to enable

readingthe symbol from left to right. Pin 1 is at the lower

left corner of the device.

Terminal Functions

TERMINAL

DESCRIPTION

NO.

NAME

VIN

1, 2

Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor. Place cap as close to device as

possible; see Figure 23 for an example.

3

4

5

6

UVLO

PWRGD

RT

Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal

default VIN start and stop thresholds.

Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage.

There is an internal rising edge filter on the output of the PWRGD comparator.

Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to

ground or floating will set the frequency to an internally preselected frequency.

SYNC

Bidirectionalsynchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a

fallingedge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock

by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the

ApplicationInformation section. In ALL cases, a 10 kΩ resistor Must be tied to the SYNC pin in parallel with ground. For

information on how to extend slow start, see the Enable (ENA) and Internal Slow Start section on page 9.

7

8

ENA

Enable. Below 0.5 V, the device stops switching. Float pin to enable.

Error amplifier output. Do NOT connect ANYTHING to this pin.

Feedback pin

COMP

VSENSE

AGND

PGND

9

10

11

Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.

Power ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Connect

to AGND and PowerPAD.

12

13

VBIAS

LSG

Internal 8.0-V bias voltage. A 1.0-µF ceramic bypass capacitance is required on the VBIAS pin.

Gate drive for optional low side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency synchronous buck

converter configuration. Otherwise, leave open and connect schottky diode from ground to PH pins.

14, 15 PH

16 BOOT

Phase node—Connect to external L−C filter.

Bootstrap capacitor for high side gate driver. Connect a 0.1-µF ceramic capacitor from BOOT to PH pins.

PowerPAD PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 23 for an example PCB

layout.

7

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SLVS519 − MAY 2004

FUNCTIONAL BLOCK DIAGRAM

BOOT

VIN

PH

320 kΩ

Hiccup

UVLO

Current Limit

(1)

125 kΩ

1.2V

SYNC

RT

2x Oscillator

PWM Ramp

Bias + Drive

Regulator

VBIAS

(FeedFoward)

Z3

S

R

Q

Adaptive Deadtime

and

Control Logic

PWM

Comparator

VBIAS

COMP

Z1

Z4

VSENSE

LSG

Z2

Error

Amplifier

Z5

VBIAS

Thermal

Shutdown

Reference

System

PWRGD

UVLO

Rising

Edge

Delay

VSENSE

97% Ref

5 µA

UVLO

ENA

Hiccup

Timer

TPS5435X

POWERPAD

VBIAS

PGND

AGND

(1)

75 kΩ for the TPS54357

DETAILED DESCRIPTION

Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) system has an internal

voltage divider from VIN to AGND. The defaults for the

start/stop values are labeled VIN and given in Table 1. The

internal UVLO threshold can be overridden by placing an

external resistor divider from VIN to ground. The internal

divider values are approximately 320 kΩ for the high side

resistor and 125 kΩ for the low side resistor. The divider

ratio (and therefore the default start/stop values) is quite

accurate, but the absolute values of the internal resistors

may vary as much as 15%. If high accuracy is required for

an externally adjusted UVLO threshold, select lower value

external resistors to set the UVLO threshold. Using a 1-kΩ

resistor for the low side resistor (R2 see Figure 1) is

recommended. Under no circumstances should the UVLO

pin be connected directly to VIN.

Table 1. Start/Stop Voltage Threshold

START VOLTAGE THRESHOLD

STOP VOLTAGE THRESHOLD

TPS54352−6

TPS54357

4.49

6.65

1.24

3.69

5.45

1.02

VIN (Default)

UVLO

The equations for selecting the UVLO resistors are:

(R1 ꢃ 1 kW) ꢁ 1.02 V

1 kW

VIN(stop) ꢀ

(2)

VIN(start) ꢁ 1 kW

R1 ꢀ

ꢂ

1

k

W

1.24 V

(1)

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SLVS519 − MAY 2004

Input

Voltage

Supply

320 kΩ

125 kΩ

R1

R2

(1)

1 kΩ

5 µA

R

Disabled

Enabled

SS

(1)

75 kΩ for the TPS54357

C

SS

Figure 1. Circuit Using External UVLO Function

Figure 2. Interfacing to the ENA Pin

Extending Slow Start Time

For applications which require an undervoltage lock out

(UVLO) threshold greater than 4.49 V (6.6 V for

TPS54357), external resistors may be implemented, see

Figure 1, to adjust the start voltage threshold. For example,

an application needing an UVLO start voltage of

approximately 7.8 V using the equation (1), R1 is

calculated to the nearest standard resistor value of

5.36 kΩ. Using equation (2), the input voltage stop

threshold is calculated as 6.48 V.

In applications that use large values of output capacitance

there may be a need to extend the slow start time to

prevent the startup current from tripping the current limit.

The current limit circuit is designed to disable the high side

MOSFET and reset the internal voltage reference for a

short amount of time when the high side MOSFET current

exceeds the current limit threshold. If the output

capacitance and load current cause the startup current to

exceed the current limit threshold, the power supply output

will not reach the desired output voltage. To extend the

slow start time and to reduce the startup current, an

external resistor and capacitor can be added to the ENA

pin. The slow start capacitance is calculated using the

following equation:

Enable (ENA) and Internal Slow Start

The TPS5435x has an internal digital slow start that ramps

the reference voltage to its final value in 1150 switching

cycles. The internal slow start time (10% − 90%) is

approximated by the following expression:

−3

C

(µF) = 5.55 ꢁ 10 ꢁ n ꢁ T (ms)

ss

SS

(4)

1.15k

ƒ (kHz) ꢁ n

T

(ms) ꢀ

Use n in Table 2

SS_INTERNAL

s

(3)

Use n in Table 2

The R resistor must be 2 kΩ and the slow start capacitor

SS

must be less than 0.47 µF.

Switching Frequency (RT)

Table 2. Slow Start Characteristics

The TPS5435x has an internal oscillator that operates at

twice the PWM switching frequency. The internal oscillator

frequency is controlled by the RT pin. Grounding the RT

pin sets the PWM switching frequency to a default

frequency of 250 kHz. Floating the RT pin sets the PWM

switching frequency to 500 kHz.

DEVICE

TPS54352

TPS54353

TPS54354

TPS54355

TPS54356

TPS54357

n

1.485

1.2

1

Connecting a resistor from RT to AGND sets the frequency

according to the following equation (also see Figure 30).

1.084

0.818

0.900

46000

ƒ (kHz) ꢂ 35.9

RT(kW) ꢀ

(5)

s

The RT pin controls the SYNC pin functions. If the RT pin

is floating or grounded, SYNC is an output. If the switching

frequency has been programmed using a resistor from RT

to AGND, then SYNC functions as an input.

Once the TPS5435x device is in normal regulation, the

ENA pin is high. If the ENA pin is pulled below the stop

threshold of 0.5 V, switching stops and the internal slow

start resets. If an application requires the TPS5435x to be

disabled, use open drain or open collector output logic to

interface to the ENA pin (see Figure 2). The ENA pin has

an internal pullup current source. Do not use external

pullup resistors.

The internal voltage ramp charging current increases

linearly with the set frequency and keeps the feed forward

modulator constant (Km = 8) regardless of the frequency

set point.

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SLVS519 − MAY 2004

Table 3.

SWITCHING FREQUENCY

250 kHz, internally set

500 kHz, internally set

SYNC PIN

RT PIN

AGND

Float

Generates SYNC output signal

Terminate to quiet ground

Externally set to 250 kHz to 700 kHz

R = 215 kΩ to 69 kΩ

with 10-kΩ resistor.

Set RT resistor equal to 90% to 110% of external synchronization

frequency.When using a dual setup (see Figure 27 for example),

if the master 35x device RT pin is left floating, use a 110 kΩ

resistor to tie the slave RT pin to ground. Conversely, if the master

35x device RT pin is grounded, use a 237 kΩ resistor to tie the

slave RT pin to ground.

Externally synchronized frequency

Synchronization Signal

1805 Out of Phase Synchronization (SYNC)

The SYNC pin is configurable as an input or as an output,

per the description in the previous section. When

operating as an input, the SYNC pin is a falling-edge

triggered signal (see Figures 3, 4, and 19). When operating

as an output, the signal’s falling edge is approximately

180° out of phase with the rising edge of the PH pins. Thus,

two TPS5435x devices operating in a system can share an

input capacitor and draw ripple current at twice the

frequency of a single unit.

When operating the two TPS5435x devices 180° out of

phase, the total RMS input current is reduced. Thus

reducing the amount of input capacitance needed and

increasing efficiency.

When synchronizing a TPS5435x to an external signal, the

timing resistor on the RT pin must be set so that the

oscillator is programmed to run at 90% to 110% of the

synchronization frequency.

V

I(SYNC)

V

O(PH)

Figure 3. SYNC Input Waveform

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SLVS519 − MAY 2004

Internal Oscillator

V

O(PH)

V

O(SYNC)

Figure 4. SYNC Output Waveform

capacitor value of 1.0 µF. X7R or X5R grade dielectric

ceramic capacitors are recommended because of their

stable characteristics over temperature.

Power Good (PWRGD)

The VSENSE pin is compared to an internal reference

signal, if the VSENSE is greater than 97% and no other

faults are present, the PWRGD pin presents a high

impedance. A low on the PWRGD pin indicates a fault. The

PWRGD pin has been designed to provide a weak

pull-down and indicates a fault even when the device is

unpowered. If the TPS5435x has power and has any fault

flag set, the TPS5435x indicates the power is not good by

driving the PWRGD pin low. The following events, singly

or in combination, indicate power is not good:

Bootstrap Voltage (BOOT)

The BOOT capacitor obtains its charge cycle by cycle from

the VBIAS capacitor. A capacitor from the BOOT pin to the

PH pins is required for operation. The bootstrap

connection for the high side driver must have a bypass

capacitor of 0.1 µF.

Error Amplifier

The VSENSE pin is the error amplifier inverting input. The

error amplifier is a true voltage amplifier with 1.5 mA of

drive capability with a minimum of 60 dB of open loop

voltage gain and a unity gain bandwidth of 2 MHz.

D

VSENSE pin out of bounds

Overcurrent

Thermal shutdown

UVLO undervoltage

Input voltage not present (weak pull-down)

Slow-starting

Voltage Reference

The voltage reference system produces a precision

reference signal by scaling the output of a temperature

stable bandgap circuit. During production testing, the

bandgap and scaling circuits are trimmed to produce

0.891 V at the output of the error amplifier, with the

amplifier connected as a voltage follower. The trim

procedure improves the regulation, since it cancels offset

errors in the scaling and error amplifier circuits.

VBIAS voltage is low

Once the PWRGD pin presents a high impedance (i.e.,

power is good), a VSENSE pin out of bounds condition

forces PWRGD pin low (i.e., power is bad) after a time

delay. This time delay is a function of the switching

frequency and is calculated using equation 6:

1000

PWM Control and Feed Forward

T

ꢀ

ms

delay

ƒ (kHz)

s

(6)

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, PWM latch, and the

adaptive dead-time control logic. During steady-state

operation below the current limit threshold, the PWM

comparator output and oscillator pulse train alternately

reset and set the PWM latch.

Bias Voltage (VBIAS)

The VBIAS regulator provides a stable supply for the

internal analog circuits and the low side gate driver. Up to

1 mA of current can be drawn for use in an external

application circuit. The VBIAS pin must have a bypass

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SLVS519 − MAY 2004

Once the PWM latch is reset, the low-side driver and

integrated pull-down MOSFET remain on for a minimum

duration set by the oscillator pulse width. During this

period, the PWM ramp discharges rapidly to the valley

voltage. When the ramp begins to charge back up, the

low-side driver turns off and the high-side FET turns on.

The peak PWM ramp voltage varies inversely with input

voltage to maintain a constant modulator and power stage

gain of 8 V/V.

Low Side Gate Driver (LSG)

LSG is the output of the low-side gate driver. The 100-mA

MOSFET driver is capable of providing gate drive for most

popular MOSFETs suitable for this application. Use the

SWIFT Designer Software Tool to find the most

appropriate MOSFET for the application.

Integrated Pulldown MOSFET

The TPS5435x has a diode-MOSFET pair from PH to

PGND. The integrated MOSFET is designed for light−load

continuous-conduction mode operation when only an

external Schottky diode is used. The combination of

devices keeps the inductor current continuous under

conditions where the load current drops below the

inductor’s critical current. Care should be taken in the

selection of inductor in applications using only a low-side

Schottky diode. Since the inductor ripple current flows

through the integrated low-side MOSFET at light loads, the

inductance value should be selected to limit the peak

current to less than 0.3 A during the high-side FET turn off

time. The minimum value of inductance is calculated using

the following equation:

As the PWM ramp voltage exceeds the error amplifier

output voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side driver remains on until the next

oscillator pulse discharges the PWM ramp.

During transient conditions, the error amplifier output can

be below the PWM ramp valley voltage or above the PWM

peak voltage. If the error amplifier is high, the PWM latch

is never reset and the high-side FET remains on until the

oscillator pulse signals the control logic to turn the

high-side FET off and the internal low-side FET and driver

on. The device operates at its maximum duty cycle until the

output voltage rises to the regulation set point, setting

VSENSE to approximately the same voltage as the

internal voltage reference. If the error amplifier output is

low, the PWM latch is continually reset and the high-side

FET does not turn on. The internal low-side FET and low

side driver remain on until the VSENSE voltage decreases

to a range that allows the PWM comparator to change

states. The TPS5435x is capable of sinking current

through the external low side FET until the output voltage

reaches the regulation set point.

VO

VI

ꢄ

ꢅ

VO ꢁ 1 ꢂ

L(H) ꢀ

ƒ ꢁ 0.6

s

(7)

Thermal Shutdown

The device uses the thermal shutdown to turn off the

MOSFET drivers and controller if the junction temperature

exceeds 165°C. The device is restarted automatically

when the junction temperature decreases to 7°C below the

thermal shutdown trip point and starts up under control of

the slow-start circuit.

The minimum on time is designed to be 180 ns. During the

internal slow-start interval, the internal reference ramps

from 0 V to 0.891 V. During the initial slow-start interval, the

internal reference voltage is very small resulting in a

couple of skipped pulses because the minimum on time

causes the actual output voltage to be slightly greater than

the preset output voltage until the internal reference ramps

up.

Overcurrent Protection

Overcurrent protection is implemented by sensing the

drain-to-source voltage across the high-side MOSFET

and compared to a voltage level which represents the

overcurrent threshold limit. If the drain-to-source voltage

exceeds the overcurrent threshold limit for more than

100 ns, the ENA pin is pulled low, the high-side MOSFET

is disabled, and the internal digital slow-start is reset to 0 V.

ENA is held low for approximately the time that is

calculated by the following equation:

Deadtime Control

Adaptive dead time control prevents shoot through current

from flowing in the integrated high-side MOSFET and the

external low-side MOSFET during the switching

transitions by actively controlling the turn on times of the

drivers. The high-side driver does not turn on until the

voltage at the gate of the low-side MOSFET is below 1 V.

The low-side driver does not turn on until the voltage at the

gate of the high-side MOSFET is below 1 V.

2250

T

(ms) ꢀ

HICCUP

ƒ (kHz)

s

(8)

Once the hiccup time is complete, the ENA pin is released

and the converter initiates the internal slow-start.

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SLVS519 − MAY 2004

TYPICAL CHARACTERISTICS

Conditions are V = 12 V, V = 3.3 V, f = 500 kHz, I = 3 A, T = 25 °C, unless otherwise noted

I

O

s

O

A

LINE REGULATION

MEASURED LOOP RESPONSE

LOAD REGULATION

0.1

0.3

0.2

0.1

60

50

40

30

20

10

180

150

120

90

0.08

0.06

0.04

0.02

Phase

V

= 12 V

I

= 3 A

O

I

= 1.5 A

O

60

V

= 6 V

I

30

Gain

0

−0.1

−0.2

−0.3

0

−10

−20

−30

0

−0.02

−30

−60

−90

= 18 V

I

= 0 A

I

O

−0.04

−0.06

See Figure 25

−40

−50

−60

−120

See Figure 25

−0.08

−0.1

See Figure 25

−150

−180

10 12 14 16 18 20 22

4

6

8

0

0.5

1

1.5

2

2.5

3

3.5

100

1 k

10 k

100 k

1 M

V − Input Voltage − V

I

− Output Current − A

O

f − Frequency − Hz

Figure 5

Figure 6

Figure 7

EFFICIENCY

vs

OUTPUT CURRENT

INPUT RIPPLE VOLTAGE

OUTPUT RIPPLE VOLTAGE

100

95

90

85

80

75

70

65

60

V

= 6 V

I

V

= 100 mV/div (ac coupled)

V

= 12 V

I(RIPPLE)

I

V

= 10 mV/div (ac coupled)

O(RIPPLE)

V

= 18 V

I

V

= 5 V/div

V

= 5 V/div

(PH)

55

50

See Figure 25

1

See Figure 25

Time − 1 µs/div

0

2

3

4

Time − 1 µs/div

I

− Output Current − A

O

Figure 8

Figure 9

Figure 10

POWER UP

LOAD TRANSIENT RESPONSE

GATE DRIVE VOLTAGE

V

= 50 mV/div (ac coupled)

O

V

= 5 V/div

(LSG)

V

= 5 V/div

I

= 1 A/div

(PH)

V

= 2 V/div

O

V

= 5 V/div

(PH)

V

= 2 V/div

(PWRGD)

See Figure 25

Time − 2 ms/div

See Figure 25

Time − 200 µs/div

Time − 1 µs/div

Figure 11

Figure 12

Figure 13

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SLVS519 − MAY 2004

Conditions are V = 12 V, V = 3.3 V, f = 500 kHz, I = 3 A, T = 25 °C, unless otherwise noted

I

O

s

O

A

EFFICIENCY

vs

OUTPUT CURRENT

CONTINUOUS CONDUCTION MODE

100

95

90

85

80

75

70

65

60

55

50

POWER DOWN

V

= 6 V

V

= 5 V/div

(PH)

I

V

= 12 V

I

V

I

= 5 V/div

V

= 18 V

I

= 200 mA/div

(L1)

V

= 2 V/div

O

V

= 2 V/div

(PWRGD)

See Figure 26

1

See Figure 26

Time − 1 µs/div

See Figure 25

0

2

3

4

I

− Output Current − A

Time − 2 ms/div

O

Figure 14

Figure 15

Figure 16

LIGHT LOAD CONDUCTION

SEQUENCING WAVEFORMS

INPUT RIPPLE CANCELLATION

V

= 5 V/div

V

= 10 V/div

(PH)

(PH1)

V

= 10 V/div

I

V

= 2 V/div

O1(3.3)

V

= 10 V/div

(PH2)

I

= 200 mA/div

(L1)

V

= 50 mV/div (ac coupled)

V

= 2 V/div

(PWRGD1)

I

V

= 2 V/div

O2(1.8)

See Figure 27

See Figure 26

See Figure 27

Time − 1 µs/div

Time − 2 ms/div

Time − 1 µs/div

Figure 17

Figure 18

Figure 19

MEASURED LOOP RESPONSE

2 x 180 mF SP CAPACITORS

MEASURED LOOP RESPONSE

100 mF POSCAP

330 mF OSCON

60

50

40

30

20

180

150

120

90

60

50

40

180

150

60

50

40

30

20

10

0

180

150

Phase

120

90

120

90

30

20

10

0

60

Gain

30

10

0

30

0

−10

−30

−60

−30

−60

−90

−120

−150

−10

−30

−60

−90

−120

−20

−30

−20

−30

−20

−30

−40

−50

−60

−90

−40

−50

−60

−120

−150

−180

−40

−50

−60

See Figure 28

See Figure 29

See Figure 30

−150

−180

1 M

100

1 k

10 k

100 k

1 M

100

1 k

10 k

100 k

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

Figure 20

Figure 21

Figure 22

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SLVS519 − MAY 2004

LAYOUT INFORMATION

Figure 23. TPS5435x PCB Layout

PCB LAYOUT

The VIN pins should be connected together on the printed

circuit board (PCB) and bypassed with a low ESR ceramic

bypass capacitor. Care should be taken to minimize the

loop area formed by the bypass capacitor connections, the

VIN pins, and the TPS5435x ground pins. The minimum

recommended bypass capacitance is 10-µF ceramic with

a X5R or X7R dielectric and the optimum placement is

closest to the VIN pins and the AGND and PGND pins. See

Figure 23 for an example of a board layout. The AGND and

PGND pins should be tied to the PCB ground plane at the

pins of the IC. The source of the low-side MOSFET and the

anode of the Schottky diode should be connected directly

to the PCB ground plane. The PH pins should be tied

together and routed to the drain of the low-side MOSFET

or to the cathode of the external Schottky diode. Since the

PH connection is the switching node, the MOSFET (or

diode) should be located very close to the PH pins, and the

area of the PCB conductor minimized to prevent excessive

capacitive coupling. The recommended conductor width

from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce

copper. The length of the copper land pattern should be no

more than 0.2 inch.

For operation at full rated load, the analog ground plane

must provide adequate heat dissipating area. A 3-inch by

3-inch plane of copper is recommended, though not

mandatory, dependent on ambient temperature and

airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the bottom or top layers also help dissipate heat, and

any area available should be used when 3 A or greater

operation is desired. Connection from the exposed area of

the PowerPAD to the analog ground plane layer should be

made using 0.013-inch diameter vias to avoid solder

wicking through the vias. Four vias should be in the

PowerPAD area with four additional vias outside the pad

area and underneath the package. Additional vias beyond

those recommended to enhance thermal performance

should be included in areas not under the device package.

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SLVS519 − MAY 2004

j0.0130

Minimum recommended thermal vias: 4 x

.013 dia. inside powerpad area and

8 PL

Minimum recommended exposed copper

area for powerpad. 5mil stencils may

4 x .013 dia. under device as shown.

Additional .018 dia. vias may be used if top

side Analog Ground area is extended.

require 10 percent larger area.

0.0150

0.06

0.0371

0.0400

0.1970

0.1942

0.0570

0.0400

0.0256

Connect Pin 10 AGND

and Pin 11 PGND to

Analog Ground plane in

this area for optimum

performance.

0.1700

0.1340

Minimum recommended top

side Analog Ground area.

0.0690

0.0400

Figure 24. Thermal Considerations for PowerPAD Layout

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SLVS519 − MAY 2004

APPLICATION INFORMATION

+

Figure 25. Application Circuit, 12 V to 3.3 V

Figure 25 shows the schematic for a typical TPS54356

application. The TPS54356 can provide up to 3-A output

current at a nominal output voltage of 3.3 V. For proper

thermal performance, the exposed PowerPAD underneath

the device must be soldered down to the printed circuit

board.

For this design example, use the following as the input

parameters:

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

6 V to 18 V

3.3 V

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

300 mV

10 mV

DESIGN PROCEDURE

3 A

The following design procedure can be used to select

component values for the TPS54356. Alternately, the

SWIFT Designer Software may be used to generate a

complete design. The SWIFT Designer Software uses an

iterative design procedure and accesses a comprehensive

database of components when generating a design. This

section presents a simplified discussion of the design

process.

500 kHz

SWITCHING FREQUENCY

The switching frequency is set using the RT pin.

Grounding the RT pin sets the PWM switching frequency

to a default frequency of 250 kHz. Floating the RT pin sets

the PWM switching frequency to 500 kHz. By connecting

a resistor from RT to AGND, any frequency in the range of

250 kHz to 700 kHz can be set. Use equation 9 to

determine the proper value of RT.

To begin the design process a few parameters must be

decided upon. The designer needs to know the following:

D

Input voltage range

Output voltage

46000

ƒ (kHz) ꢂ 35.9

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

RT(kW) ꢀ

s

(9)

In this example circuit, RT is not connected and the

switching frequency is set at 500 kHz.

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SLVS519 − MAY 2004

For this design example use K

= 0.1 to keep the

INPUT CAPACITORS

IND

inductor ripple current small. The minimum inductor value

is calculated to be 17.96 µH. The next highest standard

value is 22 µH, which is used in this design.

The TPS54356 requires an input decoupling capacitor

and, depending on the application, a bulk input capacitor.

The minimum value for the decoupling capacitor, C9, is

10µF. A high quality ceramic type X5R or X7R is

recommended. The voltage rating should be greater than

the maximum input voltage. Additionally some bulk

capacitance may be needed, especially if the TPS54356

circuit is not located within about 2 inches from the input

voltage source. The value for this capacitor is not critical

but it also should be rated to handle the maximum input

voltage including ripple voltage and should filter the output

so that input ripple voltage is acceptable.

For the output filter inductor it is important that the RMS

current and saturation current ratings not be exceeded.

The RMS inductor current can be found from equation 13:

2

ꢄ

V

_OUTꢅ

V

ꢁ

ꢂ V

IN(MAX)

ꢁ L

ꢁ ƒ_swꢁ 0.8

OUT

1

12

_I2

ꢆ _OUT(MAX)

I

ꢀ

ꢃ

ꢁ

ꢄ

ꢅ

(13)

L(RMS)

V

IN(MAX)

OUT

and the peak inductor current can be determined with

equation 14:

This input ripple voltage can be approximated by equation

10:

ꢄ

_OUTꢅ

V

ꢁ

V

ꢂ V

IN(MAX)

OUT

1.6 ꢁ V

I

ꢀ I

ꢃ

(14)

L(PK)

OUT(MAX)

I

ꢁ 0.25

ꢁ L

ꢁ ƒ_sw

OUT(MAX)

IN(MAX)

OUT

ꢄ

I

_(MAX)ꢅ

DV

ꢀ

ꢃ

ꢁ

E

S

R

IN

OUT(MAX)

C

ꢁ

ƒ

s

w

BULK

(10)

For this design, the RMS inductor current is 3.007 A and

the peak inductor current is 3.15 A. The chosen inductor

is a Coiltronics DR127−220 22 µH. It has a saturation

current rating of 7.57 A and a RMS current rating of 4 A,

easily meeting these requirements. A lesser rated inductor

could be used if less margin is desired. In general, inductor

values for use with the TPS54356 are in the range of 6.8

µH to 47 µH.

Where I

switching frequency, C

is the maximum load current, ƒ

is the

OUT(MAX)

SW

is the bulk capacitor value and

BULK

ESR

is the maximum series resistance of the bulk

MAX

capacitor.

The maximum RMS ripple current also needs to be

checked. For worst case conditions, this can be

approximated by equation 11:

Capacitor Requirements

I

OUT(MAX)

The important design factors for the output capacitor are

dc voltage rating, ripple current rating, and equivalent

series resistance (ESR). The dc voltage and ripple current

ratings cannot be exceeded. The ESR is important

because along with the inductor current it determines the

amount of output ripple voltage. The actual value of the

output capacitor is not critical, but some practical limits do

exist.

I

ꢀ

CIN

2

(11)

In this case the input ripple voltage would be 140 mV and

the RMS ripple current would be 1.5 A. The maximum

voltage across the input capacitors would be VIN max plus

delta VIN/2. The chosen bulk and bypass capacitors are

each rated for 25 V and the combined ripple current

capacity is greater than 3 A, both providing ample margin.

It is very important that the maximum ratings for voltage

and current are not exceeded under any circumstance.

Consider the relationship between the desired closed loop

crossover frequency of the design and LC corner

frequency of the output filter. In general, it is desirable to

keep the closed loop crossover frequency at less than 1/5

of the switching frequency. With high switching

frequencies such as the 500-kHz frequency of this design,

internal circuit limitations of the TPS54356 limit the

practical maximum crossover frequency to about 70 kHz.

Additionally, the capacitor type and value must be chosen

to work with the internal compensation network of the

TPS5435x family of dc/dc converters. To allow for

adequate phase gain in the compensation network, the LC

corner frequency should be about one decade or so below

the closed loop crossover frequency. This limits the

minimum capacitor value for the output filter to:

OUTPUT FILTER COMPONENTS

Inductor Selection

To calculate the minimum value of the output inductor, use

equation 12:

ꢄ

_OUTꢅ

ꢁ ƒ

V

ꢁ

V

ꢂ

V

OUT

IN(MAX)

ꢁ K ꢁ I

L

ꢀ

(MIN)

V

sw

IN(MAX)

IND

OUT

(12)

K

is a coefficient that represents the amount of inductor

IND

ripple current relative to the maximum output current. For

designs using low ESR output capacitors such as

ceramics, use K

1

K

2

C

ꢀ

ꢁ

(_2pƒ)

= 0.3. When using higher ESR output

IND

OUT(MIN)

L

CO

OUT

(15)

capacitors, K

= 0.2 yields better results.

IND

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SLVS519 − MAY 2004

Where K is the frequency multiplier for the spread between

For a stable design, the closed loop crossover frequency

should be set less than one fifth of the switching frequency,

and the phase margin at crossover must be greater than

45 degrees. The general procedure outlined here

produces results consistent with these requirements

without going into great detail about the theory of loop

compensation.

f

LC

and f . K should be between 5 and 15, typically 10 for

CO

one decade difference. For a desired crossover of 20 kHz

and a 22-µH inductor, the minimum value for the output

capacitor is 288 µF. The selected output capacitor must be

rated for a voltage greater than the desired output voltage

plus one half the ripple voltage. Any derating amount must

also be included. The maximum RMS ripple current in the

output capacitor is given by equation 16:

In this case, the output filter LC corner frequency should be

selected to be near the first compensation zero frequency

as described by equation 17:

ꢄ

ꢅ

V

ꢁ V

ꢂ V

ꢈ

ꢊ

OUT

V

IN(MAX)

OUT

1

ƒ

ꢀ

ꢌ ƒ

I

ꢀ

ꢁ

ꢇ

ꢉ

ꢇ

ꢋ

COUT(RMS)

ꢆ

LC

Z1

ꢁ L

ꢁ ƒ

sw

12

2p ꢆL

C2

IN(MAX)

OUT

(16)

OUT

(17)

Placement of the LC corner frequency at f is not critical,

Z1

The calculated RMS ripple current is 156 mA in the

output capacitors.

it only needs to be close. For the design example, f = 2

LC

kHz.

Solving for C2 using equation 18:

CHOOSING CAPACITOR VALUE

1

C2 ꢌ

2

4p²ƒ

L

For this design example, a relatively large aluminum

electrolytic capacitor is combined with a smaller value

ceramic capacitor. This combination provides a stable high

performance design at a relatively low cost. Also, by

carefully choosing the capacitor values and ESRs, the

design can be tailored to complement the internal

compensation poles and zeros of the TPS54356.

Z1 OUT

(18)

The desired value for C2 is calculated as 184 µF. A close

standard value of 330 µF is chosen with a resulting LC

corner frequency of 1.9 kHz. As to be shown, this value is

not critical as long as it results in a corner frequency in the

vicinity of f

.

Z1

Next, when using a large ceramic capacitor in parallel with

a high ESR electrolytic capacitor, there is a pole in the

These preconfigured poles and zeroes internal to the

TPS54356 limit the range of output filter configurations. A

variety of capacitor values and types of dielectric are

supported. There are a number of different ways to

calculate the output filter capacitor value and ESR to work

with the internal compensation network. This procedure

outlines a relatively simple procedure that produces good

results with an output filter consisting of a high ESR

dielectric capacitor in parallel with a low ESR ceramic

capacitor. Use of the SWIFT Designer Software for

designs with unusually high closed loop crossover

frequencies, low value, low ESR output capacitors such as

ceramics or if the designer is unsure about the design

procedure.

output filter that should be at f as shown in equation 19:

Z2

1

ƒ

ꢀ

ƒ

P(ESR)

Z2

2pR

C5

(C2ESR)

(19)

Now the actual C2 capacitor must be selected based on

the ESR and the value of capacitor C5 so that the above

equation is satisfied. In this example, the R

C5

(C2ESR)

−5

product should be 3.18 ꢁ 10 . From the available

capacitors, by choosing a Panasonic EEVFKOJ331XP

aluminum electrolytic capacitor with a nominal ESR of

0.34 Ω yields a calculated value for C5 of 98 µF. The

closest standard value is 100 µF. As the actual ESR of the

capacitor can vary by a large amount, this value also is not

critical.

The TPS54356 contains a compensation network with the

following nominal characteristics:

The closed loop crossover frequency should be greater

than f and less than one fifth of the switching frequency.

LC

ƒ

ꢀ

1

.

7

k

H

Z

INT

Also, the crossover frequency should not exceed 70 kHz,

as the error amplifier may not provide the desired gain. As

stated previously, closed loop crossover frequencies

ꢀ 2.5 kHZ

ꢀ 4.8 kHZ

ꢀ 95 kHZ

ꢀ 125 kHZ

Z1

Z2

P1

P2

between 5 and 15 times f work well. For this design, the

LC

crossover frequency can be estimated by:

ꢂ

3

ƒ

ꢀ

1

.

1

2

5

ꢁ

1

0

ꢁ

ƒ

ꢁ

ƒ

CO

P(ESR)

LC

(20)

This simplified equation is valid for this design because the

output filter capacitors are mixed technology. Compare

this result to the actual measured loop response plot of

19

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SLVS519 − MAY 2004

Figure 5. The measured closed loop crossover frequency

of 19.95 kHz differs from the calculated value because the

actual output filter capacitor component parameters

differed slightly from the specified data sheet values.

The selected FET must meet the absolute maximum

ratings for the application:

D

Drain-source voltage (V

) must be higher

DSS

than the maximum voltage at the PH pin,

which is V + 0.5 V.

INMAX

CAPACITOR ESR AND OUTPUT RIPPLE

D

Gate-source voltage (V

than 8 V.

) must be greater

GSS

The amount of output ripple voltage as specified in the

initial design parameters is determined by the

maximum ESR of the output capacitor and the input

ripple current. The output ripple voltage is the inductor

ripple current times the ESR of the output filter so the

maximum specified ESR as listed in the capacitor data

sheet is given by equation 21:

Drain current ( ) must be greater than 1.1 x

ld

I

.

OUTMAX

Drain-source on resistance (R

as small as possible, less than 30 mW is

desirable. Lower values for R result in

) should be

DSON

designs with higher efficiencies. It is

important to note that the low-side FET on

time is typically longer than the high-side

FET on time, so attention paid to low-side

FET parameters can make a marked

improvement in overall efficiency.

V

ꢁ L

ꢁ ƒ_swꢁ 0.8

_OUTꢅ

IN(MAX)

OUT

ESR

ꢀ

ꢁ DV

pꢂ p(MAX)

ꢄ

ꢅ

(MAX)

ꢄ

V

ꢁ

ꢂ

V

IN(MAX)

OUT

(21)

and the maximum ESR required is 33 mΩ. In this design,

the aluminum electrolytic capacitor has an ESR of 0.340

mΩ, but it is in parallel with an ultra low ESR ceramic

capacitor of 2 mΩ maximum. The measured output ripple

D

Total gate charge (Q ) must be less than 50

nC. Again, lower Q characteristics result in

g

higher efficiencies.

Additionally, check that the device chosen is

capable of dissipating the power losses.

g

voltage for this design is approximately 4 mV

in Figure 10.

as shown

p−p

For this design, a Fairchild FDR6674A 30-V n-channel

MOSFET is used as the low-side FET. This particular FET

is specifically designed to be used as a low-side

synchronous rectifier.

BIAS AND BOOTSTRAP CAPACITORS

Every TPS54356 design requires a bootstrap capacitor,

C3 and a bias capacitor, C4. The bootstrap capacitor must

be 0.1 µF. The bootstrap capacitor is located between the

PH pins and BOOT pin. The bias capacitor is connected

between the VBIAS pin and AGND. The value should be

1.0 µF. Both capacitors should be high quality ceramic

types with X7R or X5R grade dielectric for temperature

stability. They should be placed as close to the device

connection pins as possible.

POWER GOOD

The TPS54356 is provided with a power good output pin

PWRGD. This output is an open drain output and is

intended to be pulled up to a 3.3-V or 5-V logic supply. A

10-kΩ, pull-up resistor works well in this application. The

absolute maximum voltage is 6 V, so care must be taken

not to connect this pull-up resistor to VIN if the maximum

input voltage exceeds 6 V.

LOW-SIDE FET

SNUBBER CIRCUIT

The TPS54356 is designed to operate using an external

low-side FET, and the LSG pin provides the gate drive

output. Connect the drain to the PH pin, the source to

PGND, and the gate to LSG. The TPS54356 gate drive

circuitry is designed to accommodate most common

n-channel FETs that are suitable for this application. The

SWIFT Designer Software can be used to calculate all the

design parameters for low-side FET selection. There are

some simplified guidelines that can be applied that

produce an acceptable solution in most designs.

R10 and C11 of the application schematic in Figure 25

comprise a snubber circuit. The snubber is included to

reduce over-shoot and ringing on the phase node when the

internal high-side FET turns on. Since the frequency and

amplitude of the ringing depends to a large degree on

parasitic effects, it is best to choose these component

values based on actual measurements of any design

layout. See literature number SLVP100 for more detailed

information on snubber design.

20

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SLVS519 − MAY 2004

+

Figure 26. 3.3-V Power Supply With Schottky Diode

Figure 26 shows an application where a clamp diode is

used in place of the low-side FET. The TPS54352−7

incorporates an integrated pull-down FET so that the

circuit remains operating in continuous mode during light

load operation. A 3-A, 40-V Schottky diode such as the

Motorola MBRS340T3 or equivalent is recommended.

See Figures 15−17 for efficiency data and switching

waveforms for this circuit.

+

Figure 27. 3.3-V/1.8-V Power Supply with Sequencing

21

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Figure 27 is an example of power supply sequencing using

a TPS54356 (U1) to generate an output of 3.3 V, and a

TPS54354 (U2) to generate a 1.8-V output. These output

voltages are typical I/O and core voltages for

microprocessors and FPGAs. In the circuit, the 3.3-V

supply is designed to power up first.

ALTERNATE OUTPUT FILTER DESIGNS

The previous design procedure example demonstrated a

technique to design a 3.3-V power supply using both

aluminum electrolytic and ceramic output filter capacitors.

Other types of output filter capacitors are supported by the

TPS5435x family of dc/dc converters. Figures 26−28 show

designs using other popular capacitor types.

The PWRGD pin of U1 is tied to the ENA pin of U2 so that

the 1.8-V supply starts to ramp up after the 3.3-V supply is

within regulation. Figure 18 shows these start up

sequence waveforms.

In Figure 28, the TPS54356 shown with a single 100-µF

6-V POSCAP as the output filter capacitor. C10 is a high

frequency bypass capacitor and does not enter into the

design equations. The design procedure is similar to the

previous example except in the design of the output filter.

In the previous example, the output filter LC corner was set

at the first zero in the compensation network, while the

second compensation zero was used to counteract the

output filter pole caused by the interaction of the C2

capacitor ESR with C5. In this design example, the output

LC corner frequency is to be set at the second zero

Since the RT pin of U1 is floating, the SYNC pin is an

output. This synchronization signal is fed the SYNC pin of

U2. The RT pin of U2 has a 110-kΩ resistor to ground, and

the SYNC pin for this device acts as an input. The 1.8-V

supply operates synchronously with the 3.3-V supply and

their switching node rising edges are approximately 180

degrees out of phase allowing for a reduction in the input

voltage ripple. See Figure 19 for this wave form.

frequency f

of the internal compensation network,

Z2

approximately 5 kHz, while the first zero is used to provide

phase boost prior to the LC corner frequency.

+

Figure 28. 3.3-V Power Supply with Sanyo POSCAP Output Filter Capacitor

Inductor Selection

1

C2 ꢀ

ꢀ

ꢀ 101 mF

ꢂ 5

4p²ƒ_Z2²L

4 ꢁ p²ꢁ 5000²ꢁ 10

out

Using equation 12 and a K

of 0.2, the minimum inductor

IND

value required is 8.98 µH. The closest standard value, 10

µH is selected. RMS and peak inductor currents are the

same as calculated previously.

Use 100 µF as the closest standard value.

Calculating the RMS ripple current in the output capacitor

using equation 16 yields 156 mA. The POSCAP

6TPC100M capacitor selected is rated for 1700 mA. See

the closed loop response curve for this design in Figure 20.

Capacitor Selection

With the inductor set at 10 µH and a desired corner

frequency of 5 kHz, the output capacitor value is given by:

22

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SLVS519 − MAY 2004

+

Figure 29. 3.3-V Power Supply with Panasonic SP Output Filter Capacitors

In Figure 29, the TPS54356 shown with two 180-µF 4-V

special polymer dielectric output filter capacitors(C2 and

C5). C10 is a high frequency bypass capacitor and does

not enter into the design equations. In the previous

example, the output LC corner frequency is to be set at the

Capacitor Selection

To lower the closed loop crossover it is necessary to

reduce the LC corner frequency below 5 kHz. Using a

target value of 2500 Hz, the output capacitor value is given

by:

second zero frequency f of the internal compensation

Z2

network, approximately 5 kHz, while the first zero is used

to provide phase boost prior to the LC corner frequency.

The special polymer electrolytic capacitors used in this

design require that the closed loop crossover frequency be

lowered due to the significantly lower ESR of this type of

capacitor.

1

C2 ꢀ

ꢀ

ꢀ 405 mF

ꢂ 5

4p²ƒ_Z2²L

4 ꢁ p²ꢁ 2500²ꢁ 10

out

Use 2 x 180 µF = 360 µF as a combination of standard

values that is close to 405 µF.

Inductor Selection

The RMS ripple current in the output capacitor is the same

as before. The selected capacitors are each 3.3 A. See the

closed loop response curve for this design in Figure 21.

The inductor is the same 10-µH value as the previous

example.

+

Figure 30. 3.3-V Power Supply with Sanyo OSCON Output Filter Capacitor

In Figure 30, the TPS54356 shown with a Sanyo OSCON

output filter capacitor(C2). C10 is a high frequency bypass

capacitor and does not enter into the design equations.

This design is identical to the previous example except that

a single OSCON capacitor of 330 µF is used for the

calculated value of 405 µF. Compare the closed loop

response for this design in Figure 22 to the closed loop

response in Figure 21. Note that there is only a slight

difference in the response and the general similarity in both

the gain and phase plots. This is the expected result for

these two similar output filters.

Many other additional output filter designs are possible.

Use the SWIFT Designer Software to generate other

designs or follow the general design procedures illustrated

in this application section.

23

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VIN(UVLO) START AND STOP

vs

FREE-AIR TEMPERATURE

MAXIMUM SWITCHING FREQUENCY

RT RESISTANCE

vs

SWITCHING FREQUENCY

vs

INPUT VOLTAGE

6.5

6.0

5.5

5.0

4.5

4.0

3.5

800

700

600

500

400

300

200

225

200

175

150

125

100

75

V

= 2.5 V

Start

O

TPS54357

Stop

TPS54352−6

V

= 1.2 V

O

Start

Stop

V

= 1.5 V

O

V

= 1.8 V

O

50

200

−50 −25

0

25 50 75 100 125 150

4

6

8

10 12 14 16 18 20

300

400

500

600

700

T

A

− Free-Air Temperature − 5C

V

− Input Voltage − V

Switching Frequency − kHz

I

Figure 31

Figure 32

Figure 33

ENABLED SUPPLY CURRENT

DISABLED SUPPLY CURRENT

BIAS VOLTAGE

vs

INPUT VOLTAGE

vs

INPUT VOLTAGE

10

9

1.3

1.2

1.1

1.0

0.9

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

T

f

= 25°C

= 500 kHz

J

S

T

J

= 25°C

T

J

= 25°C

8

7

6

5

4

3

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

− Input Voltage − V

I

15

20

25

V

− Input Voltage − V

I

V

− Input Voltage − V

V

I

Figure 34

Figure 35

Figure 36

CURRENT LIMIT

vs

POWER GOOD THRESHOLD

vs

INTERNAL VOLTAGE REFERENCE

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

6.0

98.0

97.5

97.0

96.5

96.0

0.8912

0.8910

0.8908

0.8906

0.8904

0.8902

T

J

= 25°C

VIN = 12 V

5.5

5.0

4.5

4.0

0.8900

0.8898

5.0

7.5

10.0 12.5 15.0 17.5 20.0

−50 −25

0

25 50 75 100 125 150

−50 −25

0

25 50 75 100 125 150

V

− Input Voltage − V

T

J

− Junction Temperature − 5C

T

J

− Junction Temperature − 5C

Figure 38

I

Figure 39

Figure 37

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SLVS519 − MAY 2004

ON RESISTANCE

PH VOLTAGE

vs

SINK CURRENT

SLOW START CAPACITANCE

vs

TIME

JUNCTION TEMPERATURE

2

1.75

1.50

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

150

130

110

90

V

= 12 V

= 0.5 A

I

O

R

= 2 kΩ

SS

V

= 4.5 V

I

V

= 12 V

I

1.25

1

70

0.05

0

50

−50 −25

0

10 20 30 40 50 60 70 80

100

150

200

250

300

0

25 50 75 100 125 150

t − Time − ms

I

− Sink Current − mA

T

J

− Junction Temperature − 5C

CC

Figure 40

Figure 41

Figure 42

POWER GOOD DELAY

vs

HICCUP TIME

vs

INTERNAL SLOW START TIME

vs

SWITCHING FREQUENCY

5

4.5

4

10

9

4.5

4

TPS54354

3.5

3

8

7

3.5

2.5

2

6

3

2.5

2

5

1.5

1

4

3

2

1.5

1

0.5

0

250

350

450

550

650

750

250

350

450

550

650

750

250

350

450

550

650

750

Switching Frequency − kHz

Figure 43

Figure 44

Figure 45

FREE-AIR TEMPERATURE

vs

MAXIMUM OUTPUT VOLTAGE

POWER DISSIPATION

vs

MAXIMUM OUTPUT CURRENT

INPUT VOLTAGE

FREE-AIR TEMPERATURE

6

5

4

140

120

100

80

2.5

T = 125°C

J

TPS54357

2

θ

JA

= 42.1°C/W

TPS54356

1.5

3

2

TPS54355

TPS54354

60

40

20

0

1

θ

JA

= 191.9°C/W

0.5

0

1

0

TPS54352

TPS54353

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

45

65

85

105

125

I

− Output Current − A

V

− Input Voltage − V

T

A

− Free-Air Temperature − °C

O

I

Figure 46

Figure 47

Figure 48

25

ꢀ ꢁ

ꢂꢃ ꢄ ꢅ ꢃ ꢆꢇ

ꢂ ꢃ ꢄꢅ ꢃ ꢄ ꢇ

ꢂ ꢃ ꢄꢅ ꢃ ꢈ ꢇ

ꢀ ꢁ

ꢂ ꢃ ꢄ ꢅ ꢃ ꢅ

ꢂ ꢃꢄ ꢅ ꢃ ꢃ

ꢂ ꢃ ꢄ ꢅ ꢃ ꢉ

www.ti.com

SLVS519 − MAY 2004

THERMAL PAD MECHANICAL DATA

PWP (R−PDSO−G16)

PowerPADt PLASTIC SMALL−OUTLINE

PPTD024

26

IMPORTANT NOTICE

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型号：	TPS54354PWP
厂家：	TEXAS INSTRUMENTS
描述：	4.5V TO 20 V INPUT 3-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET 4.5V到20V输入3 -A输出同步PWM具有集成FET SWITCHER 输出元件输入元件
文件：	总28页 (文件大小：539K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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