TPS54361 [TI]
具有软启动和 Eco-Mode™ 的 4.5 至 60V 输入 3.5A 降压直流/直流转换器;
| 型号： | TPS54361 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有软启动和 Eco-Mode™ 的 4.5 至 60V 输入 3.5A 降压直流/直流转换器 软启动 转换器 |
| 文件： | 总52页 (文件大小：2181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
TPS54361 具有软启动和 Eco-Mode™ 的 4.5V 至 60V 输入、
3.5A、降压 DC-DC 转换器
1 特性
3 说明
1
•
•
•
可在轻负载条件下实现高效率，使用脉冲跳跃 Eco-
mode™
TPS54361 器件是一款集成高侧 MOSFET 的 60V、
3.5A 降压稳压器。根据 ISO 7637 标准，该器件可承
受高达 65V 的负载突降脉冲。电流模式控制提供了简
单的外部补偿和灵活的组件选择。一个低纹波脉冲跳跃
模式将无负载输出电源电流减小至 152μA。当使能引
脚被拉至低电平时，关断电源电流将降至 2μA。
89mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
152μA 静态运行电流和
2μA 关断电流
•
•
•
100kHz 至 2.5MHz 可调开关频率
欠压锁定在内部设定为 4.3V，但可通过使能引脚上的
外部电阻分压器将之提高。输出电压启动斜坡受控于软
启动引脚，该引脚还可被配置用来控制电源排序和跟
踪。一个开漏电源正常信号表示输出处于标称电压值的
93% 至 106% 之内。
同步至外部时钟
可在轻负载条件下使用集成型引导 (BOOT) 再充电
场效应晶体管 (FET) 实现低压降
•
•
•
•
•
可调欠压闭锁 (UVLO) 电压和迟滞
欠压 (UV) 和过压 (OV) 电源正常输出
可调节软启动和定序
宽范围可调开关频率允许针对效率或者外部组件尺寸进
行优化。逐周期电流限制、频率折返和热关断功能可在
过载情况下保护内部和外部组件。
0.8V 1% 内部电压基准
带有散热焊盘的 10 引脚晶圆级小外形无引线
(WSON) 封装
TPS54361 器件采用 10 引脚 4mm x 4mm WSON 封
装。
•
•
TJ 运行范围为 -40°C 至 150°C
使用 TPS54361 并借助 WEBENCH Power
Designer 创建定制设计方案
器件信息
器件编号
TPS54361
封装（引脚）
封装尺寸
2 应用范围
WSON (10)
4.00mm x 4.00mm
•
•
工业自动化和电机控制
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
车辆附件：全球卫星定位 (GPS)（请参见
SLVA412），娱乐系统
•
•
USB 专用充电端口和电池充电器（请参见
SLVA464）
12V、24V 和 48V 工业、汽车及通信用电源系统
简化电路原理图
效率与负载电流间的关系
100
VIN
36 V to 12 V
tíwD5
ëLb
95
Çt{ꢁ4361
90
85
.hhÇ
9b
12 V to 3.3 V
80
wÇꢀ/[Y
{{ꢀÇw
VOUT
12 V to 5 V
{í
75
70
/hat
VOUT = 12 V, fsw = 620kHz,
VOUT = 5 V and 3.3 V, f sw = 400 kHz
65
60
C.
0
1
2
3
4
5
C024
IO - Output Current (A)
Db5
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSC39
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 27
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Applications ................................................ 28
Power Supply Recommendations...................... 41
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 42
10.3 Estimated Circuit Area .......................................... 42
11 器件和文档支持 ..................................................... 43
11.1 器件支持................................................................ 43
11.2 文档支持 ............................................................... 43
11.3 接收文档更新通知 ................................................. 43
11.4 社区资源................................................................ 43
11.5 商标....................................................................... 44
11.6 静电放电警告......................................................... 44
11.7 Glossary................................................................ 44
12 机械、封装和可订购信息....................................... 44
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (February 2016) to Revision D
Page
•
•
•
•
WEBENCH 信息至特性，详细设计流程和器件支持部分........................................................................................................ 1
Changed Equation 10 and Equation 11 .............................................................................................................................. 20
Changed Equation 30 .......................................................................................................................................................... 29
Changed From: "PowerPAD" To: "thermal pad" in the Layout Guidelines section .............................................................. 42
Changes from Revision B (August 2015) to Revision C
Page
•
•
•
•
Added SW, 5-ns Transient to the Absolute Maximum Ratings .............................................................................................. 4
Changed text in the Application Information From: "iterative design procedure" To: "interactive design procedure".......... 28
Changed = 47 W To: = 0.444W in Equation 56 ................................................................................................................... 35
Changed = 47 W To: = 0.444W and = 0.616 W To: 0.591 W in Equation 60...................................................................... 36
Changes from Revision A (December 2013) to Revision B
Page
•
已添加 ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
Changes from Original (November 2013) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
www.ti.com.cn
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
5 Pin Configuration and Functions
DPR Package
10-Pin WSON With Thermal Pad
Top View
1
2
3
4
5
10
9
BOOT
VIN
PWRGD
SW
8
EN
GND
COMP
FB
7
SS/TR
RT/CLK
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between the BOOT and SW pin. If the voltage on this capacitor is below
the minimum required to turn on the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
BOOT
1
I
I
I
This pin is the error amplifier output and input to the output switch current (PWM) comparator. Connect
frequency compensation components to this pin.
COMP
EN
7
3
This pin is the enable pin. An internal pullup current source enables the TPS54361 if the EN pin is floating.
Pull EN below 1.2 V to disable. Adjust the input undervoltage lockout with two resistors. See Enable and
Adjusting Undervoltage Lockout.
FB
6
8
I
This pin is the inverting input of the transconductance (gm) error amplifier.
Ground
GND
–
The Power Good pin is an open drain output that asserts low if the output voltage is out of regulation
because of thermal shutdown, dropout, overvoltage, or EN shutdown.
PWRGD
RT/CLK
10
O
I
This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop,
the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
5
This pin is the soft start and tracking pin. An external capacitor connected to this pin sets the output rise
time. Because the voltage on this pin overrides the internal reference, the SS/TR pin can be used for
tracking and sequencing.
SS/TR
4
I
SW
VIN
9
2
O
I
The SW pin is the source of the internal high-side power MOSFET and switching node of the converter.
Connect to this pin the input voltage supply with a 4.5-V to 60-V operating range.
The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Thermal Pad
–
Copyright © 2013–2017, Texas Instruments Incorporated
3
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–7
MAX
65
8.4
3
UNIT
VIN
EN
FB
COMP
PWRGD
3
6
Voltage
SS/TR
3
V
RT/CLK
3.6
8
BOOT-SW
SW
65
65
65
150
150
SW, 5-ns Transient
SW, 10-ns Transient
–2
Operating junction temperature
Storage temperature, Tstg
–40
–65
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
60
UNIT
V
VIN
VO
IO
Supply input voltage
Output voltage
4.5
0.8
0
58.8
3.5
V
Output current
A
TJ
Junction Temperature
–40
150
°C
6.4 Thermal Information
TPS54361
DPR (WSON)
10 PINS
35.1
THERMAL METRIC(1) (2)
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ψJT
0.3
ψJB
12.5
RθJC(top)
RθJC(bot)
RθJB
34.1
2.2
12.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See the power dissipation estimate in Power Dissipation Estimate for more information.
4
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
www.ti.com.cn
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
4.1
60
V
V
Internal undervoltage lockout
threshold
Rising
4.3
4.48
Internal undervoltage lockout
threshold hysteresis
325
2.25
152
mV
μA
μA
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V
4.5
Operating: nonswitching supply
current
FB = 0.9 V, TA = 25°C
200
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold +50 mV
1.1
1.2
–4.6
–1.2
–3.4
1.3
V
Input current
μA
μA
Enable threshold –50 mV
–0.58
–2.2
–1.8
–4.5
Hysteresis current
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
ON-resistance
0.792
0.8
89
0.808
190
V
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance
(gm)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
350
μS
Error amplifier transconductance
(gm) during soft start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
77
μS
Error amplifier DC gain
Min unity gain bandwidth
Error amplifier source/sink
VFB = 0.8 V
10 000
2500
±30
V/V
kHz
μA
V(COMP) = 1 V, 100-mV overdrive
COMP to SW current
transconductance
12
A/V
CURRENT LIMIT
All VIN and temperatures, open loop(1)
All temperatures, VIN = 12 V, open loop(1)
VIN = 12 V, TA = 25°C, open loop(1)
4.5
4.5
5.2
5.5
5.5
5.5
6.8
6.3
5.9
Current limit threshold
A
THERMAL SHUTDOWN
Thermal shutdown
176
12
°C
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
1.55
1.2
2
V
V
RT/CLK low threshold
0.5
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
Copyright © 2013–2017, Texas Instruments Incorporated
5
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START AND TRACKING (SS/TR PIN)
Charge current
VSS/TR = 0.4 V
1.7
42
µA
mV
V
SS/TR-to-FB matching
SS/TR-to-reference crossover
VSS/TR = 0.4 V
98% nominal
1.16
SS/TR discharge current
(overload)
FB = 0 V, VSS/TR = 0.4 V
FB = 0 V
354
54
µA
SS/TR discharge voltage
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low
FB threshold for PWRGD high
FB threshold for PWRGD low
FB threshold for PWRGD high
Hysteresis
mV
FB falling
90%
93%
108%
106%
2.5%
10
FB rising
FB rising
FB falling
FB falling
Output high leakage
VPWRGD = 5.5 V, TA = 25°C
IPWRGD = 3 mA, VFB < 0.79 V
nA
Ω
ON-resistance
45
Minimum VIN for defined output VPWRGD < 0.5 V, IPWRGD = 100 µA
0.9
2
V
6.6 Timing Requirements
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
RT/CLK
Minimum CLK input pulse width
15
ns
6.7 Switching Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
60
MAX
UNIT
ns
SW
VIN = 23.7 V, VOUT = 5 V, IOUT = 3.5
A, RT = 39.6 kΩ, TA = 25°C
ton
Minimum ON-time
CURRENT LIMIT
Current limit threshold delay
RT/CLK
Switching frequency range using RT mode
ƒSW Switching frequency
ns
100
450
2500
550
kHz
kHz
RT = 200 kΩ
500
Switching frequency range using CLK
mode
160
2300
kHz
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with an RT
resistor in series
55
78
ns
PLL lock-in time
Measured at 500 kHz
μs
ERROR AMPLIFIER
Enable to COMP active
VIN = 12 V, TA = 25°C
540
µs
6
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
www.ti.com.cn
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
6.8 Typical Characteristics
0.25
0.2
0.15
0.1
0.05
0
0.814
0.809
0.804
0.799
0.794
0.789
0.784
BOOT-SW = 3 V
BOOT-SW = 6 V
VIN=12V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C001
C002
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
Figure 1. ON-Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
6.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
4.9
-40 °C
25 °C
150 °C
4.7
4.5
V=12V
IN
0
10
20
30
40
50
60
0
25
50
75
100
125
150
œ50
œ25
C004
C003
VI - Input Voltage (V)
TJ Junction - Temperature (°C)
Figure 4. Switch Current Limit vs Input Voltage
Figure 3. Switch Current Limit vs Junction Temperature
550
540
530
520
510
500
490
480
470
500
450
400
350
300
250
200
150
100
460
450
RT = 200 kꢀ, VIN = 12 V
0
25
50
75
100
125
150
200
300
400
500
600
700
800
900 1000
œ50
œ25
C005
C006
TJ œ Junction Temperature (°C)
RT/CLK - Resistance (kꢀ)
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance
Low-Frequency Range
Copyright © 2013–2017, Texas Instruments Incorporated
7
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
Typical Characteristics (continued)
2500
500
450
400
350
300
250
200
2000
1500
1000
500
0
VIN = 12 V
0
50
100
150
200
0
25
50
75
100
125
150
œ50
œ25
C007
C008
RT/CLK - Resistance (kꢀ)
TJ œ Junction Temperature (°C)
Figure 7. Switching Frequency vs RT/CLK Resistance
High-Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
120
1.3
110
100
90
1.27
1.24
1.21
1.18
80
70
60
50
40
30
VIN = 12 V
VIN = 12 V
20
1.15
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C009
C010
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
Figure 9. EA Transconductance During Soft Start vs
Junction Temperature
Figure 10. EN Pin Voltage vs Junction Temperature
œ0.5
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
œ4.7
œ4.9
œ5.1
œ5.3
œ5.5
œ0.7
œ0.9
œ1.1
œ1.3
œ1.5
œ1.7
œ1.9
œ2.1
œ2.3
œ2.5
VIN = 12 V, IEN = Threshold + 50 mV
VIN = 12 V, IEN = Threshold - 50 mV
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C011
C012
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
Figure 11. EN Pl Current vs Junction Temperature
Figure 12. EN Pin Current vs Junction Temperature
8
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
www.ti.com.cn
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
Typical Characteristics (continued)
œ2.5
œ2.7
œ2.9
œ3.1
œ3.3
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
100.0
75.0
50.0
25.0
0.0
V
Falling
SENSE
VIN = 12 V
VSENSERising
0.6 0.7
0
25
50
75
100
125
150
0.0
0.1
0.2
0.3
0.4
0.5
0.8
œ50
œ25
C013
C014
TJ œ Junction Temperature (°C)
VSENSE (V)
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
Figure 14. Switching Frequency vs FB
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
TJ = 25 °C
VIN = 12 V
0
10
20
30
40
50
60
0
25
50
75
100
125
150
œ50
œ25
C016
VIN - Input Voltage (°C)
C015
TJ œ Junction Temperature (°C)
Figure 15. Shutdown Supply Current vs Junction
Temperature
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
210
190
170
150
130
110
90
210
190
170
150
130
110
90
TJ = 25 °C
VIN = 12 V
70
70
0
10
20
30
40
50
60
0
25
50
75
100
125
150
œ50
œ25
C018
VIN - Input Voltage (°C)
C017
TJ œ Junction Temperature (°C)
Figure 17. VIN Supply Current vs Junction Temperature
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
2.6
2.5
2.4
2.3
2.2
2.1
2
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
UVLO Start Switching
UVLO Stop Switching
BOOT-PH UVLO Falling
BOOT-PH UVLO Rising
1.9
1.8
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
C020
TJ œ Junction Temperature (°C)
C019
TJ œ Junction Temperature (°C)
Figure 20. Input Voltage UVLO vs Junction Temperature
Figure 19. BOOT-SW UVLO vs Junction Temperature
80
110
FB
108
70
60
50
40
30
20
10
106
FB Falling
104
102
100
98
96
94
92
90
88
VIN = 12 V
FB Rising
VIN = 12 V
FB Falling
25
0
0
25
50
75
100
125
150
0
50
75
100
125
150
œ50
œ25
œ50
œ25
C021
C022
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
Figure 21. PWRGD ON-Resistance vs Junction Temperature
Figure 22. PWRGD Threshold vs Junction Temperature
900
60
VIN = 12 V, 25 °C
800
700
600
500
400
300
200
100
0
55
50
45
40
35
30
25
VIN = 12 V, FB = 0.4 V
20
0
100
200
300
400
500
600
700
800
0
25
50
75
100
125
150
œ50
œ25
C024
C025
SS/TR (mV)
TJ œ Junction Temperature (°C)
Figure 23. SS/TR to FB Offset vs FB
Figure 24. SS/TR to FB Offset vs Temperature
10
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Typical Characteristics (continued)
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
Start
Stop
Dropout
Voltage
Dropout
Voltage
4.6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
C026
Output Current (A)
Figure 25. 5-V Start and Stop Voltage
(see Low Dropout Operation and Bootstrap Voltage (BOOT))
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7 Detailed Description
7.1 Overview
The TPS54361 device is a 60-V, 3.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. The device implements constant-frequency current-mode control which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows either efficiency or size optimization when selecting the output filter components. The switching frequency
is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turnon to a falling edge of an
external clock signal.
The TPS54361 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the input voltage
undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source enables
operation when the EN pin is floating. The operating current is 152 μA under no load condition when not
switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54361 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54361 device to operate at high
duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage
of the application. The minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an overvoltage protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor-
divider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an overtemperature
fault, UVLO fault or a disabled condition. When the overload condition is removed, the soft-start circuit controls
the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the
switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor
current.
12
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7.2 Functional Block Diagram
PWRGD
EN
VIN
Shutdown
Thermal
Shutdown
UVLO
Enable
UV
OV
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Boot
Current
UVLO
Sense
Skip
Error
Amplifier
PWM
BOOT
FB
Comparator
SS/TR
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Foldback
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
10/9/2013 A0272435
GND
Thermal Pad
RT/ CLK
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54361 device uses fixed-frequency peak current-mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier
output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current-limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54361 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
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Feature Description (continued)
7.3.3 Pulse-Skip Eco-Mode
The TPS54361 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by
reducing switching and gate drive losses. The device enters Eco-mode if the output voltage is within regulation
and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage control-loop responds to
the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54361 device senses and controls the peak switch current and not the
average load current. Therefore the load current at which the device enters Eco-mode is dependent on the
output inductor value. As the load current approaches zero, the device enters a pulse-skip mode during which it
draws only a 152-μA input quiescent current. The circuit in Figure 46 enters Eco-mode at about a 25-mA output
current and with no external load has an average input current of 260 µA.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54361 device provides an integrated bootstrap voltage-regulator. A small capacitor between the BOOT
and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when
the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R-grade dielectric with a voltage rating of 10 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54361
device operates at a 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high output voltages, the small low-side MOSFET disables at 24-V output and re-enables when the output
reaches 21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle
of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during
dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-
side diode voltage and the printed circuit board (PCB) resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is
plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty-cycle (low-dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged which results in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1
calculates the minimum input voltage for this condition.
14
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Feature Description (continued)
VOmax = Dmax × (VVINmin – IOmax × RDS(on) + Vd) – Vd – IOmax × Rdc
where
•
•
•
•
•
•
Dmax ≥ 0.9
Vd = Forward Drop of the Catch Diode
RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 x VB2SW – 4.246)
VB2SW = VBOOT + Vd
VBOOT = (1.41 × VVIN – 0.554 – Vd × ƒsw × 10-6 – 1.847 × 103 × IB2SW) / (1.41 + ƒsw × 10-6)
IB2SW = 100 × 10-6
A
(1)
7.3.5 Error Amplifier
The TPS54361 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μS during normal operation. During soft-start operation,
the transconductance is reduced to 78 μS and the error amplifier is referenced to the internal soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. Divider resistors with a 1%-tolerance or better are recommended.
Select the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors from the FB input current may become noticeable.
V
- 0.8 V
æ
ç
è
ö
÷
ø
OUT
RHS = RLS
´
0.8 V
(2)
7.3.7 Enable and Adjust Undervoltage Lockout
The TPS54361 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54361 device disables when the VIN pin voltage falls below 4 V or when the
EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA that enables
operation of the TPS54361 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3-μA
IHYS current is removed. This additional current facilitates the adjustable input-voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin experiences a voltage greater than the absolute maximum
voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN
resistors, the EN pin is clamped internally with a 5.8-V Zener diode that sinks up to 150 μA.
V
- V
STOP
START
R
=
UVLO1
I
HYS
(3)
(4)
V
ENA
R
=
UVLO2
V
- V
ENA
START
+ I
1
R
UVLO1
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Feature Description (continued)
VIN
TPS54361
TPS54361
VIN
i1 ihys
R
UVLO1
EN
R
UVLO1
10 kW
EN
Node
VEN
R
UVLO2
5.8 V
R
UVLO2
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Adjustable Undervoltage Lockout
(UVLO)
Figure 27. Internal EN Pin Clamp
7.3.8 Soft-Start/Tracking Pin (SS/TR)
The TPS54361 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a soft-start time. The TPS54361 has an internal pullup current source of 1.7 μA
that charges the external soft-start capacitor. The calculations for the soft-start time (10% to 90%) are shown in
Equation 5. The voltage reference (VREF) is 0.8 V and the soft-start current (ISS) is 1.7 μA. The soft-start capacitor
must remain lower than 0.47 μF and greater than 0.47 nF.
TSS (ms) ´ ISS (μA)
CSS (nF) =
VREF (V) ´ 0.8
(5)
At power up, the TPS54361 device does not start switching until the soft-start pin is discharged to less than 54
mV to ensure a proper power up, see Figure 28.
Also, during normal operation, the TPS54361 device stops switching and the SS/TR must discharge to 54 mV
when one of the following occurs: the VIN UVLO is exceeded, the EN pin pulled below 1.2 V, or a thermal
shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42 mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.
Figure 28. Operation of SS/TR Pin When Starting
16
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Feature Description (continued)
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 29 using two TPS54361 devices. The power good is
connected to the EN pin on the TPS54361 which enables the second power supply once the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-
ms start-up delay. Figure 30 shows the results of Figure 29.
TPS54361
PWRGD
TPS54361
EN
EN
SS/TR
SS /TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Schematic for Sequential Start-Up Sequence
Figure 30. Sequential Startup Using EN and PWRGD
TPS54361
3
4
6
EN
SS/TR
PWRGD
TPS54361
3
4
6
EN
SS/TR
PWRGD
Figure 32. Ratiometric Startup Using Coupled SS/TR pins
Copyright © 2017, Texas Instruments Incorporated
Figure 31. Schematic for Ratiometric Start-Up Sequence
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Feature Description (continued)
Figure 31 shows a method for ratiometric start up sequence by connecting the SS/TR pins together. The
regulator outputs ramps up and reaches regulation at the same time. When calculating the soft-start time the
pullup current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.
TPS54361
EN
VOUT 1
SS/TR
PWRGD
TPS54361
VOUT 2
EN
R1
SS/TR
R2
PWRGD
R3
R4
Copyright © 2017, Texas Instruments Incorporated
Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 33 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2
slightly before, after or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and VOUT2
at the 95% of nominal output regulation.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset
(VSSoffset) in the soft-start circuit and the offset created by the pullup current source (ISS) and tracking resistors,
the VSSoffset and ISS are included as variables in the equations.
To design a ratiometric start up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown
fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the
calculated R1 value from Equation 6 is greater than the value calculated in Equation 9 to ensure the device can
recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSoffset becomes larger as
the soft-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in
Figure 33.
VOUT2 + DV VSSoffset
´
R1=
VREF
VREF ´ R1
VOUT2 + DV - VREF
ISS
(6)
R2 =
(7)
18
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Feature Description (continued)
DV = VOUT1 - VOUT2
(8)
(9)
R1> 2800 ´ VOUT1 -180 ´ DV
Figure 34. Ratiometric Startup With Tracking Resistors
Figure 35. Ratiometric Startup With Tracking Resistors
Figure 36. Simultaneous Startup With Tracking Resistor
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54361 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size
one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage and minimum controllable on time must be considered. The minimum controllable on
time is typically 100 ns which limits the maximum operating frequency in applications with high input to output
step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in Maximum Switching Frequency.
101756
f sw (kHz)1.008
RT (kW) =
(10)
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Feature Description (continued)
92417
RT (kW)0.991
f sw (kHz) =
(11)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V and
have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit
must be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when
the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is
connected in parallel with an AC coupling capacitor to a termination resistor (for example, 50 Ω) as shown in
Figure 37. The two resistors in series provide the default frequency setting resistance when the signal source is
turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. AC
coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold the TPS54361 switches from the RT resistor free-
running frequency mode to the PLL synchronized mode. The internal 0.5-V voltage source is removed and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency
can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor
mode to the PLL mode and locks onto the external clock frequency within 78 ms. During the transition from the
PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then increases or
decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 38, Figure 39 and Figure 40 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse-skip mode (Eco-Mode).
SPACER
TPS54361
PLL
TPS54361
PLL
RT/CLK
RT
RT/CLK
RT
Hi-Z
Clock
Source
Clock
Source
Copyright © 2017, Texas Instruments Incorporated
Figure 37. Synchronizing to a System Clock
20
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Feature Description (continued)
Figure 39. Plot of Synchronizing in DCM
Figure 38. Plot of Synchronizing in CCM
Figure 40. Plot of Synchronizing in Eco-mode
7.3.12 Maximum Switching Frequency
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54361
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls
from 0.8 V to 0 V. The TPS54361 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current may exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 13 calculates the maximum switching frequency at
which the inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating
frequency must not exceed the calculated value.
Copyright © 2013–2017, Texas Instruments Incorporated
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Feature Description (continued)
Equation 12 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
æ
ç
ö
÷
IO ´Rdc + VOUT + Vd
1
ƒSW maxskip
=
´
(
)
ç
÷
tON
VIN -IO ´ RDS on + Vd
( )
è
ø
(12)
æ
ç
ö
ICL ´Rdc + VOUT sc + Vd
ƒDIV
( )
÷
ƒSW(shift)
=
´
ç
÷
tON
VIN -ICL ´RDS on + Vd
( )
è
ø
where
•
•
•
•
•
•
•
•
•
•
IO is the output current
ICL is the current limit
Rdc is the inductor resistance
VIN is the maximum input voltage
VOUT is the output voltage
VOUT(SC) is the output voltage during short
Vd is the diode voltage drop
RDS(on) is the switch ON-resistance
tON is the controllable ON-time
ƒDIV is the frequency divide equals (1, 2, 4, or 8)
(13)
7.3.13 Accurate Current Limit Operation
The TPS54361 implements peak current mode control in which the COMP pin voltage controls the peak current
of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side switch is
turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the
peak switch current limit. The TPS54361 provides an accurate current limit threshold with a typical current limit
delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The relationship
between the inductor value and the peak inductor current is shown in Figure 41.
22
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
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ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
Feature Description (continued)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = V /L x tCLdelay
IN
tCLdelay
tON
Figure 41. Current Limit Delay
7.3.14 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output. Once the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is deasserted and the pin floats. TI recommends a pullup resistor of 1 kΩ to a voltage
source that is 5.5 V or less. A higher pullup resistance reduces the amount of current drawn from the pullup
voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but
with reduced current sinking capability. The PWRGD achieves full current-sinking capability as VIN input voltage
approaches 3 V.
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.15 Overvoltage Protection
The TPS54361 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable
time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current limit
threshold. When the overload condition is removed, the regulator output rises and the error amplifier output
transitions to the normal operating level. In some applications, the power supply output voltage can increase
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
Copyright © 2013–2017, Texas Instruments Incorporated
23
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
7.3.16 Thermal Shutdown
The TPS54361 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence controlled
by discharging the SS/TR pin.
7.3.17 Small Signal Model for Loop Response
Figure 42 shows a simplified equivalent model for the TPS54361 control loop which can be simulated to check
the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a
gmea of 350 μS. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor
RO and capacitor CO model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
V
O
Power Stage
gm
12 A/V
ps
a
b
R(ESR)
R(HS)
R(L)
COMP
c
FB
C(O)
0.8 V
C(OEA) R(OEA)
R(COMP)
gm
ea
C(POLE)
R(LS)
350 µA/V
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Small Signal Model for Loop Response
7.3.18 Simple Small Signal Model for Peak Current Mode Control
Figure 43 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54361 device power stage can be approximated by a voltage-controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stage
transconductance, gmps. The gmps for the TPS54361 device is 12 A/V. The low-frequency gain of the power
stage is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 43. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 17).
24
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TPS54361
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ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
Feature Description (continued)
V
O
Adc
VC
R
ESR
ƒP
R
L
gm
ps
C
OUT
ƒZ
Figure 43. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
ç
è
ö
s
1+
÷
2p ´ ƒZ ø
VOUT
VC
= Adc ´
æ
ç
ö
÷
s
1+
2p ´ ƒP ø
è
(14)
(15)
Adc = gmps ´ RL
1
ƒP
=
COUT ´ RL ´ 2p
(16)
(17)
1
ƒZ
=
COUT ´ RESR ´ 2p
7.3.19 Small Signal Model for Frequency Compensation
The TPS54361 uses a transconductance amplifier for the error amplifier and supports three of the commonly-
used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 44. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small
signal model in Figure 44. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 44. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
Copyright © 2013–2017, Texas Instruments Incorporated
25
TPS54361
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www.ti.com.cn
Feature Description (continued)
V
O
R1
FB
Type 2A
Type 2B
Type 1
gmea
COMP
VREF
C2
R3
C1
R3
R2
C2
R
C
O
O
C1
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol V / V
(
gmea
)
RO
=
(18)
(19)
gmea
CO
=
2p ´ BW (Hz)
æ
ö
s
1+
ç
÷
2p ´ ƒZ1 ø
è
EA = A0 ´
æ
ö
æ
ç
è
ö
æ
ç
è
ö
s
s
1+
´ 1+
ç
÷
÷
÷
ç
è
÷
2p ´ ƒP1 ø
2p ´ ƒP2 ø
ø
(20)
(21)
(22)
R2
A0 = gmea ´ RO
´
+
R2
A1= gmea ´ RO P R3 ´
+
1
P1=
2p ´ RO ´ C1
(23)
26
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TPS54361
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ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
Feature Description (continued)
1
Z1=
2p´R3´ C1
(24)
(25)
(26)
(27)
1
P2 =
Type 2A
2p ´ R3PRO ´ C2 + C
(
)
O
1
P2 =
P2 =
Type 2B
2p ´ R3PRO ´ CO
1
Type 1
2p ´ RO ´ C2 + C
(
)
O
7.4 Device Functional Modes
The TPS54361 is designed to operate with input voltages above 4.5 V. When the VIN voltage is above the 4.3 V
typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device is active. If the
VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the EN voltage falls
below the 1.2-V threshold the device stops switching and enters a shutdown mode with low supply current of 2
µA typical.
The TPS54361 will operate in CCM when the output current is enough to keep the inductor current above 0 A at
the end of each switching period. As a nonsynchronous converter, it will enter DCM at low output currents when
the inductor current falls to 0 A before the end of a switching period. At very low output current the COMP
voltage will drop to the pulse-skipping threshold and the device operates in a pulse-skipping Eco-mode. In this
mode, the high-side MOSFET does not switch every switching period. This operating mode reduces power loss
while keeping the output voltage regulated. For more information on Eco-mode see the Pulse-Skip Eco-Mode
section.
Copyright © 2013–2017, Texas Instruments Incorporated
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TPS54361
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www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54361 device is a 60-V, 3.5-A, step-down regulator with an integrated high-side MOSFET. This device is
typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of
3.5 A. Example applications are: 12 V, 24 V, and 48 V industrial, automotive, and communications power
systems. Use the following design procedure to select component values for the TPS54361 device. This
procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use
the WEBENCH® software to generate a complete design. The WEBENCH software uses an interactive design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
8.2 Typical Applications
8.2.1 Buck Converter With 7-V to 60-V Input and 5-V at 3.5-A Output
PWRGD
PWRGD PULL UP
R8
7 V to 60 V
C11
U1
TP10
TP9
1.00k
2
1
2
3
5
4
7
10
1
VIN
VIN
PWRGD
BOOT
SW
C4
TP1
TP2
GND
L1
EN
+
5 V @ 3.5A
R1
442k
C10
DNP
2.2µF
C3
DNP
2.2µF
C1
2.2µF
C2
2.2µF
0.1µF
DNP
9
1
2
J2
VOUT
GND
RT/CLK
SS/TR
COMP
TP5
TP6
TP4
TP7
TP8
7447797820
8.2µH
SS/TR
C13
6
FB
FB
R3
162k
R7
49.9
8
J1
GND
PAD
D1
PDS560-13
+
C12
GND
C9
C7 DNP
DNP
C6
47µF
R4
13.0k
TPS54361DPR
47µF
47µF
GND
0.01µF
1
C8
39pF
2
1
GND
GND
J4
R5
53.6k
C5
6800pF
R2
90.9k
2
1
EN
GND
FB
GND
GND
J3
R6
10.2k
TP3
GND
GND
SS/TR
GND
2
1
SS/TR
GND
J5
Copyright © 2017, Texas Instruments Incorporated
Figure 46. 5-V Output TPS54361 Design Example
8.2.1.1 Design Requirements
A few parameters must be known in order to start the design process. These requirements are typically
determined at the system level. This example is designed to the known parameters in Table 1:
Table 1. Design Parameters
DESIGN PARAMETER
Output Voltage
EXAMPLE VALUE
5 V
ΔVOUT = ±4 %
3.5 A
Transient Response 0.875-A to 2.625-A Load Step
Maximum Output Current
Input Voltage
12 V nominal 7 V to 60 V
0.5% of VOUT
6.5 V
Output Voltage Ripple
Start Input Voltage (rising VIN)
Stop Input Voltage (falling VIN)
5 V
28
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TPS54361
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54361-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
–
–
–
–
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand the thermal performance of your board
Export your customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because the highest switching frequency produces the smallest solution size. High
switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum ON-
time of the internal power switch, the input voltage, the output voltage, and the frequency foldback protection.
Equation 12 and Equation 13 must be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 100 ns for the TPS54361. For this example, the output voltage is 5 V and
the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 960 kHz to avoid pulse
skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits use Equation 13
to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage
of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 25 mΩ, switch resistance of 89 mΩ, a current
limit value of 4.7 A, and short-circuit output voltage of 0.1 V, the maximum switching frequency is 1220 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 46. For 600-kHz operation, the closest
standard value resistor is 162 kΩ.
1
3.5 A ´ 25 mW + 5 V + 0.7 V
60 V – 3.5 A ´ 87 mW + 0.7 V
æ
ö
ƒSW(maxskip)
=
´
= 710 kHz
ç
÷
135 ns
è
ø
(28)
(29)
(30)
8
4.7 A ´ 25 mW + 0.1 V + 0.7 V
60 V – 4.7 A ´ 87 mW + 0.7 V
æ
ö
ƒSW(shift)
=
´
= 902 kHz
ç
÷
135 ns
è
ø
101756
600 (kHz)1.008
RT (kW) =
= 161 kW
8.2.1.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer, however, the following guidelines may be used.
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TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current must always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, choosing a relatively large inductor ripple current is
best to provide sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 7.3 μH. The nearest
standard value is 8.2 μH. The RMS current and saturation current ratings of the inductor must not be exceeded.
The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design, the RMS
inductor current is 3.5 A and the peak inductor current is 3.97 A. The chosen inductor is a WE 7447797820,
which has a saturation current rating of 5.8 A and an RMS current rating of 5.05 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54361 which is nominally 5.5 A.
V
- VOUT
IN max
(
VOUT
)
60 V – 5 V
5 V
LO min
=
´
=
´
= 7.3 µH
(
)
I
OUT ´ KIND
V
´ ƒSW 3.5 A ´ 0.3
60 V ´ 600 kHz
IN max
(
)
(31)
(32)
spacer
IRIPPLE
V
OUT ´ (V
- VOUT )
IN max
(
)
5 V ´ (60 V – 5 V)
=
=
= 0.932 A
V
´ LO ´ ƒSW
60 V ´ 8.2 µH ´ 600 kHz
IN max
(
)
spacer
2
æ
ö
2
V
´ V
- V
OUT
(
OUT
)
æ
ç
ç
è
ö
÷
÷
ø
IN max
(
5 V ´ 60 V – 5 V
)
(
)
1
ç
ç
÷
1
2
)
2
)
I
=
I
(
+
´
=
3.5 A
(
+
´
= 3.5 A
OUT
÷
L rms
(
)
12
V
´ L ´ ƒ
12
60 V ´ 8.2 µH ´ 600 kHz
O
SW
IN max
(
)
ç
÷
è
ø
(33)
spacer
IL peak = IOUT
IRIPPLE
0.932 A
2
+
= 3.5 A +
= 3.97 A
(
)
2
(34)
8.2.1.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency, and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A – 0.875 A = 1.75 A and ΔVOUT = 0.04 × 5 = 0.2 V. Using these numbers gives a
minimum capacitance of 29.2 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
30
Copyright © 2013–2017, Texas Instruments Incorporated
TPS54361
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ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 47. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 36
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and Vi is the initial voltage. For this example, the worst-case load step is from 2.625 A to
0.875 A. The output voltage increases during this load transition and the stated maximum in our specification is
4 % of the output voltage which makes Vf = 1.04 × 5 = 5.2. Vi is the initial capacitor voltage which is the nominal
output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of 25 μF.
Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 37 yields 7.8 μF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR must be less than 27 mΩ.
The most stringent criteria for the output capacitor is 29 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, two
47-μF, 10-V ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 58 µF, well above the
minimum required capacitance of 29 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 39 yields 269 mA.
2´ DI
2 ´ 1.75 A
OUT
C
>
=
= 29.2 mF
OUT
f
´ DV
600 kHz x 0.2 V
SW
OUT
(35)
2
(OH ) (OL )
2
2.625 A2 - 0.875 A2
I
-
I
(
)
(
)
= 24.6 mF
COUT > LO
x
= 8.2 mH x
2
2
5.2 V2 - 5 V2
V
-
V
I
( ) ( )
(
)
f
(
)
(36)
1
1
1
1
C
>
´
=
x
= 7.8 mF
OUT
8´ f
8 x 600 kHz
25 mV
0.932 A
æ
ç
è
ö
÷
ø
æ
ö
V
SW
ORIPPLE
ç
è
÷
ø
I
RIPPLE
25 mV
0.932 A
(37)
(38)
V
ORIPPLE
R
<
=
= 27 mW
ESR
I
RIPPLE
V
´ V
(
IN max
(
- V
OUT
OUT
)
=
IN max
(
5 V ´ 60 V - 5 V
)
(
)
12 ´ 60 V ´ 8.2 mH ´ 600 kHz
I
=
= 269 mA
COUT(rms)
12 ´ V
´L ´ f
O
SW
)
(39)
8.2.1.2.5 Catch Diode
The TPS54361 requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54361.
For the example design, the PDS560 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the PDS560 is 0.55 V at 3.5 A.
Copyright © 2013–2017, Texas Instruments Incorporated
31
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The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the OFF-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is
used to calculate the total power dissipation, including conduction losses and AC losses of the diode.
The PDS560 diode has a junction capacitance of 90 pF. Using Equation 40, the total loss in the diode is 1.13 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
)
V
(
- V
´ I
´ Vf d
OUT
)
IN max
OUT
C ´ f
´ V + Vf d
(
2
IN max
(
)
j
SW
IN
P =
+
=
D
V
(
)
2
12 V - 5 V ´ 3.5 A x 0.55 V
)
(
90 pF x 600 kHz x (12 V + 0.55 V)
+
= 1.13 W
12 V
2
(40)
8.2.1.2.6 Input Capacitor
The TPS54361 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54361. The input ripple current can be calculated using Equation 41.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V, or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 42. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒsw = 600 kHz,
yields an input voltage ripple of 331 mV and a RMS input ripple current of 1.72 A.
V
- V
OUT
)
= 3.5 A
(
IN min
(
8.5 V - 5 V
)
V
(
)
5 V
OUT
I
= I
x
x
´
= 1.72 A
OUT
CI rms
(
)
V
V
8.5 V
8.5 V
IN min
(
IN min
(
)
)
(41)
(42)
I
´ 0.25
3.5 A ´ 0.25
OUT
DV
=
=
= 331 mV
IN
C
´ f
4.4 mF ´ 600 kHz
IN
SW
32
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TPS54361
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Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
1 to 4.7
1
EIA Size
VOLTAGE (V)
DIALECTRIC
COMMENTS
100
50
1210
GRM32 series
Murata
100
50
1206
2220
2225
1812
1210
1210
1812
GRM31 series
VJ X7R series
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
50
100
50
Vishay
TDK
100
100
50
X7R
C series C4532
C series C3225
100
50
50
100
50
AVX
X7R dielectric series
1 to 4.7
1 to 2.2
100
8.2.1.2.7 Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time required for the output voltage to reach its
nominal programmed value during power-up. This feature of the soft-start capacitor is useful if a load requires a
controlled voltage slew rate. This feature is also used if the output capacitance is large and would require large
amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to
charge the capacitor can make the TPS54361 device reach the current limit or excessive current draw from the
input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of
these problems.
The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 43 can be used to find the minimum soft-start time, TSS
,
necessary to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average
soft-start current of ISSavg. In the example, to charge the effective output capacitance of 58 µF up to 5 V with an
average current of 1 A requires a 0.2-ms soft-start time.
Once the soft-start time is known, the soft-start capacitor value can be calculated using Equation 5. For the
example circuit, the soft-start time is not too critical because the output capacitor value is 2 × 47 μF which does
not require much current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of
3.5 ms which requires a 9.3-nF soft start capacitor calculated by Equation 44. For this design, the next larger
standard value of 10 nF is used.
COUT ´ VOUT ´ 0.8
>
ISSavg
TSS
(43)
(44)
TSS (ms) ´ ISS (µA)
VREF (V) ´ 0.8
3.5 ms ´ 1.7 µA
0.8 V ´ 0.8
CSS (nF) =
=
= 9.3 nF
(
)
8.2.1.2.8 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10-V or higher voltage
rating.
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8.2.1.2.9 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54361 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply must turn on and
start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
must continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor-divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the
example application, a 442 kΩ between VIN and EN (RUVLO1) and a 90.9 kΩ between EN and ground (RUVLO2) are
required to produce the 6.5-V and 5-V start and stop voltages.
(45)
V
1.2 V
6.5 V - 1.2 V
442 kW
ENA
R
=
=
= 90.9 kW
UVLO2
V
- V
ENA
START
+1.2 mA
+ I
1
R
UVLO1
(46)
8.2.1.2.10 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the
output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
VOUT - 0.8 V
5 V - 0.8 V
æ
ö
RHS = RLS
x
= 10.2 kW x
= 53.5 kW
ç
÷
0.8 V
0.8 V
è
ø
(47)
8.2.1.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least ten-times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 48 and
Equation 49. For COUT, use a derated value of 58.3 μF. Use equations Equation 50 and Equation 51 to estimate
a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1912 Hz and ƒz(mod) is 1092
kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of
modulator pole and the switching frequency. Equation 50 yields 45.7 kHz and Equation 51 gives 23.9 kHz. Use
the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒco
is 23.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT max
(
)
3.5 A
fP mod
=
=
2´ p´ VOUT ´ COUT 2 ´ p ´ 5 V ´ 58.3 mF
= 1912 Hz
(
)
(48)
1
1
f
=
=
= 1092 kHz
Z mod
(
)
2´ p´R
´ C
2 ´ p ´ 2.5 mW ´ 58.3 mF
ESR
OUT
(49)
(50)
f
=
f
f
=
1912 Hz x 1092 kHz = 45.7 kHz
co
p(mod) x z(mod)
f
600 kHz
SW
f
=
f
=
1912 Hz x
= 23.9 kHz
co
p(mod) x
2
2
(51)
34
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To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gmps,
is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5 V, 0.8 V,
and 350 μS, respectively. R4 is calculated to be 13 kΩ, which is a standard value. Use Equation 53 to set the
compensation zero to the modulator pole frequency. Equation 53 yields 6404 pF for compensating capacitor C5.
6800 pF is used for this design.
æ
ö
æ
ç
è
ö
÷
ø
2 ´ p ´ ƒ ´ C
V
OUT
æ
ç
è
ö
÷
ø
2 ´ p ´ 23.9 kHz ´ 58.3 µF
5 V
æ
ö
co
OUT
R4 = ç
÷ ´
=
´
= 13 kW
ç
÷
ç
è
÷
ø
gm
V
x gm
12 A / V
0.8 V ´ 350 µA / V
è
ø
ps
REF
ea
(52)
1
1
C5 =
=
= 6404 pF
2´ p´R4 x f
2´ p´13 kW x 1912 Hz
p(mod)
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the
compensation pole. The selected value of C8 is 39 pF for this design example.
C
x R
ESR
58.3 mF x 2.5 mW
OUT
C8 =
=
= 11.2 pF
R4
13 kW
(54)
(55)
1
1
C8 =
=
= 40.8 pF
R4 ´ ƒ
´ p
13 kW ´ 600 kHz ´ p
sw
8.2.1.2.12 Power Dissipation Estimate
The following formulas show how to estimate the TPS54361 power dissipation under continuous conduction
mode (CCM) operation. These equations must not be used if the device is operating in discontinuous conduction
mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD), and
supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.
æ
ç
è
ö
÷
ø
V
5 V
2
2
OUT
P
= I
´R
´
= 3.5 A ´ 87 mW ´
= 0.444 W
(
)
COND
OUT
DS on
( )
V
12 V
IN
(56)
(57)
(58)
spacer
P
= V ´ f
´I
´ t
= 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
rise
SW
IN
SW
OUT
spacer
P
= V ´ Q ´ f
= 12 V ´ 3nC´ 600 kHz = 0.022 W
SW
GD
IN
G
spacer
P
= V ´ I = 12 V ´ 146 mA = 0.0018 W
IN Q
Q
where
•
•
•
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the ON-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
ƒSW is the switching frequency (Hz)
trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
(59)
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Therefore,
P
= P
+ P
+ P + P = 0.444 W + 0.123 W + 0.022 W + 0.0018 W = 0.591 W
TOT
COND
SW GD Q
(60)
(61)
For given TA,
T = T + R ´P
TOT
J
A
TH
For given TJ(MAX) = 150°C
TA max = TJ max - RTH ´PTOT
(
)
(
)
where
•
•
•
•
•
•
PTOT is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance from junction to ambient for a given PCB layout (°C/W)
TJ(MAX) is maximum junction temperature (°C)
TA(MAX) is maximum ambient temperature (°C)
(62)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,
and PCB trace resistance impacting the overall efficiency of the regulator.
8.2.1.2.13 Discontinuous Conduction Mode and Eco-Mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 300 mA. The power supply enters Eco-mode when the output current is lower than 24 mA. The input
current draw is 260 μA with no load.
8.2.1.3 Application Curves
V
IN
C4: I
OUT
C4
C3: V
OUT
ac coupled
C3
VOUT -5 V offset
Time = 5 ms/div
Time = 100 ms/div
Figure 47. Load Transient
Figure 48. Line Transient (8 V to 40 V)
36
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C1: V
IN
C1: EN
C1
C2
C1
C2
C2: SS/TR
C2: EN
C3: V
OUT
C3: V
OUT
C4: PGOOD
C3
C4
C3
Time = 2 ms/div
Time = 2 ms/div
Figure 49. Start-Up With VIN
Figure 50. Start-Up With EN
C1: SW
C1: SW
C1
C1
C4
C4: I
C4: I
L
L
I
= 3.5 A
I
= 100 mA
OUT
OUT
C3: V
OUT
ac coupled
C3: V
OUT
ac coupled
C3
C3
C4
Time = 2 ms/div
Time = 2 ms/div
Figure 51. Output Ripple CCM
Figure 52. Output Ripple DCM
C1: SW
C1: SW
C1
C4
C3
C1
C4: I
L
C4: I
L
I
= 3.5 A
OUT
C3: V
ac coupled
C3: V
IN
ac coupled
OUT
C3
C4
No Load
Time = 2 ms/div
Time = 2 ms/div
Figure 53. Output Ripple PSM
Figure 54. Input Ripple CCM
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C1: SW
C1: SW
C1
C4: I
L
C4
C4
C3
C4: I
L
I
OUT
= 100 mA
C3: V
ac coupled
IN
C3
C3: V
ac coupled
OUT
V
V
= 5.5 V
= 5 V
IN
No Load
EN Floating
OUT
Time = 2 ms/div
Figure 55. Input Ripple DCM
Time = 20 ms/div
Figure 56. Low-Dropout Operation
I
= 100 mA
I
= 1 A
OUT
EN Floating
OUT
EN Floating
V
V
IN
IN
V
V
OUT
OUT
Time = 40 ms/div
Figure 57. Low-Dropout Operation
Time = 40 ms/div
Figure 58. Low-Dropout Operation
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5 V, fsw = 600 kHz
VOUT = 5 V, fsw = 600 kHz
VIN = 12 V VIN = 24 V
VIN = 24 V
VIN = 7 V
VIN = 7 V
VIN = 12 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
0.001
0
0.5
1
1.5
2
2.5
3
3.5
0.01
0.10
1.00
C024
C024
IO - Output Current (A)
IO - Output Current (A)
Figure 59. Efficiency Versus Load Current
Figure 60. Light-Load Efficiency
38
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TPS54361
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ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
10
0
VIN = 6 V
VIN = 12 V
VIN =24V
VIN =36V
VIN = 48 V
VOUT = 3.3 V, fsw = 600 kHz
VIN = 12 V
VIN = 6 V
VIN = 24 V
VOUT = 3.3 V, fsw = 600 kHz
VIN = 48 V
VIN = 36 V
VIN = 60 V
60V
VIN = 60 V
60
0
0.001
0.5
1
1.5
2
2.5
3
3.5
0.01
0.10
1.00
C024
C024
IO - Output Current (A)
IO - Output Current (A)
Figure 61. Efficiency Versus Load Current
Figure 62. Light-Load Efficiency
0.10
60
40
180
0.08
0.06
Phase
120
60
Gain
0.04
20
0.02
0
0
0.00
œ0.02
œ0.04
œ0.06
œ0.08
œ0.10
œ20
œ40
œ60
œ120
œ180
ëLb = 12 ë, ëhÜÇ = 5 ë, LhÜÇ = 3.5 !, f{í = 600
VIN = 12 V, VOUT = 5 V, fsw = 600 kHz
œ60
10
100
1k
10k
100k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
C053
Frequency (Hz)
C024
IO - Output Current (A)
Figure 63. Overall Loop-Frequency Response
Figure 64. Regulation Versus Load Current
0.10
0.08
0.06
0.04
0.02
0.00
œ0.02
œ0.04
œ0.06
œ0.08
VOUT = 5 V, IOUT = 1.75 A, fsw = 600 kHz
œ0.10
0
10
20
30
40
50
60
C024
VI - Input Voltage (V)
Figure 65. Regulation Versus Input Voltage
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8.2.2 Inverting Power Supply
The TPS54361 can be used to convert a positive input voltage to a negative output voltage. Example
applications are amplifiers requiring a negative power supply. For a more detailed example, see SLVA317.
VIN
+
Cin
Cboot
Lo
PH
GND
BOOT
VIN
Cd
R1
R2
+
GND
Co
TPS54361
VOUT
VSENSE
EN
COMP
SS/TR
Rcomp
Czero Cpole
RT/CLK
Css
RT
Copyright © 2017, Texas Instruments Incorporated
Figure 66. TPS54361 Inverting Power Supply Based on the Application Note, SLVA317
8.2.3 Split-Rail Power Supply
The TPS54361 can be used to convert a positive input voltage to a split-rail positive and negative output voltage
by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negative
voltage power supply. For a more detailed example, see SLVA369.
VOPOS
+
Copos
VIN
+
Cin
Cboot
PH
GND
BOOT
VIN
GND
Lo
Cd
R1
R2
+
Coneg
TPS54361
VONEG
VSENSE
EN
COMP
SS/TR
Rcomp
RT/CLK
Czero Cpole
Css
RT
Copyright © 2017, Texas Instruments Incorporated
Figure 67. TPS54361 Split Rail Power Supply Based on the Application Note, SLVA369
40
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 60 V. This input supply must
remain within this range. If the input supply is located more than a few inches from the TPS54361 converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 68 for a PCB layout example.
•
To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
•
Care must be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and
the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the
output inductor. Since the SW connection is the switching node, the catch diode and output inductor should
be located close to the SW pin, and the area of the PCB conductor minimized to prevent excessive capacitive
coupling.
•
The GND pin should be tied directly to the thermal pad under the IC. The thermal pad should be connected to
internal PCB ground planes using multiple vias directly under the IC.
•
•
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
•
•
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
10.2 Layout Example
VOUT
Output
Capacitor
Output
Inductor
Topside
Ground
Area
Route Boot Capacitor
Catch
Diode
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
VIN
PWRGD
VIN
SW
EN
GND
UVLO
SS/TR
COMP
FB
Adjust
Resistors
RT/CLK
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Soft-Start
Frequency
Capacitor
Set Resistor
Figure 68. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of Figure 46, the estimated printed circuit board surface area is 1.025 in2
(661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be
done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.
42
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11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
有关 TPS54360、TPS54361 和 TPS54361-Q1 系列 Excel 设计工具的信息，请参见 SLVC452。
如需了解 WEBENCH Design Center，请访问 www.ti.com/WEBENCH.
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
《使用降压稳压器创建反向电源》，SLVA317
《使用宽范围输入电压降压稳压器创建分离轨电源》，SLVA369
《针对 TPS54361 降压转换器的评估模块》，SLVU992
《利用 TPS54240 和 TPS2511 制作供 USB 设备使用的通用车载充电器》，SLVA464
《基于 TPS54260 创建 GSM/GPRS 电源》，SLVA412
11.2.2 《使用 WEBENCH® 工具定制设计方案》
请单击此处，借助 WEBENCH®Power Designer 并使用 TPS54361-Q1 器件定制设计方案。
1. 首先输入您的 VIN、VOUT 和 IOUT 要求。
2. 使用优化器拨盘可优化效率、封装和成本等关键设计参数并将您的设计与德州仪器 (TI) 的其他可行解决方案进
行比较。
3. WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
4. 在多数情况下，您还可以：
–
–
–
–
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
5. 有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.3 接收文档更新通知
要接收文档更新通知，请访问 www.ti.com.cn 您器件对应的产品文件夹。点击右上角的提醒我 (Alert me) 注册后，
即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档的修订历史记录
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
版权 © 2013–2017, Texas Instruments Incorporated
43
TPS54361
ZHCSBZ0D –NOVEMBER 2013–REVISED JANUARY 2017
www.ti.com.cn
11.5 商标
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
下列封装信息和附录反映了针对指定器件可提供的最新数据。这些数据会在无通知且不对本文档进行修订的情况下
发生改变。
44
版权 © 2013–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54361DPRR
TPS54361DPRT
ACTIVE
WSON
WSON
DPR
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TPS
54361
ACTIVE
DPR
NIPDAU
TPS
54361
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54361DPRR
TPS54361DPRT
WSON
WSON
DPR
DPR
10
10
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54361DPRR
TPS54361DPRT
WSON
WSON
DPR
DPR
10
10
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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