TPS543B22 [TI]
具有 4V 至 18V 输入和高级电流模式的 20A 同步 SWIFT™ 降压转换器;
| 型号： | TPS543B22 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4V 至 18V 输入和高级电流模式的 20A 同步 SWIFT™ 降压转换器 转换器 |
| 文件： | 总41页 (文件大小：2111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS543B22
ZHCSM43A –AUGUST 2022 –REVISED DECEMBER 2022
TPS543B22 具有内部补偿高级电流模式控制功能的4V 至18V 输入、20A 同步
SWIFT™ 降压转换器
1 特性
2 应用
• 固定频率、内部补偿高级电流模式(ACM) 控制
• 集成式6.5mΩ和2mΩMOSFET
• 4V 至18V 输入电压范围
• 无线和有线通信基础设施设备
• 光纤网络
• 测试和测量
• 医疗和保健
• 0.5V 至7V 输出电压范围
• 真差分遥感放大器(RSA)
3 说明
• 三种可选的PWM 斜坡选项，可优化控制环路性能
• 五种可选的开关频率：500kHz、750kHz、1MHz、
1.5MHz 和2.2MHz
TPS543B22 是一款高效率 18V、20A 同步降压转换
器，采用内部补偿的定频高级电流模式 (ACM) 控制架
构，可在处于 FCCM 模式长期运行的同时，产生 0.5V
至 7V 的输出电压。该器件可提供高效率，且运行时的
开关频率高达 2.2MHz，从而适用于需要小巧解决方案
尺寸的设计。固定频率控制器可以在 500kHz 至
2.2MHz 范围内运行，并且可以通过 SYNC 引脚与外
部时钟同步。其他功能包括高精度电压基准、双线遥
感、可选软启动时间、单调启动至预偏置输出、可选电
流限制、可调UVLO（通过EN 引脚实现）以及全套故
障保护。
• 与一个外部时钟同步
• 0.5V，整个温度范围内的电压基准精度为±0.5%
• 可选的软启动时间：1ms、2ms、4ms 和8ms
• 单调启动至预偏置输出
• 可选的电流限制，支持20A 和16A 运行
• 具有可调节输入欠压锁定功能的使能端
• 电源正常输出监视器
• 输出过压、输出欠压、输入欠压、过流和过热保护
• –40°C 至150°C 的工作结温范围
• 2.5mm × 4.5mm、17 引脚WQFN-HR 封装，间距
为0.5mm
TPS543B22 可采用小尺寸 2.5mm × 4.5mm HotRod™
WQFN-FCRLF 封装。
• 无铅（符合RoHS 标准）
封装信息
封装(1)
• 与以下器件引脚兼容： TPS543A26 and
封装尺寸（标称值）
器件型号
TPS543A22
RYS（WQFN-FCRLF，
17）
• 可提供PSpice 和SIMPLIS 模型
TPS543B22
2.50mm x 4.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
95
VIN
VIN
BOOT
SW
CBOOT
VDRV
VCC
CIN
2.2 μF
L
10 Ω
VOUT
0.1 μF
RFBT
90
COUT
FB
PGND
AGND
RFBB
85
SYNC/FSEL
MSEL
PGND
GOSNS
PGND
80
AGND
VOUT = 0.8 V, 1 MHz
RFSEL
RMSEL
VOUT = 1.0 V, 1 MHz
VOUT = 1.2 V, 1 MHz
VOUT = 1.8 V, 1 MHz
VOUT = 3.3 V, 1 MHz
75
VIN = 12V
220nH 0.39m
PGND
AGND
TPS543B22 简化应用
70
0
5 10
15 20
Output Current (A)
典型应用效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFW2
TPS543B22
ZHCSM43A –AUGUST 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
8.3 Power Supply Recommendations.............................33
8.4 Layout....................................................................... 33
9 Device and Documentation Support............................36
9.1 接收文档更新通知..................................................... 36
9.2 支持资源....................................................................36
9.3 Trademarks...............................................................36
9.4 Electrostatic Discharge Caution................................36
9.5 术语表....................................................................... 36
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
Information.................................................................... 36
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August 2022) to Revision A (December 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
• 首次公开发布...................................................................................................................................................... 1
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5 Pin Configuration and Functions
13
13
14
14
15
15
12
PG 11
EN 10
1
2
1
2
12
11 PG
10 EN
SYNC/FSEL
AGND
VCC
AGND
VCC
SYNC/FSEL
16
PGND
16
PGND
3
VDRV
VDRV
3
17
PGND
17
PGND
4
4
VIN
VIN
VIN
VIN
9
8
9
8
PGND
5
5
PGND
PGND
PGND
BOOT
BOOT
7
SW
SW
7
6
6
Not to scale
Not to scale
图5-1. 17-Pin WQFN-FCRLF RYS Package (Bottom
图5-2. 17-Pin WQFN-FCRLF RYS Package
View)
(Top View)
表5-1. Pin Functions
Pin
Type(1)
Description
Name
No.
AGND
1
Ground return for internal analog circuits
—
Supply for analog control circuitry. Connect a 10-Ω resistor from VDRV to this pin and bypass
with a 0.1-μF capacitor to AGND.
VCC
2
3
I
Internal 5-V regulator output and internal connection to drivers. Bypass these pins with a 2.2-μF
capacitor to PGND. See 节7.3.2.
VDRV
VIN
O
I
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A
1-μF capacitor from each VIN to PGND close to the IC is required.
4, 9
5, 8, 16,
17
Ground return for the power stage. This pin is internally connected to the source of the low-side
MOSFET.
PGND
—
SW
6
7
O
I
Switch node of the converter. Connect this pin to the output inductor.
BOOT
Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to SW.
Enable pin. Float or tie high to enable, or enable and disable with an external signal, or adjust
the input undervoltage lockout with a resistor divider. See 节7.3.3.
EN
PG
10
11
I
O
Open-drain power-good indicator. See 节7.3.10.
Frequency select and external clock synchronization. A resistor to ground sets the switching
frequency of the device. An external clock can also be applied to this pin to synchronize the
switching frequency. See 节7.3.5.3.
SYNC/FSEL
12
I
A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude. See 节
7.3.9.
MSEL
GOSNS
FB
13
14
15
I
I
I
Ground sense return and input to the differential remote sense amplifier
Feedback pin and input to the differential remote sense amplifier for output voltage regulation.
Connect this pin to the midpoint of a resistor divider to set the output voltage. See 节7.3.6.
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.3
–0.3
–5
MAX
20
20
22
20
25
25
6
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Sink current
TJ
VIN
SW, DC
V
SW, transient 20ns
VIN to SW, DC
VIN to SW, transient 20ns
BOOT
V
V
–0.3
–6
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
BOOT to SW
V
EN, PG, MSEL, SYNC/FSEL, FB
VCC, VDRV
6
V
6
V
GOSNS
0.3
5
V
PG
mA
°C
°C
Operating junction temperature
150
150
–40
–55
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to PGND.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
±2000
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
4
NOM
MAX
18
UNIT
V
VIN
Pin voltage
Input voltage range
VOUT
Output voltage range
Pin voltage
0.5
7
V
SW - PGND
18
V
–0.1
–0.1
–0.3
Pin voltage
EN, FB, PG, MSEL, SYNC/FSEL
GOSNS
5.5
0.3
20
V
Pin voltage
V
IOUT
IPG
TJ
Output current range
Power Good input current
Operating junction temperature
A
2
5
mA
°C
Operating junction temperature
150
–40
6.4 Thermal Information
RYS (QFN, JEDEC)
RYS (QFN, TI EVM)
17 PINS
THERMAL METRIC(1)
UNIT
17 PINS
33.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18.6
°C/W
°C/W
°C/W
RθJC(top)
RθJB
10.6
Not applicable (2)
Not applicable (2)
5.5
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6.4 Thermal Information (continued)
RYS (QFN, JEDEC)
RYS (QFN, TI EVM)
THERMAL METRIC(1)
UNIT
17 PINS
0.8
17 PINS
1.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ψJT
5.5
6.6
ψJB
RθJC(bot)
5.9
Not applicable
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM layout.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1
MHz
IQ(VIN)
VIN operating non-switching supply current
1200
1600
µA
ISD(VIN)
VIN shutdown supply current
VIN UVLO rising threshold
VIN UVLO hysteresis
VEN = 0 V, VVIN = 12 V
VIN rising
20
4.00
150
32
µA
V
VINUVLO(R)
VINUVLO(H)
INTERNAL LDO
VVDRV
3.8
4.2
mV
Internal linear regulator output voltage
Internal linear regulator dropout voltage
VVIN = 12 V, IVDRV = 25 mA
4.5
V
390
mV
V
VIN –VVDRV, VVIN = 3.8 V, IVDRV = 25 mA
Internal linear regulator short-circuit current
limit
VVIN = 12 V
150
mA
VCCUVLO(R)
VCCUVLO(H)
ENABLE
VEN(R)
VCC UVLO rising threshold
VCC UVLO hysteresis
3.4
0.4
V
V
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
EN rising, enable switching
EN falling, disable switching
1.2
1.1
1.25
V
V
VEN(F)
1.05
VEN(H)
100
1.75
11.6
1
mV
µA
µA
ms
EN pin sourcing current
VEN = 1.1 V
EN pin sourcing current
VEN = 1.3 V
EN HIGH to start of switching delay (1)
EN from 0V to 3V rising
REFERENCE VOLTAGE
VFB
Feedback Voltage
Input leakage current into FB pin
497.5
500
3
502.5
mV
nA
TJ = –40°C to 150°C
VFB = 500 mV, non-switching, VVIN = 12 V,
VEN = 0 V
IFB(LKG)
REMOTE SENSE AMPLIFIER
ILEAK(GOSNS) Current out of GOSNS pin
85
90
95
µA
GOSNS common mode voltage for
regulation
VIRNG(GOSNS)
AGND +/- VGOSNS
100
mV
–100
SWITCHING FREQUENCY AND OSCILLATOR
fSW
Switching frequency
Switching frequency
Switching frequency
Switching frequency
Switching frequency
450
675
500
750
550
825
kHz
kHz
kHz
kHz
kHz
RFSEL = 24.3 kΩto AGND
RFSEL = 17.4 kΩto AGND
RFSEL = 11.8 kΩto AGND
RFSEL = 8.06 kΩto AGND
RFSEL = 4.99 kΩto AGND
fSW
fSW
900
1000
1500
2200
1100
1650
2420
fSW
1350
1980
fSW
SYNCHRONIZATION
VIH(sync)
High-level input voltage
Low-level input voltage
1.8
V
V
VIL(sync)
0.8
Frequency synchronization range to not
adversly affect loop stability. (1)
FCLK
20%
+
FCLK
20%
–
FSYNC(range)
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT-START
tSS1
Soft-start time 0 to 100% VOUT
Soft-start time 0 to 100% VOUT
Soft-start time 0 to 100% VOUT
Soft-start time 0 to 100% VOUT
1
2
4
8
ms
ms
ms
ms
RMSEL = 2.1 kΩ
RMSEL = 2.49 kΩ
RMSEL = 2.94 kΩ
RMSEL = 3.57 kΩ
tSS2
tSS3
tSS4
POWER STAGE
RDS(on)HS
RDS(on)LS
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V
TJ = 25°C, VVDRV = 4.5 V
6.5
2.0
mΩ
mΩ
TJ = 25°C. Weaken high-side gate drive
upon VIN rising
VVIN(TH_r)
VVIN(TH_f)
VIN throttle rising threshold
VIN throttle falling threshold
16
V
V
TJ = 25°C. Recover high-side gate drive
upon VIN falling
15.5
VBOOT-SW(UV_R)
VBOOT-SW(UV_F)
TON(min)
BOOT-SW UVLO rising threshold
BOOT-SW UVLO falling threshold
Minimum ON pulse width
VBOOT-SW rising
VBOOT-SW falling
3.2
2.8
22
V
V
28
ns
ns
TOFF(min)
Minimum OFF pulse width (1)
115
CURRENT SENSE AND OVERCURRENT PROTECTION
IHS(OC1)
IHS(OC2)
ILS(OC1)
ILS(OC2)
ILS(NOC)
High-side peak current limit
Low-side valley current limit
Low-side negative current limit
26.1
20.7
21.15
16.74
7
29
23
31.9
25.3
A
A
A
A
A
RMSEL = 2.1 kΩ
RMSEL = 22.1 kΩ
RMSEL = 2.1 kΩ
RMSEL = 22.1 kΩ
Current into SW pin
23.5
18.6
25.85
20.46
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
Overvoltage-protection (OVP) threshold
voltage
VOVP
VFB rising
VFB falling
120%
80%
VREF
VREF
Undervoltage-protection (UVP) threshold
voltage
VUVP
POWER GOOD
Power good threshold
Power good threshold
Power good threshold
Power good threshold
VFB rising (Good)
88%
112%
91%
115%
94%
118%
VREF
VREF
VREF
VREF
VFB rising (OV Fault)
VFB falling (Good)
VFB falling (UV Fault)
103.5%
79%
106.5%
82%
109.5%
85%
Leakage current into PG pin when open
drain output is high
IPG(LKG)
VPG = 4.7 V
5
µA
VPG(low)
PG low-level output voltage
Min VIN for valid PG output
PG delay going from low to high
PG delay going from high to low
IPG = 2 mA, VIN = 12 V
0.6
V
V
EN = 0V, PGOOD pulled up to 5V
1
201
11
us
µs
HICCUP
Hiccup time before re-start
Output discharge resistance
7*tSS
100
ms
OUTPUT DISCHARGE
VVIN = 12 V, VSW = 0.5 V, power conversion
disabled.
RDischg
Ω
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
165
12
175
°C
°C
TJ(HYS)
(1) Specified by design
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6.6 Typical Characteristics
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
V(BOOT- SW) = 4.5 V
V(VDRV) = 4.5 V
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Junction Temperature (oC)
图6-1. High-Side FET RdsON
图6-2. Low-Side FET RdsON
30
10
9
8
7
6
5
4
3
2
1
0
29
28
27
26
25
24
23
22
21
20
High Limit
Low Limit
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Junction Temperature (oC)
图6-3. Overcurrent Limit
图6-4. Negative Overcurrent Limit
0.525
0.5125
0.5
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4875
Rising
Falling
EN voltage to Switch
0.475
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
图6-6. VREF
图6-5. Enable Voltage
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6.6 Typical Characteristics
4.25
4
3.75
3.5
3.25
3
4.125
4
2.75
2.5
2.25
2
3.875
Rising
Falling
Rising
3.75
-60 -40 -20
0
20 40 60 80 100 120 140 160
Junction Temperature (oC)
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
图6-7. VIN UVLO
图6-8. VCC UVLO
图6-9. PG Threshold
图6-10. PG Leakage Current
5
4.5
4
15
14
13
12
11
10
9
1 ms
VIN = 4V
VIN = 12V
VIN = 18V
2 ms
4 ms
8 ms
3.5
3
8
7
6
2.5
2
5
4
3
1.5
1
2
1
0
-50
0.5
0
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Junction Temperature (oC)
图6-11. Enable Pin Current at Different VIN
图6-12. Soft Start
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6.6 Typical Characteristics (continued)
5
30
25
20
15
10
5
VIN = 12 V
EN = 1.3 V
FB = 550 mV
4.5
4
3.5
3
2.5
2
1.5
1
VIN = 12V
EN = 0V
0.5
0
0
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Junction Temperature (oC)
图6-13. Non-Switching Supply Current
图6-14. Shutdown Supply Current
8/31/2022
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
5
4.5
4
500 kHz
750 kHz
1000 kHz
1500 kHz
2200 kHz
3.5
3
VIN = 4 V
VIN = 12 V
VIN = 18 V
2.5
2
500
250
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
图6-16. Switching Frequency vs Temperature
图6-15. VDRV vs Temperature
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7 Detailed Description
7.1 Overview
The TPS543B22 is a 20-A, high-performance synchronous buck converter with two integrated N-channel
MOSFETs. The TPS543B22 has a maximum operating junction temperature of 150°C, making it suitable for
high-ambient temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V
and the output voltage range is 0.5 V to 7 V. The device features a fixed-frequency advanced current mode
(ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz,
allowing for efficiency and size optimization when selecting output filter components. The switching frequency of
the device can be synchronized to an external clock applied to the FSEL/SYNC pin.
Advanced current mode is an emulated peak current-mode control topology, supporting stable static and
transient operation without the requirement for a complex external compensation design. ACM includes an
internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output
capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-
noise ratio for good noise immunity. The TPS543B22 has three ramp options to optimize the internal feedback
loop for various inductor and output capacitor combinations with only a single resistor to AGND (see 节 7.3.7.2
for details). The TPS543B22 is easy to use and allows low external component count with fast load transient
response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise.
7.2 Functional Block Diagram
VDRV
VIN
VCC
VIN_UVLO
UVLO
VCC_UVLO
UVLO
CLK
SYNC/
FSEL
Linear Regulator
EN_UVLO
Oscillator
Cramp
ILIM
Pinstrap
Detect
Boot
Charge
BOOT
MSEL
VREF
Soft-Start
Control
EN_UVLO
EN
FB
UVLO
ACM
Controller
Control
Logic
SW
VDRV
Remote
Sense
OV/UV
Comparators
GOSNS
PGND
Thermal
Shutdown
Fault Logic
BOOT
SW
UVLO
HS and LS
OC_FLT
Current Sense
OC_FLT
ILIM
VIN_UVLO
VCC_UVLO
AGND
AGND
PG
7.3 Feature Description
7.3.1 VIN Pins and VIN UVLO
The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the
power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO
circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO
threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV.
A second means to enable the device is provided by interfacing to the EN pin. See 节7.3.3 for more details.
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7.3.2 Internal Linear Regulator and Bypassing
The VDRV pin is connected internally to the output of the internal (4.5 V nominal) linear regulator (LDO) and to
the MOSFET drivers. Bypass VDRV to PGND with a ceramic capacitor. A value of 2.2 μF to 10 μF is
recommended. The VCC pin is the source for the internal control circuitry. Connect a 10-Ω resistor from VDRV to
VCC and bypass VCC to AGND with a ceramic capacitor (0.1 μF recommended).
VIN
Linear
Regulator
VDRV
(LDO)
2.2 μF
To bootstrap, drivers
10
PGND
VCC
To analog, digital circuits
0.1 μF
UV
AGND
图7-1. Device Bypassing
It is not intended to drive VCC with any source other than VDRV.
It is also not intended to connect VDRV to any external source or load.
7.3.3 Enable and Adjustable UVLO
The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold
voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current
source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any
circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not
be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector
output logic can be interfaced with the pin.
Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in
图 7-2. The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function
by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can
be calculated using 方程式 1 and 方程式 2. When using the adjustable UVLO function, 500 mV or greater
hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed
from the EN pin to ground to filter any noise on the input voltage.
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Ip
Ih
VIN
EN
RENT
+
–
RENB
图7-2. Adjustable UVLO Using EN
≈
∆
«
’
÷
VENFALLING
VSTART
ì
- V
STOP
VENRISING ◊
RENT
=
≈
’
÷
VENFALLING
I ì 1-
+ I
h
∆
p
VENRISING ◊
«
(1)
(2)
RENT ì VENFALLING
RENB
=
VSTOP - VENFALLING + RENT ì I +I
p
h
7.3.3.1 Internal Sequence of Events During Startup
The enable feature of the TPS543B22 provides two-threshold-level functionality. When the EN pin voltage is less
than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When
the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the
external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO
threshold (approximately 3.6 V), the TPS543B22 reads the pin strap configuration as determined by the MSEL
pin (see 节7.3.9) and SYNC/FSEL pin (see 节7.3.5.3) settings, and then enters a standby state.
The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO
thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the
TPS543B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on
delay, the power stage is enabled and soft start begins.
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EN Upper Threshold 1.2 V
EN Lower THRESHOLD 0.8 V
EN Pin
Enable LDO
Read Pin Strap, assumes LDOOK
Initialize control circuits
Soft Start
Power ON Delay
图7-3. Internal Start-Up Sequence
If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of
the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded,
reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical).
7.3.4 Switching Frequency Selection
The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to
AGND. The frequency options and their corresponding programming resistors are listed in 表 7-1. It is required
to use a 1% tolerance resistor or better.
表7-1. Switching Frequency Selection
RFSEL Allowed Recommended Recommended
Nominal
Range (1%)
(kΩ)
E96 Standard E12 Standard
fSW (kHz)
Value (1%)
Value (1%)
(kΩ)
(kΩ)
24.3
17.4
11.8
8.06
4.99
27.0
17.8
12.1
8.25
4.75
500
750
≥24.0
17.4 –18.0
11.8 –12.1
8.06 –8.25
≤5.11
1000
1500
2200
7.3.5 Switching Frequency Synchronization to an External Clock
The TPS543B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/
FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts
up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to
AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be
within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device
starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles
with the external clock pulse present. See 节7.3.5.2.
Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the
stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization
clock is within ±20% of the frequency set by the SYNC/FSEL resistor.
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7.3.5.1 Internal PWM Oscillator Frequency
When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the
external clock is not present, the device defaults to the internal PWM oscillator frequency.
If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set
by the RFSEL resistor according to 节 7.3.5.3. The device switches at this frequency until the external clock is
applied or anytime the external clock is not present.
If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then
decodes the external clock frequency and selects an internal PWM oscillator frequency.
表7-2. Internal Oscillator Frequency Decode
External Sync Clock Frequency
(kHz)
Decoded Internal PWM
Oscillator Frequency (kHz)
500
750
400 –600
600 –857
1000
1500
2200
857 –1200
1200 –1810
1810 –2640
The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the
external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to
be decoded as either the frequency above or below that threshold. Because the internal frequency is what is
used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection
are chosen for stability for either frequency. 表 7-3 shows the tolerance range of the decode thresholds. If the
external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter
stability for both possible internal PWM oscillator frequencies.
表7-3. Frequency Decode Thresholds
Minimum (kHz)
Typical (kHz)
Maximum (kHz)
570
814
600
630
900
857
1140
1736
1200
1260
1884
1810
7.3.5.2 Loss of Synchronization
If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM
oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device
switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without
clock pulses, the device operates at the normal internal PWM oscillator frequency.
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图7-4. Clock Synchronization Transition
7.3.5.3 Interfacing the SYNC/FSEL Pin
If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is
enabled, a high impedance buffer is recommended to ensure proper detection of the RFSEL value. 图 7-5 shows
the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure
proper detection of the RFSEL value. Power the buffer from the VDRV output of the device to ensure its VCC
voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value.
When powering the buffer from the VDRV pin, the external load on the VDRV pin must be less than 2 mA.
VDRV
VCC
SYNC/FSEL
RFSEL
GND
图7-5. Interfacing the SYNC/FSEL Pin with a Buffer
7.3.6 Remote Sense Amplifier and Adjusting the Output Voltage
Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation
type amplifier. Connect the output voltage setting resistive divider described below from the output voltage
sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be
tied to the converter output voltage return at a location near to the load.
The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as
shown in 图7-6. Use 1% tolerance or better divider resistors.
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VOUT
RFBT
FB
–
–
E/A
+
RSA
+
RFBB
VREF
GOSNS
VOUTRTN
图7-6. FB Resistor Divider
Starting with a fixed value for the bottom resistor, typically 10 kΩ, use 方程式3 to calculate the top resistor in the
divider.
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(3)
7.3.7 Loop Compensation Guidelines
The TPS543B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop
compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to
generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM
cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with
any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter
design are provided in the following sections.
7.3.7.1 Output Filter Inductor Tradeoffs
The selection of the output inductor is one of the most important choices to make in designing a converter. The
following is a short list of considerations to make when determining the value of the inductance used. Other
considerations are found in the 节8.
Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load.
V
− V
∆ I
V
OUT
IN
OUT
1
L =
×
×
(4)
V
f
IN
SW
• A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can
result in poor load transient response.
• The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure
that the peak valley current at full load is less than the current limit threshold by an adequate margin. A
recommended range is 60% to 80% of the current limit threshold.
• The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher
the RMS losses.
7.3.7.2 Ramp Capacitor Selection
The TPS543B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal
ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values
for CRAMP can be selected with a resistor to AGND on the MSEL pin (see 节 7.3.9). The capacitor options are 1
pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control
loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in 图
8-1.
Many applications perform best with a CRAMP value of 4 pF, however, its up to the user to measure the loop gain
and phase to determine the optimum CRAMP value for their specific application.
1. First, calculate the RAMP time constant using 方程式5 and 表7-4.
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6
C
× 10
RAMP
τ
=
(5)
CRAMP
V
OUT
Lookup1 − Lookup2 ×
V
IN
表7-4. RAMP Selection Lookup Values
fSW (kHz)
Lookup1 Value
Lookup2 Value
500
750
0.372
0.297
0.445
0.594
0.891
1.31
0.548
1000
1500
2200
0.719
1.04
1.46
2. Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a
ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load
transient.
V
×
t
+ 100 ns
ON
IN
V
=
(6)
CRAMP
τ
CRAMP
• A larger CRAMP capacitance results in highest loop gain.
• A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency.
图7-7 and 图7-8 show how the loop changes with each ramp setting for the schematic in 节8.
80
Ramp = 1pF
Ramp = 2pF
70
60
50
40
30
20
10
0
Ramp = 4pF
-10
-20
-30
-40
Vin = 12 V, Vout = 1.0 V
Iout = 20 A 1000 kHz
1000 2000 5000 10000
100000
1000000
Frequency (Hz)
图7-8. Loop Phase vs Ramp Settings
图7-7. Loop Gain vs Ramp Settings
7.3.7.3 Output Capacitor Selection
• Ensure the ESR zero frequency of the capacitors used is at lease 5× the expected crossover frequency. This
way, the impact of the ESR on the loop gain is reduced to a manageable level.
1
f
=
(7)
ESR_ZERO
2π × R
× C
ESR
• The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little
capacitance and the bandwidth can be too high to maintain stability.
• The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too
little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot
during a sharp load decrease.
• The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the
output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or
both) can result in output ripple above system requirements.
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1
V
= ∆ I × R
+
(8)
RIPPLE
ESR
2π × f
× C
SW
7.3.7.4 Design Method for Good Transient Response
The following method to design converter compensation optimizes the load transient response.
1. Calculate the require output impedance to meet transient response goals. This equation assumes the load
step transient is faster than the BW of the converter.
delta_V
OUT
Z
=
(9)
OUT_REQUIRED
delta_I
OUT
2. Select a value for output inductance.
V
− V
∆ I
V
OUT
IN
OUT
1
L =
×
×
(10)
V
f
IN
SW
3. Calculate the required converter output impedance to meet the transient response goal.
L
0.00135 +
τ
V
OUT
CRAMP
Z
=
×
(11)
OUT_CONVERTER
34
V
REF
Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP
is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value.
4. Calculate the minimum output capacitance required to meet the impedance requirements.
1
C
=
(12)
OUT_MIN
2π × Z
× f
CO_DESIRED
OUT_CONVERTER
where
• fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the
converter switching frequency.
5. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to
select a capacitor type and value, then use the equation here to find the number of capacitors required.
Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen
crossover frequency) is used.
1
Z
= R
+
(13)
CAPACITOR
ESR_CAPACITOR
2π × C
× F
CO
CAPACITOR
Z
CAPACITOR
N
=
(14)
CAPACITORS
Z
OUT_CONVERTER
6. Using one of the tools on TI.com, simulate with the values for the design.
7.3.8 Soft Start and Prebiased Output Start-Up
During start-up, the device softly increases the reference voltage from zero to its final value, thereby reducing
converter inrush current. There are four options for the soft-start time, which is the time it takes for the reference
to ramp to 0.5 V:
• 1 ms
• 2 ms
• 4 ms
• 8 ms
The soft-start time is selected with a resistor to AGND on the MSEL pin. See 节7.3.9.
If a prebiased output condition exists prior to start-up, the device prevents current from being discharged from
the output. During monotonic prebiased start-up, the low-side MOSFET is not allowed to sink current until the SS
pin voltage is higher than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if
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the BOOT-SW voltage is below its UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed
to turn on to charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another
layer of protection for the device after the high-side MOSFET begins to switch.
7.3.9 MSEL Pin
The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, RMSEL, from
MSEL to AGND. 表 7-5 lists the resistor values for the available options. Use a 1% tolerance resistor or better.
See 节7.3.11.1 for the corresponding current limit thresholds for the "High" and "Low" settings.
表7-5. MSEL Pin Selection
Soft-Start Time
Current Limits
CRAMP (pF)
RMODE (kΩ)
(ms)
1.78
2.21
2.74
3.32
4.02
4.87
5.9
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
1
1
1
1
2
2
2
2
4
4
4
4
1
1
1
1
2
2
2
2
4
4
4
4
1
2
4
8
1
2
4
7.32
9.09
11.3
14.3
18.2
22.1
26.7
33.2
40.2
49.9
60.4
76.8
102
8
1
2
4
8
1
2
4
8
1
2
4
8
137
1
174
2
243
4
412
8
7.3.10 Power Good (PG)
The TPS543B22 PG pin is an open-drain output requiring an external pullup resistor to output a high signal.
After the FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a
256-µs deglitch time, the PG pin is de-asserted and the pin floats. A pullup resistor between the values of 10 kΩ
and 100 kΩ to a voltage source that is 5.5 V or less is recommended. PG is in a defined state after the VIN input
voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or greater
than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PG pin is pulled low. PG is
immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters thermal
shutdown.
7.3.11 Output Overload Protection
The TPS543B22 protects against output overload (that is, overcurrent) events by cycle-by-cycle current limiting
both the high-side MOSFET and low-side MOSFET. In an extended overcurrent condition, the device enters
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hiccup mode. Different protections are active during positive inductor current and negative inductor current
conditions.
7.3.11.1 Positive Inductor Current Protection
Current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to
settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned
off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls
below the low-side MOSFET overcurrent threshold, effectively limiting the peak current in the case of a short-
circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup mode.
The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received
from the controller, the device skips processing that PWM pulse. The device does not turn the high-side
MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent
threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate
counters for the high-side and low-side overcurrent events. If the off time is too short, the low-side overcurrent
can not trip. The low-side overcurrent, however, begins tripping after the high-side peak overcurrent limit is
crossed, as exceeding the peak current limit shortens the on time and lengthens the off time.
Both the high-side and low-side positive overcurrent thresholds are programmable using the MSEL pin. Two sets
of thresholds are available ("High" and "Low"), which are summarized in 表 7-6. The values for these thresholds
are obtained using open-loop measurements with a DC current to accurately specify the values. In real
applications, the inductor current ramps and the ramp rate is a function of the voltage across the inductor (VIN –
VOUT) as well as the inductance value. The ramp rate combined with delays in the current sense circuitry then
results in slightly different values than specified. The current at which the high-side overcurrent limit takes effect
can be slightly higher than specified, and the current at which the low-side overcurrent limit takes effect can be
slightly lower than specified.
表7-6. Overcurrent Thresholds
High-Side
Overcurrent Typical
Value (A)
MSEL Current
Limit Setting
Low-Side Overcurrent
Typical Value (A)
High
Low
29
23
22
17.6
7.3.11.2 Negative Inductor Current Protection
Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is
immediately turned off. The next high-side MOSFET turn-on is determined by the clock and PWM comparator.
The negative overcurrent threshold minimum value is 7 A. Similar to the positive inductor current protections, the
actual value of the inductor current when the current sense comparators trip is a function of the current ramp
rate. As a result, the current at which the negative inductor current limit takes effect can be slightly more
negative than specified.
7.3.12 Output Overvoltage and Undervoltage Protection
The TPS543B22 incorporates both output overvoltage and undervoltage protection. If an overvoltage is
detected, the device tries to discharge the output voltage to a safe level before attempting to restart. When the
overvoltage threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent
threshold is reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero.
Then, the low-side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. The
process repeats until the output voltage falls back into the PG window. After this happens, the device restarts
and goes through a soft start cycle. The device does not wait the hiccup time before restarting.
When an undervoltage condition is detected, the device enters hiccup where it waits seven soft-start cycles
before restarting. Undervoltage protection is enabled after soft start is complete.
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7.3.13 Overtemperature Protection
When the die temperature exceeds 165°C, the device turns off. After the die temperature cools below the
hysteresis level, typically by 12°C, the device restarts. While waiting for the temperature to fall below the
hysteresis level, the device does not switch or attempt to hiccup to restart. After the temperature falls below the
hysteresis level, the device restarts without going through hiccup.
7.3.14 Output Voltage Discharge
When the TPS543B22 is enabled, but the high-side FET and low-side FET are disabled due to a fault condition,
the output voltage discharge mode is enabled, turning on the discharge FET from SW to PGND to discharge the
output voltage. The discharge FET is turned off when the converter is ready to resume switching, either after the
fault clears or after the wait time before hiccup is over.
The output voltage discharge mode is activated by any of the following fault events:
• High-side or low-side positive overcurrent
• Thermal shutdown
• Output voltage undervoltage
• VIN UVLO
7.4 Device Functional Modes
7.4.1 Forced Continuous-Conduction Mode
The TPS543B22 operates in forced continuous-conduction mode (FCCM) throughout normal operation.
7.4.2 Discontinuous Conduction Mode During Soft Start
At the beginning of soft start, the converter operates in discontinuous conduction mode (DCM) for the first 16
PWM cycles. During this time, a zero-cross detect comparator is used to turn off the low-side MOSFET when the
current reaches zero amps, preventing the discharge of any prebiased conditions on the output. After the 16
cycles of DCM, the converter enters FCCM mode for the remainder of start-up and into regulation.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS543B22 is a synchronous buck converter designed for 4-V to 18-V input and 20-A load. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
8.2 Typical Applications
8.2.1 1.0-V Output, 1-MHz Application
CI7
CI5
CI3
10uF
CHF1
1uF
22uF
U1
CBT
RBT
0
VIN
4
9
7
VIN
VIN
BOOT
SW
PGND
LO
Output: 1.0 V at 20 A
VIN
0.1uF
VOUT
+
CBULK
CHF2
1uF
3
2
6
SW
VDRV
VCC
CI8
CI6
CI4
RFLT
RENT
RENB
22uF
10µF
VCC
CO1
CO2
CO3
CO4
15
14
FB
10.0
FB
CO5
CO6
100uF
RPGD
10k
Net-Tie
VO_SNS
100uF
100uF
100uF
PGND
EN
EN
100µF
10
11
EN
100uF
GOSNS
PGND
PG
RBODE
10.0
1
AGND
PGND
PGND
PGND
CBP
0.1uF
CBIAS
2.2uF
MODE 13
12
5- 8
16
17
MSEL
Net-Tie
BODE-
SYNC/FSEL
RFBB
TPS543B22RYS
FSEL
Net-Tie
RMODE
RFBT
AGND
PGND
AGND
RFSEL
CFF
PGND
AGND
AGND
图8-1. 12-V Input, 1.0-V Output, 1-MHz Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters shown in 表8-1.
表8-1. Design Parameters
Parameter
Example Value
4.5 to 18 V, 12 V nominal
1.0 V
Input voltage range (VIN)
Output voltage (VOUT
Output current rating (IOUT
Switching frequency (fSW
)
)
20 A
)
1000 kHz
Steady state output ripple voltage
Output current load step
Transient response
10 mV
10 A
± 50 mV (± 5%)
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency
The first step is to decide on a switching frequency. The TPS543B22 can operate at five different frequencies
from 500 kHz to 2.2 MHz. fSW is set by the resistor value from the FSEL pin to ground. Typically, the highest
switching frequency possible is desired because it produces the smallest solution size. A high switching
frequency allows for smaller inductors and output capacitors compared to a power supply that switches at a
lower frequency. The main tradeoff made with selecting a higher switching frequency is extra switching power
loss, which hurts the efficiency of the regulator.
The maximum switching frequency for a given application can be limited by the minimum on time of the regulator
and the maximum fSW can be estimated with 方程式 15. Using the maximum minimum on time of 40 ns and
18.0-V maximum input voltage for this application, the maximum switching frequency is 1389 kHz. The selected
switching frequency must also consider the tolerance of the switching frequency. A switching frequency of 1000
kHz was selected for a good balance of solution size and efficiency. To set the frequency to 1000 kHz the
selected FSEL resistor is 11.8 kΩper 表7-1.
VOUT
V max
IN
1
fSW max =
ì
(
)
tonmin
(15)
图 8-2 shows the maximum recommended input voltage versus output voltage for each FSEL frequency. This
graph uses the maximum minimum on time of 40 ns and includes 10% tolerance on the switching frequency.
20
19
18
17
16
15
14
13
12
11
10
9
8
fsw = 500 kHz
fsw = 750 kHz
7
6
5
4
fsw = 1000 kHz
fsw = 1500 kHz
fsw = 2200 kHz
0.5
0.7
0.9
1.1
1.3
Output Voltage (V)
1.5
1.7
1.9
图8-2. Maximum Input Voltage vs Output Voltage
8.2.1.2.2 Output Inductor Selection
To calculate the value of the output inductor, use 方程式16. KIND is a ratio that represents the amount of inductor
ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor
because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple
current. Choosing small inductor ripple currents can degrade the transient response performance. The inductor
ripple, KIND, is normally from 0.1 to 0.4 for the majority of applications giving a peak to peak ripple current range
of 2 A to 8 A. The target IRIPPLE must be 1 A or larger.
For this design example, KIND = 0.2 is used and the inductor value is calculated to be 0.236 0.286 µH. An
inductor with an inductance of 0.220 µH is selected. It is important that the RMS (root mean square) current and
saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found
from 方程式 18 and 方程式 19. For this design, the RMS inductor current is 20.46 A, and the peak inductor
current is 22.1 A. The chosen inductor is a SLR1050A-221. The inductor has a saturation current rating of 35 A,
an RMS current rating of 56.7 A, and a typical DC series resistance of 0.39 mΩ.
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The peak current through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in 方程式 19. In transient conditions, the inductor current can increase up to the switch current
limit of the device. For this reason, the most conservative approach is to specify the current ratings of the
inductor based on the switch current limit rather than the steady-state peak inductor current.
V
− V
V
OUT
IN
OUT
IND
1
L1 =
×
×
(16)
Io × K
V
f
IN
SW
vertical spacer
V
− V
V
INMAX
OUT
OUT
× f
I
=
×
V
(17)
ripple
L1
INMAX
SW
vertical spacer
2
V
− V
V
2
1
12
INMAX
L1
OUT
OUT
× f
IL
=
I
+
+
×
×
(18)
(19)
rms
O
V
INMAX
SW
vertical spacer
I
ripple
2
IL
= I
OUT
peak
8.2.1.2.3 Output Capacitor
There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple
and how the regulator responds to a large change in load current. The output capacitance must be selected
based on the more stringent of these criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop must sense
the change in the output voltage then adjust the peak switch current in response to the change in load. The
minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop
bandwidth is near fSW / 10. 方程式20 estimates the minimum output capacitance necessary.
For this example, the transient load response is specified as a 3% change in VOUT for a load step of 10 A .
Therefore, ΔIOUT is 10 A and ΔVOUT is 50 mV. Using this target gives a minimum capacitance of 318 μF. This
value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic
capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response.
DIOUT
DVOUT
1
COUT
>
ì
fSW
10
2pì
(20)
where
• ΔIOUT is the change in output current.
• ΔVOUT is the allowable change in the output voltage.
In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator
responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down
after a load step down can be the limiting factor. 方程式 21 estimates the minimum output capacitance
necessary to limit the change in the output voltage after a load step down. Using the 0.22-µH inductance
selected gives a minimum capacitance of 91 µF.
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2
LOUT ì DIOUT
2ì DVOUT ì VOUT
COUT
>
(21)
方程式 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In
this case, the target maximum steady state output voltage ripple is 10 mV. Under this requirement, 方程式 22
yields 52 µF.
1
1
Co >
´
Voripple
8 ´ ¦sw
Iripple
(22)
where
• ΔIOUT is the change in output current.
• ΔVOUT is the allowable change in the output voltage.
• fSW is the regulators switching frequency.
• VORIPPLE is the maximum allowable steady state output voltage ripple.
• IRIPPLE is the inductor ripple current.
Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum
amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on
the MODE pin. 方程式 23 estimates the minimum capacitance needed for loop stability. 方程式 23 sets the
minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum
value. See 图 8-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 1-V output,
the minimum ratio is 35 and with this ratio, 方程式23 gives a minimum capacitance of 141 µF.
2
≈
∆
«
’
÷
Ratio
1
COUT
>
ì
2pì fSW ◊ LOUT
(23)
方程式 24 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification and this shows the ESR must be less than 6 mΩ. In this case, ceramic capacitors are used
and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple.
Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and
failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data
sheet specifies the RMS value of the maximum ripple current. 方程式25 can be used to calculate the RMS ripple
current the output capacitor must support. For this application, 方程式 25 yields 1.2 A and ceramic capacitors
typically have a ripple current rating much higher than this.
Voripple
Resr <
Iripple
(24)
vertical spacer
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(25)
Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high
capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected
with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic
capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website.
For this application example, six 100-µF, 10-V, X5R, 1210 ceramic capacitors each with 3 mΩ of ESR are used.
With the six parallel capacitors, the estimated effective output capacitance after derating using the capacitor
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manufacturer's website is 570 µF. There is about -5% DC bias derating at 1 V. This design was able to use less
than the calculated minimum because the loop crossover frequency was above the fSW / 10 estimate as shown
in 图8-8.
8.2.1.2.4 Input Capacitor
Input decoupling ceramic capacitors type X5R, X7R, or similar from VIN to PGND that are placed as close as
possible to the IC are required. A total of at least 66 µF of capacitance is required and some applications can
require a bulk capacitance. At least 1 µF of bypass capacitance is recommended as close as possible to each
VIN pin to minimize the input voltage ripple. A 1-µF capacitor must be placed as close as possible to both VIN
pins 4 and 9 on the same side of the board of the device to provide high frequency bypass to reduce the high
frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor must be
greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the
maximum RMS input current. The RMS input current can be calculated using 方程式26.
For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the
maximum input voltage. Two 22-µF, 1210, X7R, 25-V, two 10-µF, 0805, X7S, 25-V, and two 1-μF, 0402 or 0603,
X7R 25-V capacitors in parallel has been selected to be placed on both sides of the IC near both VIN pins to
PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 25 µF
at the nominal input voltage of 12 V. Additional 100-µF ceramic capacitance and 220-µF aluminum electrolytic
are also used to bypass long leads when connected a lab bench top power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 方程式 26. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using
the nominal design example values of IOUT(MAX) = 20 A , CIN = 25 μF, and fSW = 1000 kHz, the input voltage
ripple with the 12-V nominal input is 61 mV and the RMS input ripple current with the 4.5-V minimum input is 8.3
A.
V
− V
V
OUT
INMIN
V
OUT
I
= I
×
×
(26)
CINRMS
OUT
V
INMIN
INMIN
vertical spacer
V
V
OUT
OUT
I
OUTMAX
×
1 −
×
V
V
IN
IN
∆ V
=
(27)
IN
C
× fsw
IN
8.2.1.2.5 Adjustable Undervoltage Lockout
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The
UVLO has two thresholds: one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply is set to turn on and start
switching after the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 3.95 V (UVLO stop or disable). In this example,
these start and stop voltages set by the EN resistor divider were selected to have more hysteresis than the
internally fixed VIN UVLO.
方程式 1 and 方程式 2 can be used to calculate the values for the upper and lower resistor values. For these
equations to work, VSTART must be 1.1 × VSTOP due to the voltage hysteresis of the EN pin. For the voltages
specified, the standard resistor value used for RENT is 16.9 kΩ and for RENB is 6.04 kΩ.
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8.2.1.2.6 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by RFBT and RFBB from the output node to the FB pin.
Use 1% tolerance or better resistors. For this example design, 4.99 kΩwas selected for RFBB. Using 方程式 28,
RFBT is calculated as 4.99 kΩ. This is a standard 1% resistor.
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(28)
If the PCB layout does not use the recommended AGND to PGND connection in 节8.4.1, noise on the feedback
pin can degrade the output voltage regulation at maximum load. Using a smaller RFBB of 1.00 kΩ minimizes the
impact of this noise.
8.2.1.2.7 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. The
capacitor must be rated for at least 10-V to minimize DC bias derating.
A resistor can be added in series with the BOOT capacitor to slow down the turn on of the high-side MOSFET
and reduce overshoot rising edge overshoot on the SW pin. This comes with the tradeoff of more power loss and
lower efficiency. As a best practice, include a 0-Ω placeholder in prototype designs in case parasitic inductance
in the PCB layout results in more voltage overshoot at the SW pin than is normal. This helps keep the voltage
within the ratings of the device and reduces the high frequency noise on the SW node.
8.2.1.2.8 VDRV and VCC Capacitor Selection
A 2.2-µF ceramic capacitor must be connected between the VDRV pin and PGND for proper operation. The
capacitor must be rated for at least 10 V to minimize DC bias derating. The VDRV pin is the output of an internal
linear regulator and the supply to the gate drivers. The VCC pin is the supply for the analog control circuits and
must have a 0.1-µF and 10-V rated or better ceramic capacitor connected from VCC to AGND. A 10-Ω 0402
resistor must be connected between the VDRV to VCC pins.
8.2.1.2.9 PGOOD Pullup Resistor
A 10-kΩ resistor is used to pull up the power-good signal when FB conditions are met. The pullup voltage
source must be less than the 6-V absolute maximum of the PGOOD pin.
8.2.1.2.10 Current Limit Selection
The MODE pin is used to select between two current limit settings. Select the current limit setting whose
minimum is greater than at least 1.1 times the maximum steady state peak current. This is to provide margin for
component tolerance and load transients. For this design, the minimum current limit must be greater than 7.45 A
so the high current limit setting is selected.
8.2.1.2.11 Soft-Start Time Selection
The MODE pin is used to select between four different soft-start times, which is useful if a load has specific
timing requirements for the output voltage of the regulator. A longer soft-start time is also useful if the output
capacitance is very large and requires large amounts of current to quickly charge the output capacitors to the
output voltage level. The large currents necessary to charge the capacitor can reach the current limit or cause
the input voltage rail to sag due excessive current draw from the input power supply. Limiting the output voltage
slew rate solves both of these problems. The example design has the soft-start time set to 1.0 ms. With this soft-
start time, the current required to charge the output capacitors to the nominal output voltage is only 0.14 A.
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8.2.1.2.12 Ramp Selection and Control Loop Stability
The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends
on VOUT, fSW, LOUT, and COUT. To get started, calculate LC double pole frequency using 方程式 29. Then
calculate the ratio between fSW and fLC. Based on this ratio and the output voltage, select the recommended
ramp setting using 图 8-3. With a 1-V output, the 1-pF ramp is recommended for ratios between approximately
35 and 58, the 2-pF ramp is recommended for ratios between approximately 58 and 86, and the 4-pF ramp is
recommended for ratios greater than approximately 86. In general, it is best to use the largest ramp capacitor the
design can support. Increasing the ramp capacitor improves transient response but can reduce stability margin
or increase on-time jitter.
For this design, fLC is 17.5 kHz and the ratio is 57 which is on the border of the 1-pF and 2-pF ramp settings.
Through bench evaluation, it was found the design had sufficient stability margin with the 2-pF ramp so this
setting was selected for the best transient response. The recommended ramp settings given by 图 8-3 include
margin to account for potential component tolerances and variations across operating conditions so it is possible
to use a higher ramp setting as shown in this example.
1
fLC
=
2ì pì LOUT ìCOUT
(29)
5.5
5
4.5
4
4 pF
3.5
3
2 pF
2.5
2
1 pF
1.5
1
0.5
20
30
40
50
60
fSW/fLC
70
80
90
100
图8-3. Recommended Ramp Settings
Use a feedforward capacitor (CFF) in parallel with the upper feedback resistor (RFBT) to add a zero into the
control loop to provide phase boost. Include a placeholder for this capacitor as the zero it provides can be
required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the
zero. The pole and zero frequency are not independent so as a result, after the zero location is chosen, the pole
is fixed as well. The zero is placed at 1 / 4 the fSW by calculating the value of CFF with 方程式 30. The calculated
value is 128 pF —round this down to the closest standard value of 120 pF.
Using bench measurements of the AC response, the feedforward capacitor for this example design was
increased to 180 pF to improve the transient response.
1
CFF
=
fSW
pìRFBT
ì
2
(30)
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It is possible to use larger feedforward capacitors to further improve the transient response but take care to
ensure there is a minimum of –9-dB gain margin in all operating conditions. The feedforward capacitor injects
noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node.
Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 100-Ω resistor in series
with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB
layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer
together degrading the phase boost the feedforward capacitor provides.
When using higher ESR output capacitors, such as polymer or tantalum, their ESR zero (fESR) must be
accounted for. The ESR zero can be calculated using 方程式 31. If the ESR zero frequency is less than the
estimated bandwidth of 1/10th the fSW, it can affect the gain margin and phase margin. A series R-C from the FB
pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this
design so the effect of the ESR zero is ignored.
1
fESR
=
2ì pìCOUT ìRESR
(31)
8.2.1.2.13 MODE Pin
The MODE resistor is set to 4.87 kΩto select the high current limit setting, 1.0-ms soft-start, and the 2-pF ramp.
See 表7-5 for the full list of the MODE pin settings.
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8.2.1.3 Application Curves
100
95
90
85
80
1.01
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
0.99
VIN = 5 V, 1 MHz
VIN = 5.0 V, 1 MHz
VIN = 8.0 V, 1 MHz
VIN = 12.0 V, 1 MHz
VIN = 14.0 V, 1 MHz
VIN = 8.0 V, 1 MHz
VIN = 12.0 V, 1 MHz
VIN = 14.0 V, 1 MHz
75
70
Vout = 1V
0
5
10
15
20
0
5
10
Output Current (A)
15
20
Output Current (A)
图8-5. Load Regulation
图8-4. Efficiency Curves
80
70
60
50
40
30
20
10
0
400
350
300
250
200
150
100
50
1.005
1.004
1.003
1.002
1.001
1
Gain
Phase
0.999
0.998
0.997
0.996
0.995
0
-10
-20
-50
-100
-150
-200
Vin = 12 V, Vout = 1.0 V
Iout = 20 A 1000 kHz 2pF
IOUT = 0 A, 1 MHz
IOUT = 10 A, 1 MHz
IOUT = 20 A, 1 MHz
-30
-40
1000 2000 5000 10000
100000
1000000
Frequency (Hz)
4
6
8
10
12
14
16
18
Input Voltage (V)
图8-7. Bode Plot
图8-6. Line Regulation
SW (10V/div)
VIN (10V/div)
VOUT (20mV/div) 1V dc o set
EN (2V/div)
VOUT (500mV/div)
ILOAD (20A/div)
VDRV (5V/div)
VIN=12V IOUT = 0A
400ꢀs/div
VIN=12V IOUT = 0A to 20A
200 ꢀs/div
图8-9. EN Start-Up –Measuring BP5
图8-8. Load Transient
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EN (2V/div)
EN (2V/div)
SW (5V/div)
VDRV (5V/div)
VOUT (500mV/div)
VOUT (500mV/div)
PGOOD (5V/div)
PGOOD (5V/div)
VIN=12V IOUT = 10A
1 ms/div
VIN=12V IOUT = 0A
400ꢀs/div
图8-10. EN Start-Up –Measuring SW
图8-11. EN Shutdown
EN (2V/div)
EN (2V/div)
SW (5V/div)
SW (5V/div)
VOUT (500mV/div)
PGOOD (5V/div)
VOUT (500mV/div)
PGOOD (5V/div)
VIN=12V IOUT = 0A
400ꢀs/div
VIN=12V IOUT = 10A
1 ms/div
图8-13. EN Start-Up –0.5-V Prebias
图8-12. EN Start-Up –With Load
VIN (5V/div)
VIN (5V/div)
EN (5V/div)
EN (5V/div)
VOUT (500mV/div)
VOUT (500mV/div)
PGOOD (5V/div)
PGOOD (5V/div)
VIN=12V IOUT = 0A
2 ms/div
VIN=12V IOUT = 10A
2 ms/div
图8-14. VIN Start-Up
图8-15. VIN Shutdown
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SW (10V/div)
SW (10V/div)
VOUT (10mV/div) 1V dc o set
VOUT (10mV/div) 1V dc o set
ILOAD (10A/div)
ILOAD (10A/div)
VIN=12V IOUT = 0A
2 ꢀs/div
VIN=12V IOUT = 20A
2 ꢀs/div
图8-16. Output Ripple –No Load
图8-17. Output Ripple –Full Load
SW (10V/div)
SW (10V/div)
VIN (20mV/div) ac coupled
VIN (200mV/div) ac coupled
ILOAD (10A/div)
ILOAD (10A/div)
VIN=12V IOUT = 0A
1 ꢀs/div
VIN=12V IOUT = 20A
1 ꢀs/div
图8-18. Input Ripple –No Load
图8-19. Input Ripple –Full Load
SW (10V/div)
SW (10V/div)
VOUT (1V/div)
VOUT (1V/div)
ILOAD (10A/div)
ILOAD (10A/div)
VIN=12V
100 ꢀs/div
VIN=12V
400 ꢀs/div
图8-20. Overcurrent Protection –Overload
图8-21. Overcurrent Protection –Short
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SW (10V/div)
VOUT (1V/div)
ILOAD (10A/div)
VIN=12V
4 ms/div
图8-22. Overcurrent Protection –Hiccup and Recover
8.3 Power Supply Recommendations
The TPS543B22 is designed to operate from an input voltage supply range between 4 V and 18 V. This supply
voltage must be well regulated. Proper bypassing of the input supply is critical for proper electrical performance,
as is the PCB layout and the grounding scheme. A minimum of 10-μF (after derating) ceramic capacitance, type
X5R or better, must be placed near the device. TI recommends splitting the ceramic input capacitance equally
between the VIN and PGND pins on each side of the device resulting in at least 5 µF of ceramic capacitance on
each side of the device.
8.4 Layout
8.4.1 Layout Guidelines
Layout is a critical portion of good power supply design. See 图 8-23 for a PCB layout example. Key guidelines
to follow for the layout are:
• VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat
dissipation. Use vias and traces on others layers to reduce VIN and PGND trace impedance.
• Use multiple vias near the PGND pins and use the layer directly below the device to connect them together,
which helps to minimize noise and can help heat dissipation.
• Use vias near both VIN pins and provide a low impedance connection between them through an internal
layer.
• Place a 1-μF/25-V/X6R or better dielectric ceramic capacitors from each VIN to PGND pins and place them
as close as possible to the device on the same side of the PCB. Place the remaining ceramic input
capacitance next to these high frequency bypass capacitors. The remaining input capacitance can be placed
on the other side of the board but use as many vias as possible to minimize impedance between the
capacitors and the pins of the IC.
• Place the inductor as close as possible to the device to minimize the length of the SW node routing.
• Place the BOOT-SW capacitor as close as possible to the BOOT and SW pins. Use a 0.1-μF/16-V/X6R or
better dielectric ceramic capacitor for the BOOT capacitor.
• Place the 2.2-μF/10-V/X6R or better dielectric ceramic capacitor as close as possible to the VDRV and
PGND pins.
• Connect 10-Ωresistor from VDRV to VCC and a 0.1-μF/10-V/X6R or better dielectric ceramic capacitor from
VCC to AGND.
• Place the bottom resistor in the FB divider as close as possible to the FB and GOSNS pins of the IC. Also
keep the upper feedback resistor and the feedforward capacitor near the IC. Connect the FB divider to the
output voltage at the desired point of regulation.
• Use vias on the AGND islands on top layer to connect to AGND layer island on an internal layer. Connect the
internal AGND island to PGND at one point.
• Return the FSEL and MODE resistors to a quiet AGND island.
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8.4.2 Layout Example
1210
PGND
1210
0402
0402
AGND
VIN
0805
0402
0402
AGND
0402
0402
0402
MSEL
GOSNS
0402
SW
VOUT
FB
0402
AGND
0402
0402
PGND
0805
1210
1210
VIN
PGND
图8-23. Example PCB Layout
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8.4.3 Thermal Performance
Test conditions: fSW = 1 MHz, VIN = 12 V, VOUT = 1 V, IOUT = 20 A, Inductor = 220 nH (0.325 mΩ typical),
ambient temperature = 25°C
图8-24. Thermal Image at 25°C Ambient
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
SWIFT™, HotRod™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS543B22RYSR
ACTIVE WQFN-FCRLF
RYS
17
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
T543B22
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RYS0017A
WQFN-FCRLF - 0.7 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
A
B
4.6
4.4
PIN 1 INDEX AREA
(0.085)
(0.18)
ALTERNATE PIN SHAPE
0.7
0.6
C
SEATING PLANE
0.08 C
0.01
0.00
1.2
1.0
2X
(0.125) TYP
(0.13) TYP
6
7
2
1.5
1
2
(0.3) TYP
5
8
1.05
0.85
0.825
0.625
0.5
0.000 PKG
4
9
0.2875
17
2X 0.5
2X 1
0.775
0.575
1.2375
16
2X 1.5
2X 2
12
0.3
1
28X
0.2
15
0.1
C A B
C
0.475
0.275
17X
0.05
SEE ALTERNATE
PIN SHAPE DETAIL
PIN 1 ID
(45 X 0.27)
1.25
1.05
4228726/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RYS0017A
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.15)
3X (0.575)
3X (0.575)
15
SOLDER MASK
OPENING, TYP
(2.163)
2X (2)
1
12
2X (1.5)
2X (1.238)
2X (1)
(0.675)
13X (0.25)
16
7X (0.575)
2X (0.5)
9
17
(0.75)
2X (0.288)
(0.725)
4
0.000 PKG
(0.3)
2X (0.5)
4X (0.7)
(2.25)
8
2X (0.95)
2X (1)
(1.25)
(
0.2) TYP VIA
5
4X (1.3)
15X (0.25)
2X (1.5)
(2)
(2)
7
(0.575)
6
(R0.05) TYP
15X (0.325)
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SCALE: 20X
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
METAL EDGE
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4228726/C 10/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RYS0017A
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.08)
4X (0.5)
SOLDER MASK
OPENING, TYP
EXPOSED METAL
TYP
15
(2.163)
12
4X (0.5)
1
2X (2)
22X (0.25)
2X (1.5)
(R0.05)
TYP
(1.238)
(0.62)
16
17
2X (1)
10X (0.575)
2X (0.5)
(0.288)
(0.66)
9
4
0.000 PKG
2X (0.25)
2X (0.5)
5
8
2X
0.9)
4X (1)
EXPOSED METAL
2X (1.5)
6X (0.25)
6X (0.2)
(
7
2X (2)
6
(2.163)
METAL UNDER
SOLDER MASK
TYP
EXPOSED METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
PRINTED SOLDER COVERAGE BY AREA
PADS 1, 7 & 12: 83%
PAD 5 & 8: 87%
PAD 6: 73%
PAD 16: 85%
PAD 17: 86%
4228726/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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