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TPS543C20A

ZHCSJ36 –NOVEMBER 2018

具备自适应内部补偿功能的 TPS543C20A4 V_IN至 16 V_IN、40A 可堆叠、同

步降压 SWIFT™ 转换器

1 特性

2 应用

1

•

内部补偿高级电流模式控制 40A POL

•

无线和有线通信基础设施设备

输入电压范围：4V 至 16V

输出电压范围：0.6V 至 5.5V

企业服务器、交换机和路由器

企业级存储、SSD

集成 3.4/0.9mΩ 堆叠式 NexFET™功率级，带有无

损低侧电流检测功能

ASIC、SoC、FPGA、DSP 内核和 I/O 电源轨

3 说明

•

固定频率 - 同步到外部时钟和/或同步输出

TPS543C20A 采用内部补偿的仿真峰值电流模式控制

方式，具有适用于 EMI 敏感型 POL 的时钟同步固定频

率调制器。内部积分器和直接放大式斜坡跟踪环路在较

宽频率范围内消除了对外部补偿的需求，从而使系统设

计具有灵活、密集和简单的特点。可选的 API 和体制

动功能有助于分别通过显著减少下冲和过冲来提高瞬态

性能。具有低损耗开关特性的集成式

可通过引脚搭接进行编程的开关频率

–

独立模式下为 300kHz 至 2MHz

堆叠模式下为 300kHz 至 1MHz

•

通过双倍堆叠实现高达 80A 负载，并具有电流共

享、电压共享和 CLK 同步功能

可通过引脚搭接进行编程的基准电压介于 0.6V 至

1.1V 之间，精度达 0.5%

•

差分遥感

NexFET™MOSFET 有助于提高效率和提供高达 40A

的输出电流（采用 5mm × 7mm 的 PowerStack™封

装，带有方便布局的散热垫）。两个 TPS543C20A 器

件可以堆叠在一起，以便提供高达 80A 的负载点。

安全启动至预偏置输出电压

高精度打嗝电流限制

异步脉冲注入 (API) 和体制动

40 引脚 5mm × 7mm LQFN 封装，具有 0.5mm 间

距和单个散热垫

器件信息

使用 TPS543C20A 并借助 WEBENCH^®电源设计

器创建定制设计方案

器件编号

封装

封装尺寸（标称值）

•

TPS543C20A

LQFN-CLIP (40)

5.00mm x 7.00mm

1. 如需了解所有可用封装，请参阅数据表末尾的可订

购产品附录。

简化原理图

V_IN

V_OUT

ILIM

RSP

RSN

BOOT

SW

RAMP

RT

TPS543C20A

VSEL

+

LOAD

t

BP

SS

MODE

AGND

PGND

GND

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDE0

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

9

Application and Implementation ........................ 24

9.1 Application Information............................................ 24

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information ................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 11

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 15

9.2 Typical Application: TPS543C20A Stand-alone

Device ...................................................................... 24

9.3 System Example ..................................................... 30

10 Power Supply Recommendations ..................... 32

11 Layout................................................................... 33

11.1 Layout Guidelines ................................................. 33

11.2 Layout Example .................................................... 34

11.3 Package Size, Efficiency and Thermal

Performance............................................................. 35

12 器件和文档支持 ..................................................... 37

12.1 器件支持................................................................ 37

12.2 接收文档更新通知 ................................................. 37

12.3 社区资源................................................................ 37

12.4 商标....................................................................... 37

12.5 静电放电警告......................................................... 37

12.6 术语表 ................................................................... 37

13 机械、封装和可订购信息....................................... 38

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 11 月

*

最初发布版本

2

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

5 Device Comparison Table

DEVICE

OUTPUT CURRENT

TPS543B20

TPS543C20

TPS543C20A

25 A

40 A

6 Pin Configuration and Functions

RVF Package

40-Pin LQFN-CLIP With Thermal Pad

Top View

RSP

RSN

NC

1

32

31

30

29

28

27

26

25

24

23

22

21

VSHARE

ISHARE

ILIM

2

3

NC

4

AGND

BP

NC

5

NC

6

GND

Thermal

Pad

BOOT

SW

7

VDD

8

PVIN

SW

9

SW

10

11

12

SW

Not to scale

3

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

Pin Functions

I/O/P⁽¹⁾

DESCRIPTION

NO.

NAME

The positive input of the remote sense amplifier. Connect RSP pin to the output voltage

at the load. For multi-phase configuration, the remote sense amplifier is not needed for

slave devices.

1

RSP

I

The negative input of the remote sense amplifier. Connect RSN pin to the ground at load

side. For multi-phase configuration, the remote sense amplifier is not needed for slave

devices.

2

RSN

NC

I

3,4,5,6

—

Not connected

Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor

from this pin to SW. To reduce the voltage spike at SW, a BOOT resistor with a value

between 1 Ω to 10 Ω may be placed in series with the BOOT capacitor to slow down

turnon of the high-side FET.

7

BOOT

I

8,9,10,11,12

SW

B

Output of converted power. Connect this pin to the output Inductor.

13,14,15,16,17,18,19,

20

PGND

G

These ground pins are connected to the return of the internal low-side MOSFET

Input power to the power stage. Low impedance bypassing of these pins to PGND is

critical. A 10-nF to 100-nF capacitor from PVIN to PGND close to IC is required.

21,22,23,24,25

26

PVIN

VDD

I

Controller power supply input

Ground return for the controller. This pin should be directly connected to the thermal pad

on the PCB board. A 10-nF to 100-nF capacitor from PVIN to GND close to IC is

required.

27

28

GND

BP

G

O

Output of the 5 V on board regulator. This regulator powers the driver stage of the

controller and must be bypassed with a minimum of 2.2 µF to the thermal pad (power

stage ground, that is, GND). Low impedance bypassing of this pin to PGND is critical.

29

30

31

32

33

AGND

ILIM

G

O

I

GND return for internal analog circuits.

Current protection pin; connect a resistor from this pin to AGND sets current limit level.

Current sharing signal for multi-phase operation. Float this pin for single phase

Voltage sharing signal for multi-phase operation. Float this pin for single phase.

The enable pin turns on the switcher.

ISHARE

VSHARE

EN

B

I

Open-drain power-good status signal which provides start-up delay after the FB voltage

falls within the specified limits. After the FB voltage moves outside the specified limits,

PGOOD goes low.

34

PGD

O

For frequency synchronization. This pin can be configured as sync in or sync out by

MODE pin and RT pin for master and slave devices.

35

SYNC

B

36

37

VSEL

SS

I

Connect a resistor from this pin to AGND to select internal reference voltage.

Connect a resistor from this pin to AGND to select soft-start time.

O

Frequency setting pin. Connect a resistor from this pin to AGND to program the

switching frequency. This pin also selects sync point for devices in stackable

applications

38

RT

O

Enable or disable API or body brake function, choose API threshold, also selects the

operation mode in stackable applications

39

40

MODE

RAMP

B

Ramp level selection, with a resistor to AGND to adjust internal loop.

Package thermal tab, internally connected to PGND. The thermal tab must have

adequate solder coverage for proper operation.

Thermal Pad

Thermal Tab

—

(1) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground

4

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

18

UNIT

VIN

–0.3

VIN to SW⁽³⁾

25

VDD

–0.3

–5

18

BOOT

34.5

6.5

7

DC

BOOT to SW

< 10 ns

Input voltage⁽¹⁾

V

VSEL, SS, MODE, RT, SYNC, EN, ISHARE, ILIM

7

RSP

3.6

0.3

20

RSN

PGND, GND

DC

SW to PGND⁽⁴⁾

< 10 ns

20

BP, RAMP

–0.3

–55

7

Output voltage

PGD

7

V

VSHARE

3.6

150

Junction temperature, T_J

Storage temperature, T_stg

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

(3) VIN to SW must not exceed 25 V.

(4) SW to PGND must not exceed 20 V.

7.2 ESD Ratings

VALUE

±2500

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

5

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

4

MAX

UNIT

VIN

16

22

DC

–0.1

VIN to SW⁽³⁾

< 10 ns

22

VDD

4

–0.1

16

BOOT

23.5

5.5

6

DC

BOOT to SW

< 10 ns

Input voltage⁽²⁾

V

VSEL, SS, MODE, RT, SYNC, EN,

ISHARE, ILIM

–0.1

5.5

RSP

–0.1

–5

1.7

0.1

18

RSN

PGND, GND

DC

SW to PGND

< 10 ns

18

BP, RAMP

PGD

–0.3

–40

–55

7

Output voltage⁽²⁾

7

V

VSHARE

3.6

125

Junction temperature, T_J

Storage temperature, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

(3) See Layout Guidelines for VIN capacitor placement requirement to reduce MOSFET voltage stress.

7.4 Thermal Information

TPS543C20A

THERMAL METRIC⁽¹⁾

RVF (LQFN)

40 PINS

28.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

Junction-to-ambient thermal resistance EVM (TPS543C20AEVM-054:6-

layer, 2-oz Cu per layer, 2.75 inch by 3 inch)

12

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.9

4.1

1.3

4.1

1

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

MOSFET R_DS(ON)

R_DS(on)HS

HS FET

LS FET

VBST – VSW = 5 V, I_D= 20 A, T_J= 25°C

VDD = 5 V, I_D= 20 A, T_J= 25°C

3.4

0.9

mΩ

R_DS(on)LS

Power stage driver dead-time

from Low-side off to High-side

on⁽¹⁾

t_DEAD(LtoH)

VDD ≥ 12 V, T_J= 25°C

VDDN ≥ 12 V, T_J= 25°C

12

15

ns

Power stage driver dead-time

from High-side off to Low-side

on⁽¹⁾

t_DEAD(HtoL)

INPUT SUPPLY and CURRENT

V_VIN

Power stage voltage

4

16

V_VDD

VDD supply voltage

T_A= 25°C, no load, power conversion

enabled (no switching)

I_VDD

VDD bias current

4.3

mA

T_A= 25°C, no load, power conversion

disabled

I_VDDSTBY

VDD standby current

UNDERVOLTAGE LOCKOUT

V_{VDD_UVLO}

VDD UVLO rising threshold

3.8

0.2

3.2

0.2

1.6

300

0

V

v

V_{VDD_UVLO_HYS}VDD UVLO hysteresis

V_{VIN_UVLO}

V_{VIN_UVLO_HYS}

V_{EN_ON_TH}

V_HYS

VIN UVLO rising threshold

VIN UVLO hysteresis

EN on threshold

V

v

1.45

270

–1

1.75

330

1

V

EN hysteresis

mV

µA

I_{EN_LKG}

EN input leakage current

INTERNAL REFERENCE VOLTAGE

V_INTREF

Internal REF voltage

R_VSEL= OPEN

1000

mV

V

V_INTREFTOL

V_{INTREF_VSEL}

OUTPUT VOLTAGE

Internal REF voltage tolerance

T_J= –40°C to 125°C

Programable by VSEL (pin 36)

–0.5%

0.6

0.5%

1.1

Internal REF voltage range

I_RSP

RSP input current

V_RSP= 600 mV

–1

1

µA

DIFFERENTIAL REMOTE SENSE AMPLIFIER

f_UGBW

A0

Unity gain bandwidth⁽¹⁾

Open loop gain⁽¹⁾

5

8.5

MHz

dB

75

SR

SLew rate⁽¹⁾

Input common mode range⁽¹⁾

±10

V/µs

V

V_ICM

–0.2

–1

1.7

1

V_RSN-VGND= 0 mV

V_OFFSET

Input offset voltage⁽¹⁾

mV

V_RSN-VGND= ±100 mV

–1.9

1.9

(1) Specified by design. Not production tested.

7

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

MAX UNIT

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SWITCHING FREQUENCY

TEST CONDITIONS

MIN

TYP

V_IN= 12 V, V_VO= 1 V, RT = 66.5 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 48.7 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 39.2 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 28.0 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 22.6 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 19.1 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 15.4 kΩ

V_IN= 12 V, V_VO= 1 V, RT = 8.06 kΩ

DRVH rising to falling

300

400

500

700

850

1000

1200

2000

30

V_Oswitching frequency

maximum frequency for multi-

phase is 1MHz

F_SW

kHz

t_ON(min)

Minimum on-time⁽¹⁾

Minimum off-time⁽¹⁾

ns

t_OFF(min)

DRVH falling to rising

250

INTERNAL BOOTSTRAP SWITCH

V_F

Forward voltage

V_BP-VBST, T_A= 25°C, I_F= 5 mA

0.1

0.2

V

VSEL

R_VSEL= 0 kΩ

0.6

0.7

R_VSEL= 8.66 kΩ

R_VSEL= 15.4 kΩ

R_VSEL= 23.7 kΩ

R_VSEL= 34.8 kΩ

R_VSEL= 51.1 kΩ

R_VSEL= 78.7 kΩ

R_VSEL= OPEN

R_VSEL= 121 kΩ

R_VSEL= 187 kΩ

0.75

0.8

0.85

0.9

VSEL

Internal reference voltage

V

0.95

1

1.05

1.1

SOFT START

R_SS= 0 kΩ

0.5

1

R_SS= 8.66 kΩ

R_SS= 15.4 kΩ

R_SS= Open

2

4

V_Orising from 0

V to 95% of

final set point

R_SS= 23.7 kΩ

5

t_SS

Soft-start time

ms

R_SS= 34.8 kΩ

8

R_SS= 51.1 kΩ

R_SS= 78.7 kΩ

R_SS= 121 kΩ

R_SS= 187 kΩ

12

16

24

32

POWER ON DELAY

t_PODLYPower-on delay time

Delay from enable to switching

512

µs

8

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

PGOOD COMPARATOR

TEST CONDITIONS

MIN

TYP

MAX UNIT

OV warning threshold on RSP

pin, PGOOD fault threshold on

rising

VREF = 600 mV

108

84

112

88

116

V_PG(thresh)

%V_REF

UV warning threshold on RSP

pin, PGOOD fault threshold on

falling

92

PGOOD threshold on rising and

UV warning threshold de-

assertion threshold at RSP pin

V_PGD(rise)

95

%V_REF

PGOOD threshold on falling and

OV warning threshold de-

V_PGD(fall)

105

assertion threshold at RSP pin

R_PGD

PGOOD pulldown resistance

I_PGOOD= 5 mA, VRSP = 0 V

Delay for PGOOD going in

Delay for PGOOD coming out

30

45

60

Ω

1.024

ms

µs

t_PGDLY

PGOOD delay time

2

0.8

15

PGOOD output low level voltage

at no supply voltage

V_PGD(OL)

I_PGLK

VDD=0, I_PGOOD= 80 µA

V_PGOOD= 5 V

V

PGOOD leakage current

µA

CURRENT SHARE ACCURACY

Output current sharing accuracy

I

_OUT≥ 20 A/phase

_OUT≤ 20 A/phase

–15%

15%

among stackable devices,

defined as the ratio of the current

difference between devices to

total current(sensing error

only)⁽¹⁾

I_SHARE(acc)

I

±3

A

CURRENT DETECTION

V_ILIMV_TRIPvoltage range

R_dsonsensing

0.1

1.2

V

A

R_ILIM= 33.2 kΩ

OC tolerance

35

±10%

25

Low-side FET current protection

threshold and tolerance

I_OCP

R_ILIM= 23.7 kΩ

OC tolerance

A

Low-Side FET current protection

threshold and tolerance

I_OCP

±15%

–23

I_{OCP_N}

Negative current limit threshold

Valley-point current sense

A

Clamp current at V_TRIPclamp at

lowest

I_{CLMP_LO}

25°C, V_TRIP= 0.1 V

5.5

6.5

7.5

9

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

HIGH-SIDE SHORT-CIRCUIT PROTECTION

High-side short circuit protection

I_HSOC

55

A

fault threshold⁽¹⁾

OV / UV PROTECTION

V_OVP

OVP threshold voltage

OVP response time⁽¹⁾

UVP threshold voltage

UVP delay⁽¹⁾

OVP detect voltage

113

79

117

83

121 %VREF

t_OVPDLY

V_UVP

t_UVPDLY

t_HICDLY

OVP response time with 100-mV overdrive

UVP detect voltage

1

µs

87 %VREF

UVP delay

1.5

5.5

µs

Hiccup delay time

Regular t_SSsetting

7 × t_SS

ms

BP LDO REGULATOR

BP

LDO output voltage

V_IN= 12 V, I_LOAD= 0 to 10 mA

Wakeup

4.5

5

3.32

3.11

V

V_BPUVLO

BP UVLO threshold voltage

Shutdown

VLDO_BP

I_LDOMAX

LDO low dropout voltage

LDO overcurrent limit

V_IN= 4.5 V, I_LOAD= 30 mA, T_A= 25°C

V_IN= 12 V, T_A= 25°C

365

mV

mA

100

SYNCHRONIZATION

V_IH(SYNC)

V_IL(SYNC)

t_PSW(SYNC)

High-level input voltage

2

V

Low-level input voltage

Sync input minimum pulse width

Synchronization frequency

Dual-phase

0.8

100

ns

300

2000

1000

F_SYNC

kHz

Sync to SW delay tolerance,

percentage from phase-to-

phase⁽¹⁾

t_{SYNC to SW}

F_SYNC= 300 kHz to 1 MHz,

F_SYNC= 300 kHz

10%

5

t_{Lose_SYNC_delay}Delay when lose sync clock⁽¹⁾

µs

°C

THERMAL SHUTDOWN

Shutdown temperature

Hysteresis

155

165

30

Built-in thermal shutdown

T_SDN

threshold⁽¹⁾

10

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

7.6 Typical Characteristics

VIN = VDD = 12 V, T_A= 25°C, R_RT= 40.2 kΩ, T_A= 25°C (unless otherwise specified)

10

9

8

7

6

5

4

3

2

1

0

100%

95%

90%

85%

80%

75%

70%

.9 Vout

1 Vout

1.5 Vout

2.5 Vout

3.3 Vout

1 Vout

0.9 Vout

1.5 Vout

2.5 Vout

3.3 Vout

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Output Current (A)

D001

D005

V_IN= 5 V

500 kHz

25°C

V_IN= 5 V

500 kHz

25°C

Figure 2. Efficiency vs Output Current

Figure 3. Power Loss vs Output Current

100%

10

.9 Vout

1 Vout

1.5 Vout

2.5 Vout

3.3 Vout

5 Vout

9

95%

90%

85%

80%

75%

70%

8

7

6

5

4

3

2

1

0

0.9 Vout

1 Vout

1.5 Vout

2.5 Vout

3.3 Vout

5 Vout

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Output Current (A)

D002

D006

V_IN= 12 V

500 kHz

V_IN= 12 V

500 kHz

Figure 4. Efficiency vs Output Current

Figure 5. Power Loss vs Output Current

100%

12

5 Vin

9 Vin

12 Vin

14 Vin

16 Vin

5 Vin

9 Vin

12 Vin

14 Vin

16 Vin

95%

90%

85%

80%

75%

70%

10

8

6

4

2

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Output Current (A)

D003

D007

V_OUT= 1 V

1 MHz

V_OUT= 1 V

1 MHz

Figure 6. Efficiency vs Output Current

Figure 7. Power Loss vs Output Current

6

5

4

3

2

1

0

800

700

600

500

400

300

200

0.6 V_OUT

1 V_OUT

1.5 V_OUT

2.5 V_OUT

3.3 V_OUT

5 V_OUT

0.6 V_OUT

1 V_OUT

1.5 V_OUT

2.5 V_OUT

3.3 V_OUT

5 V_OUT

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Output Current (A)

D007

D010

V_IN= 12 V

500 kHz

25°C

V_IN= 12 V

500 kHz

25°C

Figure 8. Output Voltage vs Output Current

Figure 9. Switching Frequency vs Output Current

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Typical Characteristics (continued)

VIN = VDD = 12 V, T_A= 25°C, R_RT= 40.2 kΩ, T_A= 25°C (unless otherwise specified)

1.05

14 V_IN

12 V_IN

9 V_IN

5 V_IN

4 V_IN

1

0.95

0

5

10

15

20

25

30

35

40

Output Current (A)

D019

V_OUT= 1 V

1 MHz

25°C

Figure 10. Output Voltage vs Output Current

Figure 11. Start-Up From EN

Figure 12. Output Voltage Start-Up and Shutdown

Figure 13. Output Voltage Ripple at Steady State

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Typical Characteristics (continued)

VIN = VDD = 12 V, T_A= 25°C, R_RT= 40.2 kΩ, T_A= 25°C (unless otherwise specified)

15 A to 25 A to 15 A, 10-A Step at 40 A/µs

Figure 14. Output Voltage Transient Response

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8 Detailed Description

8.1 Overview

The device is 40-A, high-performance, synchronous buck converter with two integrated N-channel NexFET™

power MOSFETs. These devices implement the fixed frequency non-compensation mode control. Safe pre-bias

capability eliminates concerns about damaging sensitive loads. Two devices can be paralleled together to

provide up to -A load. Current sensing for over-current protection and current sharing between devices is done

by sampling a small portion of the power stage current providing accurate information independent on the device

temperature.

Advanced Current Mode (ACM) is an emulated peak current control topology. It supports stable static and

transient operation without complex external compensation design. This control architecture includes an internal

ramp generation network that emulates inductor current information, enabling the use of low ESR output

capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal to

noise ratio for good noise immunity. The has 10 ramp options (see Ramp Selections for detail) to optimize

internal loop for various inductor and output capacitor combinations with only a simple resistor to GND. The is

easy to use and allows low external component count with fast load transient response. Fixed-frequency

modulation also provides ease-of-filter design to overcome EMI noise.

8.2 Functional Block Diagram

VDD

PVIN

BP

BOOT

BP

Linear Regulators

BP3

MODE

API

SW

SYNC

RT

Driver

Phase Managment

PWM

Q

S

R

Control:

Anti-Cross-

Conduction,

Prebias

Oscillator

BP

Stacked NexFET

Power Stage

PGND

ACM Controller

Overcurrent

Detection,

Current sensing

OC Event

Average Iout

GND

VSHARE

ISHARE

Phase

Balance

AGND

Fault

Control

RSP

RSN

Fault

Start and Reference

EN

SS

VSEL

PGD

ILIM

REMOTE SENSE AMP

RAMP

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8.3 Feature Description

The device is a high-performance, integrated FET converter supporting current rating up to 40-A thermally. It

integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB layout area.

The drain-to-source breakdown voltage for these FETs is 25-V DC and transient. Avalanche breakdown occurs if

the absolute maximum voltage rating exceeds 25 V. In order to limit the switch node ringing of the device, TI

recommends adding a R-C snubber from the SW node to the PGND pins. Also a 10~100nF capacitor from VIN

(Pin 25) to GND (Pin2 7) is mandatory to reduce high side FET stress. Refer to Layout Guidelines for the

detailed recommendations.

The typical on-resistance (RDS(on)) for the high-side MOSFET is 3.4 mΩ and typical on-resistance for the low-

side MOSFET is 0.9 mΩ with a nominal gate voltage (VGS) of 5 V.

8.4 Device Functional Modes

8.4.1 Soft-Start Operation

In the TPS543C20A device, the soft-start time controls the inrush current required to charge the output capacitor

bank during start-up. The device offers 10 selectable soft-start options ranging from 0.5 ms to 32 ms. When the

device is enabled the reference voltage ramps from 0 V to the final level defined by VSEL pin strap configuration,

in a given soft-start time, which can be selected by SS pin. See Table 1 for details.

Table 1. SS Pin Configuration

SS TIME (ms)

RESISTOR VALUE (kΩ)⁽¹⁾

0.5

1

0

8.66

15.4

23.7

OPEN

34.8

51.1

78.7

121

2

5

4

8

12

16

24

32

187

(1) The E48 series resistors with no more than 1% tolerance are recommended.

8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection

The provides fixed VIN and VDD undervoltage lockout threshold and hysteresis. The typical VIN turnon threshold

is 3.2 V and hysteresis is 0.2 V. The typical VDD turnon threshold is 3.8 V and hysteresis is 0.2 V. No specific

power-up sequence is required.

8.4.3 Power Good and Enable

The has power-good output that indicates logic high when output voltage is within the target. The power-good

function is activated after soft-start has finished. When the soft-start ramp reaches 90% of setpoint, PGOOD

detection function will be enabled. If the output voltage becomes within ±8% of the target value, internal

comparators detect power-good state and the power good signal becomes high after a delay. If the output

voltage goes outside of ±12% of the target value, the power good signal becomes low after an internal delay.

The power-good output is an open-drain output and must be pulled up externally.

This part has internal pull up for EN. EN is internally pulled up to BP when EN pin is floating. EN can be pulled

low through external grounding. When EN pin voltage is below its threshold, enters into shutdown operation, and

the minimum time for toggle EN to reset is 5 µs.

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8.4.4 Voltage Reference

VSEL pin strap is used to program initial boot voltage value from 0.6 V to 1.1 V by the resistor connected from

VSEL to AGND. The initial boot voltage is used to program the main loop voltage reference point. VSEL voltage

settings provide TI designated discrete internal reference voltages. Table 2 lists internal reference voltage

selections.

Table 2. VSEL Pin Configuration

DEFAULT Vref (V)

RESISTOR VALUE (kΩ)⁽¹⁾

0.6

0.7

0

8.66

15.4

23.7

34.8

51.1

78.7

OPEN

121

0.75

0.8

0.85

0.9

0.95

1.0

1.05

1.1

187

(1) The E48 series resistors with no worse than 1% tolerance are

recommended

8.4.5 Prebiased Output Start-up

The device prevent current from being discharged from the output during start-up, when a pre-biased output

condition exists. No SW pulses occur until the internal soft-start voltage rises above the error amplifier input

voltage, if the output is pre-biased. As soon as the soft-start voltage exceeds the error amplifier input, and SW

pulses start, the device limits synchronous rectification after each SW pulse with a narrow on-time. The low-side

MOSFET on-time slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the

synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of

current from a pre-biased output, and ensures the output voltage start-up and ramp-to regulation sequences are

smooth and monotonic.

8.4.6 Internal Ramp Generator

Internal ramp voltage is generated from duty cycle that contains emulated inductor ripple current information and

then feed it back for control loop regulation and optimization according to required output power stage, duty ratio

and switching frequency. Internal ramp amplitude is set by RAMP pin by adjusting an internal ramp generation

capacitor C_RAMP, selected by the resistor connected from MODE pin to GND. For best performance, we

recommend ramp signal to be no more than 4 times of output ripple signal for all Low ESR output capacitor

(MLCC) applications, or no more than 2 times larger than output ripple signal for regular ESR output capacitor

(Pos-cap) applications. For design recommendation, see the design tool at www.ti.com/WEBENCH.

RAMP

R_RAMP

Duty Cycle

RAMP

SLOPE

Slope

Compensation

10 Selections

C_RAMP

Figure 15. Internal Ramp Generator

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8.4.6.1 Ramp Selections

RAMP pin sets internal ramp amplitude for the control loop. RAMP amplitude is determined by internal RC,

selected by the resistor connected from MODE pin to GND, to optimize the control loop. See Table 3.

Table 3. RAMP Pin-Strapping Selection

C_RAMP(pF)

1

RESISTOR VALUE (kΩ)⁽¹⁾

0

1.42

1.94

2.58

3.43

4.57

6.23

8.91

14.1

29.1

8.66

15.4

23.7

34.8

51.1

78.7

121

187

Open

(1) The E48 series resistors with tolerance of 1% or less are

recommended.

8.4.7 Switching Frequency

The converter supports analog frequency selections from 300 kHz to 2 MHz, for stand alone device and sync

frequency from 300 kHz to 1 MHz for stackable configuration. The RT pin also sets clock sync point (SP) for the

slave device.

Switching Frequency Configuration for Stand-alone and Master Device in Stackable Configuration

Master

MODE

TPS543C20

SYNC

RT

Figure 16. Standalone: RT Pin Sets the Switching Frequency

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Master

Slave

VSHARE

ISHARE

VSHARE

ISHARE

MODE

RT

SYNC

Figure 17. Stackable: Master (as Clock Master) RT Pin Sets Switching Frequency, and passes it to Slave

Resistor R_RTsets the continuous switching frequence selection by

20 ´ 10⁹

¦

´ 2

SW

R_RT

=

-

¦

2000

SW

where

•

R is the resistor from RT pin to GND, in Ω

ƒ_SWis the desired switching frequency, in Hz

(1)

8.4.8 Clock Sync Point Selection

The device implements an unique clock sync scheme for phase interleaving during stackable configuration. The

device will receive the clock through sync pin and generate sync points for another device to sync to one of them

to achieve phase interleaving. Sync point options can be selected through RT pin when 1) device is configurated

as master sync in, 2) device is configured as slave. See Table 5 for control mode selection.

System Clock

or

Master Clock

0

1/2

0

Slave clock

1/2

Figure 18. 2-Phase Stackable with 180° Clock Phase Shift

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Table 4. RT Pin Sync Point Selection

CLOCK SYNC OPTIONS

0 (0° Interleaving)

RESISTOR VALUE (kΩ)

0

1/4 (90° Interleaving)

1/3 (120° Interleaving)

2/3 (240° Interleaving)

3/4 (270° Interleaving)

1/2 (180° Interleaving)

8.66

15.4

23.7

34.8

OPEN

8.4.9 Synchronization and Stackable Configuration

The device can synchronize to an external clock which must be equal to or higher than internal frequency setting.

For stand alone device, the external clock should be applied to the SYNC pin before VDD ramps up. A sudden

change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot

or undershoot on the output voltage.

In dual phase stackable configuration:

1. when there is no external system clock applied, the master device will be configured as clock master,

sending out pre-set switching frequency clock to slave device through SYNC pin. Slave receives this clock as

switching clock with phase interleaving.

2. when a system clock is applied, both master and slave devices will be configured as clock slave, they sync

to the external system clock as switching frequency with proper phase shift

8.4.10 Dual-Phase Stackable Configurations

8.4.10.1 Configuration 1: Master Sync Out Clock-to-Slave

•

Direct SYNC, VSHARE and ISHARE connections between master and slave.

Switching frequency is set by RT pin of master, and pass to slave through SYNC pin. SYNC pin of master will

be configured as sync out by it’s MODE pin.

•

Slave receives clock from SYNC pin. Its RT pin determines the sync point for clock phase shift.

Master

Slave

VSHARE

ISHARE

VSHARE

ISHARE

MODE

23.7 k

F_SW

51.1 k

RT

SYNC

Open

Sync Point

Figure 19. 2-Phase Stackable with 180° Phase Shift: Master Sync Out Clock-to-Slave

8.4.10.2 Configuration 2: Master and Slave Sync to External System Clock

•

Direct connection between external clock and SYNC pin of master and slave.

Direct VSHARE and ISHARE connections between master and slave.

SYNC pin of master is configured as sync in by its MODE pin.

Master and slave receive external system clock from SYNC pin. Their RT pin determine the sync point for

clock phase shift.

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Master

Slave

VSHARE

ISHARE

VSHARE

ISHARE

MODE

34.8 k

51.1 k

Open

RT

SYNC

0 k

Sync Point

System Clock

Figure 20. 2-Phase Stackable with 180° Phase Shift: Master and Slave Sync to External System Clock

8.4.11 Operation Mode

The operation mode and API/body brake feature is set by the MODE pin. They are selected by the resistor

connected from MODE pin to GND. Mode pin sets the device to be stand-alone mode or stackable mode. In

stand-alone mode, MODE pin sets the API on/off or trigger point sensitivity of API (1× stands for most sensitive

and 4× stands for least sensitive). In stackable mode, the MODE pin sets the device as master or slave, as well

as SYNC pin function (sync in or sync out) of the master device.

Table 5. MODE Pin-Strapping Selection

CONTROL MODE

SELECTION

RESISTOR VALUE (kΩ) and API/BB

API/BODY BRAKE

NOTE

Threshold⁽¹⁾

API OFF

BB OFF

Open

API ON

BB OFF

15.4, API = 35 mV

Standalone

API/body brake

•

Sync pin to receive clock

RT pin to set frequency

121, API = 15 mV, BB = 30 mV

187, API = 25 mV, BB = 30 mV

8.66, API = 35 mV, BB = 30 mV

78.7, API = 45 mV, BB = 30 mV

API ON

BB ON

(API Threshold Setting)

•

Sync pin to send out clock

RT pin to set frequency

(Master sync out)

(Master sync in)

(Slave sync In)

23.7

34.8

51.1

API OFF

BB OFF

•

Sync pin to receive clock

RT pin to set sync point

•

Sync pin to receive clock

RT pin to set sync point

(1) The E48 series resistors with tolerance of 1% or less are recommended.

8.4.12 API/Body Brake

is a true fixed frequency converter. The major limitation for any fixed frequency converter is that during transient

load step up, the converter needs to wait for the next clock cycle to response to the load change, depending on

loop bandwidth design and the timing of load transient, this delay time could cause additional output voltage

drop. implements a special circuitry to improve transient performance. During load step up, the converter senses

both the speed and the amplitude of the output voltage change, if the output voltage change is fast and big

enough, the converter will issue an additional PWM pulse before the next available clock cycle to stop output

voltage from further dropping, thus reducing the undershoot voltage.

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During load step-down, implements a body-brake function, that turns off both high-side and lowside FET, and

allows power to dissipate through the low-side body diode, reducing overshoot. This approach is very effective

while having some impact on efficiency during transient. See Figure 21 and Figure 22.

Vout œ API enabled

Vout œ API disabled

Vout œ Body Brake disabled

Vout œ Body Brake enabled

LOAD

Switch Node

Figure 21. Undershoot Comparison with API ON/OFF

Figure 22. Overshoot Comparison with Body Brake

ON/OFF

8.4.13 Sense and Overcurrent Protection

8.4.13.1 Low-Side MOSFET Overcurrent Protection

The utilizes ILIM pin to set the OCP level. The ILIM pin must be connected to AGND through the ILIM voltage

setting resistor, RILIM. The ILIM terminal sources IILIM current, which is around 11.2 μA typically at room

temperature, and the ILIM level is set to the OCP ILIM voltage VILIM as shown in Equation 2. In order to provide

both good accuracy and cost effective solution, supports temperature compensated MOSFET R_DS(on)sensing.

V_ILIMmV = R_ILIM(kW) ì I_ILIM(mA)

(

)

Consider R_DS(on)variation vs VDD in calculation

(2)

Also, performs both positive and fixed negative inductor current limiting.

The inductor current is monitored by the voltage between GND pin and SW pin during the OFF time. ILIM has

1200 ppm/°C temperature slope to compensate the temperature dependency of the R_DS(on). The GND pin is used

as the positive current sensing node.

The device has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF

state and the controller maintains the OFF state during the period that the inductor current is larger than the

overcurrent ILIM level. V_ILIMsets the peak level of the inductor current. Thus, the load current at the overcurrent

threshold, I_OCP, can be calculated as shown in .

I_OCP= V

(16 × R_DS(on)) - I

2

ILIM

IND(ripple)

V

(V_IN- V_OUT) × V_OUT

1

ILIM

=

-

16 × R_DS(on)2 × L × ƒ_SW

×

V

IN

where

•

R_DS(on)is the on-resistance of the low-side MOSFET.

(3)

Equation 3 is valid for VDD ≥ 5 V. Use 0.58 mΩ for R_DS(on)in calculation, which is the pure on-resistance for

current sense.

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If an overcurrent event is detected in a given switching cycle, the device increments an overcurrent counter.

When the device detects three consecutive overcurrent (either high-side or low-side) events, the converter

responds, entering continuous restart hiccup. In continuous hiccup mode, the device implements a 7 soft-start

cycle timeout, followed by a normal soft-start attempt. When the overcurrent fault clears, normal operation

resumes; otherwise, the device detects overcurrent and the process repeats.

8.4.13.2 High-Side MOSFET Overcurrent Protection

The device also implements a fixed high-side MOSFET overcurrent protection to limit peak current, and prevent

inductor saturation in the event of a short circuit. The device detects an overcurrent event by sensing the voltage

drop across the high-side MOSFET during ON state. If the peak current reaches the IHOSC level on any given

cycle, the cycle terminates to prevent the current from increasing any further. High-side MOSFET overcurrent

events are counted. If the devices detect three consecutive overcurrent events (high-side or low-side), the

converter responds by entering continuous restart hiccup.

8.4.14 Output Overvoltage and Undervoltage Protection

The device includes both output overvoltage protection and output undervoltage protection capability. The

devices compare the RSP pin voltage to internal selectable pre-set voltages. If the RSP voltage with respect to

RSN voltage rises above the output overvoltage protection threshold, the device terminates normal switching and

turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output

voltage. Then the device enters continuous restart hiccup.

If the RSP pin voltage falls below the undervoltage protection level, after soft-start has completed, the device

terminates normal switching and forces both the high-side and low-side MOSFETs off, then enters hiccup time-

out delay prior to restart.

8.4.15 Overtemperature Protection

An internal temperature sensor protects the devices from thermal runaway. The internal thermal shutdown

threshold, T_SD, is fixed at 165°C typical. When the devices sense a temperature above T_SD, power conversion

stops until the sensed junction temperature falls by the thermal shutdown hysteresis amount; then, the device

starts up again.

8.4.16 RSP/RSN Remote Sense Function

RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for

output voltage programming, the RSP pin should be connected to the mid-point of the resistor divider and the

RSN pin should always be connected to the load return.

When feedback resistors are not required as when the VSEL programs the output voltage set point, connect the

RSP pin to the positive sensing point of the load and the RSN pin should always be connected to the load return.

RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier.

The feedback resistor divider should use resistor values much less than 100 kΩ. A simple rule of thumb is to use

a 10-kΩ lower divider resistor and then size the upper resistor to achieve the desired ratio.

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TPS543C20

2

1

RSN

RSP

2

1

RSN

RSP

BOOT

5

BOOT

5

Load

+

–

+

–

Figure 23. Remote Sensing With Feedback Resistors

Figure 24. Remote Sensing Without Feedback Resistors

8.4.17 Current Sharing

When devices operate in dual-phase stackable application, a current sharing loop maintains the current balance

between devices. Both devices share the same internal control voltage through VSHARE pin. The sensed

current in each phase is compared first in a current share block by connecting ISHARE pin of each device, then

the error current is added into the internal loop. The resulting voltage is compared with the PWM ramp to

generate the PWM pulse.

8.4.18 Loss of Synchronization

During sync clock condition, each individual converter will continuously compare current falling edge and

previous falling edge, if current falling edge exceeded a 1us delay versus previous pulse, converter will declare a

lost sync fault, and response by pulling down ISHARE to shut down all phases.

Declare fault and take action

Sync fault delay

Switching

pulses

Tp

Tdelay

Tp +

Figure 25. Switching Response When Sync Clock Lost

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS543C20A device is a highly-integrated synchronous step-down DC/DC converter. The device is used to

convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 40 A. Use the

following design procedure to select key component values for this device.

9.2 Typical Application: TPS543C20A Stand-alone Device

PVIN

EN

PGND

PGOOD

PGD

SYNC

VSEL

SS

RT

Thermal Tab

MODE

RAMP

+

-

Figure 26. 4.5-V to 16-V Input, 1-V Output, 40-A Converter

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9.2.1 Design Requirements

For this design example, use the input parameters shown in Table 6.

Table 6. Design Example Specifications

PARAMETER

Input voltage

V_IN(ripple)Input ripple voltage

TEST CONDITION

MIN

TYP

MAX

UNIT

V_IN

4

12

V

I_OUT= A

0.4

V_OUT

Output voltage

0.9

Line regulation

5 V ≤ V_IN≤ 16 V

0 V ≤ I_OUT≤ A

I_OUT= A

0.5%

Load regulation

V_PP

V_OVER

V_UNDER

I_OUT

t_SS

Output ripple voltage

Transient response overshoot

Transient response undershoot

Output current

20

50

mV

A

I_STEP= 10 A

I_STEP= 10A

50

5 V ≤ V_IN≤ 16 V

V_IN= 12 V

35

40

Soft-start time

4

ms

A

I_OC

Overcurrent trip point⁽¹⁾

45

η

Peak efficiency

I_OUT= A, V_IN= 12 V, V_DD= 5 V

90%

500

f_SW

Switching frequency

300

700

kHz

(1) DC overcurrent level

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS543C20A device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Switching Frequency Selection

Select a switching frequency for the TPS543C20A. There is a trade off between higher and lower switching

frequencies. Higher switching frequencies may produce smaller solution size using lower valued inductors and

smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher

switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.

In this design, a moderate switching frequency of 500 kHz achieves both a small solution size and a high

efficiency operation is selected. The device supports continuous switching frequency programming; see

Equation 4. additional considerations (internal ramp compensation) other than switching frequency need to be

included.

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TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

20 ´ 10⁹

500 ´10³

R_RT

=

- 2 ´

= 39.5 kW

500 ´10³

(4)

2000

In this case, a standard resistor value of 40.2 kΩ is selected.

9.2.2.3 Inductor Selection

To calculate the value of the output inductor (L), use Equation 5. The coefficient K_INDrepresents the amount of

inductor-ripple current relative to the maximum output current. The output capacitor filters the inductor-ripple

current. Therefore, selecting a high inductor-ripple current impacts the selection of the output capacitor because

the output capacitor must have a ripple-current rating equal to or greater than the inductor-ripple current.

Generally, the K_INDmust be kept between 0.1 and 0.3 for balanced performance. Using this target ripple current,

the required inductor size can be calculated as shown in .

V_OUT

_IN´ ƒ_SW

V

_IN- V_OUT

1 V ´ (12 V - 1V)

L =

-

=

= 458 nH

V

I

_OUT´KIND

12 V ´ 500 kHz ´ 40 A ´ 0.1

(5)

A standard inductor value of 470 nH is selected. For this application, Wurth 744309047 was used from the web-

orderable EVM.

9.2.2.4 Input Capacitor Selection

The TPS543C20A devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a

value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input

decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high

switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage

ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input

capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating

greater than the maximum input current ripple to the device during full load. The input ripple current can be

calculated using Equation 6.

V -V

V_OUT

(

)

IN OUT

I_CIN(rms)= I_OUT(max)

´

= 16 Arms

V

IN

(6)

The minimum input capacitance and ESR values for a given input voltage ripple specification, V_IN(ripple), are

shown in Equation 7 and Equation 8. The input ripple is composed of a capacitive portion, V_RIPPLE(cap), and a

resistive portion, V_RIPPLE(esr)

.

I_{OUT (max )}× V_OUT

C_{IN(min )}

=

= 38.5 JF

V_RIPPLE

× V

× f

;

IN max SW

:

cap

;

:

(7)

(8)

V_RIPPLE(ESR)

ESR_{CIN (max )}

=

= 7 m3

I_RIPPLE

I_{OUT max}+ @

A

:

;

2

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor

must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at

least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input

ripple for V_RIPPLE(cap), and 0.3-V input ripple for V_RIPPLE(esr). Using Equation 7 and Equation 8, the minimum input

capacitance for this design is 38.5 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25-V

ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the

power stage.

9.2.2.5 Bootstrap Capacitor Selection

A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper

operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with

a voltage rating of 25 V or higher.

26

TPS543C20A

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ZHCSJ36 –NOVEMBER 2018

9.2.2.6 BP Pin

Bypass the BP pin to GND with 4.7-µF of capacitance. In order for the regulator to function properly, it is

important that these capacitors be localized to the TPS543C20A , with low-impedance return paths. See Power

Good and Enable section for more information.

9.2.2.7 R-C Snubber and VIN Pin High-Frequency Bypass

Though it is possible to operate the TPS543C20A within absolute maximum ratings without ringing reduction

techniques, some designs may require external components to further reduce ringing levels. This example uses

two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between

the SW area and GND.

The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the

outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and

discharge once the high-side MOSFET is turned on. For this example twin 2.2-nF, 25-V, 0603-sized high-

frequency capacitors are used. The placement of these capacitors is critical to its effectiveness.

Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF

capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125

W, nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.

9.2.2.8 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

affects three criteria:

•

Stability

Regulator response to a change in load current or load transient

Output voltage ripple

These three considerations are important when designing regulators that must operate where the electrical

conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these

three criteria.

9.2.2.8.1 Response to a Load Transient

The output capacitance must supply the load with the required current when current is not immediately provided

by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects

the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.

Use Equation 9 and Equation 10 to estimate the amount of capacitance needed for a given dynamic load step

and release.

NOTE

There are other factors that can impact the amount of output capacitance for a specific

design, such as ripple and stability.

27

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

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2

L ´ DI_LOAD(max)

DI_LOAD(max)´ 1- D ´ t

SW

(

)

DV_LOAD(INSERT)

C_{OUT(min_under)}

=

+

2 ´ DV_LOAD(INSERT)´ (V -V_VOUT

)

IN

(9)

2

L_OUT

´

DI

LOAD(max)

(

)

2 ´ DV_{LOAD(release)}× V_OUT

C_{OUT(min_over)}

=

where

•

C_{OUT(min_under)}is the minimum output capacitance to meet the undershoot requirement

C_{OUT(min_over)}is the minimum output capacitance to meet the overshoot requirement

D is the duty cycle

L is the output inductance value (0.47 µH)

∆I_LOAD(max)is the maximum transient step (10 A)

V_OUTis the output voltage value (900 mV)

t_SWis the switching period (2 µs)

V_INis the minimum input voltage for the design (12 V)

∆V_LOAD(insert)is the undershoot requirement (50 mV)

∆V_{LOAD(release)}is the overshoot requirement (50 mV)

(10)

•

This example uses a combination of POSCAP and MLCC capacitors to meet the overshoot requirement.

–

POSCAP bank #1: 2 × 330 µF, 2.5 V, 3 mΩ per capacitor

MLCC bank #2: 3 × 100 µF, 6.3 V, 1 mΩ per capacitor

9.2.2.8.2 Ramp Selection Design to Ensure Stability

Certain criteria is recommended for to achieve optimized loop stability, bandwidth and switching jitter

performance. As a rule of thumb, the internal ramp voltage should be 2~4 times bigger than the output capacitor

ripple(capacitive ripple only). is defined to be ease-of-use, for most applications, TI recommends ramp resistor to

be 187 kΩ to achieve the optimized jitter and loop response. For detailed design procedure, see the

WEBENCH® Power Designer.

28

TPS543C20A

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ZHCSJ36 –NOVEMBER 2018

9.2.3 Application Curves

Figure 27. Transient Response of 0.9-V Output at 12-V_IN

,

Figure 28. Output Ripple and SW Node of 0.9-V Output at

12-V_IN, -A Output

Transient is 15 A to 25 A to 15 A,

the Step is 10 A at 40 A/μs

Figure 30. Start up from Control, 0.9-V Output at 12-V_IN

,

Figure 29. Output Ripple and SW Node of 0.9-V Output at

12-V_IN, 0-A Output

10-mA Output

Figure 31. 0.5-V Prebias start up from Control, 0.9-V

Output at 12-V_IN, 20-A Output

Figure 32. Output Voltage Start-up and Shutdown, 0.9-V

Output at 12-V_IN, 0.5-A Output

29

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

9.3 System Example

9.3.1 Two-Phase Stackable

PGND

RAMP

MODE

RT

SS

Slave

VSEL

SYNC

PGD

EN

LOAD

PVIN

+

œ

EN

PGND

PGD

SYNC

VSEL

SS

Master

RT

Thermal Tab

MODE

RAMP

Figure 33. 2-Phase Stackable

See Synchronization and Stackable Configuration section.

30

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

System Example (continued)

9.3.1.1 Application Curves

Figure 35. Transient Response of 25-A to 50-A Load

Figure 34. Transient Response of 0.9-V Output at 12 V_IN

,

Transient is 25 A to 50 A, Step is 25 A at 30 A/μs

at 30 A/μs Rise

Figure 36. Transient Response of 50-A to 25-A Load

Figure 37. Output Ripple and SW Node

of 0.9-V Output at 12 V_IN, -A Output

at 30 A/μs Fall

Figure 39. Start up from Enable,

0.9-V Output at 12 V_IN, 80-A Output

Figure 38. Output Ripple and SW Node

of 0.9-V Output at 12 V_IN, 0-A Output

31

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

System Example (continued)

Figure 40. 0.6-V Pre-Bias Start Up From Enable,

0.9-V Output at 12 V_IN, 0-A Output

Figure 41. Output Voltage Start-up and Shutdown,

0.9-V Output at 12 V_IN, 5-A Output

Figure 42. Master-Slave 180° Synchronization

10 Power Supply Recommendations

This device is designed to operate from an input voltage supply between 4 V and 16 V. Ensure the supply is well

regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance, as is

the quality of the PCB layout and grounding scheme. See the recommendations in Layout.

32

TPS543C20A

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ZHCSJ36 –NOVEMBER 2018

11 Layout

11.1 Layout Guidelines

•

It is absolutely critical that all GND pins, including AGND (pin 29), GND (pin 27), and PGND (pins 13, 14, 15,

16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane.

The number of thermal vias needed to support 40-A thermal operation should be as many as possible; in the

EVM design orderable on the Web, a total of 23 thermal vias are used. The TPS543C20EVM-799 is available

for purchase at ti.com.

•

Place the power components (including input/output capacitors, output inductor, and TPS543C20 device) on

one side of the PCB (solder side). At least one or two innner layers/planes must be inserted, connecting to

power ground, in order to shield and isolate the small signal traces from noisy power lines.

Place the VIN decoupling capacitors as close to the PVIN and PGND as possible to minimize the input AC

current loop. The high frequency decoupling capacitor (1 nF to 0.1 µF) should be placed next to the PVIN pin

and PGND pin as close as the spacing rule allows. This helps surpressing the switch node ringing.

•

Place a 10-nF to 100-nF capacitor close to IC from Pin 25 VIN to Pin 27 GND.

Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane

connection for VDD. VDD needs to be tapped off from PVIN with separate trace connection. Ensure to

provide GND vias for each decoupling capacitor and make the loop as small as possible.

•

The PCB trace defined as switch node, which connects the SW pins and up-stream of the output inductor

should be as short and wide as possible. In web orderable EVM design, the SW trace width is 400 mil. Use

separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these

connections.

All sensitive analog traces and components such as RAMP, RSP, RSN, ILIM, MODE, VSEL and RT should

be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise

coupling. In addition, MODE, VSEL, ILIM, RAMP and RT programming resistors should be placed near the

device/pins.

The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high

impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.

Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit

uses the RSP pin for on-time adjustment. It is critical to tie the RSP pin directly tied to VOUT (load sense

point) for accurate output voltage result.

•

Use caution when routing of the SYNC, VSHARE and ISHARE traces for 2-phase configurations. The SYNC

trace carries a rail-to-rail signal and should be routed away from sensitive analog signals, including the

VSHARE, ISHARE, RT, and FB signals. The VSHARE and ISHARE traces should also be kept away from

fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and BP pins.

33

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

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11.2 Layout Example

Place PVIN bypass

Bypass for internal regulators

BP, VDD. Use multiple vias

to reduce parasitic

capacitors as close as

possible to IC, with best

high frequency capacitor

closest to PVIN/PGND pins

inductance.

10nF to 100nF

at pin 25 and

27

EN

Signal

PVIN

10nF to

100nF at

pin 20 and

21

Internal AGND

Plane to reduce

the BP bypass

parasitics.

PGND

Kelvin Connect to

IC RSP and RSN

pins

EN

PGND

Connect GND to

Thermal Pad

Connect AGND to

Thermal Pad

PGD

SYNC

Thermal Pad

VSEL

SS

RSN

RT

MODE

RAMP

RSNSœ

Place best high

frequency output

capacitor between

AGND and GND

are only

connected

together on

Thermal Pad.

sense point

AGND

RSNS+

CBOOT

RBOOT

Optional RC

Snubber, tight

loop around

RSP

VOUT

pin 12 and 13

Sense point

should be

directly at the

load

L1

Minimize SW

For best efficiency, use a heavy

weight copper and place these

planes on multiple PCB layers

area for least

noise. Keep

sensitive

traces away

from SW and

BOOT on all

layers

图 43. Example Layout

34

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

11.3 Package Size, Efficiency and Thermal Performance

The TPS543C20A device is available in a 5 mm × 7 mm, QFN package with 40 power and I/O pins. It employs

TI proprietary MCM packaging technology with thermal pad. With a properly designed system layout, applications

achieve optimized safe operating area (SOA) performance. The curves shown in and are based on the orderable

evaluation module design.

110

100

90

110

100

90

80

70

60

50

Nat conv

100 LFM

200 LFM

400 LFM

Nat conv

100 LFM

200 LFM

400 LFM

40

30

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

Output Current (A)

D012

D011

V_IN= 12 V

V_OUT= 5 V

图 44. Safe Operating Area

500 kHz

V_IN= 12 V

V_OUT= 1 V

图 45. Safe Operating Area

500 kHz

图 46. Thermal Image at 1.0-V Output at 12 V_IN, 40-A Output, at 25°C Ambient

35

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

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Package Size, Efficiency and Thermal Performance (接下页)

t_P

T_P

T_L

T_S(max)

T_S(min)

t_L

r_RAMP(up)

r_RAMP(down)

t_S

t_25P

Time (s)

25

图 47. Recommended Reflow Oven Thermal Profile

表 7. Recommended Thermal Profile Parameters

PARAMETER

MIN

TYP

MAX UNIT

RAMP UP AND RAMP DOWN

r_RAMP(up)

Average ramp-up rate, T_S(MAX)to T_P

3

6

°C/s

r_RAMP(down)Average ramp-down rate, T_Pto T_S(MAX)

PRE-HEAT

T_S

Pre-heat temperature

150

60

200

180

°C

s

t_S

Pre-heat time, T_S(min) to T_S(max)

REFLOW

T_L

T_P

t_L

Liquidus temperature

217

°C

s

Peak temperature

260

150

40

Time maintained above liquidus temperature, T_L

Time maintained within 5°C of peak temperature, T_P

Total time from 25°C of peak temperature, T_P

60

20

t_P

s

t_25P

480

s

36

TPS543C20A

www.ti.com.cn

ZHCSJ36 –NOVEMBER 2018

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 TPS543C20A 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

12.1.2 文档支持

12.1.2.1 相关文档

请参阅如下相关文档：

《TPS543C20A 40A 单相同步降压转换器》

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

NexFET, PowerStack, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

37

TPS543C20A

ZHCSJ36 –NOVEMBER 2018

www.ti.com.cn

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

38

PACKAGE OUTLINE

RVF0040A

LQFN-CLIP - 1.52 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

A

B

PIN 1 INDEX AREA

7.1

6.9

C

1.52

1.32

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.3 0.1

EXPOSED

THERMAL PAD

36X 0.5

13

20

12

21

41

SYMM

2X

5.3 0.1

5.5

32

1

0.3

40X

0.2

40

33

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

40X

4222989/B 10/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220.

www.ti.com

EXAMPLE BOARD LAYOUT

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.3)

6X (1.4)

40

33

40X (0.6)

1

32

40X (0.25)

2X

(1.12)

36X (0.5)

6X

(1.28)

(6.8)

(5.3)

41

SYMM

(R0.05) TYP

(

0.2) TYP

VIA

12

21

13

20

SYMM

(4.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222989/B 10/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.815) TYP

40

33

40X (0.6)

1

41

32

40X (0.25)

(1.28)

TYP

36X (0.5)

(0.64)

TYP

SYMM

(6.8)

(R0.05) TYP

8X

(1.08)

12

21

METAL

TYP

20

13

8X (1.43)

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

71% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4222989/B 10/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

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型号：	TPS543C20ARVFR
厂家：	TEXAS INSTRUMENTS
描述：	具有自适应内部补偿功能的 4V 至 16V、40A 同步 SWIFT™ 降压转换器 \| RVF \| 40 \| -40 to 125 转换器
文件：	总46页 (文件大小：6161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS543C20ARVFR [TI]

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