TPS54424 [TI]

4.5V 至 17V 输入、电流模式、4A SWIFT™ 同步降压转换器;


型号：	TPS54424
厂家：	TEXAS INSTRUMENTS
描述：	4.5V 至 17V 输入、电流模式、4A SWIFT™ 同步降压转换器转换器
文件：	总41页 (文件大小：2102K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS54424

ZHCSGK1 –JULY 2017

具有电流模式控制的 TPS54424 4.5V 至 17V 输入、4A 同步 SWIFT™ 降

压转换器

1 特性

3 说明

•

小型 3.5mm x 3.5mm HotRod™四方扁平无引线

(QFN) 封装

TPS54424 是一款全功能 17V、4A 同步降压直流/直流

转换器，采用了 3.5mm x 3.5mm HotRod™QFN 封

装。

•

集成的 14.1mΩ 和 6.1mΩ MOSFET

峰值电流模式控制，提供快速瞬态响应

200kHz 至 1.6MHz 的固定开关频率

与外部时钟同步

该器件专门进行了优化，具有高效率并集成了高侧和低

侧 MOSFET，适用于小型解决方案。它还通过使用峰

值电流模式控制（可减少组件数量）并选择高开关频率

（缩小电感器尺寸）进一步节省了空间。

0.6V 电压基准，在广泛的温度范围内提供 ±0.85%

的精度

•

输出电压范围：0.6V 至 12V

断续电流限制

峰值电流模式控制简化了环路补偿并可提供快速瞬态响

应。在器件过载的情况下，针对高侧和低侧拉电流限制

的逐周期峰值电流限制功能可保护器件。断续模式可在

短路或者过载故障持续存在的情况下限制 MOSFET 功

率损耗。

安全启动至预偏置输出电压

可调软启动和电源排序

可调节输入欠压锁定

3µA 关断电流

电源正常监控电路会对稳压器输出进行监控。PGOOD

引脚是一个开漏输出，会在输出电压调节过程中进入高

阻抗。除非出现故障，否则内部抗尖峰脉冲时间会阻止

拉低 PGOOD 引脚。

针对欠压及过压的电源良好输出监控

输出过压保护

非锁存热关断保护

运行结温范围：-40°C 至 150°C

使用 TPS54424 并借助 WEBENCH^®电源设计器

创建定制设计方案

专用 EN 引脚可以用于控制稳压器开/关，并且调整输

入欠压锁定。输出电压启动斜坡由 SS/TRK 引脚控

制，该引脚既支持独立电源运行，又支持跟踪模式。

2 应用

器件信息₍₁₎

•

电信和无线基础设施

器件型号

TPS54424

封装

RNV (18)

封装尺寸（标称值）

测试和测量

医疗成像设备

企业交换

3.50mm x 3.50mm

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

服务器

简化电路原理图

效率

TPS54424

BOOT

C_BT

100

L_O

V_OUT

V_IN

VIN

C_I

C_O

R_FBT

PGOOD

SS/TRK

RT/CLK

COMP

R_FBB

C_SS

AGND

R_C

C_Z

R_T

PGND

5 V to 1.8 V, 700 kHz, 1.8 µH, 18 mW

C_P

9 V to 1.8 V, 700 kHz, 1.8 µH, 18 mW

12 V to 1.8 V, 700 kHz, 1.8 µH, 18 mW

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output Current (A)

D001

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDV8

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application ................................................. 23

Power Supply Recommendations...................... 32

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 7

6.7 Timing Requirements................................................ 7

6.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 32

10.1 Layout Guidelines ................................................. 32

10.2 Layout Example .................................................... 32

10.3 Alternate Layout Example..................................... 34

11 器件和文档支持 ..................................................... 35

11.1 文档支持................................................................ 35

11.2 接收文档更新通知 ................................................. 35

11.3 社区资源................................................................ 35

11.4 商标....................................................................... 35

11.5 静电放电警告......................................................... 35

11.6 Glossary................................................................ 35

12 机械、封装和可订购信息....................................... 35

4 修订历史记录

日期

修订版本

注意

2017 年 7 月

初始发行版。

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

5 Pin Configuration and Functions

RNV Package

18-Pin VQFN-HR

Top View

Bottom View

BOOT 1

VIN 2

12 AGND

AGND 12

1 BOOT

2 VIN

11 VIN

VIN 11

PGND 3

PGND 4

PGND 5

10 PGND

9 PGND

8 PGND

PGND 10

PGND 9

PGND 8

3 PGND

4 PGND

5 PGND

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Floating supply voltage for high-side MOSFET gate drive circuit. Connect a 0.1-µF ceramic

capacitor between BOOT and SW pins.

BOOT

Input voltage supply pin. Power for the internal circuit and the connection to drain of high-

side MOSFET. Connect both pins to the input power source with a low impedance

connection. Connect both pins and their neighboring PGND pins.

VIN

2, 11

3, 4, 5, 8, 9,

PGND

–

Ground return for low-side power MOSFET and its drivers.

Switching node. Connected to the source of the high-side MOSFET and drain of the low-side

MOSFET.

6, 7

–

AGND

RT/CLK

Ground of internal analog circuitry. AGND must be connected to the PGND plane.

Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching

frequency. In CLK mode, the device synchronizes to an external clock input to this pin.

Converter feedback input. Connect to the output voltage with a resistor divider.

Error amplifier output and input to the PWM modulator. Connect loop compensation to this

pin.

COMP

Soft-start and tracking pin. Connecting an external capacitor sets the soft-start time. This pin

can also be used for tracking and sequencing.

SS/TRK

Enable pin. Float or pull high to enable the device. Connect a resistor divider to this pin to

implement adjustable under voltage lockout and hysteresis.

Open-drain power good indicator. It is asserted low if output voltage is outside if the PGOOD

thresholds, VIN is low, EN is low, device is in thermal shutdown or device is in soft-start.

PGOOD

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VIN

–0.3

–1

BOOT

BOOT (10 ns transient)

Voltage

BOOT (vs SW)

SW (10 ns transient)

–3

EN, SS/TRK, PGOOD, RT/CLK, FB, COMP

–0.3

-40

6.5

150

Operating Junction Temperature Range, T_J

Storage Temperature Range, T_STG

°C

-55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Parameter

MIN

4.5

NOM

MAX

UNIT

V_IN

Input voltage range

Output Voltage

V_OUT

I_OUT

T_J

0.6

Output current

Operating junction temperature

-40

150

1600

°C

kHz

f_SW

Switching Frequency (RT mode and PLL

mode)

200

6.4 Thermal Information

TPS54424

THERMAL METRIC⁽¹⁾

RNV

18 PINS

57.1

UNIT

Theta_JA

Theta_JCtop

Theta_JB

Psi_JT

Junction-to-ambient thermal resistance JEDEC

°C/W

Junction-to-ambient thermal resistance EVM

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.3

18.8

0.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Psi_JB

18.8

1.2

Theta_JCbot

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

T_J= -40°C to 150°C, VIN = 4.5 V to 17 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE

UVLO_rise

UVLO_fall

UVLO_hys

Ivin

V_(VIN)rising

V_(VIN)falling

4.1

3.9

0.2

580

4.3

VIN under-voltage lockout

3.7

Hysteresis VIN voltage

V_(EN)= 5 V, V_(FB)= 1.5 V

V_(EN)= 0 V

Operating non-switching supply current

Shutdown supply current

800

µA

Ivin_sdn

ENABLE

Ven_rise

Ven_fall

Ven_hys

V_(EN)rising

V_(EN)falling

1.20

1.15

1.26

EN threshold

1.1

EN pin threshold voltage hysteresis

EN pin sourcing current

µA

V_(EN)= 1.1V

V_(EN)= 1.3V

1.2

Iph

EN pin sourcing current

4.8

EN pin hysteresis current

3.6

T_J= 25°C

596

595

600

604

605

V_FB

Regulated FB voltage

ERROR AMPLIFIER

gmea

Error Amplifier Transconductance (gm)

–2 µA < I_(COMP)< 2 µA, V_(COMP)= 1 V

1100

µA/V

Error Amplifier DC gain

Icomp_src

Icomp_snk

gmps

Error Amplifier source current

Error Amplifier sink current

Power Stage Transconductance

V_(FB)= 0 V

V_(FB)= 2 V

100

-100

µA

A/V

SOFT-START

Iss

Soft-start current

µA

V_(SS/TRK)to V_(FB)matching

V_(SS/TRK)= 0.4 V

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

Electrical Characteristics (continued)

T_J= -40°C to 150°C, VIN = 4.5 V to 17 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MOSFET

T_A= 25°C, V_(VIN)= 12 V

14.1

15.9

6.1

mΩ

Rds(on)_h

High-side switch resistance

T_A= 25°C, V_(VIN)= 4.5 V, V_(BOOT-SW)= 4.5 V

T_A= 25°C, V_(VIN)= 12 V

Rds(on)_l

Low-side switch resistance

BOOT UVLO Falling

T_A= 25°C, V_(VIN)= 4.5 V

6.9

2.2

2.6

8.5

7.3

CURRENT LIMIT

Ioc_HS_pk

Ioc_LS_snk

Ioc_LS_src

RT/CLK

High-side peak current limit

Low-side sinking current limit

Low-side sourcing current limit

V_(VIN)= 12 V

5.6

4.8

6.8

-3.4

6.2

V_IH

Logic high input voltage

Logic low input voltage

V_IL

0.8

PGOOD

V_(FB)rising (fault)

V_(FB)falling (good)

V_(FB)rising (good)

V_(FB)falling (fault)

108

106

Power good threshold

Leakage current into PGOOD pin when

pulled high

Ipg_lkg

V_(PGOOD)= 5 V

Vpg_low

PGOOD voltage when pulled low

Minimum VIN for valid output

I_(PGOOD)= 2 mA

0.3

V_(PGOOD)< 0.5 V, I_(PGOOD)= 4 mA

0.7

Thermal protection

T_TRIP

Thermal protection trip point

Thermal protection hysteresis

Temperature Rising

170

°C

T_HYST

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

6.6 Switching Characteristics

T_J= -40°C to 150°C, V_(VIN)= 4.5 V to 17 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EN to start of switching

135

µs

PGOOD

Deglitch time PGOOD going high

Deglitch time PGOOD going low

272

Cycles

Measured at 50% to 50% of V_IN, L = 1.5 µH,

I_OUT= 0 A

(1)

ton_min

Minimum on time

130

(2)

toff_min

RT/CLK

fsw_min

Minimum off time

V_(BOOT-SW)≥ 2.6 V

Minimum switching frequency (RT mode)

Switching frequency (RT mode)

R_(RT/CLK)= 250 kΩ

R_(RT/CLK)= 100 kΩ

R_(RT/CLK)= 30.1 kΩ

200

500

1.6

kHz

MHz

450

200

550

fsw_max

fsw_clk

Maximum switching frequency (RT mode)

Switching frequency synchronization range

(PLL mode)

1600

kHz

RT/CLK falling edge to SW rising edge

delay (PLL mode)

Measure at 500kHz with RT resistor in

series with RT/CLK

HICCUP

Wait time before hiccup

Hiccup time before restart

512

Cycles

16384

(1) Characterized. Not production tested.

(2) Specified by design.

6.7 Timing Requirements

T_J= -40°C to 150°C, V_(VIN)= 4.5 V to 17 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

Minimum synchronization signal pulse width

(PLL mode)

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

6.8 Typical Characteristics

100

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 9 V

V_IN= 12 V

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

Output Current (A)

f_SW= 800 kHz

L = 2.2 µH

Output Current (A)

f_SW= 700 kHz

L = 2.2 µH

D002

D003

V_OUT= 5 V

T_A= 25 °C

V_OUT= 3.3 V

T_A= 25 °C

WE 744311220

DCR = 11.4 mΩ

WE 744311220

DCR = 11.4 mΩ

图 1. Efficiency for 5 V Output

图 2. Efficiency for 3.3 V Output

100

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

Output Current (A)

f_SW= 700 kHz

L = 2.2 µH

Output Current (A)

f_SW= 700 kHz

L = 1.8 µH

D004

D006

V_OUT= 2.5 V

T_A= 25 °C

V_OUT= 1.5 V

T_A= 25 °C

WE 744311220

DCR = 11.4 mΩ

WE 74438357018

DCR = 18 mΩ

图 3. Efficiency for 2.5 V Output

图 4. Efficiency for 1.5 V Output

100

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 5 V, f_SW= 600 kHz

V_IN= 9 V, f_SW= 600 kHz

V_IN= 12 V, f_SW= 500 kHz

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

Output Current (A)

f_SW= 600 kHz

L = 1.2 µH

Output Current (A)

D007

D008

V_OUT= 1.2 V

T_A= 25 °C

V_OUT= 1.0 V

T_A= 25 °C

WE 74438357012

DCR = 13.4 mΩ

WE 74438357012

L = 1.2 µH

DCR = 13.4 mΩ

图 5. Efficiency for 1.2 V Output

图 6. Efficiency for 1.0 V Output

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

Typical Characteristics (接下页)

620

V_IN= 4.5 V

V_IN= 12 V

V_IN= 17 V

V_IN= 4.5 V

V_IN= 12 V

V_IN= 17 V

610

600

590

580

570

560

550

540

530

520

510

500

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (

èC)

Junction Temperature (èC)

D005

D006

V_(EN)= 5 V

V_(FB)= 0.8 V

V_(EN)= 0.4 V

图 7. VIN Pin Nonswitching Supply Current vs Junction

图 8. VIN Pin Shutdown Current vs Junction Temperature

Temperature

1.22

5.5

1.21

1.2

4.5

1.19

1.18

1.17

1.16

1.15

1.14

1.13

1.12

3.5

2.5

V_(EN)= 1.1 V

V_(EN)= 1.3 V

1.5

EN Rising

EN Falling

0.5

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D007

D0087

图 9. EN Pin Voltage Threshold vs Junction Temperature

图 10. EN Pin Current vs Junction Temperature

0.605

High-side, V_(BOOT-SW)= 4.5 V

High-side, V_(VIN)= 12 V

Low-side, V_(VIN)= 4.5 V

Low-side, V_(VIN)= 12 V

0.604

0.603

0.602

0.601

0.6

0.599

0.598

0.597

0.596

0.595

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (

Junction Temperature (èC)

D009

D010

图 11. Regulated FB Voltage vs Junction Temperature

图 12. MOSFET Rds(on) vs Junction Temperature

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

Typical Characteristics (接下页)

1400

1350

1300

1250

1200

1150

1100

1050

1000

950

900

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

Ambient Temperature (èC)

D011

D009

图 13. Error Amplifier Transconductance vs Junction

图 14. COMP to SW Transconductance vs Junction

Temperature

5.3

5.25

5.2

5.15

5.1

5.05

4.95

4.9

4.85

4.8

4.75

4.7

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D013

D014

V_(SS/TRK)= 0.4 V

图 15. SS/TRK Current vs Junction Temperature

图 16. SS/TRK to FB Offset vs Junction Temperature

0.7

0.65

0.6

V_IN= 4.5 V

V_IN= 12 V

V_IN= 17 V

7.75

7.5

7.25

0.55

0.5

0.45

0.4

0.35

0.3

6.75

6.5

6.25

0.25

0.2

0.15

0.1

0.05

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50

-25

100

125

150

V_(SS/TRK)(V)

Junction Temperature (èC)

D022

D010

图 17. FB voltage vs SS/TRK Voltage

图 18. High-side Peak Current Limit vs Junction

Temperature

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

Typical Characteristics (接下页)

110

108

106

104

102

100

1100

1000

900

800

700

600

500

400

300

200

100

V_(FB)falling (fault)

V_(FB)rising (good)

V_(FB)rising (fault)

V_(FB)falling (good)

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D016

D017

V_(FB)= 0.6 V

V_(PGOOD)= 5 V

图 19. PGOOD Thresholds vs Junction Temperature

图 20. PGOOD Leakage Current vs Junction Temperature

110

105

100

520

515

510

505

500

495

490

485

480

I_OUT= 0 A

I_OUT= 0.1 A

I_OUT= 0.5 A

-50

-25

100

125

150

-50

-25

100

125

150

Ambient Temperature (èC)

Junction Temperature (èC)

D020

D011

R_(RT/CLK)= 100 kΩ

V_IN= 12 V

L = 1.5 µH

图 22. Switching Frequency vs Junction Temperature (500

图 21. Minimum on-time vs Ambient Temperature

kHz)

650

600

550

500

450

400

350

300

250

200

1660

1650

1640

1630

1620

1610

1600

1590

1580

1570

1560

1550

1540

-50

-25

100

125

150

100 120 140 160 180 200 220 240 260

Junction Temperature (èC)

R_(RT/CLK)(kW)

D021

D023

R_(RT/CLK)= 30.1 kΩ

图 23. Switching Frequency vs Junction Temperature (1600

图 24. Switching Frequency vs RT/CLK Resistor (Low

kHz)

Range)

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

Typical Characteristics (接下页)

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

25 30 35 40 45 50 55 60 65 70 75 80 85

R_(RT/CLK)(kW)

D024

图 25. Switching Frequency vs RT/CLK Resistor (High Range)

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

7 Detailed Description

7.1 Overview

The TPS54424 is a 17-V, 4-A, synchronous step-down (buck) converter with two integrated n-channel

MOSFETs. To improve performance during line and load transients the device implements a constant frequency,

peak current mode control which also simplifies external frequency compensation. The wide switching frequency

of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components.

The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The TPS54424 also has an

internal phase lock loop (PLL) connected to the RT/CLK pin that can be used to synchronize the switching cycle

to the falling edge of an external system clock.

The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 4

amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. The device

reduces the external component count by integrating a bootstrap recharge circuit. The bias voltage for the

integrated high-side MOSFET is supplied by a capacitor between the BOOT and SW pins. The BOOT capacitor

voltage is monitored by a BOOT to SW UVLO (BOOT-SW UVLO) circuit allowing SW pin to be pulled low to

recharge the BOOT capacitor. The device can operate at 100% duty cycle as long as the BOOT capacitor

voltage is higher than the preset BOOT-SW UVLO threshold which is typically 2.2 V.

The TPS54424 has been designed for safe monotonic startup into pre-biased loads. The default start up is when

VIN is typically 4.1 V. The EN pin has an internal pull-up current source that can be used to adjust the input

voltage under voltage lockout (UVLO) with two external resistors. In addition, the internal pull-up current of the

EN pin allows the device to operate with the EN pin floating. The operating current for the TPS54424 is typically

580 μA when not switching and under no load. When the device is disabled, the supply current is typically 3 μA.

The SS/TRK (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing

during power up. A small value capacitor or resistor divider should be coupled to the pin for soft start or critical

power supply sequencing requirements. The output voltage can be stepped down to as low as the 0.6 V voltage

reference (V_REF). The device has a power good comparator (PGOOD) with hysteresis which monitors the output

voltage through the FB pin. The PGOOD pin is an open drain MOSFET which is pulled low when the FB pin

voltage is less than 89% or greater than 108% of the reference voltage V_REFand asserts high when the FB pin

voltage is 91% to 106% of V_REF

The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes

excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.

When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning

on until the FB pin voltage is lower than 106% of the V_REF. The device implements both high-side MOSFET over

current protection and bidirectional low-side MOSFET over current protections which help control the inductor

current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal

shutdown trip point. The device is restarted under control of the soft start circuit automatically when the junction

temperature drops 15°C typically below the thermal shutdown trip point.

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7.2 Functional Block Diagram

PGOOD

VIN

Thermal

Shutdown

UVLO

Shutdown

Enable

Comparator

Shutdown

Logic

Hiccup

Shutdown

Enable

Threshold

BOOT

Charge

Minimum

Clamp

Pulse Skip

Current

Sense

ERROR

AMPLIFIER

BOOT

Boot

UVLO

SS/TRK

HS MOSFET

Current

Comparator

Voltage

Reference

Power Stage

& Deadtime

Control

Logic

Slope

Compensation

VIN

Regulator

Hiccup

Shutdown

Oscillator

with PLL

Maximum

Clamp

Overload

Recovery

MOSFET

Current

Limit

Current

Sense

PGND

COMP

RT/CLK

AGND

7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The device uses an adjustable fixed frequency, peak current mode control. The output voltage is compared

through external resistors on the FB pin to an internal voltage reference by an error amplifier which drives the

COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is

converted into a current reference which compares to the high-side power switch current. When the power switch

current reaches current reference generated by the COMP voltage level the high-side power switch is turned off

and the low-side power switch is turned on.

The device adds an internal slope compensation ramp to prevent subharmonic oscillations. The peak inductor

current limit remains constant over the full duty cycle range.

7.3.2 Continuous Conduction Mode Operation (CCM)

As a synchronous buck converter, the device works in CCM (Continuous Conduction Mode) under all load

conditions.

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Feature Description (接下页)

7.3.3 VIN Pins and VIN UVLO

The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power

converter system. The input voltage for VIN can range from 4.5 V to 17 V. The device implements internal UVLO

circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO

threshold. The internal VIN UVLO threshold has a hysteresis of 200 mV. A voltage divider connected to the EN

pin can adjust the input voltage UVLO appropriately. See Enable and Adjustable UVLO for more details.

7.3.4 Voltage Reference and Adjusting the Output Voltage

The voltage reference system produces a precise ±0.85%, 0.6 V voltage reference over temperature by scaling

the output of a temperature stable band gap circuit. The output voltage is set with a resistor divider from the

output (V_OUT) to the FB pin shown in 图 26. It is recommended to use 1% tolerance or better divider resistors.

Start with a fixed value for the bottom resistor in the divider, typically 10 kΩ, then use 公式 1 to calculate the top

resistor in the divider. To improve efficiency at light loads consider using larger value resistors. If the values are

too high the regulator is more susceptible to noise and voltage errors from the FB input current are noticeable.

The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high

side MOSFET and bootstrap voltage (BOOT-SW voltage) respectively.

V_OUT

TPS54424

R_FBT

0.6 V

R_FBB

图 26. FB Resistor Divider

≈

∆

’

V_OUT

V_REF

R_FBT= R_FBB

-1

◊

(1)

7.3.5 Error Amplifier

The device uses a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower

of the SS/TRK pin voltage or the internal 0.6-V voltage reference. The transconductance of the error amplifier is

1100 μA/V. The frequency compensation network is connected between the COMP pin and ground.

When operating at current limit the COMP pin voltage is clamped to a maximum level to improve response when

the load current decreases. When FB is greater than the internal voltage reference or SS/TRK the COMP pin

voltage is clamped to a minimum level and the devices enters a high-side skip mode.

7.3.6 Enable and Adjustable UVLO

The EN pin provides on/off control of the device. Once the EN pin voltage exceeds its threshold voltage, the

device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching

and enters low operating current state. The EN pin has an internal pull-up current source, Ip, allowing the user to

float the EN pin for enabling the device. If an application requires controlling the EN pin, an open drain or open

collector output logic can be interfaced with the pin.

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Feature Description (接下页)

An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown

in 图 27. The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no

external components are connected. The pull-up current is also used to control the voltage hysteresis for the

UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can

be calculated using 公式 2 and 公式 3. When using the adjustable UVLO function, 500 mV or greater hysteresis

is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN

pin to ground to filter any glitches on the input voltage.

TPS54424

VIN

I_p

I_h

R_ENT

R_ENB

图 27. Adjustable UVLO Using EN

≈

∆

’

V_ENFALLING

V_START

- V

STOP

V_{ENRISING ◊}

R_ENT

≈

’

V_ENFALLING

I ì 1-

∆

V_{ENRISING ◊}

(2)

(3)

vertical spacer

R_ENTì V_ENFALLING

R_ENB

V_STOP- V_ENFALLING+ R_ENTì I +I

(

)

7.3.7 Soft Start and Tracking

The TPS54424 regulates to the SS/TRK pin while its voltage is lower than the internal reference to implement

soft start. A capacitor on the SS/TRK pin to ground sets the soft start time. The SS/TRK pin has an internal pull-

up current source of 5 μA that charges the external soft start capacitor. 公式 4 calculates the required soft start

capacitor value. The FB voltage will follow the SS/TRK pin voltage with a 25 mV offset up to 90% of the internal

voltage reference. When the SS/TRK voltage is greater than 90% of the internal reference voltage the offset

increases as the effective system reference transitions from the SS/TRK voltage to the internal voltage reference.

I_SSµA ì t

(

)

(

)

= 8.3ì t_SSms

C_SSnF =

(

)

(

)

V_REF

(

)

(4)

If during normal operation, VIN goes below the UVLO, EN pin pulled below 1.15 V, or a thermal shutdown event

occurs, the TPS54424 stops switching and the SS/TRK pin floats. When the VIN goes above UVLO, EN goes

above 1.20 V, or a thermal shutdown is exited, the SS/TRK pin is discharged to near ground before reinitiating a

powering up sequence.

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Feature Description (接下页)

When the COMP pin voltage is clamped by the maximum COMP clamp in an overload condition the SS/TRK pin

is discharged to near the FB voltage. When the overload condition is removed, the soft-start circuit controls the

recovery from the fault output level to the nominal output regulation voltage. At the beginning of recovery a spike

in the output voltage may occur while the COMP voltage transitions from the maximum clamp to the value

determined by the loop.

7.3.8 Safe Start-up into Pre-Biased Outputs

The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During

monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TRK pin voltage is

higher than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if the BOOT-

SW voltage is below the UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed to turn on

to charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another layer of

protection for the device after the high-side MOSFET begins to switch.

7.3.9 Power Good

The PGOOD pin is an open-drain output requiring an external pull-up resistor to output a high signal. Once the

FB pin is between 91% and 106% of the internal voltage reference and SS/TRK is greater than 0.75 V, after a

272 cycle deglitch time the PGOOD pin is de-asserted and the pin floats. A pull-up resistor between the values of

10 kΩ and 100 kΩ to a voltage source that is 6.5 V or less is recommended. PGOOD is in a defined state once

the VIN input voltage is greater than 1 V but with reduced current sinking capability.

When the FB is lower than 89% or greater than 108% of the nominal internal reference voltage, after a 16 cycle

deglitch time the PGOOD pin is pulled low. PGOOD is immediately pulled low if VIN falls below its UVLO, EN pin

is pulled low or the TPS54424 enters thermal shutdown.

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Feature Description (接下页)

7.3.10 Sequencing (SS/TRK)

Many of the common power supply sequencing methods can be implemented using the SS/TRK, EN and

PGOOD pins.

The sequential method is illustrated in 图 28 using two TPS54424 or similar devices. The power good of the first

device is coupled to the EN pin of the second device which enables the second power supply once the primary

supply reaches regulation.

图 29 shows the method implementing ratiometric sequencing by connecting the SS/TRK pins of two devices

together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start

time the current source must be doubled in 公式 4.

TPS54424

PGOOD

TPS54424

SS/TRK

PGOOD

SS/TRK

PGOOD

TPS54424

SS/TRK

PGOOD

图 28. Sequential Start-Up Sequence

图 29. Ratiometric Start-Up Sequence

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Feature Description (接下页)

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network

of R_TRTand R_TRBshown in 图 30 to the output of the power supply that needs to be tracked or another voltage

reference source. Using 公式 6 and 公式 7, the tracking resistors can be calculated to initiate the V_OUT2slightly

before, after or at the same time as V_OUT1. 公式 5 is the voltage difference between V_OUT1and V_OUT2

To design a ratiometric start-up in which the V_OUT2voltage is slightly greater than the V_OUT1voltage when V_OUT2

reaches regulation, use a negative number in 公式 6 and 公式 7 for deltaV. 公式 5 results in a positive number

for applications where the V_OUT2is slightly lower than V_OUT1when V_OUT2regulation is achieved.

The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TRK to

FB offset (Vssoffset = 25 mV) in the soft-start circuit and the offset created by the pull-up current source (Iss = 5

μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.

To ensure proper operation of the device, the calculated R_TRTvalue from 公式 6 must be greater than the value

calculated in 公式 8.

DV = V_OUT1- V_OUT2

(5)

vertical spacer

V_OUT2+ DV

Vssoffset

Iss

R_TRT

vertical spacer

R_TRB

V_REF

(6)

V_REFìR_TRT

V_OUT2+ DV - V_REF

(7)

(8)

vertical spacer

R_TRT> 2800ì V_OUT1-180ì DV

TPS54424

V_OUT1

SS/TRK

PGOOD

TPS54424

V_OUT2

R_TRT

SS/TRK

PGOOD

R_FBT

R_FBB

R_TRB

图 30. Ratiometric and Simultaneous Start-Up Sequence

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Feature Description (接下页)

7.3.11 Adjustable Switching Frequency (RT Mode)

In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and AGND. The switching frequency

of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 250 kΩ and minimum of 30.1 kΩ

respectively. To determine the RT resistance for a given switching frequency, use 公式 9. To reduce the solution

size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and

minimum controllable on-time should be considered. 公式 10 can be used to calculate the switching frequency for

a given RT resistance.

-1.028

RT kW = 58650 ì f

kHz

(

)

(

)

(9)

vertical spacer

f_SWkHz = 43660 ìRT kW

-0.973

(

)

(

)

(10)

7.3.12 Synchronization (CLK Mode)

An internal Phase Locked Loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz,

and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square

wave clock signal to the RT/CLK pin with a duty cycle from 20% to 80%. If the clock signals rising edge occurs

near the falling edge of SW, increased SW jitter may occur. Use 公式 11 to calculate the maximum clock pulse

width to minimize jitter in CLK mode. The clock signal amplitude must transition lower than 0.8 V and higher than

2 V. The start of the switching cycle is synchronized to the falling edge of the RT/CLK pin.

OUT

0.75´ 1-

IN min

(

)

CLK _PW

MAX

(11)

In applications where both RT mode and CLK mode are needed, the device can be configured as shown in 图

31. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT

resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin

is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and

the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock.

If the input clock goes away the internal clock frequency begins to drop and after 10 µs without a clock the

device returns to RT mode. Output undershoot while the switching frequency drops can occur. Output overshoot

can also occur when the switching frequency steps back up to the RT mode frequency. A high impedance tri-

state buffer as shown in 图 33 is recommended for best performance during the transition from CLK mode to RT

mode because it minimizes the loading on the RT/CLK pin allowing faster transition back to RT mode. 图 34

shows the typical performance for the transition from RT mode to CLK mode then back to RT mode.

A series RC circuit as shown in 图 32 can also be used to interface the RT/CLK pin but the capacitive load slows

down the transition back to RT mode. The series RC circuit is not recommended if the transition from CLK mode

to RT mode is important. A capacitor in the range of 47 pF to 470 pF is recommended. When using the series

RC circuit verify the amplitude of the signal at the RT/CLK pin goes above the high threshold.

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Feature Description (接下页)

RT/CLK Mode Select

TPS54424

RT/CLK

2 kꢀ

47 pF

R_T

图 31. Simplified Circuit When Using Both RT Mode 图 32. Interfacing to the RT/CLK Pin with Series RC

and CLK Mode

TPS54424

RT/CLK

CH2: VOUT DC OFFSET

R_T

CH3: RT/CLK

CH1: SW

V_IN= 12 V, I_OUT= 4 A,

V_OUT= 3.3 V, fsw = 1.2 MHz

图 33. Interfacing to the RT/CLK Pin with Buffer

图 34. RT to CLK to RT Transition with Buffer

7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)

The device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW

pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the low-

side MOSFET is on. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R

or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over

temperature and voltage.

When operating with a low voltage difference from input to output, the high side MOSFET of the device will

operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.2 V. The device will begin

to transition to 100% duty cycle operation when the high-side MOSFET off-time is less than 200 ns typical. When

the voltage from BOOT to SW drops below 2.2 V, the high-side MOSFET is turned off due to BOOT UVLO and

the low side MOSFET pulls SW low to recharge the BOOT capacitor. When operating at 100% duty cycle the

high-side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the

capacitor because the gate drive current sourced by the BOOT capacitor is small. The effective switching

frequency reduced and the effective maximum duty cycle of the switching regulator is near 100%. The output

voltage of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the

inductor resistance, and the printed circuit board resistance.

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Feature Description (接下页)

7.3.14 Output Overvoltage Protection (OVP)

The TPS54424 incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.

The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. The OVP

threshold is the same as the 108% PGOOD threshold. If the FB pin voltage is greater than the OVP threshold

the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output

overshoot. When the high-side MOSFET turns off, the low-side MOSFET turns on and the current in the inductor

discharges. The output voltage can overshoot the OVP threshold as the current in the inductor discharges to 0 A.

When the FB voltage drops lower than the 106% PGOOD threshold, the high-side MOSFET is allowed to turn on

at the next clock cycle.

7.3.15 Overcurrent Protection

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side

MOSFET and the low-side MOSFET. In an extended overcurrent condition the device will enter hiccup to reduce

power dissipation.

7.3.15.1 High-side MOSFET Overcurrent Protection

The device implements current mode control which uses the COMP pin voltage to control the turnoff of the high-

side MOSFET and the turnon of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current

and the current reference generated by the COMP pin voltage are compared, when the peak switch current

intersects the current reference the high-side switch is turned off. The maximum peak switch current through the

high-side MOSFET for overcurrent protection is done by limiting the current reference internally. If the peak

current required to regulate the output is greater than the internal limit, the output voltage is pulled low and the

error amplifier responds by driving the COMP pin high. The maximum COMP voltage is then clamped by an

internal COMP clamp circuit. If the COMP voltage is clamped high for more than the hiccup wait time of 512

switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles.

7.3.15.2 Low-side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on the current through it is monitored. During normal operation the low-

side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing

current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is

exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The

high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at

the start of a cycle. The low-side sourcing current limit prevents current runaway.

The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are

off until the start of the next cycle. If the low-side MOSFET turns off due to sinking current limit protection, the

low-side MOSFET can only turn on again after the high-side MOSFET turns on then off or if the device enters

BOOT UVLO.

7.4 Device Functional Modes

The EN pin and a VIN UVLO is used to control turn on and turn off of the TPS54424. The device becomes active

when V_(VIN)exceeds the 4.1 V typical UVLO and when V_(EN)exceeds 1.20 V typical. The EN pin has an internal

current source to enable the output when the EN pin is left floating. If the EN pin is pulled low the device is put

into a low quiescent current state.

TPS54424

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54424 is a synchronous buck converter designed for 4.5 V to 17 V input and 4-A load. This procedure

illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Alternatively the

WEBENCH^®software can be used to generate a complete design. The WEBENCH^®software uses an interactive

design procedure and accesses a comprehensive database of components when generating a design. This

section presents a simplified discussion of the design process.

8.2 Typical Application

图 35. TPS54424 4.5-V to 15-V Input, 1.8-V Output Converter Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters shown in 表 1.

表 1. Design Parameters

PARAMETER

EXAMPLE VALUE

4.5 to 15 V, 12 V Nominal

1.8 V

Input voltage range (V_IN

)

Output voltage (V_OUT

)

Transient response

+/- 4%, +/- 72 mV

0.5%, 9 mV

Output ripple voltage

Output current rating (I_OUT

)

4 A

Operating frequency (f_SW

)

700 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS54424 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Switching Frequency

The first step is to decide on a switching frequency for the converter. It is capable of running from 200 kHz to 1.6

MHz. Typically the highest switching frequency possible is desired because it will produce the smallest solution

size. A high switching frequency allows for lower valued inductors and smaller output capacitors compared to a

power supply that switches at a lower frequency. The main trade off made with selecting a higher switching

frequency is extra switching power loss, which hurt the converter’s efficiency.

The maximum switching frequency for a given application is limited by the minimum on-time of the converter and

is estimated with 公式 12. Using a maximum minimum on-time of 130 ns for the TPS54424 and 17 V maximum

input voltage for this application, the maximum switching frequency is 814 kHz. Considering the 10% tolerance of

the switching frequency, a switching frequency of 700 kHz was selected. 公式 13 calculates R7 to be 69.7 kΩ. A

standard 1% 69.8 kΩ value was chosen in the design.

V_OUT

max

f_SWmax =

(

)

tonmin

(

)

(12)

(13)

vertical spacer

-1.028

RT kW = 58650 ì f

kHz

(

)

(

)

8.2.2.3 Output Inductor Selection

To calculate the value of the output inductor, use 公式 14. K_INDis a ratio that represents the amount of inductor

ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.

Additionally with current mode control the sensed inductor current ripple is used in the PWM modulator.

Choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the

high-side MOSFET on-time. The inductor ripple, K_IND, is normally from 0.2 to 0.4 for the majority of applications

giving a peak to peak ripple current range of 0.8 A to 1.6 A. For applications requiring operation near the

minimum on-time, with on-times less than 200 ns, the target Iripple must be 1.2 A or larger for best performance.

For other applications the target Iripple should be 0.8 A or larger.

For this design example, K_IND= 0.3 is used and the inductor value is calculated to be 1.92 μH. The nearest

standard value 1.8 µH is selected. It is important that the RMS current and saturation current ratings of the

inductor not be exceeded. The RMS and peak inductor current can be found from 公式 16 and 公式 17. For this

design, the RMS inductor current is 4.0 A and the peak inductor current is 4.6 A. The chosen inductor is a Würth

Elektronik 74438357018. It has a saturation current rating of 8.0 A (20% inductance loss) and a RMS current

rating of 5.8 A (40 °C temperature rise). The DC series resistance is 18 mΩ typical.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up,

faults or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated in 公式 17. In transient conditions, the inductor current can increase up to the switch current limit

of the device. For this reason, the most conservative approach is to specify the ratings of the inductor based on

the switch current limit rather than the steady-state peak inductor current.

Vinmax - Vout

Vout

L1 =

Io ´ Kind

Vinmax ´ ¦sw

(14)

vertical spacer

TPS54424

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Iripple =

ZHCSGK1 –JULY 2017

Vinmax - Vout

Vout

Vinmax ´ ¦sw

(15)

vertical spacer

ö²

Vo ´ (Vinmax - Vo)

Vinmax ´ L1 ´ ¦sw

ILrms = Io²

(16)

(17)

vertical spacer

ILpeak = Iout +

Iripple

8.2.2.4 Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple

and how the regulator responds to a large change in load current. The output capacitance needs to be selected

based on the more stringent of these two criteria.

The desired response to a large change in the load current is the first criteria and is typically the most stringent.

A regulator does not respond immediately to a large, fast increase or decrease in load current. The output

capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to

sense the change in the output voltage then adjust the peak switch current in response to the change in load.

The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically the loop

bandwidth is f_SW/10. 公式 18 estimates the minimum output capacitance necessary, where ΔI_OUTis the change in

output current and ΔV_OUTis the allowable change in the output voltage.

For this example, the transient load response is specified as a 4% change in V_OUTfor a load step of 2 A.

Therefore, ΔI_OUTis 2 A and ΔV_OUTis 72 mV. Using these numbers gives a minimum capacitance of 63 μF. This

value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic

capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum

capacitors have higher ESR that must be considered for load step response.

公式 19 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the

inductor ripple current. In this case, the target maximum output voltage ripple is 9 mV. Under this requirement, 公

式 19 yields 25 μF.

vertical spacer

DI_OUT

DV_OUT

C_OUT

f_SW

2pì

(18)

(19)

vertical spacer

Co >

Voripple

8 ´ ¦sw

Iripple

Where:

•

ΔI_OUTis the change in output current

ΔV_OUTis the allowable change in the output voltage

fsw is the regulators switching frequency

vertical spacer

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

公式 20 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple

specification and this shows the ESR should be less than 7 mΩ. In this case ceramic capacitors will be used and

the ESR of ceramic capacitors is typically much less than 7 mΩ. Capacitors also have limits to the amount of

ripple current they can handle without producing excess heat and failing. An output capacitor that can support

the inductor ripple current must be specified. Capacitor datasheets specify the RMS (Root Mean Square) value

of the maximum ripple current. 公式 21 can be used to calculate the RMS ripple current the output capacitor

needs to support. For this application, 公式 21 yields 370 mA and the ceramic capacitors used in this design will

have a ripple current rating much higher than this.

Voripple

Resr <

Iripple

(20)

vertical spacer

Vout ´ (Vinmax - Vout)

Icorms =

12 ´ Vinmax ´ L1 ´ ¦sw

(21)

X5R and X7R ceramic dielectrics or similar should be selected for power regulator capacitors because they have

a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be

selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a

ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the manufacturer's website.

For this application example, one 100 μF 6.3 V 1210 X5R ceramic capacitor with 2 mΩ of ESR is used. The

estimated capacitance after derating using the capacitor manufacturer's website is 80 µF.

8.2.2.5 Input Capacitor

The TPS54424 requires input decoupling ceramic capacitors type X5R, X7R or similar from VIN to PGND placed

as close as possible to the IC. A total of at least 4.7 μF of capacitance is required and some applications may

require a bulk capacitance. At least 1 µF of bypass capacitance is recommended near both VIN pins to minimize

the input voltage ripple. A 0.1 µF to 1 µF capacitor must be placed by both VIN pins 2 and 11 to provide high

frequency bypass to reduce the high frequency overshoot and ringing on VIN and SW pins. The voltage rating of

the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple

current rating greater than the maximum RMS input current of the TPS54424. The RMS input current can be

calculated using 公式 22.

For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the

maximum input voltage. Two 10 µF 1206 X5R 25 V and two 0.1 μF 0603 X7R 25 V capacitors in parallel has

been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the capacitor

manufacturer's website, the total ceramic input capacitance derates to 7.6 µF at the nominal input voltage of 12

V. A 100 µF bulk capacitance is also used in this circuit to bypass long leads when connected a lab bench top

power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be

calculated using 公式 23. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the

nominal design example values of Ioutmax = 4 A, Cin = 7.6 μF, and f_SW= 700 kHz, the input voltage ripple with

the 12 V nominal input is 100 mV and the RMS input ripple current with the 4.5 V minimum input is 2.0 A.

Vinmin - Vout

(

)

Vout

Icirms = Iout ´

vertical spacer

Vinmin

(22)

Vout

Vin

Vout

≈

’

◊

Ioutmaxì 1-

∆

Vin

DVin =

Cinì f_SW

(23)

8.2.2.6 Output Voltage Resistors Selection

The output voltage is set with a resistor divider created by R8 (R_FBT) and R6 (R_FBB) from the output node to the

FB pin. It is recommended to use 1% tolerance or better resistors. For this example design, 6.04 kΩ was

selected for R8. Using 公式 24, R6 is calculated as 12.08 kΩ. The nearest standard 1% resistor is 12.1 kΩ.

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

≈

∆

’

V_OUT

V_REF

R_FBT= R_FBB

-1

◊

(24)

8.2.2.7 Soft-start Capacitor Selection

The soft-start capacitor determines the amount of time it takes for the output voltage to reach its nominal

programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also

used if the output capacitance is very large and would require large amounts of current to quickly charge the

capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54424 reach its current limit or cause the input voltage rail to sag due excessive current draw from the input

power supply. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor value

can be calculated using 公式 25. For the example circuit, the soft-start time is not critical because the output

capacitor value of 100 μF does not require much current to charge to 1.8 V. The example circuit has the soft-start

time set to an arbitrary value of 1 ms which requires a 8.2-nF capacitor.

I_SSµA ì t

(

)

(

)

= 8.3ì t_SSms

C_SSnF =

(

)

(

)

V_REF

(

)

(25)

8.2.2.8 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) is adjusted using the external voltage divider network of R2 (R_ENT) and R9

(R_ENB). The UVLO has two thresholds; one for power up when the input voltage is rising and one for power-down

or brown outs when the input voltage is falling. For the example design, the supply should turn on and start

switching once the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts

switching, it should continue to do so until the input voltage falls below 4.0 V (UVLO stop or disable). 公式 2 and

公式 3 can be used to calculate the values for the upper and lower resistor values. For the voltages specified, the

standard resistor value used for R2 is 86.6 kΩ and for R4 is 30.9 kΩ.

8.2.2.9 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. A 1 Ω to 5.6

Ω resistor can be added in series with the BOOT capacitor to slow down the turn on of the high-side MOSFET.

This can reduce voltage spikes on the SW node with the trade off of more power loss and lower efficiency.

8.2.2.10 PGOOD Pull-up Resistor

A 100 kΩ resistor is used to pull-up the power good signal when FB conditions are met. The pull-up voltage

source must be less than the 6.5 V absolute maximum of the PGOOD pin.

8.2.2.11 Compensation

There are several methods used to compensate DC - DC regulators. The method presented here is easy to

calculate and ignores the effects of the slope compensation internal to the device. Because the slope

compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency

used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the

ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low

ESR output capacitors. Use the WEBENCH^®software for more accurate loop compensation. These tools include

a more comprehensive model of the control loop.

To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using 公式 26 and 公式 27.

For Cout, use a derated value of 80 μF and an ESR of 2 mΩ. Use equations 公式 28 and 公式 29, to estimate a

starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 4.4

kHz and fzmod is 995 kHz. 公式 28 is the geometric mean of the modulator pole and the ESR zero. 公式 29 is

the mean of modulator pole and one half the switching frequency. 公式 28 yields 66 kHz and 公式 29 gives 39

kHz. Use the lower value of 公式 28 or 公式 29 for an initial crossover frequency. Next, the compensation

components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A

capacitor in parallel to these two components forms the compensating pole.

Ioutmax

¦p mod =

2 × p × Vout × Cout

(26)

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

vertical spacer

¦z mod =

2 ´ p ´ Resr × Cout

(27)

(28)

vertical spacer

f_co

vertical spacer

f_cof_pmod´

f_pmod´ f_zmod

f_sw

(29)

To determine the compensation resistor, R5, use 公式 30. R5 is calculated to be 3.17 kΩ and the closest

standard value 3.16 kΩ. Use 公式 31 to set the compensation zero to the modulator pole frequency. 公式 31

yields 11.4 nF for compensating capacitor C18 and the closest standard value is 0.012 µF.

≈

∆

’ ≈

’

2ì pì f_COìC_OUT

V_OUT

R_COMP

÷ ∆

gm_PS

V_REFì gm_{EA ◊}

◊ «

(30)

Where:

•

Power stage transconductance, gm_PS= 17 A/V

V_OUT= 1.8 V

V_REF= 0.6 V

Error amplifier transconductance, gm_EA= 1100 µA/V

C_COMP

2ì pìR_COMPì f_PMOD

(31)

A compensation pole is implemented using an additional capacitor C17 in parallel with the series combination of

R5 and C18. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal.

Use the larger value of 公式 32 and 公式 33 to calculate the C17 and to set the compensation pole. C17 is

calculated to be the largest of 41 pF and 134 pF. The closest standard value is 120 pF.

C_OUTìR_ESR

C_HF

R_COMP

(32)

vertical spacer

C_HF

pìR_COMPì f_SW

(33)

Type III compensation can be used by adding the feed forward capacitor C19 in parallel with the upper feedback

resistor. Type III compensation adds phase boost above what is possible from type II compensation because it

places an additional zero/pole pair. The zero/pole pair is not independent. As a result once the zero location is

chosen, the pole is fixed as well. The zero is placed at 1/2 the f_SWby calculating the value of C19 with 公式 34.

The calculated value is 37 pF and the closest standard value is 39 pF. It is possible to use larger feedforward

capacitors to further improve the transient response but care should be taken to ensure there is a minimum of

-10 dB gain margin at 1/2 the f_SWin all operating conditions. The feedforward capacitor injects noise on the

output into the FB pin and this added noise can result in more jitter at the switching node. To little gain margin

can cause a repeated wide and narrow pulse behavior. This example design does not use the optional

feedforward capacitor.

C_FF

pìR_FBTì f_SW

(34)

The initial compensation based on these calculations is R5 = 3.16 kΩ, C18 = 0.012 µF, and C17 = 120 pF.

These values yield a stable design but after testing the real circuit these values were changed to target a higher

crossover frequency to improve transient response performance. The crossover frequency is increased by

increasing the value of R5 and decreasing the value of the compensation capacitors. The final values used in

this example are R5 = 3.48 kΩ, C18 = 8200 pF, and C17 = 68 pF.

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

8.2.3 Application Curves

100

V_IN= 5 V

V_IN= 12 V

V_IN= 17 V

V_IN= 5 V

V_IN= 12 V

V_IN= 17 V

0.001

0.005

0.02 0.05 0.1 0.2

Load Current (A)

0.5

2 3 4

0.5

1.5

2.5

3.5

Load Current (A)

D002

D001

T_A= 25°C

V_OUT= 1.8 V

f_SW= 700 kHz

T_A= 25°C

V_OUT= 1.8 V

f_SW= 700 kHz

图 37. Efficiency (Log Scale)

图 36. Efficiency

0.5

0.4

0.3

0.2

0.1

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

V_IN= 5 V

V_IN= 12 V

V_IN= 17 V

I_OUT= 0 A

I_OUT= 2 A

I_OUT= 4 A

0.5

1.5

2.5

3.5

Load Current (A)

Input Voltage (V)

D004

D005

T_A= 25°C

V_OUT= 1.8 V

f_SW= 700 kHz

T_A= 25°C

V_OUT= 1.8 V

f_SW= 700 kHz

图 38. Load Regulation

图 39. Line Regulation

180

120

-20

-40

-60

-120

Gain

Phase

-180

100 200 5001000

10000

100000

1000000

Frequency (Hz)

D006

V_IN= 12 V

V_OUT= 1.8 V

图 40. Loop Response

I_OUT= 2 A

V_IN= 12 V

V_OUT= 1.8 V

图 41. Transient Response

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

V_IN= 12 V

V_OUT= 1.8 V

I_OUT= 0 A

V_IN= 12 V

V_OUT= 1.8 V

I_OUT= 4 A

图 42. Output Ripple, No Load

图 43. Output Ripple, Full Load

V_IN= 12 V

V_OUT= 1.8 V

I_OUT= 0 A

V_IN= 12 V

V_OUT= 1.8 V

I_OUT= 4 A

图 44. Input Voltage Ripple, No Load

图 45. Input Voltage Ripple, Full Load

R_LOAD= 1 Ω

图 46. V_INStartup

图 47. EN Startup

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

R_LOAD= 1 Ω

V_IN= 12 V

R_LOAD= 1 Ω

图 48. V_INShutdown

图 49. EN Shutdown

V_IN= 12 V

I_OUT= short

V_IN= 12 V

图 50. EN Startup with Pre-biased Output

图 51. Output Short Circuit Response

V_IN= 12 V

I_OUT= short

V_IN= 12 V

I_OUT= short

removed

图 52. Hiccup Mode Current Limit

图 53. Hiccup Mode Recovery

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

9 Power Supply Recommendations

The TPS54424 is designed to be powered by a well regulated dc voltage between 4.5 and 17 V. The TPS54424

is a buck converter so the input supply voltage must be greater than the desired output voltage to regulate the

output voltage to the desired value. If the input supply voltage is not high enough the output voltage will begin to

drop. Input supply current must be appropriate for the desired output current.

10 Layout

10.1 Layout Guidelines

•

VIN and PGND traces should be as wide as possible to reduce trace impedance and improve heat

dissipation.

At least 1 µF of input capacitance is required on both VIN pins of the IC and must be placed as close as

possible to the IC. The input capacitors must connect directly to the adjacent PGND pins.

It is recommended to use a ground plane directly below the IC to connect the PGND pins on both sides of the

IC together.

The PGND trace between the output capacitor and the PGND pin should be as wide as possible to minimize

its trace impedance.

•

Provide sufficient vias for the input capacitor and output capacitor.

Keep the SW trace as physically short and wide as practical to minimize radiated emissions.

A separate VOUT path should be connected to the upper feedback resistor.

Voltage feedback loop should be placed away from the high-voltage switching trace. It is preferable to use

ground copper near it as a shield.

•

The trace connected to the FB node should be as small as possible to avoid noise coupling.

Place components connected to the RT/CLK, FB, COMP and SS/TRK pins as close to the IC as possible and

minimize traces connected to these pins to avoid noise coupling.

•

AGND must be connected to PGND on the PCB. Connect AGND to PGND in a region away from switching

currents.

10.2 Layout Example

图 54 through 图 57 shows an example PCB layout and the following list provides a description of each layer.

•

The top layer has all components and the main traces for VIN, SW, VOUT and PGND. Both VIN pins are

bypassed with two input capacitors placed as close as possible to the IC and are connected directly to the

adjacent PGND pins. Multiple vias are placed near the input and output capacitors. The AGND trace is

connected to PGND with a wide trace away from the input capacitors to minimize switching noise.

•

Midlayer 1 has a solid PGND plane to connect the PGND pins on both sides of the IC together with the

shortest path possible and to aid with thermal performance.

Midlayer 2 has a wide trace connecting both VIN pins of the IC. It is also used to route the BOOT pin to the

BOOT-SW capacitor (CBT). It also has a parallel trace for VOUT to minimize trace resistance. The rest of this

layer is covered with PGND.

•

The bottom layer has the trace connecting the FB resistor divider to VOUT at the point of regulation. PGND is

filled into the rest of this layer to aid with thermal performance.

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

Layout Example (接下页)

图 54. TPS54424 Layout Top

图 55. TPS54424 Layout Midlayer 1

图 56. TPS54424 Layout Midlayer 2

图 57. TPS54424 Layout Bottom

TPS54424

ZHCSGK1 –JULY 2017

www.ti.com.cn

10.3 Alternate Layout Example

图 58 through 图 61 shows an alternate example PCB layout with unsymmetrical placement of the input

capacitors and output capacitors. Both VIN pins are still bypassed to their adjacent PGND pins with an input

capacitor placed as close as possible to the IC. When using this alternate layout, CI2 should be increased to 1

µF.

Solid PGND plane below the IC

to connect PGND pins. Do not

cut this connection with other

traces.

图 58. TPS54424 Alternate Layout Top

图 59. TPS54424 Alternate Layout Midlayer 1

图 60. TPS54424 Alternate Layout Midlayer 2

图 61. TPS54424 Alternate Layout Bottom

TPS54424

www.ti.com.cn

ZHCSGK1 –JULY 2017

11 器件和文档支持

11.1 文档支持

11.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 TPS54424 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 在开始阶段键入输出电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

11.2 接收文档更新通知

要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我进行注册，即可

收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

HotRod, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不

会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

25-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS54424RNVR

TPS54424RNVT

ACTIVE

VQFN-HR

RNV

3000 RoHS & Green

250 RoHS & Green

Call TI

Level-2-260C-1 YEAR

-40 to 150

54424

Samples

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Mar-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54424RNVR

TPS54424RNVT

VQFN-

RNV

3000

250

330.0

12.4

3.75

1.15

8.0

12.0

VQFN-

180.0

12.4

3.75

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS54424RNVR

TPS54424RNVT

VQFN-HR

RNV

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

重要声明和免责声明

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS54424 [TI]

相关型号：

TPS54424RNVR

TPS54424RNVT

TPS54425

TPS54425PWP

TPS54425PWPR

TPS54425_10

TPS54426

TPS54426PWP

TPS54426PWPR

TPS54426RSAR

TPS54426RSAT

TPS54426_10