TPS54426RSAR [TI]
具有 Eco-Mode™ 的 4.5V 至 18V 输入、4A 同步降压转换器 | RSA | 16 | -40 to 85;
| 型号： | TPS54426RSAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-Mode™ 的 4.5V 至 18V 输入、4A 同步降压转换器 | RSA | 16 | -40 to 85 开关 控制器 开关式稳压器 开关式控制器 电源电路 转换器 开关式稳压器或控制器 |
| 文件： | 总22页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54426
www.ti.com
SLVSAD6 –AUGUST 2010
4.5V to 18V Input, 4-A Synchronous Step-Down SWIFT™ Converter with Eco-Mode™
Check for Samples: TPS54426
1
FEATURES
DESCRIPTION
23
•
D-CAP2™ Mode Enables Fast Transient
Response
The TPS54426 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54426
enables system designers to complete the suite of
various end equipment’s power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54426 uses the D-CAP2™ mode control which
provides a very fast transient response with no
external compensation components. The adaptive
on-time control supports seamless transition between
PWM mode at higher load conditions and
Eco-mode™ operation at light loads. Eco-mode™
allows the TPS54426 to maintain high efficiency
during lighter load conditions. The TPS54426 also
has a proprietary circuit that enables the device to
adopt to both low equivalent series resistance (ESR)
output capacitors, such as POSCAP, SP-CAP, and
ultra-low ESR ceramic capacitors. The device
operates from 4.5-V to 18-V VIN input. The output
voltage can be programmed between 0.76 V and 5.5
V. The device also features an adjustable soft start
time and a power good function. The TPS54426 is
available in the 14-pin HTSSOP package, and
designed to operate from –40°C to 85°C.
•
Low Output Ripple and Allows Ceramic Output
Capacitor
•
•
•
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 5.5 V
Highly Efficient Integrated FET’s Optimized
for Lower Duty Cycle Applications
– 65 mΩ (High Side) and 55 mΩ (Low Side)
•
•
•
•
•
•
•
•
High Efficiency, less than 10 mA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
700-kHz Switching Frequency (fSW
)
Cycle By Cycle Over Current Limit
Power Good Output
Auto-Skip Eco-mode™ for High Efficiency at
Light Load
APPLICATIONS
•
Wide Range of Applications for Low Voltage
System
–
–
–
–
Digital TV Power Supply
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
Vout (50 mV/div)
Iout (2 A/div)
100 ms/div
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS54426
SLVSAD6 –AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TRANSPORT
MEDIA, QUANTITY
TA
PACKAGE(2) (3)
PIN
ECO PLAN
TPS54426PWP
Tube
PowerPAD™
(HTSSOP) – PWP
Green
(RoHS & no Sb/Br)
–45°C to 85°C
14
TPS54426PWPR
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 20
–0.3 to 26
–0.3 to 28
–0.3 to 6.5
–2 to 20
–3 to 22
–0.3 to 6.5
–0.3 to 0.3
–0.2 to 0.2
2
UNIT
V
VIN1, VIN2, EN
VBST
V
VBST (10 ns transient)
VFB, VO, SS, PG
SW1, SW2
V
VI
Input voltage range
Output voltage range
V
V
SW1, SW2 (10 ns transient)
VREG5
V
V
VO
PGND1, PGND2
V
Vdiff
Voltage from GND to POWERPAD
V
Human Body Model (HBM)
Charged Device Model (CDM)
kV
V
Electrostatic
discharge
ESD rating
500
TJ
Operating junction temperature
Storage temperature
–40 to 150
–55 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54426
THERMAL METRIC(1)
PWP
14 PINS
55.6
UNITS
qJA
Junction-to-ambient thermal resistance
qJCtop
qJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.3
36.4
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
yJB
20.6
qJCbot
4.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
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SLVSAD6 –AUGUST 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
18
UNIT
VIN
Supply input voltage range
V
VBST
–0.3
–0.3
–0.1
–0.1
–0.1
–1.8
–3
24
VBST (10 ns transient)
SS, PG
27
5.7
18
EN
VI
Input voltage range
V
VO, VFB
5.5
18
SW1, SW2
SW1, SW2 (10 ns transient)
PGND1, PGND2
VREG5
21
–0.1
–0.1
0
0.1
5.7
10
VO
IO
Output voltage range
V
Output Current range
IVREG5
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
–40
–40
85
150
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
IVIN
Operating - non-switching supply current
Shutdown supply current
850
1.8
1300
10
mA
mA
IVINSDN
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
EN high-level input voltage
EN low-level input voltage
EN
EN
2
V
V
0.4
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB voltage light load mode, TA = 25°C,
VO = 1.05 V, IO=10mA
771
765
TA = 25°C, VO = 1.05 V, continuous mode
757
753
773
777
VFBTH
VFB threshold voltage
mV
TA = 0°C to 85°C, VO = 1.05 V, continuous
mode(1)
TA = –40°C to 85°C, VO = 1.05 V, continuous
mode(1)
751
779
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
0
±0.1
100
mA
RDischg
VO discharge resistance
EN = 0 V, VO = 0.5 V, TA = 25°C
50
Ω
VREG5 OUTPUT
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 output voltage
5.3
5.5
5.7
V
VLN5
Line regulation
Load regulation
Output current
6.0 V < VIN < 18 V, IVREG5 = 5 mA
0 mA < IVREG5 < 5 mA
20
mV
mV
mA
VLD5
100
IVREG5
MOSFET
Rdsonh
Rdsonl
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
70
High side switch resistance
Low side switch resistance
25°C, VBST - SW1,2 = 5.5 V
25°C
63
55
mΩ
mΩ
CURRENT LIMIT
Iocl
Current limit
L out = 1.5 mH(1), TA = -20 ºC to 85 ºC
4.7
5.4
7.5
A
(1) Not production tested.
Copyright © 2010, Texas Instruments Incorporated
3
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(2)
Shutdown temperature
165
30
TSDN
Thermal shutdown threshold
°C
(2)
Hysteresis
ON-TIME TIMER CONTROL
TON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.7 V
145
260
ns
ns
TOFF(MIN)
Minimum off time
310
2.6
SOFT START
ISSC SS charge current
ISSD SS discharge current
POWER GOOD
VSS = 0 V
1.4
0.1
2.0
0.2
mA
VSS = 0.5 V
mA
VFB rising (good)
VFB falling (fault)
PG = 0.5 V
85
2.5
115
60
90
85
5
95
%
%
VTHPG
PG threshold
IPG
PG sink current
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
Output OVP prop delay
OVP detect
120
10
125
70
%
ms
%
TOVPDEL
UVP detect
Hysteresis
65
VUVP
Output UVP trip threshold
10
%
TUVPDEL
TUVPEN
UVLO
Output UVP delay
0.25
x 1.7
ms
Output UVP enable delay
Relative to soft-start time
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.55
0.23
3.8
4.05
0.47
VUVLO
UVLO threshold
V
0.35
(2) Not production tested.
4
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
www.ti.com
SLVSAD6 –AUGUST 2010
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
14
13
1
2
VIN2
VIN1
VO
VFB
3
4
5
VREG5
12
11
VBST
SW2
POWER PAD
SS
SW1
10
9
GND
6
7
PGND2
PGND1
PG
EN
8
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
VO
NO.
1
Connect to output of converter. This terminal is used for On-Time Adjustment.
Converter feedback input. Connect to output voltage with feedback resistor divider.
VFB
2
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
when EN is low.
VREG5
3
SS
4
5
6
7
Soft-start control. A external capacitor should be connected to GND.
Signal ground pin.
GND
PG
Open drain power good output.
EN
Enable control input. EN is active high and must be pulled up to enable the device.
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
GND strongly together near the IC.
PGND1, PGND2
SW1, SW2
VBST
8, 9
10, 11
12
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
comparators.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator for the
control circuitry.
VIN1, VIN2
PowerPAD™
13, 14
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected
to PGND.
Copyright © 2010, Texas Instruments Incorporated
5
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TPS54426
SLVSAD6 –AUGUST 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
-35%
VIN
UV
OV
VIN2
VIN1
14
13
VO
1
+20%
SS
VREG5
Control Logic
VBST
SW
12
Ref
VFB
VO
11
10
2
VREG5
Ceramic
Capacitor
VREG5
3
4
GND
SS
PGND
9
8
SW
ZC
SS
Softstart
PGND
PGND
GND
PGND
5
SW
GND
OCP
PGND
GND
VCC
Ref
-10%
PG 6
UV
OV
VREG5
Protection
Logic
UVLO
TSD
UVLO
EN
EN
7
Logic
REF
Ref
6
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
www.ti.com
SLVSAD6 –AUGUST 2010
OVERVIEW
The TPS54426 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54426 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54426 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54426 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode™ Control
The TPS54426 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
V
(
-VOUT ×V
)
1
IN
OUT
IOUT (LL)
=
=
2× L× fsw
VIN
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2 mA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
2 mA.
C6(nF) • Vref
C6(nF) • 0.765
Tss(ms) =
=
Iss(µA)
2
(2)
The TPS54426 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Copyright © 2010, Texas Instruments Incorporated
7
Product Folder Link(s): TPS54426
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SLVSAD6 –AUGUST 2010
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Power Good
The TPS54426 has power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is
within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. The power good output, PG, is an open drain output. If the feedback voltage goes under 15% of
the target value, the power good signal becomes low after a 5 ms internal delay.
VREG5
VREG5 is an internally generated voltage source used by the TPS54425. It is derived directly from the input
voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5
regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage
(3.8 V typical) for the TPS54425 to function. Connect a 1.0 µF capacitor between pin 3 of the TPS54425 and
power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use
and can typically source up to 70 mA. The VREG5 output is disabled when the TPS54425 EN pin is open or
pulled low.
Output Discharge Control
TPS54426 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
Current Protection
Output current is limited by cycle-by-cycle overcurrent limiting control. The inductor current is monitored during
the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current
trip level. To provide both good accuracy and cost effective solution, the device supports temperature
compensated internal MOSFET RDS(on) sensing.
The inductor current is monitored by the voltage between PGND pin and SW1/SW2 pin. In an overcurrent
condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall
off. Eventually, it will end up with crossing the undervoltage protection threshold and shutdown.
Over/Under Voltage Protection
TPS54426 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback
voltage becomes lower than 65% of the target voltage, the UVP comparator output goes high and an internal
UVP delay counter begins. After 250 ms, the device latches off both internal top and bottom MOSFET. This
function is enabled approximately 1.7 x softstart time.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54426 is shut off. This is protection is non-latching.
Thermal Shutdown
TPS54426 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
8
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
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SLVSAD6 –AUGUST 2010
TYPICAL CHARACTERISTICS
Vin CURRENT
vs
Vin SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1200
1000
800
8
6
4
600
400
2
0
200
0
-50
0
50
- Junction Temperature - °C
100
150
-50
0
50
- Junction Temperature - °C
100
150
T
T
J
J
Figure 1.
Figure 2.
EN CURRENT
vs
1.05V OUTPUT VOLTAGE
vs
EN VOLTAGE
OUTPUT CURRENT
1.1
1.075
1.05
100
80
V = 18 V
I
V = 12 V
I
60
V = 5 V
I
40
20
0
1.025
1
0
1
2
- Output Current - A
3
4
0
5
10
EN Input Voltage - V
15
20
I
O
Figure 3.
Figure 4.
Copyright © 2010, Texas Instruments Incorporated
9
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TPS54426
SLVSAD6 –AUGUST 2010
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TYPICAL CHARACTERISTICS (continued)
1.05V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.05V 50mA to 4A LOAD TRANSIENT RESPONSE
1.1
1.075
1.05
Vout (50 mV/div)
I
= 10 mA
O
I
= 1 A
O
Iout (2 A/div)
1.025
1
0
5
10
15
20
V - Input Voltage - V
I
100 ms/div
Figure 5.
Figure 6.
EFFICIENCY
vs
STARTUP WAVEFORM
OUTPUT CURRENT
100
90
80
70
60
50
40
V
= 3.3 V
O
EN - 10 V/div
V
= 1.8 V
O
V
O
= 2.5 V
V
- 0.5 V/div
OUT
PG - 5 V/div
0
1
2
- Output Current - A
3
4
I
O
400 ms/div
Figure 7.
Figure 8.
10
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TPS54426
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SLVSAD6 –AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
LIGHT LOAD EFFICIENCY
SWITCHING FREQUENCY
vs
vs
OUTPUT CURRENT
INPUT VOLTAGE (IO=1A)
100
80
60
40
20
800
700
600
V
= 3.3 V
O
V
= 2.5 V
O
V
= 1.8 V
O
V
= 1.8 V
O
V
= 3.3 V
O
500
400
0
0.001
0.01
- Output Current - A
0.1
0
5
10
15
20
I
O
V - Input Voltage - V
I
Figure 9.
Figure 10.
WITCHING FREQUENCY
vs
OUTPUT CURRENT
VOLTAGE RIPPLE AT OUTPUT (IO=4A)
800
700
600
500
400
300
200
100
V
(10 mV/div)
O
V
= 1.8 V
O
V
= 2.5 V
O
SW (5 V/div)
0
0.001
0.01
0.1
- Output Current - A
1
10
I
O
Figure 11.
Figure 12.
VOLTAGE RIPPLE AT INPUT (IO=4A)
VIN (50 mV/div)
SW (5 V/div)
Figure 13.
Copyright © 2010, Texas Instruments Incorporated
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DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
Figure 14 shows the schematic diagram for this design example.
Figure 14. Schematic
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 and Equation 4 to calculate VOUT
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable
For output voltage from 0.76 V to 2.5 V:
R1
−
1 +
VOUT = 0.765 •
(
)
R2
(3)
(4)
For output voltage over 2.5 V:
R1
R2
¾
VOUT = (0.763 + 0.0017 · VOUT_SET) ·
(1 +
)
Where:
VOUT_SET = Target VOUT voltage
Output Filter Selection
The output filter used with the TPS54426 is an LC circuit. This LC filter has double pole at:
12
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
www.ti.com
SLVSAD6 –AUGUST 2010
1
FP =
2p LOUT ´COUT
(5)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54426. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 5 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Table 1. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
6.81
8.25
12.7
30.1
49.9
73.2
121
R2 (kΩ)
22.1
C4 (pF)
L1 (µH)
1.5
C8 + C9 (µF)
22 - 68
1
1.05
1.2
1.8
2.5
3.3
5
22.1
1.5
22 - 68
22.1
1.5
22 - 68
22.1
10 - 22
10 - 22
10 - 22
10 - 22
2.2
22 - 68
22.1
2.2
22 - 68
22.1
2.2
22 - 68
22.1
3.3
22 - 68
Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output
voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a
feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 6,
Equation 7 and Equation 8. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW
.
VIN (max) - VOUT
VOUT
VIN (max)
•
Ilp - p =
LO • fSW
(6)
(7)
(8)
Ilp - p
2
Ilpeak = IO +
2
IO +
2
1
−
12
ILo(RMS)
=
Ilp - p
For this design example, the calculated peak current is 4.47A and the calculated RMS current is 4.009 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54426 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 9 to
determine the required RMS current rating for the output capacitor
• (VIN - VOUT)
VOUT
ICO(RMS)
=
−
√12
•VIN
• LO
• fSW
(9)
For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is .271A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54426 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 uF. is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
Copyright © 2010, Texas Instruments Incorporated
13
Product Folder Link(s): TPS54426
TPS54426
SLVSAD6 –AUGUST 2010
www.ti.com
Bootstrap Capacitor Selection
A 0.1 mF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1.0 mF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
14
Thermal Pad
2.46
°
7
1
2.31
Figure 15. Thermal Pad Dimensions
14
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54426
TPS54426
www.ti.com
SLVSAD6 –AUGUST 2010
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN
Additional
Thermal
Vias
VIN
INPUT
BYPASS
CAPACITOR
VIN OVER
CURRENT
STABILITY
CAPACITOR
EXPOSED
POWERPAD
AREA
FEEDBACK
RESISTORS
VOUT
VFB
VREG5
SS
VIN2
VIN1
BOOST
CAPACITOR
VBST
SW1
VOUT
BIAS
CAP
GND
PG
SW2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
PGND1
PGND2
SLOW
START
CAP
EN
Connection to
POWER GROUND
on internal or
ANALOG
GROUND
TRACE
Additional
Thermal
Vias
bottom layer
To Enable
Control
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 16. PCB Layout
Copyright © 2010, Texas Instruments Incorporated
15
Product Folder Link(s): TPS54426
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54426PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
14
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
TPS54426PWPR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54426PWPR
HTSSOP PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 14
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
TPS54426PWPR
2000
Pack Materials-Page 2
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