TPS54428DRCT [TI]
具有 Eco-Mode™ 的 4.5V 至 18V 输入、4A SWIFT™ 同步降压转换器 | DRC | 10 | -40 to 85;
| 型号： | TPS54428DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-Mode™ 的 4.5V 至 18V 输入、4A SWIFT™ 同步降压转换器 | DRC | 10 | -40 to 85 开关 控制器 开关式稳压器 开关式控制器 电源电路 转换器 开关式稳压器或控制器 |
| 文件： | 总22页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54428
www.ti.com
SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
4.5V to 18 V Input, 4-A Synchronous Step-Down SWIFT™ Converter with Eco-Mode™
Check for Samples: TPS54428
1
FEATURES
DESCRIPTION
The TPS54428 is an adaptive on-time D-CAP2™
mode synchronous buck converter.
23
•
D-CAP2™ Mode Enables Fast Transient
Response
The TPS54428 enables system designers to
complete the suite of various end-equipment power
bus regulators with a cost effective, low component
count, low standby current solution.
•
Low Output Ripple and Allows Ceramic Output
Capacitor
•
•
•
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 7.0 V
The main control loop for the TPS54428 uses the
D-CAP2™ mode control that provides a fast transient
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 70 mΩ (High Side) and 53 mΩ (Low Side)
response
with
no
external
compensation
components.
•
•
•
•
•
•
•
High Efficiency, Less Than 10 μA at Shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
The adaptive on-time control supports seamless
transition between PWM mode at higher load
conditions and Eco-mode™ operation at light loads.
Pre-Biased Soft Start
Eco-mode™ allows the TPS54428 to maintain high
efficiency during lighter load conditions.
650-kHz Switching Frequency (fSW
)
Cycle By Cycle Over Current Limit
The TPS54428 also has a proprietary circuit that
enables the device to adopt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18 V
VIN input.
Auto-Skip Eco-mode™ for High Efficiency at
Light Load
APPLICATIONS
•
Wide Range of Applications for Low Voltage
System
The output voltage can be programmed between
0.76 V and 7.0 V.
–
–
–
–
Digital TV Power Supply
The device also features an adjustable soft start time.
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
The TPS54428 is available in the 8-pin DDA
package,and designed to operate from –40°C to
85°C.
.
Vout(50mV/div)
TPS54428DDA
Iout(2A/div)
100us/div
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2 is a trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS54428
SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TRANSPORT
TA
PACKAGE(2)(3)
ORDERABLE PART NUMBER
PIN
MEDIA
TPS54428DDA
Tube
–40°C to 85°C
DDA
8
TPS54428DDAR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
VIN, EN
V
V
VBST
26
VBST (10 ns transient)
VBST (vs SW)
VFB, SS
28
V
Input voltage range
Output voltage range
6.5
6.5
20
V
V
SW
V
SW (10 ns transient)
VREG5
–3
22
V
–0.3
–0.3
–0.2
6.5
0.3
0.2
2
V
GND
V
Voltage from GND to thermal pad, Vdiff
Human Body Model (HBM)
Charged Device Model (CDM)
V
kV
V
Electrostatic discharge
500
150
150
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54428
THERMAL METRIC(1)
UNITS
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance
42.1
50.9
31.8
5
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
13.5
7.1
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
18
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
-0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3
24
VBST (10 ns transient)
27
VBST(vs SW)
5.7
5.7
18
SS
VI
Input voltage range
EN
V
VFB
5.5
18
SW
SW (10 ns transient)
GND
21
–0.1
–0.1
0
0.1
5.7
10
VO
IO
Output voltage range
VREG5
V
Output Current range
IVREG5
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
–40
–40
85
150
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
IVIN
Operating - non-switching supply current
950
3.0
1400
10
μA
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.6
VEN = 12 V
225
450
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
Eco-mode™ operation
771
765
TA = 25°C, VO = 1.05 V, continuous mode
operation
VFBTH
VFB threshold voltage
VFB input current
mV
757
751
773
TA = –40°C to 85°C , VO = 1.05V, continuous
765
0
779
mode operation(1)
IVFB
VREG5 OUTPUT
VFB = 0.8 V, TA = 25°C
±0.1
μA
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 output voltage
5.2
5.5
5.7
V
VLN5
Line regulation
Load regulation
Output current
6 V < VIN < 18 V, IVREG5 = 5 mA
0 mA < IVREG5 < 5 mA
25
mV
mV
mA
VLD5
100
IVREG5
MOSFET
RDS(on)h
RDS(on)l
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
60
High side switch resistance
Low side switch resistance
25°C, VBST - SW = 5.5 V
25°C
70
53
mΩ
mΩ
CURRENT LIMIT
(1)
Iocl
Current limit
L out = 1.5 µH
4.6
5.3
6.8
A
(1) Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown temperature(2)
Hysteresis(2)
170
35
TSDN
Thermal shutdown threshold
°C
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
260
ns
ns
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
310
7.8
SOFT START
ISSC
SS charge current
VSS = 0 V
4.2
0.1
6.0
0.2
μA
ISSD
SS discharge current
VSS = 0.5 V
mA
UVLO
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.45
0.19
3.75
0.32
4.05
0.45
UVLO
UVLO threshold
V
(2) Not production tested.
4
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SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
DEVICE INFORMATION
DDA PACKAGE
(TOP VIEW)
8
1
VIN
EN
POWER
PAD
2
7
VFB
VBST
TPS54428
DDA
3
6
VREG5
SW
HSOP8
4
5
SS
GND
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
EN
NO.
1
Enable input control. Active high.
VFB
2
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when
EN is low.
SS
4
5
Soft-start control. An external capacitor should be connected to GND.
GND
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single
point.
SW
6
7
Switch node connection between high-side NFET and low-side NFET.
VBST
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An
internal diode is connected between VREG5 and VBST.
VIN
8
Input voltage supply pin.
Exposed
Thermal Pad
Back
side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND.
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SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
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FUNCTIONAL BLOCK DIAGRAM
VIN
EN
EN
VIN
1
8
7
Logic
VREG5
VBST
Control Logic
1 shot
Ref
SS
SW
VO
6
2
VFB
XCON
VREG5
VREG5
Ceramic
Capacitor
3
4
SGND
SS
5
SW
GND
ZC
Softstart
PGND
PGND
SS
SW
SGND
PGND
VIN
UVLO
TSD
VREG5
Protection
Logic
UVLO
REF
Ref
6
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TPS54428
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SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
OVERVIEW
The TPS54428 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54428 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54428 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54428 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode™ Control
The TPS54428 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
V
- VOUT ´ VOUT
)
1
(
IN
IOUT(LL)
=
´
2 ´ L ´ fSW
V
IN
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6-uA.
C6(nF) ´ Vref ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
Tss(ms) =
=
Iss(mA)
6
(2)
The TPS54428 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
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Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54428 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54428 is shut off. This protection is non-latching.
Thermal Shutdown
TPS54428 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),
the device is shut off. This is non-latch protection.
TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted)
20
1200
1000
800
15
10
600
400
200
0
5
0
-50
0
50
100
150
-50
0
50
100
150
T
- Junction Temperature - °C
T Junction Temperature - °C
J
J
Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE
Figure 2. VIN SHUTDOWN CURRENT vs JUNCTION
TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
50
1.1
1.075
1.05
V = 18 V
I
45
40
35
30
V = 18 V
I
25
20
V = 12 V
V = 5 V
I
I
15
10
5
1.025
1
0
0
5
10
15
20
0
1
2
3
4
EN Input Voltage - V
I
- Output Current - A
O
Figure 3. EN CURRENT vs EN VOLTAGE
Figure 4. 1.05V OUTPUT VOLTAGE vs OUTPUT CURRENT
1.08
1.07
1.06
1.05
1.04
Vout (50 mV/div)
I
= 10 mA
O
Iout (2 A/div)
I
= 1 A
O
0
5
10
15
20
100 ms/div
V - Input Voltage - V
I
Figure 5. 1.05V OUTPUT VOLTAGE vs VIN VOLTAGE
Figure 6. 1.05V LOAD TRANSIENT RESPONSE
100
EN (10 V/div)
90
80
70
V = 1.8 V
O
V
= 2.5 V
O
V
= 3.3 V
VREG5 (5 V/div)
Vout (0.5 V/div)
O
60
50
40
1 ms/div
0
1
2
3
4
5
I
- Output Current - A
O
Figure 7. START UP WAVEFORM
Figure 8. EFFICIENCY vs OUTPUT CURRENT
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
100
900
850
800
90
V
= 3.3 V
O
80
70
60
V
= 5 V
O
V
= 3.3 V
V
= 2.5 V
V
O
V
= 2.5 V
= 1.8 V
O
O
O
750
700
650
V
= 1.8 V
O
50
40
V
O
= 1.5 V
V
= 1.2 V
O
600
550
V
= 1.05 V
O
30
20
10
500
450
400
0
0.001
0.01
- Output Current - A
0.1
0
5
10
V - Input Voltage - V
15
20
I
O
I
Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT
Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE
0.78
800
700
0.775
0.77
600
V
= 3.3 V
O
V
= 1.8 V
O
V
= 1.05 V
O
500
400
300
0.765
0.76
200
100
0
0.755
0.75
0
1
2
- Output Current - A
3
4
-50
0
50
T - Junction Temperature - °C
J
100
150
I
O
Figure 11. SWITCHING FREQUENCY vs OUTPUT
CURRENT
Figure 12. VFB VOLTAGE vs JUNCTION TEMPERATURE
V
= 1.05 V
VIN (50 mV/div)
O
Vo = 1.5 V
Vo (10 mV/div)
SW (5 V/div)
SW (5 V/div)
500 ns/div
Figure 13. VOLTAGE RIPPLE vs RIPPLE AT OUTPUT (IO
4A
=
Figure 14. VOLTAGE RIPPLE vs RIPPLE AT INPUT (IO
4A
=
10
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DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
4.5 to 18 V
1
Δ
TPS54428DDA
1.05 V 4 A
8200 pF
Figure 15. Schematic Diagram for This Design Example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1
æ
ö
VOUT = 0.765 ´ 1+
ç
÷
ø
R2
è
(3)
Output Filter Selection
The output filter used with the TPS54228 is an LC circuit. This LC filter has double pole at:
1
F =
P
2p LOUT ´ COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54428. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 1.
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Table 1. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
6.81
8.25
12.7
21.5
30.1
49.9
73.2
124
R2 (kΩ)
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
C4 (pF)(1)
L1 (µH)
1.5
C8 + C9 (µF)
1
1.05
1.2
1.5
1.8
2.5
3.3
5
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
1.5
1.5
1.5
5 - 22
5 - 22
5 - 22
5 - 22
5 - 22
2.2
2.2
2.2
3.3
6.5
165
3.3
(1) Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW
.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
V
- VOUT
VOUT
IN(MAX)
IlP-P
=
´
V
LO ´ fSW
IN(MAX)
(5)
(6)
IlP-P
IlPEAK = IO
+
2
1
2
2
ILO(RMS)
=
IO
+
IlP -P
12
(7)
For this design example, the calculated peak current is 4.51 A and the calculated RMS current is 4.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54428 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
VOx
´
V
- VOUT
)
IN
(
ICO(RMS)
=
12 ´ V ´ LO ´ fSW
IN
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54428 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 8 to ground is optional to provide additional frequency filtering. The capacitor voltage rating
needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
12
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TPS54428
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SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor
THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in Figure 16.
8
5
Exposed Thermal Pad
2,40
1,65
1
4
3,10
2,65
Figure 16. Thermal Pad Dimensions
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TPS54428
SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
www.ti.com
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient vias for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
15. The TPS54428 can supply relatively large current up to 4A. So heat dissipation may be a concern. The
top-side area adjacent to the TPS54428 should be filled with ground as much as possible to dissipate heat.
16. The bottom-side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad using vias as shown. The ground area should be as large as practical. Additional internal
layers can be dedicated as ground planes and connected to vias as well.
Additional
Thermal
Vias
VIN INPUT
BYPASS
CAPACITOR
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS
EN
VIN
BOOST
CAPACITOR
VFB
VBST
VOUT
VREG5
SS
SW
OUTPUT
INDUCTOR
BIAS
CAP
EXPOSED
POWERPAD
AREA
PGND
Connection to
POWER GROUND
on internal or
OUTPUT
FILTER
CAPACITOR
SOFT
START
CAP
bottom layer
Additional
Thermal
Vias
POWER GROUND
ANALOG
GROUND
TRACE
Figure 17. TPS54428 Layout
14
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Product Folder Link(s) :TPS54428
TPS54428
www.ti.com
SLVSB42A –NOVEMBER 2011–REVISED JANUARY 2012
REVISION HISTORY
Changes from Original (November 2011) to Revision A
Page
•
•
Changed in 6th paragraph, page 1: alsohas to also has ...................................................................................................... 1
Deleted TA = –20ºC to 85ºC from ELEC CHARA table, CURRENT LIMIT section, Test Conditions statement .................. 3
Copyright © 2011–2012, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54428DDA
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS54428DDAR
DDA
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54428DDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS54428DDAR
8
2500
Pack Materials-Page 2
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相关型号：
TPS54478RTE
SWITCHING REGULATOR, 2000kHz SWITCHING FREQ-MAX, PQCC16, 3 X 3 MM, GREEN, PLASTIC, WQFN-16
TI
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