TPS54478RTET [TI]
2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down; 2.95 V至6 V的输入， 4 A输出， 2 - MHz的同步降压型
| 型号： | TPS54478RTET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down |
| 文件： | 总37页 (文件大小：1442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down
Switcher With Integrated FETs ( SWIFT™)
Check for Samples: TPS54478
1
FEATURES
DESCRIPTION
The TPS54478 device is a full featured 6 V, 4 A,
synchronous step down current mode converter with
two integrated MOSFETs.
2
•
Two 30-mΩ (typical) MOSFETs for High
Efficiency at 4 A Loads
200kHz to 2MHz Switching Frequency
0.6 V ± 1% Voltage Reference Over
Temperature (–40°C to 150°C)
Start up with Pre-Biased Voltage
Synchronizes to External Clock
Adjustable Slow Start / Sequencing
UV and OV Power Good Output
Cycle by Cycle Current Limit and Hiccup
Current Protection
•
•
The TPS54478 enables small designs by integrating
the MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3mm x
3mm thermally enhanced QFN package.
•
•
•
•
•
The TPS54478 provides accurate regulation for a
variety of loads with an accurate ±1% Voltage
Reference (VREF) over temperature.
•
•
Thermally Enhanced 3mm × 3mm 16-pin QFN
(RTE)
Pin Compatible to TPS54418
Efficiency is maximized through the integrated 30mΩ
MOSFETs and 525μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
2.5µA by entering a shutdown mode.
APPLICATIONS
•
•
Under voltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.
Low-Voltage, High-Density Power Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
•
Cycle-by-cycle current limit, hiccup overcuurent
protection and thermal shutdown protect the device
during an overcurrent condition.
SIMPLIFIED SCHEMATIC
vertical spacer
The TPS54478 is supported in the SwitcherPro™
Software Tool at www.ti.com/switcherpro.
For more SWIFTTM documentation, see the TI
website at www.ti.com/swift.
vertical spacer
VIN
C
BOOT
VIN
BOOT
TPS54478
C
I
R
R
4
5
L
O
VOUT
EN
95
PH
C
O
90
R
1
2
PWRGD
V
= 5 V
85
80
75
70
65
60
IN
VSENSE
V
= 3.3 V
IN
R
SS/TR
RT /CLK
COMP
GND
AGND
C
POWERPAD
ss
R
R
T
3
C
F
= 1 MHz,
1
S
DCR = 6.8 mW,
= 1.8 V
55
50
V
O
0
0.5
1
1.5
2
2.5
3
3.5
4
I
- Output Current - A
O
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SWIFT, SwitcherPro are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
3 × 3 mm QFN
TPS54478RTE
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
VIN
–0.3 to 7
–0.3 to 7
PH + 7
–0.3 to 3
–0.3 to 3
–0.3 to 7
–0.3 to 3
–0.3 to 3.3
7
EN
BOOT
VSENSE
COMP
Input voltage
V
PWRGD
SS/TR
RT/CLK
BOOT-PH
PH
Output voltage
Source current
Sink current
–0.6 to 7
–2 to 10
100
V
PH 10 ns Transient
EN
µA
RT/CLK
COMP
100
100
µA
mA
µA
kV
V
PWRGD
SS/TR
10
100
Electrostatic discharge (Human Body Model) QSS 009-105 (JESD22-A114A)(2)
2
Electrostatic discharge (Charged Devic Model) QSS 009-147 (JESD22-C101B.01)
500
Tj
Temperature
Tstg
–40 to 150
–65 to 150
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
2
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
THERMAL INFORMATION
TPS54478
(RTE)
THERMAL METRIC(1)(2)(3)
UNITS
(QFN-16) PINS
θJA
Junction-to-ambient thermal resistance
49.1
0.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
Junction-to-board thermal resistance
ψJB
21.8
50.7
7.5
°C/W
θJC(top)
θJC(bottom)
θJB
21.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation may be limited by overcurrent protection
(3) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
CONDITIONS
MIN
TYP
MAX
UNIT
2.95
6.0
V
V
Input under voltage lockout threshold
Shutdown supply current
No voltage hysteresis
2.6
0.7
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
2.5
μA
μA
Quiescent Current - Iq
VSENSE = 0.7 V, VIN = 5 V, 25°C, RT = 78.7 kΩ
525
700
ENABLE AND UVLO (EN PIN)
Rising
1.30
1.21
Enable threshold
Input current
V
Falling
Enable threshold + 50 mV
Enable threshold – 50 mV
–3.4
μA
–0.64
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference
2.95 V ≤ VIN ≤ 6 V, –40°C <TJ < 150°C
0.594 0.600 0.606
V
MOSFET
BOOT-PH = 5 V
BOOT-PH = 3.3 V
VIN = 5 V
30
37
30
37
60
70
60
70
High side switch resistance
Low side switch resistance
mΩ
mΩ
VIN = 3.3 V
ERROR AMPLIFIER
Input current
7
nA
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
225
μmhos
Error amplifier transconductance (gm) during –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
77
μmhos
slow start
Vsense = 0.4 V
Error amplifier source/sink
COMP to Iswitch gm
V(COMP) = 1 V, 100 mV overdrive
±20
μA
14
A/V
Copyright © 2011, Texas Instruments Incorporated
3
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CURRENT LIMIT
CONDITIONS
MIN
TYP
MAX
UNIT
Current limit threshold
VIN = 6V, Fs = 500 KHz
5.2
6.5
512
8.2
A
Cycles before entering hiccup
Cycles of converter in off state during hiccup
Low side Fet reverse current limit
THERMAL SHUTDOWN
Thermal shutdown
Cycles
Cycles
A
16384
3.1
165
15
°C
°C
Hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
200
400
300
75
2000
600
kHz
kHz
kHz
ns
V
Switching frequency
R(RT/CLK) = 78.7 kΩ
500
Switching frequency range using CLK mode
Minimum CLK pulse width
RT/CLK voltage
2000
R(RT/CLK) = 78.7 kΩ
0.5
1.6
0.6
75
RT/CLK high threshold
RT/CLK low threshold
2.2
V
0.4
V
RT/CLK falling edge to PH rising edge delay
PLL lock in time
Measure at 500 kHz with RT resistor in series
Measure at 500 kHz
ns
μs
14
PH (PH PIN)
Measured at 50% points on PH, VIN = 5 V, IOUT = 2 A
100
120
Minimum On time
ns
Measured at 50% points on PH, VIN = 5 V,
IOUT = 0 A
Prior to skipping off pulses, VIN = 5 V,
IOUT = 2 A
Minimum Off time
110
ns
Rise Time
1.5
1.5
VIN = 5 V, 4 A
V/ns
Fall Time
BOOT (BOOT PIN)
BOOT Charge Resistance
BOOT-PH UVLO
VIN = 5 V
15
Ω
VIN = 2.95 V
2.2
V
SLOW START AND TRACKING (SS/TR PIN)
SS voltage threshold (VSSTHR
)
0.15
45
V
Charge Current
V
(SS/TR) < VSSTHR
(SS/TR) > VSSTHR
μA
V
2.2
65
SS/TR to VSENSE matching
V(SS/TR) = 0.3 V
mV
V
SS/TR to reference crossover
98% normal
0.86
2.5
900
SS/TR discharge voltage (Overload)
SS/TR discharge current (Overload)
VSENSE = 0 V
mV
µA
VSENSE = 0 V, V(SS/TR) = 0.4 V
SS discharge current (UVLO, EN, Thermal
fault)
VIN = 5 V, V(SS) = 0.5 V
1.16
mA
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault)
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling (Good)
VSENSE falling
93
95
107
105
2
VSENSE threshold
% Vref
Hysteresis
% Vref
nA
Output high leakage
On resistance
VSENSE = VREF, V(PWRGD) = 5.5 V
VIN = 2.95 V
7
56
120
Ω
4
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
0.2
MAX
0.3
UNIT
V
Output low
I(PWRGD) = 3 mA
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
1.2
1.6
V
DEVICE INFORMATION
PIN CONFIGURATION
QFN16
RTE PACKAGE
(TOP VIEW)
16
15
14
13
1
12
11
10
9
VIN
VIN
PH
2
3
PH
PH
PowerPAD
(17)
GND
4
SS/TR
GND
5
6
7
8
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
AGND
BOOT
NO.
5
Analog Ground should be electrically connected to GND close to the device.
13
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum
required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP
EN
7
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
15
Enable pin, internal pull-up current source. Pull below 1.21 V to disable. Float to enable. Can be used to set the
on/off threshold (adjust UVLO) with two additional resistors.
GND
PH
3, 4
Power Ground. This pin should be electrically connected directly to the power pad under the IC.
10, 11, The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier
12
MOSFET.
PowerPAD
PWRGD
17
GND pin should be connected to the exposed power pad for proper operation. This power pad should be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
14
An open drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent,
over/under-voltage or EN shut down.
RT/CLK
SS/TR
8
9
Resistor Timing or External Clock input pin.
Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time. The SS
provides higer charge current when SS is below 0.15V, resulting in two slopes of the SS voltage.
This pin can also be used for tracking.
VIN
1, 2, 16 Input supply voltage, 2.95 V to 6 V.
Copyright © 2011, Texas Instruments Incorporated
5
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NAME
NO.
VSENSE
6
Inverting node of the transconductance (gm) error amplifier.
FUNCTIONAL BLOCK DIAGRAM
VIN
Shutdown
Thermal
Shutdown
Enable
Comparator
93%
Logic
Shutdown
Shutdown
Logic
107%
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
COMP Clamp
Current
Sense
ERROR
AMPLIFIER
PWM
Comparator
VSENSE
SS/TR
BOOT
PWM
Latch
R
Q
Logic
Logic
S
Shutdown
Logic
Slope
Compensation
PH
COMP
Maximum
Clamp
Overload
Recovery
Oscillator
with PLL
PGND
TPS54478RTE Block Diagram
GND
RT/CLK
POWERPAD
6
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
TYPICAL CHARACTERISTICS CURVES
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
VIN SUPPLY CURRENT vs TEMPERATURE
580
570
560
550
540
530
520
510
500
3
2.5
2
V
= 5 V
IN
V
= 5 V
IN
1.5
1
V
= 3.3 V
IN
V
= 3.3 V
IN
0.5
0
490
480
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 1.
Figure 2.
EN PIN VOLTAGE vs TEMPERATURE
EN PIN CURRENT vs TEMPERATURE
1.32
1.31
1.3
0
-0.5
-1
EN Rising, Vin = 3.3 V
EN Pin Current @ Vin = 5 V, VEN = Threshold - 50 mV
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
EN Pin Current @ Vin = 3.3 V, VEN = Threshold - 50 mV
EN Rising, Vin = 5 V
-1.5
-2
-2.5
-3
EN Falling, Vin = 3.3 V
EN Pin Current @ Vin = 5 V, VEN = Threshold + 50 mV
EN Pin Current @ Vin = 3.3 V, VEN = Threshold + 50 mV
-3.5
-4
EN Falling, Vin = 5 V
1.19
1.18
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 3.
Figure 4.
VOLTAGE REFERENCE vs
TEMPERATURE
MOSFET Rdson vs TEMPERATURE
60
55
50
45
40
35
30
25
20
0.606
0.605
0.604
0.603
0.602
0.601
0.6
High Side Rdson Vin = 3.3 V
Low Side Rdson Vin = 3.3 V
V
= 5 V
IN
0.599
0.598
0.597
0.596
V
= 3.3 V
IN
Low Side Rdson Vin = 5 V
0.595
0.594
High Side Rdson Vin = 5 V
25 50
-50
-25
0
25
50
75
100
125
150
-50
-25
0
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 5.
Figure 6.
Copyright © 2011, Texas Instruments Incorporated
7
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS CURVES (continued)
HIGH SIDE FET CURRENT LIMIT vs
TEMPERATURE
TRANSCONDUCTANCE vs TEMPERATURE
7
6.5
6
310
290
270
250
230
210
V
= 5 V
IN
V
= 3.3 V
IN
V
= 3.3 V
IN
V
= 5 V
IN
5.5
190
170
5
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
150
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 7.
Figure 8.
SWITCHING FREQUENCY vs RT RESISTANCE
SWITCHING FREQUENCY vs TEMPERATURE
2000
1800
1600
1400
1200
1000
800
500
495
490
485
480
475
RT = 84 kW,
Vin = 5 V
600
400
200
0
10
30
50
70
90
110
130
150
-50
-25
0
25
50
75
100
125
RT - Resistance - kW
T
- Junction Temperature - °C
J
Figure 9.
Figure 10.
VSS VOLTAGE THRESHOLD VSSTHR vs TEMPERATURE
SS CHARGE CURRENT vs TEMPERATURE
0.16
-40
-41
-42
-43
-44
-45
-46
-47
-48
0.159
0.158
V
= 3.3 V
IN
0.157
0.156
0.155
0.154
0.153
0.152
Vin = 5 V, Vss < 0.15 V
V
= 5 V
IN
Vin = 3.3 V, Vss < 0.15 V
0.151
0.15
-49
-50
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 11.
Figure 12.
8
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
TYPICAL CHARACTERISTICS CURVES (continued)
SS CHARGE CURRENT vs TEMPERATURE
PWRGD Rdson vs TEMPERATURE
100
-2
-2.1
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
-2.8
-2.9
-3
Vin = 5 V; Vss = 0.4 V
90
80
Vin = 3.3 V; Vss = 0.4 V
70
V
= 5 V
IN
60
50
40
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 13.
Figure 14.
PWRGD THRESHOLD vs TEMPERATURE
PWRGD LEAKAGE CURRENT vs TEMPERATURE
110
108
106
104
102
100
98
20
18
16
14
12
10
8
Vsense (Fault) Rising
Vsense (Good) Falling
Vsense (Good) Falling
V
= 5.5 V
IN
96
6
94
4
92
Vsense (Fault) Falling
2
90
0
88
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 15.
Figure 16.
EFFICIENCY vs LOAD CURRENT
EFFICIENCY vs LOAD CURRENT
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
V
= 2.5 V
O
V
= 3.3 V
O
V
= 1.8 V
O
V
= 2.5 V
O
V
= 1.8 V
V
= 1.2 V
O
O
V
= 1.2 V
O
V
= 1 V
O
V
= 1 V
O
Vin = 5 V,
Vin = 3.3 V,
DCR = 6.8 mW,
Fs = 1 MHz,
Tj = 25°C
DCR = 6.8 mW,
Fs = 1 MHz,
Tj = 25°C
55
50
0
0.5
1
1.5
2
2.5
- Output Current - A
3
3.5
4
0
0.5
1
1.5
2
2.5
- Output Current - A
3
3.5
4
I
I
O
O
Figure 17.
Figure 18.
Copyright © 2011, Texas Instruments Incorporated
9
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS CURVES (continued)
EFFICIENCY vs LOAD CURRENT
EFFICIENCY vs LOAD CURRENT
100
95
90
85
80
75
70
65
60
55
50
100
95
90
V
= 3.3 V
V
O
V
= 2.5 V
V
O
85
80
75
70
65
60
= 2.5 V
O
= 1.8 V
V
O
V
= 1.8 V
O
= 1.2 V
V
O
V
= 1.2 V
O
= 1 V
O
V
= 1 V
O
Vin = 3.3 V,
DCR = 18 mW,
Fs = 500 kHz,
Tj = 25°C
Vin = 5 V,
DCR = 18 mW,
Fs = 500 kHz,
Tj = 25°C
55
50
0
0.5
1
1.5
2
2.5
- Output Current - A
3
3.5
4
0
0.5
1
1.5
2
2.5
- Output Current - A
3
3.5
4
I
I
O
O
Figure 19.
Figure 20.
OVERVIEW
The TPS54478 is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs.
To improve performance during line and load transients the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54478 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54478 is typically 525 μA when not switching and under no load. When the device
is disabled, the supply current is less than 2.5 μA.
The integrated 30 mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 4 amperes.
The TPS54478 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot
capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54478 to operate approaching 100%. The output
voltage can be stepped down to as low as the 0.600 V reference.
TPS54478 features monotonic starup under pre-bias conditions. The low side Fet turns on for a very short time
period every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has
enough charge to turn on the top Fet when the output voltage reaches the pre-biased voltage.
The TPS54478 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54478 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power
good comparator. When the regulated output voltage is greater than 107% of the nominal voltage, the
overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until
the output voltage is lower than 105%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault
or disabled condition. To optimize the output startup waveform, two levels of SS current are implemented. The
first slope has more current so that the converter can get out of the region requiring small minimum ON time.
10
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
To reduce the power dissipation of TPS54478 during overcurrent event, the hiccup protection is implemented
beyond the cycle-by-cycle protection. Thermal shutdown prevents the overheat damage of the device.
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54478 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient response performance.
SLOPE COMPENSATION AND OUTPUT CURRENT
The TPS54478 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the
full duty cycle range.
BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION
The TPS54478 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the TPS54478 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low
side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Since the supply current
sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.
ERROR AMPLIFIER
The TPS54478 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower
of the SS/TR pin voltage or the internal 0.600 V voltage reference. The transconductance of the error amplifier is
225μA/V during normal operation. When the voltage of VSENSE pin is below 0.600 V and the device is
regulating using the SS/TR voltage, the gm is typically greater than 77 μA/V, but less than 225 μA/V. The
frequency compensation components are placed between the COMP pin and ground.
VOLTAGE REFERENCE
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.600 V at the non-inverting
input of the error amplifier.
ADJUSTING THE OUTPUT VOLTAGE
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 20 kΩ for the R1 resistor and use the Equation 1 to
calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are too
high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
vertical spacer
vertical spacer
æ
ç
è
ö
÷
ø
0.6 V
R2 = R1 ´
VO - 0.6 V
(1)
11
Copyright © 2011, Texas Instruments Incorporated
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
TPS54478
V
O
R1
R2
VSENSE
–
+
0.6 V
Figure 21. Voltage Divider Circuit
ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT
The TPS54478 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher
under-voltage lockout (UVLO), use the EN pin as shown in Figure 22 to adjust the input voltage UVLO by using
two external resistors. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) above
2.6V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply
variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54478
operating when the EN pin floats. Once the EN pin voltage exceeds 1.30 V, an additional 2.76 μA of hysteresis is
added. When the EN pin is pulled below 1.21 V, the 2.76 μA is removed. This additional current facilitates input
voltage hysteresis.
TPS54478
i
hys
VIN
2.76 mA
i
p
R1
R2
0.64 mA
+
EN
Vena
–
Figure 22. Adjustable Under Voltage Lock Out
æ
ç
è
ö
VENFALLING
VSTART
- VSTOP
÷
VENRISING
ø
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+I
p ç
h
VENRISING
è
(2)
(3)
vertical spacer
R1´ VENFALLING
R2 =
VSTOP - VENFALLING + R1(Ip + Ih )
Where Ih = 2.76uA, Ip = 0.64uA, VENRISING = 1.30V, VENFALLING = 1.21V
12
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
SLOW START / TRACKING PIN
The TPS54478 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the
SS/TR pin to ground implements a slow start time. Before the SS pin reaches the voltage threshold VSSTHR, the
charge current is about 45 μA. The TPS54478 internal pull-up current source of 2.2 μA charges the external slow
start capacitor after the SS pin voltage exceeds VSSTHR. Equation 4 calculates the required slow start capacitor
value where Tss is the desired slow start time in ms and Css is the required capacitance in nF.
vertical spacer
Css(nF) = 3 ´ Tss(mS)
(4)
If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.21 V, or a thermal shutdown
event occurs, the TPS54478 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or
a thermal shutdown is exited, then SS/TR is discharged to below 65 mV before reinitiating a powering up
sequence. The VSENSE voltage will follow the SS/TR pin voltage with a 65mV offset up to 90% of the internal
voltage reference. When the SS/TR voltage is greater than 90% of the internal reference voltage the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
SEQUENCING
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin
of another device. Figure 23 shows the sequential method. The PWRGD is coupled to the EN pin on the
TPS54478 which enables the second power supply once the primary supply reaches regulation.
Ratio-metric start up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp
up and reach regulation at the same time. When calculating the slow start time the pull up current source must
be doubled in Equation 4. The ratio metric method is illustrated in Figure 25.
TPS54478
PWRGD1
EN1
EN1
EN2
SS1
SS2
VO1
PWRGD2
PWRGD1
VO2
t - Time=1 ms/div
Figure 23. Sequential Start-Up Sequence
Figure 24. Sequential Startup using EN and
PWRGD
Copyright © 2011, Texas Instruments Incorporated
13
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
TPS54478
EN1
EN1
SS/TR1
Io
Vo1
Vo2
PWRGD1
TPS54478
EN2
t - Time = 1 ms/div
SS/TR2
PWRGD2
Figure 25. Schematic for Ratio-metric Start-Up
Figure 26. Ratio-metric Startup
Sequence
vertical spacer
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2
shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage reference
source. Using Equation 5 and Equation 6, the tracking resistors can be calculated. To minimize the effect of the
inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current
source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. As the
SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the
slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage needs to be greater than 0.86 V for a complete handoff to the internal voltage reference as shown in
Figure 28.
vertical spacer
Vout2
Vssoffset
Iss
R1 =
´
Vref
(5)
(6)
vertical spacer
Vref ´ R1
R2 =
Vout2 - Vref
vertical spacer
vertical spacer
vertical spacer
14
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
TPS54478
EN1
VOUT1
SS/TR1
PWRGD1
TPS54478
VOUT2
EN2
EN1 = 5 / div
SS2 = 500 mV / div
Vo1 = 500 mV / div
Vo2 = 500 mV / div
R1
R2
SS/TR2
PWRGD2
Time = 1 msec / div
Figure 27. Simultaneous Startup Sequence
Figure 28. Simultaneous Start-Up using Coupled
SS/TR Pins
CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)
The switching frequency of the TPS54478 is adjustable over a wide range from 200 kHz to 2000 kHz by placing
a maximum of 150 kΩ and minimum of 16 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 5 or
Equation 7.
90066
Fs(kHz)1.135
RT (kW) =
(7)
vertical spacer
23439
RT(kW)0.8813
Fs(kHz) =
(8)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 100 ns at full current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
OVERCURRENT PROTECTION
The TPS54478 implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET and turn on the low side MOSFET on a cycle by cycle basis. Each cycle the switch current and the
COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high side
switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond
by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally.
This clamp functions as a switch current limit. When the OCP reaches 512 cycles, the converter enters hiccup
mode in which no switching action happens for about 16000 cycles. This helps the reduction of the power
consumption during the over current event.
Copyright © 2011, Texas Instruments Incorporated
15
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
START-UP into Pre-Biased Output
The TPS54478 features monotonic startup into pre-biased output. The low side Fet turns on for a very short time
period every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has
enough charge to turn on the top Fet when the output voltage reaches the pre-biased voltage. The TPS54478
also implements low side current protection by detecting the voltage over the low side MOSFET. When the
converter sinks current through its low side FET is more than 3.1A, the control circuit will turn the low side Fet
off. Due to the implemented prebias function, the low side Fet reverse current protection should not be reached,
but it provides another layer of protection in the undesired events such as oscillation induced by load.
SYNCHRONIZE USING THE RT/CLK PIN
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement
the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least
75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set
by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is
synchronized to the falling edge of RT/CLK pin.
TPS54478
EXT_CLK
PLL
RT/CLK
Clock
RT
Source
PH
t - Time = 1 ms/div
Figure 29. Synchronizing to a System Clock
Figure 30. Plot of Synchronizing to System Clock
16
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
POWER GOOD (PWRGD PIN)
The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 93% or rising above 107% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 95%
or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is
recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or
less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.6 V.
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54478 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 107%
of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next
clock cycle.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 150°C, the device reinitiates the power up sequence
by discharging the SS pin to below 65 mV. The thermal shutdown hysteresis is 15°C.
SMALL SIGNAL MODEL FOR LOOP RESPONSE
Figure 31 shows an equivalent model for the TPS54478 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response without slope compensation effect. The error
amplifier is a transconductance amplifier with a gm of 225 μA/V. The error amplifier can be modeled using an
ideal voltage controlled current source. The resistor R0 and capacitor Co model the open loop gain and
frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks
the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the
frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop
response can be checked by replacing the RL with a current source with the appropriate load step amplitude and
step rate in a time domain analysis.
PH
VO
Power Stage
14 A/V
a
b
R1
RESR
RL
COMP
c
COUT
VSENSE
R2
0.6 V
CO RO
R3
C1
gm
225 µA/V
C2
Figure 31. Small Signal Model for Loop Response without Slope Comp Effect
Copyright © 2011, Texas Instruments Incorporated
17
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation without slope compensation effect. The TPS54478 power stage can be approximated to a voltage
controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The
control to output transfer function is shown in Equation 9 and consists of a dc gain, one dominant pole and one
ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in
Figure 31) is the power stage transconductance. The gm for the TPS54478 is 14 A/V. The low frequency gain of
the power stage frequency response is the product of the transconductance and the load resistance as shown in
Equation 10. As the load current increases and decreases, the low frequency gain decreases and increases,
respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with
load current [see Equation 11]. The combined effect is highlighted by the dashed line in the right half of
Figure 32. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation.
vertical spacer
vertical spacer
VO
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
Figure 32. Simple Small Signal Model and Frequency Response for Peak Current Mode Control without
Slope Comp Effect
æ
ç
è
æ
ç
è
s
ö
÷
ø
ö
÷
ø
1+
1+
2p × ¦z
vo
vc
= Adc ´
s
2p × ¦p
(9)
Adc = gmps ´ RL
(10)
1
¦p =
COUT ´ RL ´ 2p
(11)
(12)
vertical spacer
¦z =
1
COUT ´ RESR ´ 2p
SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION
The TPS54478 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 33. The Type 2
circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high frequency pole is added to attenuate high frequency noise.
18
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
VO
R1
VSENSE
Vref
Type 2A
Type 2B
COMP
gm
ea
CO
R3
C1
C2
R3
RO
R2
5pF
C1
Figure 33. Type-II of Frequency Compensation
The design guidelines for TPS54478 loop compensation will be addressed in the APPLICATION INFORMATION
section with more details. The approach is to run the Pspice model first to find the accurate response of the
power stage with slope compensation effect. The compensation network is then designed based on the desired
crossover frequency. The crossover frequency and phase margin are more closer to the measured results when
the slope compensation effect is included.
For type-II compensation, the modulator pole, fpmod, and the esr zero, fz1 can be calculated using Equation 13
and Equation 14. Derating the output capacitor (COUT) is needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 15 and
Equation 16 to estimate a starting point for the crossover frequency, fc. Equation 15 is the geometric mean of the
modulator pole and the esr zero and Equation 16 is the mean of modulator pole and the switching frequency.
Use the lower value of Equation 15 or Equation 16 as the maximum crossover frequency.
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(13)
vertical spacer
1
¦z mod =
2p ´ Resr ´ Cout
(14)
vertical spacer
¦
=
¦p mod´ ¦z mod
vertical spacer
¦p mod´
C
(15)
(16)
¦sw
¦
=
C
2
vertical spacer
The type-III compensation is recommended to achieve higher crossover frequency by introducing extra phase lift.
By adding a small capacitor C3 in parallel with R1, one-pair of zero and pole is generated as given by
Equation 17 and Equation 18. The following APPLICATION INFORMATION section provides step-by-step design
guideline for the type-III compensation wih the effect of slope compensation included.
Copyright © 2011, Texas Instruments Incorporated
19
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
Vo
R1
VSENSE
Vref
C3
gm
ea
Type 3A
Type 3B
COMP
R3
C1
RO
R2
C2
R3
CO
5 pF
C1
Figure 34. Type-III of Frequency Compensation
1
¦z =
¦p =
2p´R1´ C3
(17)
(18)
1
2p´(R1/ /R2)´ C3
20
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
This design is available as the TPS54478EVM-037 (PWR037) evaluation module (EVM). A few parameters must
be known in order to start the design process. These parameters are typically determined on the system level.
For this example, we start with the following known parameters:
Output Voltage
1.8 V
Transient Response 1 A to 3.0 A load step
Maximum Output Current
Input Voltage
ΔVout = 3%
4 A
3 V to 6V, 5 V nominal
< 30 mV p-p
1000 kHz
Output Voltage Ripple
Switching Frequency (Fsw)
The schematic diagram for this design example is shown in Figure 35. The component reference designators of
this schematic are used for the equations in APPLICATION INFORMATION.
SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible since this produces the smallest solution size. The high switching frequency allows
for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s
performance. The converter is capable of running from 300 kHz to 2 MHz. Unless a small solution size is an
ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a
high efficiency operation. Using Equation 7, R4 is calculated to be 35.4 kΩ. A standard 1% 35.7 kΩ value was
chosen in the design.
Copyright © 2011, Texas Instruments Incorporated
21
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
Figure 35. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO
22
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
OUTPUT INDUCTOR SELECTION
The inductor selected works for the entire TPS54478 input voltage range. To calculate the value of the output
inductor, use Equation 19. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.05 μH. For this design, a
nearest standard value was chosen: 1.2 μH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 21 and Equation 22.
For this design, the RMS inductor current is 4.01 A and the peak inductor current is 4.53 A. The chosen inductor
is a Coilcraft XAL5030-122ME. It has a saturation current rating 0f 11.8 A (20% inductance loss) and a RMS
current rating of 8.7 A (20 °C. temperature rise). The series resistance is 6.78 mΩ typical.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
L1 =
´
Io ´ Kind
Vinmax ´ ¦sw
(19)
vertical spacer
Vinmax - Vout
Vout
Iripple =
´
L1
Vinmax ´ ¦sw
(20)
vertical spacer
æ
ö2
÷
1
Vo ´ (Vinmax - Vo)
Vinmax ´ L1 ´ ¦sw
ILrms = Io2
+
´
ç
12
è
ø
(21)
(22)
vertical spacer
ILpeak = Iout +
Iripple
2
OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing
a tolerable amount of droop in the output voltage. Equation 23 shows the minimum output capacitance necessary
to accomplish this.
Copyright © 2011, Texas Instruments Incorporated
23
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
For this example, the transient load response is specified as a 3% change in Vout for a load step from 1 A (25%
load) to 3 A (75% load). For this example, ΔIout = 3 - 1 = 2.0A and ΔVout= 0.03 × 1.8 = 0.054 V. Using these
numbers gives a minimum capacitance of 74.1 μF. This value does not take the ESR of the output capacitor into
account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this
calculation.
Equation 24 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,
Equation 24 yields 4.4 uF.
vertical spacer
2 ´ DIout
Co >
¦sw ´ DVout
(23)
vertical spacer
1
1
Co >
´
Voripple
8 ´ ¦sw
Iripple
Where ΔIout is the change in output current, fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage.
(24)
vertical spacer
Equation 25 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 25 indicates the ESR should be less than 28.6 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 28.6 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 47 μF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used. The
estimated capacitance after derating is 2 x 45 µF = 90 µF.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 26 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 26 yields
303 mA.
Voripple
Resr <
Iripple
(25)
vertical spacer
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(26)
INPUT CAPACITOR
The TPS54478 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54478.
The input ripple current can be calculated using Equation 27.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
24
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 28. Using the design example values, Ioutmax=4 A, Cin=10 μF, Fsw=1
MHz, yields an input voltage ripple of 99 mV and a rms input ripple current of 1.95 A.
Vinmin - Vout
(
)
Vout
Icirms = Iout ´
´
Vinmin
Vinmin
(27)
(28)
vertical spacer
Ioutmax ´ 0.25
Cin ´ ¦sw
DVin =
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54478 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 29. For the example circuit, the slow start time is
not too critical since the output capacitor value is 2 x 47 μF which does not require much current to charge to 1.8
V. The example circuit has the slow start time set to an arbitrary value of 3.33 ms which requires a 10 nF
capacitor.
C6(nF) = 3 × Tss(mS)
(29)
BOOTSTRAP CAPACITOR SELECTION
A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 10.0 kΩ was selected for R7. Using Equation 30, R6 is calculated as 20.0 kΩ. The
nearest standard 1% resistor is 20.0 kΩ.
æ
ç
è
ö
VOUT
R6 = R7 ×
-1
÷
VREF
ø
(30)
Due to the internal design of the TPS54478, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 31
Voutmin = Ontimemin´Fsmax ´ Vinmax - loutmin´RDSmin -Ioutmin´ RL + RDSmin
(
(
)
)
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (100 ns typical. 120 ns no load)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDSmin = minimum high-side MOSFET on resistance (See Electrical Characteristics)
RL = series resistance of output inductor
(31)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 32
Copyright © 2011, Texas Instruments Incorporated
25
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
Offtimemax
ts
tdead
ts
æ
ö
æ
ö
Voutmax = Vin´ 1-
-Ioutmax ´ RDSmax + RI - 0.7 -Ioutmax ´RDSmax ´
(
) (
)
ç
÷
ç
÷
è
ø
è
ø
Where:
Voutmax = maximum achievable output voltage
Vin = minimum input voltage
Offtimemax = maximum off time (180 ns typical for adequate margin)
ts = 1/Fs
Ioutmax = maximum current
RDSmax = maximum high-side MOSFET on resistance (See Electrical Characteristics)
RI = DCR of the inductor
tdead = dead time (40 ns)
(32)
COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 33.
1
F
=
PMOD
2× p ×COUT ×ROUT
(33)
For the TPS54478 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of SLVM279 apply the values calculated previously to the output filter components of L1, C9 and
C10. Set Rload to the appropriate value. For this design, L1 = 1.2 µH. C8 and C9 use the derated capacitance
value of 45 µF, and the ESR is set to 3 mohm. The Rload resistor is 1.8 / 4 = 450 mΩ. Now the power stage
characteristic can be plotted as shown in Figure 36.
60
180
120
60
40
Gain
20
-0
0
-12.03 dB
-20
-40
-60
-60
-120
-180
Phase
>>
0.1
1
10
100
1000
Frequency - kHz
Figure 36. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 70 kHz. From the power stage gain and phase plots, the
gain at 70 kHz is -12.03 dB and the phase is -131.86 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 34.
26
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
-GPWRSTG
SLVSAS2 –JUNE 2011
20
Vout
10
R3 =
×
gmEA
VREF
(34)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 70 kHz.
The required value for C5 is given by Equation 35.
1
C5 =
FCO
2× p ×R3 ×
10
(35)
To maximize phase gain the high frequency pole is not implemented and C4 is not populated. The pole can be
useful to offset the ESR of aluminum electrolytic output capacitors. If desired the value for C4 can be calculated
from Equation 36.
1
C4 =
2× p ×R3 ×F
P
(36)
For maximum phase boost, the pole frequency FP will typically be one decade above the intended crossover
frequency FCO
.
The feed forward capacitor C10, is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair located at Equation 37 and
Equation 38.
1
FZ =
2× p ×C10 ×R6
(37)
1
F =
P
2× p ×C10 ×R6 P R7
(38)
This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. For
optimum performance, the zero and pole should be located symmetrically about the intended crossover
frequency. The required value for C10 can calculated from Equation 39.
1
C10 =
VREF
2× p ×R6 ×FCO
×
VOUT
(39)
For this design the calculated values for the compensation components are R3 = 30.6 kΩ ,C5 = 736 pF and C10
= 197 pF. Using standard values, the compensation components are R3 = 30.9 kΩ ,C5 = 820 pF and C10 = 220
pF.
APPLICATION CURVES
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
V
= 3.3 V
V
= 3.3 V
IN
IN
V
= 5 V
IN
V
= 5 V
IN
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0.001
0.01
0.1
Output Current - A
1
10
Output Current - A
Figure 37. EFFICIENCY vs LOAD CURRENT
Figure 38. EFFICIENCY vs LOAD CURRENT
Copyright © 2011, Texas Instruments Incorporated
27
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
V
= 5 V/div
IN
V
= 50 mV / div (ac coupled)
OUT
EN = 5 V/div
V
= 2 V/div
I
= 1 A / div
OUT
OUT
Load step = 1 - 3 A, slew rate = 0.167 A / ms
PWRGD = 5 V/div
Time = 100 ms/div
Time = 2 ms/div
Figure 39. TRANSIENT RESPONSE, 2 A STEP
Figure 40. POWER UP VOUT, VIN
V
= 5 V/div
IN
EN = 5 V/div
EN = 5 V/div
V
= 2 V/div
OUT
V
= 500 mV/div
OUT
PWRGD = 5 V/div
Pre-bias voltage = 500 mV
Time = 2 ms/div
Time = 2 msec / div
Figure 41. POWER UP VOUT, EN
Figure 42. POWER UP INTO PRE-BIAS VOLTAGE
V
= 5 V/div
V
= 5 V/div
IN
IN
EN = 5 V/div
EN = 5 V/div
V
= 2 V/div
VOUT = 2 V/div
OUT
PWRGD = 5 V/div
PWRGD = 5 V/div
Time = 2 ms/div
Time = 2 ms/div
Figure 43. POWER DOWN VOUT, VIN
Figure 44. PWER DOWN VOUT, EN
28
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
V
= 100 mV/div (ac coupled)
IN
V
= 20 mV/div (ac coupled)
OUT
PH = 2 V/div
PH = 2 V/div
Time = 500 ns/div
Time = 500 ns/div
Figure 45. OUTPUT RIPPLE, IOUT = 4 A
Figure 46. INPUT RIPPLE, IOUT = 4 A
0.2
0.15
0.1
180
150
120
90
60
50
40
V
= 5 V
IN
Phase
30
60
20
Gain
0.05
0
V
= 3.3 V
30
10
IN
0
0
-30
-60
-90
-120
-150
-180
-10
-20
-30
-40
-50
-60
-0.05
-0.1
-0.15
-0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
10
100
1k
10k
100k
1M
Output Current - A
f - Frequency - Hz
Figure 47. CLOSED LOOP RESPONSE, VIN = 5 V,
IOUT = 4 A
Figure 48. OUTPUT VOLTAGE REGULATION vs
LOAD CURRENT
0.1
I
= 2 A
OUT
0.08
0.06
0.04
0.02
0
V
= 1 V/div
OUT
-0.02
-0.04
-0.06
-0.08
-0.1
I
= 5 A/div
OUT
Time = 1 ms/div
3
3.5
4
4.5
5
5.5
6
Input Voltage - V
Figure 49. OUTPUT VOLTAGE REGULATION vs
INPUT VOLTAGE
Figure 50. HICCUP MODE CURRENT LIMIT
Copyright © 2011, Texas Instruments Incorporated
29
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
V
= 1 V/div
OUT
V = 500 mV/div
OUT
I
= 5 A/div
OUT
Time = 500 ms/div
Time = 5 ms/div
Figure 51. HICCUP MODE CURRENT LIMIT
Figure 52. START UP CHARACTERISTIC
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = Io2 × RDS_on_Temp
Pd = ƒsw × Io × 0.7 × 40 × 10–9
Psw = 1/2 × Vin × Io × ƒsw× 7 × 10–9
Pgd = 2 × Vin × ƒsw× 6 × 10–9
Pq = Vin × 525 × 10–6
Where:
IO is the output current (A).
RDS_on_Temp is the on-resistance of the high-side MOSFET with given temperature (Ω).
Vin is the input voltage (V).
ƒsw is the switching frequency (Hz).
30
Copyright © 2011, Texas Instruments Incorporated
TPS54478
www.ti.com
SLVSAS2 –JUNE 2011
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 150°C
TAmax = TJ max – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 53 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located very close to the
PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected
to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
Copyright © 2011, Texas Instruments Incorporated
31
TPS54478
SLVSAS2 –JUNE 2011
www.ti.com
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
BOOT
CAPACITOR
VIN
INPUT
OUTPUT
INDUCTOR
VIN
VIN
PH
PH
PH
SS
VOUT
BYPASS
CAPACITOR
OUTPUT
FILTER
EXPOSED
POWERPAD
AREA
CAPACITOR
GND
GND
PH
SLOW START
CAPACITOR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 53. PCB Layout Example
32
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54478RTER
TPS54478RTET
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
RFID
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明