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TPS54494RSAT [TI]

具有集成 FET 的 4A 双通道同步降压转换开关 | RSA | 16 | -40 to 85;
TPS54494RSAT
型号： TPS54494RSAT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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具有集成 FET 的 4A 双通道同步降压转换开关 | RSA | 16 | -40 to 85

开关 控制器 开关式稳压器 开关式控制器 输出元件 电源电路 开关式稳压器或控制器
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TPS54494  
www.ti.com  
SLVSBH1 –JUNE 2012  
4A/2A Dual Channel Synchronous Step-Down Switcher with Integrated FET  
Check for Samples: TPS54494  
1
FEATURES  
APPLICATIONS  
2
•
D-CAP2™ Control Mode  
•
Point-of-Load Regulation in Low Power  
Systems for Wide Range of Applications  
–
–
Fast Transient Response  
–
–
–
–
–
Digital TV Power Supply  
Networking Home Terminal  
Digital Set Top Box (STB)  
DVD Player/Recorder  
No External Parts Required For Loop  
Compensation  
–
Compatible with Ceramic Output  
Capacitors  
•
•
•
Wide Input Voltage Range : 4.5 V to 18 V  
Output Voltage Range : 0.76V to 7V  
Gaming Consoles and Other  
DESCRIPTION  
Highly Efficient Integrated FETs Optimized for  
Low Duty Cycle Applications  
The TPS54494 is a dual, adaptive on-time D-CAP2™  
mode synchronous buck converter. The TPS54494  
enables system designers to complete the suite of  
various end equipment’s power bus regulators with a  
cost effective, low component count, and low standby  
current solution. The main control loops of the  
TPS54494 use the D-CAP2™ mode control which  
provides a very fast transient response with no  
external compensation components. The adaptive on-  
time control supports seamless transition between  
PWM mode at higher load conditions and Eco-  
mode™ operation at light loads. Eco-mode™ allows  
the TPS54494 to maintain high efficiency during  
lighter load conditions. The TPS54494 is able to  
adapt to both low equivalent series resistance (ESR)  
output capacitors such as POSCAP or SP-CAP, and  
ultra-low ESR, ceramic capacitors. The device  
provides convenient and efficient operation with input  
voltages from 4.5V to 18V.  
–
90 mΩ (High Side) and 60 mΩ (Low Side)  
•
•
•
•
•
•
•
•
•
•
•
High Initial Reference Accuracy  
4A CH1 / 2A CH2 Continuous Load Current  
Low-Side rDS(on) Loss-Less Current Sensing  
Fixed Soft Start : 1.0ms  
Non-Sinking Pre-Biased Soft Start  
Powergood  
700 kHz Switching Frequency  
Cycle-by-Cycle Over-Current Limit Control  
OCL/UVLO/TSD Protections  
Hiccup Timer for Overload Protection  
Adaptive Gate Drivers with Integrated Boost  
PMOS Switch  
•
OCP Constant Due To Thermally Compensated  
rDS(on) with 4000ppm/℃  
The TPS54494 is available in a 4.4mm×5.0mm 16 pin  
TSSOP (PWP) package, and is specified for an  
ambient temperature range from –40°C to 85°C.  
•
•
16-Pin HTSSOP  
Auto-Skip Eco-mode™ꢀfor High Efficiency at  
Light Load  
Input Voltage  
V
= 1.5 V (50 mV/div)  
O2  
1
VIN2  
VIN1  
16  
15  
C12  
C11  
2
3
VBST1  
VBST2  
VO1  
C32  
C31  
L12  
L11  
VO2  
SW2 14  
SW1  
C22  
C21  
4
5
PGND1  
EN1  
PGND213  
EN2 12  
TPS54494  
Iout (1 A/div)  
HTSSOP16  
PGND  
PGND  
PG1  
6
7
8
PG2 11  
(PowerPAD)  
R11  
R21  
R12  
R22  
VFB1  
GND  
10  
VFB2  
C4  
9
t - Time - 100 ms/div  
VREG5  
PGND  
SGND  
SGND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  
TPS54494  
SLVSBH1 –JUNE 2012  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2) (3)  
ORDERING PART NUMBER  
PINS  
OUTPUT SUPPLY  
Tape-and-Reel  
Tube  
TPS54494PWPR  
–40℃ to 85℃  
PWP  
16  
TPS54494PWP  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) All packaging options have Cu NIPDAU lead/ball finish.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
(2)  
VALUE  
–0.3 to 20  
–0.3 to 26  
–0.3 to 28  
–0.3 to 6.5  
–0.3 to 6.5  
–2 to 20  
–3 to 22  
–0.3 to 6.5  
–0.3 to 0.3  
2
UNIT  
VIN1, VIN2, EN1, EN2  
VBST1, VBST2  
VBST1, VBST2 (10ns transient)  
VBST1–SW1 , VBST2–SW2  
VFB1, VFB2  
Input voltage range  
V
SW1, SW2  
SW1, SW2 (10ns transient)  
VREG5, PG1, PG2  
Output voltage range  
Electrostatic discharge  
V
PGND1, PGND2  
Human Body Model (HBM)  
Charged Device Model (CDM)  
kV  
V
500  
TA  
Operating ambient temperature range  
Storage temperature range  
–40 to 85  
–55 to 150  
–40 to 150  
°C  
°C  
°C  
TSTG  
TJ  
Junction temperature range  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to IC GND terminal.  
THERMAL INFORMATION  
TPS54494  
THERMAL METRIC(1)  
UNITS  
PWP (16) PINS  
θJA  
Junction-to-ambient thermal resistance  
41.4  
27.8  
23.2  
0.9  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
23.0  
3.5  
θJCbot  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
2
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54494  
TPS54494  
www.ti.com  
SLVSBH1 –JUNE 2012  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
VALUES  
UNIT  
MIN  
4.5  
MAX  
18  
Supply input voltage range  
Input voltage range  
VIN1, VIN2  
V
VBST1, VBST2  
–0.1  
–0.1  
–0.1  
–0.1  
–0.1  
–1.0  
–3  
24  
VBST1, VBST2 (10ns transient)  
VBST1–SW1, VBST2–SW2  
VFB1, VFB2  
27  
5.7  
5.7  
18  
V
EN1, EN2  
SW1, SW2  
18  
SW1, SW2 (10ns transient)  
VREG5, PG1 , PG2  
PGND1, PGND2  
VO1, VO2  
21  
–0.1  
–0.1  
0.76  
–40  
–40  
5.7  
0.1  
7.0  
85  
Output voltage range  
V
TA  
TJ  
Operating free-air temperature  
Operating Junction Temperature  
°C  
°C  
150  
ELECTRICAL CHARACTERISTICS(1)  
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SUPPLY CURRENT  
TA = 25°C, EN1 = EN2 = 5 V,  
VFB1 = VFB2 = 0.8 V  
IIN  
VIN supply current  
1200  
15  
2000  
20  
µA  
µA  
IVINSDN  
VIN shutdown current  
TA = 25°C, EN1 = EN2 = L after H,  
FEEDBACK VOLTAGE  
VVFBTHLx  
TCVFBx  
IVFBx  
VFBx threshold voltage  
TA = 25°C, CH1 = 3.3 V, CH2 = 1.5 V  
On the basis of 25°C(2)  
758  
–115  
–0.4  
765  
0.2  
773  
115  
0.4  
mV  
ppm/℃  
µA  
Temperature coefficient  
VFB Input Current  
VFBx = 0.8 V, TA = 25°C  
VREG5 OUTPUT  
VVREG5 VREG5 output voltage  
IVREG5  
TA = 25°C, 6 V < VIN1 < 18 V,  
IVREG = 5 mA  
5.5  
75  
V
VIN1 = 6 V, VREG5 = 4.0 V,  
TA = 25°C(2)  
Output current  
mA  
MOSFETs  
rDS(on)H  
(2)  
High side switch resistance  
Low side switch resistance  
TA = 25℃, VBSTx-SWx = 5.5 V  
90  
60  
mΩ  
mΩ  
(2)  
rDS(on)L  
TA = 25℃  
ON-TIME TIMER CONTROL  
TON1  
SW1 On Time  
SW1 = 12 V, VO1 = 1.2 V  
SW2 = 12 V, VO2 = 1.2 V  
TA = 25℃, VFB1 = 0.7 V(2)  
TA = 25℃, VFB2 = 0.7 V(2)  
165  
165  
220  
220  
ns  
ns  
ns  
ns  
TON2  
SW2 On Time  
TOFF1  
SW1 Min off time  
SW2 Min off time  
TOFF2  
SOFT START  
TSS  
Soft-start time  
Internal soft-start time  
1.0  
ms  
(1) x means either 1 or 2, e.g. VFBx means VFB1 or VFB2.  
(2) Ensured by design. Not production tested.  
Copyright © 2012, Texas Instruments Incorporated  
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3
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TPS54494  
SLVSBH1 –JUNE 2012  
www.ti.com  
ELECTRICAL CHARACTERISTICS(1) (continued)  
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
POWER GOOD  
VPGTH  
PG from lower VOx (going high)  
PG from higher VOx (going low)  
VPGx = 0.5 V  
84%  
116%  
75  
PGx threshold  
RPG  
PGx pull-down resistance  
PGx delay time  
50  
110  
Ω
Delay for PGx going high  
Delay for PGx going low  
PGx comparator wake-up delay  
1.5  
ms  
µs  
TPGDLY  
2
TPGCOMPSS  
PGx comparator start-up delay  
1.5  
ms  
UVLO  
VREG5 rising  
Hysteresis  
3.83  
0.6  
VUVREG5  
VREG5 UVLO threshold  
V
LOGIC THRESHOLDs  
VENH  
ENx H-level threshold voltage  
2.0  
V
V
VENL  
ENx L-level threshold voltage  
ENx input resistance  
0.4  
RENx_IN  
ENx = 12 V  
225  
450  
900  
kΩ  
CURRENT LIMITs  
IOCL1 CH1 Current limit  
IOCL2 CH2 Current limit  
LOUT1 = 2.2 µH(3)  
LOUT2 = 1.5 µH(3)  
4.5  
2.8  
5.7  
3.9  
7.0  
5.0  
A
A
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)  
VUVP  
Output UVP trip threshold  
Output UVP delay time  
Output UVP enable delay  
measured on VFBx  
63%  
68%  
1.5  
73%  
TUVPDEL  
TUVPEN  
ms  
ms  
1.5  
THERMAL SHUTDOWN  
Shutdown temperature(3)  
Hysteresis(3)  
155  
25  
TSD  
Thermal shutdown threshold  
°C  
(3) Ensured by design. Not production tested.  
4
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54494  
 
TPS54494  
www.ti.com  
SLVSBH1 –JUNE 2012  
DEVICE INFORMATION  
HTSSOP PACKAGE  
(TOP VIEW)  
1
16  
15  
VIN1  
VIN2  
2
VBST1  
SW1  
VBST2  
3
14  
SW2  
4
5
PGND1  
EN1  
13  
12  
11  
TPS54494  
PGND2  
EN2  
HTSSOP16  
6
PG1  
PG2  
VFB2  
(PowerPAD)  
10  
7
VFB1  
GND  
8
VREG5  
9
PIN FUNCTIONS(1)  
PIN  
I/O  
DESCRIPTION  
NAME  
NUMBER  
VIN1, VIN2  
1, 16  
I
I
Power inputs and connects to both high side NFET drains.  
Supply Input for 5.5V linear regulator.  
VBST1, VBST2  
SW1, SW2  
2, 15  
3, 14  
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between  
VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx  
I/O  
Switch node connections for both the high-side NFETs and low–side NFETs. Input of current  
comparator.  
PGND1, PGND2  
EN1, EN2  
4, 13  
5, 12  
6, 11  
I/O  
I
Ground returns for low-side MOSFETs. Input of current comparator.  
Enable. Pull High to enable according converter.  
PG1, PG2  
O
Open drain power good outputs. Low indicates the corresponding output voltage is out of  
regulation.  
VFB1, VFB2  
GND  
7, 10  
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.  
Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.  
8
9
I/O  
O
VREG5  
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least  
1.0 µF. VREG5 is active when ENx is high.  
Exposed Thermal  
Pad  
Back side  
I/O  
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be  
connected to GND.  
(1) x means either 1 or 2, e.g. VFBx means VFB1 or VFB2.  
Copyright © 2012, Texas Instruments Incorporated  
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5
Product Folder Link(s): TPS54494  
TPS54494  
SLVSBH1 –JUNE 2012  
www.ti.com  
FUNCTIONAL BLOCK DIAGRAM  
-16%  
PG  
VIN1  
Comp  
VIN1  
+16%  
PG1  
VBST1  
-
32  
UV1  
Control logic  
0.1 µF  
VO1  
SW1  
Re1f  
PGND1  
Err  
PGND1  
VFB1  
Comp  
SS1  
Ref_OCL  
PGND1  
SW1  
SW1  
OCP1  
ZC1  
EN1  
EN2  
EN  
Logic  
EN Logic  
VIN1  
VREG5  
GND  
CH1 Min-off timer  
5VREG  
1.0 µF  
CH2Min-off timer  
Ref1  
Ref2  
REF  
SS1  
SS2  
Fixed  
SoftStart  
UV1  
UV2  
UVLO  
Protection  
Logic  
UVLO  
VIN2  
VIN2  
TSD  
-32  
VBST2  
UV2  
Control logic  
0.1 µF  
VO2  
SW2  
PGND2  
PGND2  
Ref 2  
Err  
Comp  
SS2  
VFB2  
Ref_OCL  
PGND2  
SW2  
SW2  
-16%  
+16%  
PG  
Comp  
ZC2  
OCP2  
PG2  
6
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54494  
TPS54494  
www.ti.com  
SLVSBH1 –JUNE 2012  
OVERVIEW  
The TPS54494 is a 4A/2A dual synchronous step-down (buck) converter with two integrated N-channel  
MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™  
control reduces the required output capacitance to meet a specific level of performance. Proprietary internal  
circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.  
DETAILED DESCRIPTION  
PWM Operation  
The main control loop of the TPS54494 is an adaptive on-time pulse width modulation (PWM) controller that  
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an  
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with  
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.  
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal  
timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a  
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset  
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.  
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR  
induced output ripple from D-CAP™ control.  
PWM Frequency and Adaptive On-Time Control  
TPS54494 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The  
TPS54494 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set  
the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,  
therefore, when the duty ratio is VOx/VINx, the frequency is constant.  
Auto-Skip Eco-Mode™ Control  
The TPS54494 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current  
decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where  
its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous  
conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load  
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost half  
as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with  
smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current  
can be estimated with Equation 1with 700-kHz used as fSW  
.
V
- VOx ´ V  
(
)
1
INx  
Ox  
IOx(LL)  
=
´
2 ´ L1x ´ fSW  
V
INx  
(1)  
Soft Start and Pre-Biased Soft Start  
The TPS54494 has an internal, 1.0ms, soft-start for each channel. When the ENx pin becomes high, an internal  
DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is  
maintained during start up.  
The TPS54494 contains a unique circuit to prevent current from being pulled from the output during startup if the  
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start  
becomes greater than internal feedback voltage, VFBx), the controller slowly activates synchronous rectification  
by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a  
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.  
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)  
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.  
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TPS54494  
SLVSBH1 –JUNE 2012  
www.ti.com  
POWERGOOD  
The TPS54494 has power-good outputs that are measured on VFBx. The power-good function is activated after  
the soft-start has finished. If the output voltage is within 16% of the target voltage, the internal comparator  
detects the power good state and the power good signal becomes high after 1.5ms delay. During start-up, this  
internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of the power-good signal. If the  
feedback voltage goes outside of ±16% of the target value, the power-good signal becomes low after 2µs.  
Current Sensing and Over-Current Protection  
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.  
The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx  
pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the  
measurement accuracy, the voltage sensing is temperature compensated.  
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,  
VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current  
decreases linearly. The average value of the switch current is the load current IOUTx. If the sensed voltage on the  
low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on  
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle  
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is  
monitored in the same manner.  
Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak  
inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage  
tends to fall as the demanded load current may be higher than the current available from the converter. When  
the over current condition is removed, the output voltage returns to the regulated value. This protection is non-  
latching.  
Undervoltage Protection and Hiccup Mode  
Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.  
If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage  
falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay  
counter begins counting. After counting UVP delay time, the TPS54494 shuts off the power supply for a given  
time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been  
removed, the power supply starts and operates normally; otherwise, the TPS54494 detects another over-current  
event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for  
only a short duration in the hiccup cycle, therefore the junction temperature of the power device is much lower.  
UVLO Protection  
Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower  
than the UVLO threshold, the TPS54494 shuts down. As soon as the voltage increases above the UVLO  
threshold, the converter starts again.  
Thermal Shutdown  
TPS54494 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device  
shuts down. When the temperature falls below the threshold, the IC starts again.  
When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is  
lower than 155°C. As long as VIN1 rises, TJ must be kept below 110°C.  
8
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54494  
TPS54494  
www.ti.com  
SLVSBH1 –JUNE 2012  
TYPICAL CHARACTERISTICS  
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).  
2000  
1800  
1600  
1400  
1200  
1000  
800  
20  
18  
16  
14  
12  
10  
8
EN1, EN2 = ON  
EN1. EN2 = OFF  
600  
6
400  
4
200  
2
VIN1, VIN2 = 12 V  
100 150  
VIN1, VIN2 = 12 V  
100 150  
0
−50  
0
−50  
0
50  
Junction Temperature (°C)  
0
50  
Junction Temperature (°C)  
G001  
G002  
Figure 1. Input Current vs Junction Temperature  
Figure 2. Input Shutdown Current vs Junction  
Temperature  
50  
3.40  
3.38  
3.36  
3.34  
3.32  
3.30  
3.28  
3.26  
3.24  
3.22  
3.20  
VOUT = 3.3 V  
45  
40  
35  
30  
25  
20  
15  
10  
5
VIN = 6 V  
VIN = 12 V  
VIN = 18 V  
EN1  
EN2  
0
0
5
10  
15  
20  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
EN Input Voltage (V)  
Output Current (A)  
G003  
G004  
Figure 3. EN Current vs EN Voltage (VEN=12V)  
Figure 4. VO1=3.3V Output Voltage vs Output Current  
1.55  
1.54  
1.53  
1.52  
1.51  
1.50  
1.49  
1.48  
1.47  
1.46  
1.45  
3.40  
3.38  
3.36  
3.34  
3.32  
3.30  
3.28  
3.26  
VOUT = 1.5 V  
VIN = 5 V  
VIN = 12 V  
VIN = 18 V  
3.24  
IOUT = 10 mA  
IOUT = 1 A  
3.22  
3.20  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
Output Current (A)  
Input Voltage (V)  
G005  
G006  
Figure 5. VO2=1.5V Output Voltage vs Output Current  
Figure 6. VO1=3.3V Output Voltage vs Input Voltage  
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TYPICAL CHARACTERISTICS (continued)  
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).  
1.55  
1.54  
Vout(50mV/div)  
1.53  
1.52  
1.51  
1.50  
1.49  
Iout(2A/div)  
1.48  
1.47  
IOUT = 10 mA  
IOUT = 1 A  
1.46  
1.45  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
Input Voltage (V)  
100 ms/div  
G007  
Figure 7. VO2=1.5V Output Voltage vs Input Voltage  
Figure 8. VO1=3.3V, 0 A to 4 A Load Transient Response  
EN1(10V/div)  
Vout(50mV/div)  
Vout(1V/div)  
Iout(1A/div)  
PG1(5V/div)  
400 ms/div  
100 ms/div  
Figure 9. VO2=1.5V, 0 A to 2 A Load Transient Response  
Figure 10. VO1=3.3V, PG1  
100  
90  
80  
70  
60  
50  
40  
30  
EN2(10V/div)  
Vout2(0.5V/div)  
VIN = 6 V  
VIN = 12 V  
VIN = 18 V  
20  
10  
0
PG2(5V/div)  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
Output Current (A)  
400 ms/div  
G012  
Figure 11. VO2=1.5V, PG2  
Figure 12. VO1=3.3V, Efficiency vs Output Current  
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TYPICAL CHARACTERISTICS (continued)  
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 6 V  
VIN = 12 V  
VIN = 18 V  
VIN = 5 V  
VIN = 12 V  
VIN = 18 V  
0.001  
0.01  
0.1  
1
10  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Output Current (A)  
Output Current (A)  
G013  
G014  
Figure 13. VO1=1.5V, Efficiency vs Output Current  
Figure 14. VO1=3.3V, Efficiency vs Output Current  
100  
800  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
750  
700  
650  
600  
550  
500  
450  
400  
VIN = 5 V  
VIN = 12 V  
VIN = 18 V  
IOUT1 = 1 A  
VOUT1 = 3.3 V  
15 20  
0.001  
0.01  
0.1  
1
10  
0
5
10  
Output Current (A)  
Input Voltage (V)  
G015  
G016  
Figure 15. VO2=1.5V, Efficiency vs Output Current  
Figure 16. VO1=3.3V, SW-frequency vs Input Voltage  
800  
900  
VIN1, VIN2 = 12 V  
800  
750  
700  
650  
600  
550  
500  
450  
400  
700  
600  
500  
400  
300  
200  
100  
IOUT2 = 1 A  
VOUT2 = 1.5 V  
15 20  
VOUT1 = 3.3 V  
0
0.01  
0
5
10  
0.1  
Output Current (A)  
1
10  
Input Voltage (V)  
G017  
G018  
Figure 17. VO2=1.5V, SW-frequency vs Input Voltage  
Figure 18. VO1=3.3V, SW-frequency vs Output Current  
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TYPICAL CHARACTERISTICS (continued)  
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).  
900  
VIN1, VIN2 = 12 V  
800  
V
= 3.3 V  
V
1(10mV/div)  
O
O
700  
600  
500  
400  
300  
200  
100  
0
SW1(5V/div)  
VOUT2 = 1.5 V  
10  
0.01  
0.1  
Output Current (A)  
1
400 nsec/div)  
G019  
Figure 19. VO2=1.5V, SW-frequency vs Output Current  
Figure 20. VO1=3.3V, VO1 Ripple Voltage (IO1= 4 A)  
VIN1(50mV/div)  
V
= 3.3 V  
O
VO2(10mV/div)  
V
= 1.5 V  
O
SW2(5V/div)  
SW1(5V/div)  
400 nsec/div)  
400 nsec/div)  
Figure 21. VO2=1.5V, Ripple Voltage (IO2= 2 A)  
Figure 22. VIN1 Input Voltage Ripple (IO1= 4 A)  
V
= 1.5 V  
VIN2(50mV/div)  
O
SW2(5V/div)  
400 nsec/div)  
Figure 23. VIN2 Input Voltage Ripple (IO2= 2 A)  
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DESIGN GUIDE  
Step By Step Design Procedure  
To begin the design process, you must know a few application parameters:  
•
•
•
Input voltage range  
Output voltage  
Output current  
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated  
switching frequency of 700 kHz is used.  
VINx  
12V 1ꢀ0  
1
VIN2  
16  
VIN1  
C11  
1ꢀ mF  
C12  
1ꢀ mF  
2
3
15  
VBST2  
VBST1  
SW1  
L11  
L12  
VO1  
VO2  
C32  
C31  
2.2 mH  
1.5 mH  
3.3 V  
1.5 V  
ꢀ.1 mF  
ꢀ.1 mF  
SW2 14  
C22  
22 mF  
x2  
C21  
22 mF  
x2  
PGND  
4 PGND1  
PGND213  
EN2 12  
TPS54494  
HTSSOP16  
PGND  
5
EN1  
PG1  
6
PG2 11  
R11  
R12  
73.2 kW  
21.5 kW  
VFB1  
1ꢀ  
VFB2  
7
R21  
1uF  
C4  
R22  
22.1 kW  
22.1 kW  
9
GND  
8
VREG5  
PGND  
SGND  
SGND  
Figure 24. Schematic Diagram for the Design Example  
Output Voltage Resistors Selection  
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use  
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOx  
.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values  
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.  
R1x  
æ
ö
VOx = 0.765 V ´ 1+  
ç
÷
R2x  
è
ø
(2)  
(3)  
Output Filter Selection  
The output filter used with the TPS54494 is an LC circuit. This LC filter has double pole at:  
1
F =  
P
2p LOUT ´ COUT  
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal  
gain of the TPS545494. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain  
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero  
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the  
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole  
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the  
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the  
values recommended in Table 1.  
Table 1. Recommended Component Values  
OUTPUT VOLTAGE (V)  
R1x (kΩ)  
6.81  
8.25  
12.7  
21.5  
30.1  
49.9  
73.2  
124  
R2x (kΩ)  
22.1  
Cffx (pF)(1)  
L1x (µH)  
1.5 - 2.2  
1.5 - 2.2  
1.5 - 2.2  
1.5 - 2.2  
2.2 - 3.3  
2.2 - 3.3  
2.2 - 3.3  
4.7  
C2x (µF)  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
20 - 68  
1
1.05  
1.2  
1.5  
1.8  
2.5  
3.3  
5
22.1  
22.1  
22.1  
22.1  
5 - 22  
5 - 22  
5 - 22  
5 - 22  
5 - 22  
22.1  
22.1  
22.1  
6.5  
165  
22.1  
4.7  
(1) Optional  
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward  
capacitor (Cff) in parallel with R1.  
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,  
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak  
current and the RMS or heating current rating must be greater than the calculated RMS current.  
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the  
peak current of Equation 5 and the RMS current of Equation 6.  
V
- VOx  
VOx  
INx(MAX)  
ΔIL1x  
=
´
V
L1x ´ fSW  
INx(MAX)  
(4)  
(5)  
ΔIL  
2
ILpeakx = IOx  
+
1
2
2
ILOx(RMS)  
=
IOx  
+
ΔIL  
12  
(6)  
For the above design example, the calculated peak current is 4.46 A and the calculated RMS current is 4.01 A  
for VO1. The inductor used is a TDK CLF7045-2R2N with a rated current of 5.5 A based on the inductance  
change and of 4.3 A based on the temperature rise.  
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54494 is intended for use  
with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 7  
to determine the required RMS current rating for the output capacitor(s).  
VOx  
´
V
- VOx  
)
´ LOx ´ fSW  
(
INx  
ICOx(RMS)  
=
12 ´ V  
INx  
(7)  
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.  
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.  
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Input Capacitor Selection  
The TPS54494 requires an input decoupling capacitor and a bulk capacitor is needed depending on the  
application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1  
µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the  
SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.  
Bootstrap Capacitor Selection  
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is  
recommended to use ceramic capacitors with a dielectric of X5R or better.  
VREG5 Capacitor Selection  
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is  
recommended to use a ceramic capacitor with a dielectric of X5R or better.  
Thermal Information  
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to  
the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of  
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical  
schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.  
This design optimizes the heat transfer from the integrated circuit (IC).  
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating  
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature  
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.  
The exposed thermal pad dimensions for this package are shown in the following illustration.  
Figure 25. Thermal Pad Dimensions  
Layout Considerations  
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal  
pad.  
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and  
inductance and to minimize radiated emissions.  
3. Keep analog and non-switching components away from switching components.  
4. Make a single point connection from the signal ground to power ground.  
5. Do not allow switching currents to flow under the device.  
6. Keep the pattern lines for VINx and PGNDx broad.  
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7. Exposed pad of device must be soldered to PGND.  
8. VREG5 capacitor should be placed near the device, and connected to GND.  
9. Output capacitors should be connected with a broad pattern to the PGND.  
10. Voltage feedback loops should be as short as possible, and preferably with ground shields.  
11. Kelvin connections should be brought from the output to the feedback pin of the device.  
12. Providing sufficient vias is preferable for VIN, SW and PGND connections.  
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.  
14. VIN Capacitor should be placed as near as possible to the device.  
VIN2  
VIN HIGH  
FREQUENCY  
BYPASS  
VIN INPUT  
BYPASS  
CAPACITOR CAPACITOR  
～0.1µF 10µF x2  
Switching noise  
flows through IC  
and CIN. It avoids  
1
16 VIN2  
VIN1  
VBST1  
SW1  
.
the thermal Pad  
OUTPUT  
FILTER  
15  
2
VBST2  
VO2  
CAPACITOR  
OUTPUT  
3
14  
SW2  
INDUCTOR  
Recommend to keep  
PGND1  
EN1  
4
5
13 PGND2  
distance more than 3-4mm.  
(to avoid noise scattering,  
especially GND plane.)  
TO ENABLE  
CONTROL  
12  
11  
EN2  
PG2  
VFB2  
Keep  
distance more  
than 1inch  
PG1  
6
POWER GND  
10  
7
VFB1  
GND  
To feedback  
resisters  
8
9
VREG5  
Feedback  
resisters  
BIAS  
CAP  
Symmetrical Layout  
for CH1 and CH2  
GND  
PLANE  
2,3 or bottom  
layer  
Via to GND Plane  
- Blue parts can be placed on the bottom side  
- Connect the SWx pins through another layer with the inductor  
(yellow line)  
Figure 26. TPS54494 Layout  
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PACKAGE OPTION ADDENDUM  
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2-Jul-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TPS54494PWP  
ACTIVE  
ACTIVE  
HTSSOP  
HTSSOP  
PWP  
PWP  
16  
16  
90  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
TPS54494PWPR  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS54494PWPR  
HTSSOP PWP  
16  
2000  
330.0  
12.4  
6.9  
5.6  
1.6  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
HTSSOP PWP 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 35.0  
TPS54494PWPR  
2000  
Pack Materials-Page 2  
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