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TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

TPS544x20 4.5V 至 18V，20A 和 30A SWIFT ™

同步降压控制器（具有 PMBus™

1 特性

3 说明

1

•

启用 PMBus 的转换器：20A，30A

TPS544B20 和 TPS544C20 器件是 PMBus 兼容型非

隔离式直流/直流集成式 FET 转换器，支持高频运行并

提供 20A 或 30A 电流输出，采用 5mm × 7mm 封装，

可实现高功率密度和快速瞬态性能，具有最小的 PCB

面积。PMBus 接口用于转换器配置，并监视关键参

数，其中包括输出电压、电流和一个可选外部温度。由

集成 NexFET 功率级和经优化驱动器提供的高频、低

损耗开关可实现极高密度电源解决方案以及减小的电感

器和滤波电容器尺寸。根据系统要求，对故障情况的响

应可被设定为重新启动或锁断。

4.5V 至 18V 输入，0.6V 至 5.5V 输出

5mm x 7mm 薄型四方扁平无引线 (LQFN) 封装，

焊球间距为 0.5mm

•

单个散热焊盘

集成 4.5mΩ 和 2.0mΩ 堆叠 NexFET™功率级

600mV，0.5% 基准

无损耗、低侧金属氧化物半导体场效应晶体管

(MOSFET) 电流感测

•

可选 D-CAP™和 D-CAP2™模式控制

差分远程感应

表 1. 器件信息⁽¹⁾

单启动至预偏置输出

部件名称

TPS544B20

TPS544C20

封装

封装尺寸（标称值）

输出电压裕度和修整

输出电压和输出电流报告

使用 2N3904 时的外部温度监视

可经由 PMBus 编程

LQFN (40)

5.00mm x 7.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

–

过流保护

效率与输出电流间的关系

欠压闭锁 (UVLO)，软启动

100

95

电源正常 (PGOOD)，过压 (OV)，欠压 (UV)，

过热 (OT) 电平

90

–

故障响应

85

接通和关闭延迟

•

热关断

80

引脚兼容 20A，30A 转换器

75

Output Voltage

0.6 V

1.0 V

1.8 V

3.3 V

0.8 V

1.2 V

2.5 V

70

65

60

2 应用范围

•

测试和测量仪器

以太网交换机、光交换机、路由器、基站

服务器

0

5

10

15

20

25

30

Load Current (A)

C003

企业级存储固态硬盘 (SSD)

高密度电源解决方案

V_IN= 12 V

f_SW= 500 kHz

L = 410 nH

R_DCR= 0.3 mΩ

Snubber = Open

R_BOOT= 0 Ω

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSB69

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

8.5 Programming........................................................... 28

8.6 Register Maps......................................................... 30

Applications and Implementation ...................... 52

9.1 Application Information............................................ 52

9.2 Typical Application .................................................. 52

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics........................................... 8

7.6 Switching Characteristics........................................ 11

7.7 Typical Characteristics............................................ 12

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 27

9

10 Power Supply Recommendations ..................... 61

11 Layout................................................................... 62

11.1 Layout Guidelines ................................................. 62

11.2 Layout Example .................................................... 63

12 器件和文档支持 ..................................................... 65

12.1 器件支持................................................................ 65

12.2 相关链接................................................................ 66

12.3 商标....................................................................... 66

12.4 接收文档更新通知 ................................................. 67

12.5 社区资源................................................................ 67

12.6 静电放电警告......................................................... 67

12.7 Glossary................................................................ 67

13 机械、封装和可订购信息....................................... 67

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (February 2016) to Revision B

Page

•

Changed From: PGND to GND in the Pin Functions table Description for pins BP6 and BPEXT. ....................................... 4

Changed Pin Functions table Description for VDD pin To: "Bypass with a 0.1-µF to 1.0-µF capacitor to GND

(thermal pad or GND pins) or through a dedicated connection to AGNDSNS." ................................................................... 5

•

Changed From: "PGND" To: "GND" in Linear Regulators BP3 and BP6 and External Bypass (BPEXT) Section text. ..... 20

Changed instances From: "PGND" To: "GND" in the Device Functional Modes................................................................. 27

Changed From: " a value of 4.7 μF" To: " a value of 0.1 μF to 1.0 μF" in the Input Capacitor Selection ............................ 55

Changed text string From: "...one 4.7-μF, 25-V ceramic capacitor..." To: "...one 1.0-μF, 25-V ceramic capacitor..." in

the Input Capacitor Selection description............................................................................................................................. 56

•

Changed From: "PGND" To: "GND" in the BP6, BP3 and BPEXT section ......................................................................... 56

Added text to Layout Guidelines section for emphasis on grounding schemes. ................................................................. 62

Changed PCB Layout Recommendation figure. ................................................................................................................. 63

已添加接收文档更新通知部分............................................................................................................................................. 67

Changes from Original (May 2014) to Revision A

Page

•

Deleted package suffix and reel quantities from Device Comparison Table ......................................................................... 4

Changed "Handling" Ratings table to "ESD" Ratings and moved T_stgspec to the Absolute Maximum Ratings table........... 6

Added sentence in Switching Frequency description........................................................................................................... 20

Changed "Hiccup" to "Shutdown and latch-off" as the Default Behavior for CMD Command; and, changed Default

Register Value from 3Fh to 07h in Table 5, CMD Code 47h .............................................................................................. 29

•

Changed "address" to "frequency" in the PMBus Command Description for CMD Code 80h in Table 5. .......................... 29

Changed Default Value for Bit Position 5, 4, and 3 from 1 1 1 to 0 0 0 respectively in the

IOUT_OC_FAULT_RESPONSE (47h) table. ...................................................................................................................... 37

•

Changed "IVADDR" to "IVFREQ" for Function at Bit Position 4 of the STATUS_MFR_SPECIFIC (80h); and also in

the accompanying description. ............................................................................................................................................ 44

2

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

•

已添加社区资源部分 ........................................................................................................................................................... 66

3

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

5 Device Comparison Table

DEVICE NUMBER

CURRENT OPTION (A)

TPS544B20

TPS544C20

20

30

6 Pin Configuration and Functions

RVF Package

40-Pin LQFN with Thermal Tab

(TOP VIEW)

40 39 38 37 36 35 34 33

32

CNTL

ADDR1

ADDR0

DATA

1

VOUTSt

31

30

29

28

27

26

2

3

4

5

6

7

8

9

VOUTS+

BPEXT

VDD

CLK

BP6

BP3

SMBALERT

BOOT

PGND

25

24

23

SW

VIN

SW 10

SW

22

21

11

SW 12

VIN

Thermal Tab

13 14 15 16 17 18 19 20

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

3

ADDR0

ADDR1

O

Sets low order 3-bits of the PMBus address. Connect a resistor from this pin to AGND.

Sets high order 3-bits of the PMBus address. Connect a resistor from this pin to AGND.

2

Analog ground sense. Provides Kelvin connection point to analog ground for precise current

measurement. AGNDSNS is internally connected to the thermal tab. Do not connect to the thermal tab

externally. Kelvin connect back to AGND pin with a low impedance, low noise path. This kelvin

connection serves as the only connection between AGND and GND.

AGNDSNS

13

G

Analog ground return for control circuitry. AGND should not be connected to the exposed thermal pad,

GND or PGND, but should be Kelvin connected to the AGNDSNS pin.

AGND

BP3

38

27

28

7

G

S

Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed

with a minimum of 100-nF capacitor to AGND.

Output of the 6-V on-board regulator. This regulator powers the driver stage of the controller and should

be bypassed with a 4.7-µF ceramic capacitor to GND.

BP6

Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to

the SW pins.

BOOT

(1) I = Input, O = Output, P = Supply, G = Ground

4

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

External BP voltage for BP crossover function. Bypass with a 4.7-µF ceramic capacitor to GND if used..

Connect to GND if not used.

BPEXT

30

I

CLK

5

1

I

PMBus CLK pin. See PMBus specification.

PMBus CNTL pin. See PMBus specification.

CNTL

Output of the error amplifier. This regulates the D-CAP and D-CAP2 valley voltage reference for output

regulation and should be bypassed with a 10-nF capacitor to AGND.

COMP

35

O

DATA

4

I/O

O

PMBus DATA pin. See PMBus specification.

Output of the differential sense amplifier.

DIFFO

33

Feedback pin for the control loop. Regulates to a nominal 600 mV if there is no trim applied to the

device using VREF_TRIM.

FB

34

I

14

15

16

17

18

19

20

GND

G

Power stage ground return.

Power ground return for controller device. Connect to GND at the thermal tab with a minimum 8 mil

wide PCB trace

PGND

26

36

40

G

O

Power good output. Open drain output that floats up when the device is operating and in regulation. Any

fault condition causes this pin to pull low.

PGOOD

Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching

frequency.

RT

O

SMBALERT

6

8

SMBus alert pin. See SMBus specification.

9

Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this

group of pins.

SW

10

11

12

O

D-CAP and D-CAP2 control mode selection pin. Connect to BP3 for D-CAP2 mode control. Connect to

AGND for D-CAP mode control.

MODE

TSNS

39

37

I

External temperature sense signal input. TSNS can be connected to AGND to disable external

temperature measurement.

O

Input Voltage for analog control circuitry. Bypass with a 0.1-µF to 1.0-µF capacitor to GND (thermal pad

or GND pins) or through a dedicated connection to AGNDSNS. The VDD voltage is also used for input

feed-forward, ON-time generation and High Side Over Current (HSOC). VIN and VDD must be at the

same voltage for accurate short circuit protection.

VDD

29

I

21

22

23

24

25

Input power to the power stage. Bypass High-Frequency bypassing with multiple ceramic capacitors to

GND is critical. See Layout Recommendations

VIN

Output voltage sensing, positive side. This sensing provides remote sensing for PMBus reporting and

the voltage control loop. Connect to V_OUTat desried regulation point through < 100-Ω resistor. Route

with GND to VOUT- using coupled differential pair PCB routing.

VOUTS+

31

32

I

Output voltage sensing, negative or common side. This sensing provides remote sensing for PMBus

reporting and the voltage control loop. Connect to Ground at desried regulation point through < 100-Ω

resistor. Route with V_OUTto VOUT+ using coupled differential pair PCB routing.

VOUTS–

Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper

operation.

Thermal tab

5

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) See

(1)(2)(3)

MIN

–0.3

–1

MAX

UNIT

VIN, VDD

BOOT

20

37

7

Input voltage

BOOT – SW (BOOT to SW differential)

CLK, DATA

V

3.6

7

FB, SYNC, CNTL, VOUTS–, VOUTS+, BPEXT

BP6

7

SW

30

7

Output voltage

SW ( > 50 ns, > 10 µJ)

COMP, DIFFO, SMBALERT, PGOOD

ADDR0, ADDR1, BP3, RT, TSNS

-5

V

–0.3

–40

–55

3.6

150

T_J, operating junction temperature

T_stg, Storage temperature

°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other

conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at

which the device is functional and the device should not be operated beyond such conditions.

(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(3) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales/Office/Distributors for availability and

specifications.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

TYP

MAX UNIT

V_DD

V_IN

T_J

Controller input voltage

Power stage input voltage

Junction temperature

18

V

4.5

–40

125

°C

6

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

7.4 Thermal Information

TPS544B20

UNIT

THERMAL METRIC⁽¹⁾

TPS544C20

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

Junction-to-case (bottom) thermal resistance⁽⁶⁾

27.5

13.9

4.0

°C/W

R_θJCtop

R_θJB

ψ_JT

0.3

ψ_JB

3.9

R_θJCbot

0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

7

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

MAX UNIT

7.5 Electrical Characteristics

T_J= –40°C to 125°C, V_IN= V_VDD= 12 V, R_RT= 38.3 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

INPUT SUPPLY

V_VDD

Input supply voltage range

Power stage voltage range

Input Operating Current

4.5

18

10

V

V_VIN

I_VDD

Not switching

mA

UVLO

V_IN(on)

Input turn on voltage

Input turn off voltage

Default settings

4.05

3.8

4.25

4

4.45

4.2

V

V_IN(off)

Programmable range for turn-on

voltage

V_INON(rng)

V_INOFF(rng)

4.25

4

16

V

Programmable range for turn-off

voltage

15.75

ERROR AMPLIFIER AND FEEDBACK VOLTAGE

0°C ≤ T_J≤ 70°C

597

594

600

130

603

606

V_FB

Feedback Voltage

mV

–40°C ≤ T_J≤ 125°C

g_M

Transconductance

µS

nA

I_FB

FB pin bias current (out of pin)

Loop comparator offset voltage

V_FB= 0.6 V

50

V_{LOOP_COMP}

V_FB= 0.6 V, T_J= 25°C

-7.5

6.2

7.5

mV

BP6 REGULATOR

V_BP6

Output voltage

I_BP6= 10 mA

6.5

6.8

V

mV

mA

V

V_BP6(do)

I_BP6

Dropout voltage

Output current⁽¹⁾

Regulator UVLO voltage⁽¹⁾

V_VIN– V_BP6, V_VDD= 4.5 V, I_BP6= 25 mA

V_VDD= 12 V

100

120

3.3

V_BP6UV

3.55

255

3.8

Regulator UVLO voltage

hysteresis⁽¹⁾

V_BP6UV(hyst)

230

270

mV

BPEXT

V_{BPEXT(swover)}

V_hys(swover)

V_BPEXT(do)

BPEXT switch-over voltage

BPEXT switch-over hysteresis

BPEXT dropout voltage

VDD > V_IN(on)

4.5

4.65

V

100

200

100

mV

V_BPEXT-V_BP6, V_BPEXT= 4.8 V, I_BP6= 25 mA

BOOTSTRAP

V_BOOT(drop)

Bootstrap voltage drop

I_BOOT= 5 mA

150

3.5

mV

V

BP3 REGULATOR

V_BP3

Output voltage

V_VDD= 4.5 V, I_BP3≤ 5 mA

Factory default settings

3.1

0.6

3.3

2.7

SOFT START

t_SS

Soft-start time⁽²⁾

ms

Programmable range⁽¹⁾

Accuracy over range⁽¹⁾

Turn-on delay

9

±10%

t_ON(DELAY)

t_OFF(DELAY)

Factory default settings

0

ms

Turn-off delay

(1) Specified by design. Not production tested.

(2) Soft-start time is defined by the rise time of the internal reference, V_REF

8

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= V_VDD= 12 V, R_RT= 38.3 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REMOTE SENSE AMPLIFIER

(V_OUTS+– V_OUTS–) = 0.6 V

-5

-8

5

V_DIFFO(ERROR)

Error voltage from DIFFO to V_SNS

(V_OUTS+– V_OUTS–) = 1.2 V

(V_OUTS+– V_OUTS–) = 3.0 V

8

mV

-17

2

17

BW

Closed-loop bandwidth⁽¹⁾

MHz

R_VOUTx

Output voltage sense input

impedance

V_OUT+= 1.2V

55

80

105

kΩ

V_DIFFO(max)

I_DIFFO

Maximum DIFFO output voltage

DIFFO sourcing current

DIFFO sinking current

V_BP6-0.2

V

1

mA

POWER STAGE

R_HS

V_VDD= 4.5 V, T_J= 25°C

4.9

4.5

0.4

1.5

2.2

2.0

High-side on-resistance

High-side leakage current

Low-side on-resistance

mΩ

µA

V_VDD≥ 12 V, T_J= 25°C

V_VDD= 18 V, T_J= 25°C

V_VDD= 18 V, T_J= 125°C⁽¹⁾

V_VDD= 4.5 V, T_J= 25°C

0.7

I_HS(leak)

R_LS

mΩ

V_VDD≥ 12 V, T_J= 25°C

CURRENT LIMIT

t_OFF(OC)

Off time between restart attempts

Hiccup mode

7 × t_SS

26

ms

A

Factory default settings

Programmable range

Factory default settings

Programmable range

Factory default settings

Programmable range

Factory default settings

Programmable range

TPS544B20

TPS544C20

TPS544B20

TPS544C20

5

4

30

45

Output current overcurrent fault

threshold

I_OC(flt)

39

20

30

29.5

44.5

Output current overcurrent warning

threshold

I_OC(warn)

A

Output current overcurrent fault

and warning accuracy

I_OC(acc)

I_OCF= 20 A⁽¹⁾

±3

A

Minimum LDRV pulse width for

valid current sensing⁽¹⁾

t_LSOC(min)

400

500

ns

HIGH-SIDE SHORT CIRCUIT PROTECTION

TPS544B20

TPS544C20

30

45

58

75

High-side short-circuit protection

fault threshold

I_HSOC

T_J= 25°C

A

POWER GOOD (PGOOD)

V_FBPGH

V_FBPGL

FB PGOOD high threshold

FB PGOOD low threshold

PGOOD accuracy over range

FB PGOOD hysteresis voltage

PGOOD pull-down resistance

PGOOD pin leakage current

Factory default settings

675

525

mV

V_PG(acc)

V_pg(hyst)

R_PGOOD

I_PGOOD(lk)

–5%

10

5%

50

70

20

mV

Ω

V_FB= 0, I_PGOOD= 5 mA

30

Factory default settings, V_PGOOD= 5 V

µA

OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION

V_FBOV

FB pin over voltage threshold

FB pin under voltage threshold

FB UV, OV accuracy over range

Factory default settings

700

499

mV

V_FBUV

V_UVOV(acc)

–4.5%

4.5%

9

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= V_VDD= 12 V, R_RT= 38.3 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OUTPUT VOLTAGE TRIMMING AND MARGINING

Resolution of FB steps with trim

and margin

V_FBTM(step)

2

30

mV

µs

Transition time per trim or margin

step

t_FBTM(step)

After soft-start time

Maximum FB voltage with trim or

margin only

V_FBTM(max)

660

480

mV

Minimum FB voltage with trim or

margin only

V_FBTM(min)

FB voltage range with trim and

margin combined

V_FBTM(rng)

420

660

mV

V_FBMH

V_FBML

Margin high FB pin voltage

Margin low FB pin voltage

Factory default settings

660

540

mV

TEMPERATURE SENSE AND THERMAL SHUTDOWN

T_SD

Junction shutdown temperature⁽¹⁾

Thermal shutdown hysteresis⁽¹⁾

135

20

145

25

155

30

°C

T_HYST

Ratio of bias current flowing out of

TSNS pin, state 2 to state 1

I_TSNS(ratio)

9.7

10.0

10.3 µA/µA

I_TSNS

V_TSNS

State 1 current out of TSNS pin

State 2 current out of TSNS pin

Voltage range on TSNS pin⁽¹⁾

Overtemperature fault limit⁽¹⁾

OT fault limit range⁽¹⁾

Overtemperature warning limit⁽¹⁾

OT warning limit range⁽¹⁾

10

µA

100

0

120

100

15

1.00

165

140

25

V

Factory default settings

150

125

T_OT(flt)

°C

T_OT(warn)

°C

T_OT(step)

T_OT(hys)

OT fault, warning step⁽¹⁾

OT fault, warning hysteresis⁽¹⁾

5

°C

20

MEASUREMENT SYSTEM

Output voltage measurement

range

M_VOUT(rng)

M_VOUT(acc)

M_VOUT(lsb)

0.5

5.8

V

Output voltage measurement

accuracy

–2.0%

2.0%

Output voltage measurement bit

resolution

1.95

62.5

mV

I

_OUT≥ 20 A, -40 ≤ T_A≤ 85°C

-15%

-3

+15%

+3

Output current measurement

accuracy⁽³⁾

M_IOUT(acc)

3 A ≤ I_OUT< 20 A, –40 ≤ T_A≤ 85°C

A

Output current measurement bit

resolution⁽¹⁾

M_IOUT(lsb)

M_TSNS(rng)

M_TSNS(acc)

M_TSNS(lsb)

mA

External temperature sense

range⁽¹⁾

-40

-8

165

8

°C

External temperature sense

accuracy⁽¹⁾

-40°C ≤ T_J(sensor)≤ 165°C

External temperature sense bit

resolution⁽¹⁾

1.238

9.75

PMBus INTERFACE ADDRESSING

I_ADD

Address pin bias current

8.23

0.08

11.21

2.35

µA

V

Address pin legal address voltage

range

V_ADD(rng)

(3) Current sense amplifier gain and offset are production tested. Output current monitoring guaranteed by correlation.

10

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

7.6 Switching Characteristics

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 38.3 kΩ (unless otherwise specified).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TON GENERATOR AND SW TIMING

Adjustment range

250

210

250

340

425

550

640

720

850

1000

290

350

460

575

750

860

980

1150

R_RT= 10.0 kΩ

R_RT= 17.8 kΩ

R_RT= 27.4 kΩ

R_RT= 38.3 kΩ

R_RT= 56.2 kΩ

R_RT= 86.6 kΩ

R_RT= 133 kΩ

R_RT= 205 kΩ

250

300

400

500

650

750

850

1000

9.75

175

f_SW

Switching frequency⁽¹⁾

kHz

I_RT

RT output current

µA

ns

V

t_OFF(min)

t_ON(min)

V_DCAP2

V_DCAP

I_MODE

Minimum off-time^{(2) (3)}

Minimum controllable pulse width⁽²⁾

D-CAP2 mode threshold

D-CAP mode threshold

MODE output current

80

2.10

0.8

7

V

13

µA

SW rising

SW falling

15

t_DEAD

Power stage driver dead-time⁽²⁾

ns

SW rising (10% to 90%), I_OUT= 30

A, R_BOOT= 0 Ω

9.2

6.2

t_SLEW(SW)

SW slew rate⁽²⁾

V/ns

SW falling (90% to 10%), I_OUT= 30

A, R_BOOT= 0 Ω

(1) On-times are production tested, but steady-state switching frequency is not.

(2) Specified by design. Not production tested.

(3) Minimum off time for valid current sensing is 400-ns typical, 500-ns maximum.

11

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

7.7 Typical Characteristics

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 38.3 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

6.25

6.00

5.75

5.50

5.25

5.00

4.75

4.50

4.25

4.00

0

25

50

75

100

125

150

œ50

œ25

0

25

50

75

100

125

150

œ50

œ25

Junction Temperature (£/)

C007

C008

Figure 1. Low-Side MOSFET On-Resistance (R_DS(on)) vs.

Junction Temperature

Figure 2. High-Side MOSFET On-Resistance (R_DS(on)) vs.

Junction Temperature

8.0

7.5

7.0

6.5

6.0

605

604

603

602

601

600

599

598

597

596

595

dd = 4.5 V

V_VDD= 4.5 V

Vdd ==1122VV

5.5

5.0

VDD

dd = 18 V

V_VDD= 18 V

0

25

50

75

100

125

150

œ50

œ25

0

25

50

75

100

125

150

œ50

œ25

Junction Temperature (£/)

C001

C009

Figure 4. Non-Switching Input Current (I_VDD) vs. Junction

Temperature

Figure 3. Feedback Voltage vs. Junction Temperature

6.520

3.260

3.255

3.250

3.245

3.240

3.235

3.230

3.225

3.220

6.515

6.510

6.505

6.500

6.495

6.490

6.485

6.480

0

25

50

75

100

125

150

0

25

50

75

100

125

150

œ50

œ25

œ50

œ25

Junction Temperature (£/)

C005

C006

I_BP6= 25 mA

Figure 5. BP6 Voltage vs. Junction Temperature

I_BP3= 5 mA

Figure 6. BP3 Voltage vs. Junction Temperature

12

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 38.3 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

4.40

4.35

4.30

4.25

4.20

50

45

40

35

30

25

20

0

25

50

75

100

125

150

œ50

œ25

0

25

50

75

100

125

150

œ50

œ25

Junction Temperature (£/)

C011

C004

VIN_ON = 4.25 V

Figure 8. Turn-On Voltage vs. Junction Temperature

Figure 7. PGOOD Pull-Down Resistance vs. Junction

Temperature

4.10

125

105

85

4.05

4.00

3.95

3.90

65

Nat. Conv

100 LFM

200 LFM

400 LFM

45

25

0

25

50

75

100

125

150

0

5

10

15

20

25

30

œ50

œ25

Junction Temperature (£/)

Load Current (A)

V_OUT= 0.9 V

C012

C001

VIN_OFF = 4.00 V

V_IN= 12 V

f_SW= 650 kHz

Figure 9. Turn-Off Voltage vs. Junction Temperature

Figure 10. Safe Operating Area

125

105

85

105

85

65

Nat. Conv

100 LFM

200 LFM

400 LFM

Nat. Conv

100 LFM

200 LFM

400 LFM

45

25

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Load Current (A)

V_OUT= 0.9 V

Load Current (A)

V_OUT=1.8 V

C002

C003

V_IN= 12 V

f_SW= 300 kHz

V_IN= 12 V

f_SW= 650 kHz

Figure 11. Safe Operating Area

Figure 12. Safe Operating Area

13

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 38.3 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

125

105

85

125

105

85

65

Nat. Conv

100 LFM

200 LFM

400 LFM

Nat. Conv

100 LFM

200 LFM

400 LFM

45

25

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Load Current (A)

V_OUT= 1.8 V

Load Current (A)

V_OUT= 3.3 V

C004

C005

V_IN= 12 V

f_SW= 300 kHz

V_IN= 12 V

f_SW= 650 kHz

Figure 13. Safe Operating Area

Figure 14. Safe Operating Area

125

105

85

125

105

85

65

Nat. Conv

100 LFM

200 LFM

400 LFM

Nat. Conv

100 LFM

200 LFM

400 LFM

45

25

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Load Current (A)

V_OUT= 0.9 V

Load Current (A)

V_OUT= 3.3 V

C007

C006

V_IN= 5 V

f_SW= 650 kHz

V_IN= 12 V

f_SW= 300 kHz

Figure 16. Safe Operating Area

Figure 15. Safe Operating Area

125

105

85

125

105

85

65

Nat. Conv

100 LFM

200 LFM

400 LFM

Nat. Conv

100 LFM

200 LFM

400 LFM

45

25

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Load Current (A)

V_OUT= 0.9 V

Load Current (A)

V_OUT= 1.8 V

C008

C009

V_IN= 5 V

f_SW= 300 kHz

V_IN= 5 V

f_SW= 650 kHz

Figure 17. Safe Operating Area

Figure 18. Safe Operating Area

14

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 38.3 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

125

105

85

65

Nat. Conv

100 LFM

45

200 LFM

400 LFM

25

0

5

10

15

20

25

30

Load Current (A)

C010

V_IN= 5 V

V_OUT= 1.8 V

f_SW= 300 kHz

Figure 19. Safe Operating Area

15

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS544B20 and TPS544C20 devices are 20-A, and 30-A, high-performance, synchronous buck converters

with two integrated N-channel NexFET™ power MOSFETs. These devices implement TI's proprietary D-CAP

and D-CAP2 mode control providing natural input voltage feed-forward and fast transient response with a

precision error amplifier and low-offset differential remote sense amplifier for precise ouptut voltage regulation

with minimal external compensation. Monotonic pre-bias capability eliminates concerns about damaging sensitive

loads. Integrated PMBus capability provides current, voltage and on-board temperature monitoring, as well as

many user-programmable configuration options as well as Adaptive Voltage Scaling (AVS) and output voltage

margin testing.

8.2 Functional Block Diagram

VDD

VIN

BP6

BP3

Linear Regulators and

BP Switchover

BP6

BOOT

Minimum t_OFF

Delay

Stacked

1H[)(7Œ

Power

BPEXT

+

V_PBEXT(swovr)

Stage &

Sensefet

Fault

S

R

Q

FB

Driver Control:

Anti-Cross

Conduction,

Prebias

+

COMP

SW

BP6

SW

On-Time

Generator

GND

RT

f_SWDecode

Overcurrent

Detection,

Current

AGNDSNS

TSNS

Reference Soft-Start, Trim and Margin

VOUTS +

Reference

DAC

Sensing

Temperature

Sensing

Interface

Average I_OUT

OC Threshold

VOUTS --

AGND

CLK

DATA

Analog

Inputs and

ADC

PMBus 1.1

Interface

and

Fault

VOUT+

Device

Interface

SMBALRT

CNTL

Commands

EEPROM

+

VOUT-

PMBus Engine.

TPS544C20

ADDR0 ADDR1

PGOOD PGND

DIFFO

16

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

8.3 Feature Description

8.3.1 Turn-On and Turn-Off Delay and Sequencing

The TPS544C20 and TPS544B20 devices provide many sequencing options. Using the ON_OFF_CONFIG

command, the device can be configured to start up when the input voltage is above the undervoltage lockout

(UVLO) threshold, or to additionally require a signal on the CNTL pin and/or receive an update to the

OPERATION command according to the PMBus protocol. When the gating signal as specified by

ON_OFF_CONFIG command is asserted, a programmable turn-on delay can be set with the TON_DELAY

command to delay the start of regulation. Similarly, a programmable turn-off delay can be set with the

TOFF_DELAY command to delay the stop of regulation once the gating signal is de-asserted. Delay times are

specified as an integer multiple of the soft-start time.

When the output voltage remains within the PGOOD window after the start-up period, PGOOD is released, and

rises to an externally supplied logic level. The PGOOD signal can be connected to the CNTL pin of another

device to provide additional controlled turn-on and turn-off sequencing.

Figure 20 shows control of the start-up and shutdown operations of the device, when the device is configured to

respond to a logical AND of both CNTL and the OPERATION command. The device can also be configured to

respond to only the CNTL signal, only the OPERATION command, or to convert power whenever VDD is greater

than the VIN_ON command value setting.

TON_DELAY

TON_RISE

TOFF_DELAY

VIN

OFF

ON

OFF

OPERATION[7]

CNTL

V_OUT

(1) Bit 7 of OPERATION is used to control power conversion. Other bits in this register control output voltage margining.

Figure 20. Turn-On Controlled By Both Operation and Control

8.3.2 Pre-Biased Output Start-Up

The TPS544C20 and TPS544B20 devices prevent current from discharging from the output during start-up, when

a pre-biased output condition exists. No SW pulses occur until the internal soft-start voltage rises above the error

amplifier input voltage (FB pin), if the output is pre-biased. When the soft-start voltage exceeds the error amplifier

input, and SW pulses start, the device limits synchronous rectification time after each SW pulse with a narrow

on-time. The low-side MOSFET on-time slowly increases each switching cycle until it generates 128 pulses. After

128 pulses, the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach

prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-

regulation sequences are smooth and monotonic. These devices respond to a pre-biased output over-voltage

condition immediately upon power-up, even during soft-start, while disabled or below the PMBus programmable

undervoltage lockout on-time (UVLO_ON).

The combination of D-CAP and D-CAP2 mode control and the limited on-time of the low-side MOSFET during

the pre-bias sequence allows these devices to operate at low switching frequencies for the first 128 switching

cycles, after which the device operates using pseudo-constant frequency.

17

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

Feature Description (continued)

8.3.3 Voltage Reference

A 600-mV bandgap cell connects internally to the non-inverting input of the error amplifier. The 0.5% tolerance

on the reference voltage allows for a power supply design that yields very high DC accuracy.

8.3.4 Differential Remote Sense and Output Voltage Setting

The TPS544C20 and TPS544B20 devices implement a differential remote sense amplifier to provide excellent

load regulation by cancelling IR-drop in high current applications. The VOUTS+ and VOUTS– pins should be

kelvin-connected to the output capacitor bank directly at the load, and routed back to the device as a tightly

coupled differential pair. Ensure that these traces are isolated from fast switching signals and high current paths

on the final PCB layout to mitigate differential-mode noise. Optionally, use a small coupling capacitor (330-pF

typical) between the VOUTS+ and VOUTS– pins to improve noise immunity. The output of the differential remote

sense amplifier (DIFFO) sets the output voltage.

A voltage divider from the DIFFO pin to the FB pin sets the nominal output voltage. The output voltage must be

divided down to the nominal reference voltage of 600 mV. The feedback voltage can be adjusted within –30%

and +10% from the nominal 600 mV using PMBus commands, allowing the output voltage to vary by the same

percentage. During the power-up sequence, the feedback reference is 600 mV plus any offset generated by the

MARGIN command or VREF_TRIM command values which were previously stored in EEPROM. The initial

output voltage equals the feedback voltage scaled by the divider ratio. See the PMBus Output Voltage

Adjustment section for further details.

The device enables telemetry by digitizing the voltage at the DIFFO pin, averaging it to reduce measurement

noise, and storing it in the READ_VOUT (8Bh) register.

VOUTS+

DIFFO

FB

+

R1

VOUTSt

R_BIAS

COMP

+

R_COMP

C_COMP

C_{COMP_HF}

V_REF

To PWM

Figure 21. Output Voltage Setting

Equation 1 calculates the nominal output voltage. R1 can be arbitrarily selected to be 10-kΩ, with R_BIASbeing

scaled appropriately.

21

6_/54= l1 +

p × 6_&"

2_"©°≥

(1)

8.3.5 PMBus Output Voltage Adjustment

The nominal output voltage of the converter can be adjusted by changing the feedback voltage, V_FB, using the

VREF_TRIM command. The adjustment range is between –20% and +10% from the nominal output voltage. This

command adjusts the final output voltage of the converter to a high degree of accuracy, without relying on high-

precision feedback resistors. The resolution of the adjustment is 7 bits, with a resulting minimum step size of

approximately 2 mV, or 0.4%. The total output voltage adjustable range, including MARGIN and VREF_TRIM is

–30% to + 10%.

18

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

Feature Description (continued)

The TPS544C20 and TPS544B20 devices allow simple output voltage margin testing, by applying a either a

positive or negative offset to the feedback voltage. The STEP_VREF_MARGIN_HIGH and

STEP_VREF_MARGIN_LOW commands control the size of the applied high or low offset respectively. The

OPERATION command toggles the converter between three states:

•

Margin none (no output margining). See Equation 2

Margin high. See Equation 3

Margin low. See Equation 4

6_&"= 62%&_42)- + 0.ꢀ 6

6_&"= 62%&_42)- + 34%0_62%&_-!2')._()'( + ꢀꢁꢂ 6

6_&"= 62%&_42)-+ 34%0_62%&_-!2')._,/7 + ꢀꢁꢂ 6

(2)

(3)

(4)

Figure 22 shows an example of the VREF_TRIM and margin timing.

650 mV

630 mV

600 mV

585 mV

570 mV

V_FB

Margining Slew Rate:

30 ꢀs / 2 mV step

0

VREF_TRIM

0 mV

+20 mV

-30 mV

STEP_VREF_MARGIN_HIGH

+30 mV

-15 mV

HIGH

STEP_VREF_MARGIN_LOW

OPERATION[5:2]

NONE

LOW

NONE

Margin

Low

Trim

Low

Margin

High

Margin and Margin

Trim High None

Figure 22. VREF_TRIM and Margin Example

The nominal 600-mV FB pin references the OV fault, UV fault, and PGOOD limits, as defined by

PCT_VOUT_FAULT_PG_LIMIT command, regardless of VREF_TRIM or output margining. These limits remain

fixed percentages of the nominal 600 mV reference, regardless of output margining.

8.3.6 Switching Frequency

A resistor from the RT pin to AGND establishes the switching frequency during the power-up sequence. To

ensure proper detection, select a resistor with 1% tolerance from Table 2.

Table 2. Required RT

Resistors

NOMINAL

FREQUENCY

(kHz)

1% RESISTOR

VALUE (kΩ)

250

300

400

500

650

750

10.0

17.8

27.4

38.3

56.2

86.6

19

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

Table 2. Required RT

Resistors (continued)

NOMINAL

FREQUENCY

(kHz)

1% RESISTOR

VALUE (kΩ)

850

133

205

1000

The TPS544B20 and TPS544C20 devices detect values that are out-of-range on the RT pin. If the device

detects that RT pin has an out-of-range resistance connected to it, the device selects a frequency setting of

either 250 kHz (if the resistance is less than 5 kΩ) or 1 MHz (if the resistance is greater than 300 kΩ). In this

case, the device also asserts the IVFREQ bit in STATUS_MFR_SPECIFIC. Once VDD is applied, the frequency

latches in memory and RT pin deactives until BP6 falls below V_BP6UV. When the device has completed the

Power-on-reset sequence, it latches the frequency in memory and deactivates the RT pin until the BP6 voltage

falls below the BP6 undervoltage threshold setting.

8.3.7 Soft-Start

To control the inrush current needed to charge the output capacitors during the start-up sequence, the

TPS544C20 and TPS544B20 devices implement a soft-start time. When the device is enabled, the feedback

reference voltage, V_REF, rises from 0 V to its final value (including output margining or VREF_TRIM value) at a

slew rate defined by the TON_RISE command. The slew rate needed to increase the reference voltage from 0 V

to 600 mV at each given rise time defines the specified rise times. During the soft-start period, the error amplifier

operates as a unity-gain buffer to force the COMP pin voltage to track the internal reference and minimize the

offset between the internal reference and the output voltage. Because D-CAP mode or D-CAP2 mode control

regulates the valley voltage, the average output voltage can exceed the final regulation voltage several millivolts

at the end of the soft-start period See Figure 23.

CNTL

V_OUT

V_REF

V_COMP

COMP

STATE

Off

TON_DELAY

Off

TON_RISE

Buffer

NORMAL

Integrator

EA AMP

Figure 23. Soft-Start

8.3.8 Linear Regulators BP3 and BP6

Two on-board linear regulators provide suitable power for the internal circuitry of the devices. Externally bypass

pins BP3 and BP6 for the converter to function properly. BP3 requires a minimum of 100 nF of capacitance

connected to AGND. BP6 should be bypassed to GND with a 4.7-µF capacitor.

These devices allow the use of an internal regulator to power other circuits. Ensure that external loads placed on

the regulators do not adversely affect operation of the controller. Avoid loads with heavy transient currents that

can affect the regulator outputs. Transient voltages on these outputs can result in noisy or erratic operation.

Observe the current limits. Shorting the BP3 pin to GND can damage the BP3 regulator. The BP3 regulator input

comes from the BP6 regulator output. The BP6 regulator can supply 120 mA of current and the total current

drawn from both regulators must be less than 120 mA. This total current includes the device operating current

(I_VDD) plus the gate-drive current required to drive the power MOSFETs.

20

TPS544B20, TPS544C20

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ZHCSCI5B –MAY 2014–REVISED JULY 2016

8.3.9 External Bypass (BPEXT)

The BPEXT pin provides an external bypass of the internal BP6 regulator when the application includes an

external bias supply between 4.5 V and 6.5 V. Using an external supply reduces the power dissipation in these

devices and can slightly improve system efficiency. If the input voltage is less than the UVLO threshold, or if the

voltage on the BPEXT pin is lower than the switch-over voltage, V_{BPEXT(swover)}, these devices use the internal BP6

regulator. If the voltage on the BPEXT pin exceeds this switch-over voltage, then these devices disable the

internal BP6 regulator and BPEXT outputs to BP6, replacing the internal linear regulator, until the voltage on the

BPEXT pin falls by the BPEXT switch-over hysteresis amount, V_HYS(swover). If the application does not require the

BPEXT function, connect the BPEXT pin to GND.

12 V

VIN OK

BPEXT OK

Level Shift

Logic

VDD

6.5 V

4.2 V

5 V

VDD

BP6

BP6_INT

BPEXT

4.7 V

4.5 V

6.5 V

BPEXT

5 V

4.5V

BP6

+

V_{BPEXT(swover)}

UDG-12251

Figure 24. BP External

Figure 25. BP Crossover Diagram

NOTE

It is not recommended to transition BPEXT across the switch-over voltage, V_{BPEXT(swover)}

,

during regulation. The transition causes an overshoot or undershoot response on the

output voltage. Instead, the BPEXT voltage should be either fully established to its final

level, or pulled low to GND prior to entering regulation.

8.3.10 Current Monitoring and Low-Side MOSFET Overcurrent Protection

The TPS544C20 and TPS544B20 devices sense average output current using an internal sensefet. A sensefet

conducts a scaled-down version of the power-stage current. Sampling this current in the middle of the low-side

drive signal determines the average output current. This architecture achieves excellent current monitoring and

better overcurrent threshold accuracy than inductor DCR current sensing with minimal temperature variation and

no dependence on power loss in a higher DCR inductor. This enables the use of lower DCR inductors to improve

efficiency. Use the IOUT_CAL_OFFSET command to improve current sensing and overcurrent accuracy by

removing board layout-related systematic errors post assembly. The devices continually digitize the sensed

output current, and average it to reduce measurement noise. The devices then store the current value in the

read-only READ_IOUT register, enabling output current telemetry.

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SW

Seven

Consecutive

Cycle

LSOC

Current Sense

Amplifier

LFET

Counter

+

OCF/OCW

Comparators

Sensefet

Average

Current

Sensing

IOUT_OC_

FAULT_RESPONSE

Hiccup/

Latch-off

OCF/OCW

Thresholds

IOUT_CAL_

OFFSET

OCW

OCF

READ_IOUT

STATUS_IOUT

PMBus Engine

SMBALERT

GND

AGND

SenseFET

AGNDSNS

Figure 26. Sensefet Average Current Sensing and Low-Side Overcurrent Protection

The TPS544C20 and TPS544B20 devices also implement low-side MOSFET overcurrent protection with

programmable fault and warning thresholds. The IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT

commands set the low-side overcurrent thresholds.

As shown in Figure 26, if an overcurrent event is detected in a given switching cycle, the device increments an

overcurrent counter. When the device detects seven consecutive low-side overcurrent events, the converter

responds, flagging the appropriate status registers, triggering SMBALERT if it is not masked, and entering either

continuous restart hiccup, or latch-off according to the IOUT_OC_FAULT_RESPONSE command. In continuous

restart hiccup mode, the devices implement a time-out function that occurs after seven soft-start cycles; followed

by a normal soft-start attempt. When the overcurrent fault clears, normal operation resumes, otherwise, the

device detects overcurrent and the process repeats.

8.3.11 High-Side MOSFET Short-Circuit Protection

The TPS544B20 and devices also implement a fixed high-side MOSFET overcurrent (HSOC) protection to limit

peak current, and prevent inductor saturation in the event of a short circuit. The devices detect an overcurrent

event by sensing the voltage drop across the high-side MOSFET when it is on. If the peak current reaches the

HSOC level on any given cycle, the cycle terminates to prevent the current from increasing any further. For

accurate high-side MOSFET overcurrent protection, the VIN and VDD pins must be at the same voltage; split rail

operation is not supported.

8.3.12 Over-Temperature Protection

An internal temperature sensor protects the devices from thermal runaway. The internal thermal shutdown

threshold, T_SD, is fixed at 145°C typical. When the devices sense a temperature above T_SD, an over-temperature

fault internal (OTFI) is flagged, and power conversion stops until the sensed junction temperature falls by the

thermal shutdown hysteresis amount, T_HYST

,

(25°C typical). Additionally, the OTFI bit in

STATUS_MFR_SPECIFIC setting indicates when the devices detect an internal over-temperature event.

The TPS544C20 and TPS544B20 devices also provide programmable external over-temperature fault and

warning thresholds using measurements from an external temperature sensor connected on the TSNS pin. The

temperature sensor circuit applies two bias currents to an external NPN transistor, and measures ΔV_BEto infer

the junction temperature of the sensor. The TPS544C20 and TPS544B20 devices are designed to use a

standard 2N3904 NPN transistor as a temperature sensor. Other sensors may be used, but the devices assume

an ideality factor, n, of 1.008 for use with the 2N3904. The devices then digitize the result and compare it to the

user-configured over-temperature fault and warning thresholds. When an external over-temperature fault (OTF) is

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detected, power conversion stops until the sensed temperature falls by 20°C. The READ_TEMPERATURE_2

(8Eh) register is continually updated with the digitized temperature measurement, enabling temperature

telemetry. The OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) commands set the PMBus over-

temperature fault and warning thresholds. When an overtemperature event is detected, the device sets the

appropriate flags in STATUS_TEMPERATURE (7Dh) and triggers SMBALERT if it is not masked.

TI recommends routing a differential pair of AGND and TSNS from the TPS544B20 and TPS544C20 to the

collector-base and emitter terminals of the 2N3904. Include a 330-pF capacitor between the TSNS and AGND

pair traces to reduce temperature measurement noise and associated error. Implement the option to disable

external temperature sensing by terminating TSNS to AGNS with a 0-Ω resistor. This termination forces the

external temperature measurement to –40°C, and prevents external over-temperature faults tripping. The internal

temperature sensor, and internal over-temperature fault remain enabled regardless of the TSNS pin termination.

Internal Temp

OT Fault Internal

+

Sensor

Thermal

Shutdown

145°C

OT_FAULT_LIMIT

OT_WARN_LIMIT

OT

Fault

READ_

TEMPERATURE_2

STATUS_

TEMPERATURE

PMBus Engine

TSNS

Sampling and

Temperature

Conversion

STATUS_

MFR_SPECIFIC

∆V_BE

Measurement

Q_T

C_T

SMBALERT

Figure 27. Over-Temperature Protection

8.3.13 Input Undervoltage Lockout (UVLO)

The TPS544C20 and TPS544B20 devices provide flexible user adjustment of the undervoltage lockout threshold

and hysteresis. Two PMBus commands, VIN_ON (35h) and VIN_OFF (36h) allow the user to set these input

voltage turn-on and turn-off thresholds independently, with a minimum of 4-V turn-off to a maximum 16-V turn-on.

See the command descriptions for more details.

8.3.14 Output Overvoltage and Undervoltage Protection

The TPS544C20 and TPS544B20 devices include both output overvoltage protection (OVP) and output

undervoltage (UVP) protection. The devices compare the FB pin voltage to internal selectable pre-set voltages,

as defined by the PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h) command. As the output voltage

rises or falls from the nominal voltage, the FB voltage tracks a direct divider ratio of the output voltage. If the FB

voltage rises above the OVP threshold, the device terminates normal switching, declares an OV fault and turns

on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output voltage. If

the FB voltage falls below the OVP threshold, the low-side FET turns off and normal switching resumes.

If the FB voltage falls below the undervoltage protection level after soft-start sequence has completed, the device

terminates normal switching and forces both the high-side and low-side MOSFETs off, and awaits an external

reset or begins

a

hiccup time-out delay prior to restart, depending on the value of the

IOUT_OC_FAULT_RESPONSE (47h) command. The output undervoltage response is shared with the over-

current fault response.

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8.3.15 Fault Protection Responses

Table 3 summarizes the various fault protections and associated responses.

Table 3. Fault Protection Summary

FAULT

VDD UV

UV

OV

HSOC

LSOC

OT

TSD (OTFI)

1) Pre-biased

output

2) High-side short

3) FB short to

GND

1) Output

overcurrent

2) Low-side short

3) FB short high

High device

temperature due to

ambient or power

dissipation

1) Input

undervoltage

2) Loss of input

1) High-side short

2) Output short to

GND

1) Low-side short

2) Output

overcurrent

FAULT

CAUSES

High board

temperature

Voltage drop

across high-side

MOSFET

MONITORING Voltage on VDD

Sensed current in Voltage on TSNS

Temperature on

internal sensor

Voltage on FB pin Voltage on FB pin

SIGNAL

low-side MOSFET

Turns off on cycle-

by-cycle basis,

incrementing OC

counter; latch off

when counter

Tripping

increments OC

counter; latch off

when counter

overflows

HIGH-SIDE

MOSFET

Latch off

overflows

Latch on until

VOUT returns to

within PG window

LOW-SIDE

MOSFET

Latch off when

counter overflows

Latch off when

counter overflows

Latch off

No

Latch off

Yes⁽¹⁾

Latch off

Hiccup after

temperature

below reset

threshold

Hiccup after

temperature below

reset threshold

HICCUP

No⁽²⁾

Yes⁽¹⁾

Enabled during or

after SS once

LDRV pulse width

first exceeds CSA

sampling period

DURING

SOFT-START

Enabled

Disabled

Enabled

AFTER SOFT-

START

Enabled

(1) If the device is configured to restart continuously, triggering the fault causes a hiccup.

(2) Hiccup is not triggered if the device can bring the output voltage back to regulation. Hiccup remains enabled if the output reaches the

UV limit following an OV event

8.3.16 PMBus General Description

Timing and electrical characteristics of the PMBus specification can be found in the PMB Power Management

Protocol Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS544B20 and

TPS544C20devices support both the 100-kHz and 400-kHz bus timing requirements. The TPS544B20 and

TPS544C20 devices do not implement clock stretching when communicating with the master device.

Communication over the PMBus interface can support Packet Error Checking (PEC) if desired. If the PMbus host

supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a

STOP, the PEC is not used.

These devices support a subset of the commands in the PMBus 1.1 Power Management Protocol Specification.

See the Supported PMBus Commands section for more information.

The devices also support the SMBALERT response protocol. The SMBALERT response protocol is a mechanism

by which a slave device (such as the TPS544C20 device or the TPS544B20 device) can alert the master device

that it is available for communication. The master device processes this event and simultaneously accesses all

slave devices on the bus (that support the protocol) through the alert response address (ARA). Only the slave

device that caused the alert acknowledges this request. The host device performs a modified receive byte

operation to ascertain the slave devices address. At this point, the master device can use the PMBus status

commands to query the slave device that caused the alert. By default, these devices implement the auto alert

response, a manufacturer specific improvement to the SMBALERT response protocol, intended to mitigate the

issue of bus hogging. See the Auto ARA (Alert Response Address) Response section for more information. For

more information on the SMBus alert response protocol, see the System Management Bus (SMBus)

specification.

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The devices contain non-volatile memory that stores configuration settings and scale factors. However, the

devices do not save the settings programmed into this non-volatile memory. The STORE_USER_ALL (15h)

command must be used to commit the current settings to non-volatile memory as device defaults. Settings

available for storage in NVM are noted in their detailed descriptions.

8.3.17 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus.

The TPS544B20 and TPS544C20 devices each have 64 possible addresses (0 through 63 in decimal) that can

be assigned by connecting resistors from the ADDR0 and ADDR1 pins to AGND. The address is set in the form

of two octal (0-7) digits, one digit for each pin. ADDR1 is the high order digit and ADDR0 is the low-order digit.

These address selection resistors must be 1% tolerance or better. Using resistors other than the recommended

values can result in devices responding to adjacent addresses.

The E96 series resistors recommended for each digit value are shown in Table 4.

Table 4. Required Address Resistors

DIGIT

1% RESISTOR VALUE (kΩ)

0

1

2

3

4

5

6

7

10.0

17.8

27.4

38.3

56.2

86.6

133

205

The devices detect values that are out-of-range on the ADDR0 and ADDR1 pins. If the device detects that either

pin has an out-of-range resistance connected to it, the device continues to respond to PMBus commands, but

does so at address 127, which is outside of the possible programmed addresses. It is possible but not

recommended to use the device in this condition, especially if other devices are present on the bus or if another

device could possibly occupy the 127 address.

The device reserves certain addresses in the I²C address space for special functions. The PMBus protocol

allows the address of the device to respond to these addresses. The user is responsible for knowing which of

these reserved addresses are in use in a system and for setting the address of the device accordingly so as not

to interfere with other system operations.

NOTE

These devices can be set to respond to the reserved GLOBAL CALL address or Address

0. Do not set a device to this address unless the design allows no other devices to

respond to this address and that the overall bus is not affected by the presence of such an

address.

8.3.18 PMBus Connections

The TPS544B20 and TPS544C20 devices support both the 100-kHz and 400-kHz bus speeds. Connection for

the PMBus interface should follow the specification given in section 3.1.3 High-Power DC in the SMBus

specification V2.0 for the 400-kHz bus speed or the 3.1.2 Low Power DC section. The complete SMBus

specification is available from the SMBus web site, smbus.org.

8.3.19 Auto ARA (Alert Response Address) Response

By default, the TPS544B20 and TPS544C20 devices implement the auto alert response, a manufacturer specific

improvement to the standard SMBALERT response protocol defined in the SMBus specification. The auto alert

response is designed to prevent SMBALERT monopolizing in the case of a persistent fault condition on the bus.

The user can choose to disable the auto ARA response, and use the standard SMBALERT response as defined

in the SMBus specification, by using bit 8 of the MASK_SMBALERT (MFR_SPECIFIC_23) (E7h) command.

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In the case of a fault condition, the slave device experiencing the fault pulls down the shared SMBALERT line, to

alert the host that a fault condition has occurred. To establish which slave device has experienced the fault, the

host issues a modified receive byte operation to the alert response address (ARA), to which only the slave

device pulling down on SMBALERT should respond. The SMBus protocol provides a method for address

arbitration in the case that multiple slave devices on the same bus are experiencing fault conditions. Once the

host has established the address of the offending device, it must take any necessary action to release the

SMBALERT line. For more information on the standard SMBus alert response protocol, see the System

Management Bus (SMBus) specification.

In the case of a non-persistent fault (for example, a single-time event, such as an invalid command or data byte),

the host can ascertain the address of the slave device experiencing a fault using the standard ARA response,

and simply issue CLEAR_FAULTS (03h) to release the SMBALERT line, and resume normal operation.

However, in the case of a persistent fault (i.e. one which remains active for some time, such as a short-circuit, or

thermal shutdown), once the device issues a CLEAR_FAULTS (03h) command, the fault immediately re-triggers,

and SMBALERT continues to be pulled low. In this case, the device holds low the SMBALERT line until the host

masks the SMBALERT line using MASK_SMBALERT (MFR_SPECIFIC_23) (E7h) and then issues the

CLEAR_FAULTS (03h) command. Because the SMBALERT line remains low, the host cannot be alerted to other

fault conditions on the bus until it clears SMBALERT. This situation is known as bus hogging. Figure 28 and

Figure 29 illustrate an example of this response.

.

SMBALERT is not released until CLEAR_FAULTS

SMBALERT

is issued by the host

STATUS_CML

DATA

No Faults

Invalid Command

No Faults

PAGE

HOST

ARA Slave Address

HOST SLAVE

CLEAR_FAULT

HOST

Figure 28. Example Standard ARA Response to Non-Persistent Fault

.

SMBALERT is low until host masks fault, and issues CLEAR_FAULTS

if the fault condition persists

SMBALERT

STATUS_IOUT

DATA

No Faults

OC FAULT

ARA Slave Address

HOST SLAVE

MASK_SMBALERT

HOST

CLEAR_FAULTS

HOST

Short

Circuit

Figure 29. Example Standard ARA Response to a Persistent Fault

.

In order to mitigate the problem of bus hogging, these devices implement the Auto ARA response. When Auto

ARA is enabled, the devices release SMBALERT automatically after successfully responding to access from the

host at the alert response address. In this case, even when a device is experiencing a persistent fault, it does not

hold the SMBALERT line low following successful notification of the host, and the host can be alerted to other

faults on the bus in the normal manner. Examples of the auto ARA response are illustrated in Figure 30 and

Figure 31.

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SMBALERT is

released when slave

successfully responds to ARA

SMBALERT

STATUS_CML

DATA

No Faults

Invalid Command

No Faults

PAGE

HOST

ARA Slave Address

HOST SLAVE

CLEAR_FAULT

HOST

Figure 30. Example Auto ARA Response to Non-Persistent Fault

Host must mask SMBALERT or it will re-assert when

CLEAR_FAULTS is issued, if the fault condition persists

SMBALERT is

released when slave

SMBALERT

STATUS_IOUT

DATA

successfully responds to ARA

No Faults

OC FAULT

ARA Slave Address

HOST SLAVE

MASK_SMBALERT

HOST

CLEAR_FAULTS

HOST

Short

Circuit

Figure 31. Example Auto ARA Response to Persistent Fault

8.4 Device Functional Modes

8.4.1 Continuous Conduction Mode

The TPS544B20 and TPS544C20 devices operate in continuous conduction mode (CCM) at a fixed frequency,

regardless of the output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly

increased to prevent excessive current sinking when the device starts up with a pre-biased output. Following the

first clock 128 cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.

8.4.2 Operation with Internal BP6 Regulator

The TPS544B20 and TPS544C20 devices include an internal linear regulator to supply bias for internal logic and

the power MOSFET drivers. The BP6 regulator steps down the VDD voltage to approximately 6.5 V when V_VDDis

above 6.5 V, or operates with a maximum of 100-mV dropout when V_VDDis less than 6.5 V. In this case, the

BPEXT pin should be connected to GND.

8.4.3 Operation with BP External

The TPS544B20 and TPS544C20 devices can operate with an externally supplied voltage applied on the BPEXT

pin to bypass the BP6 regulator, which powers the MOSFET drivers. Using BP External reduces the power

dissipation inside the device, and leads to a small gain in overall efficiency. In this case, the BP6 regulator should

be bypassed as normal, but the BPEXT pin should also have a minimum of 2.2-µF bypass capacitance relative

to GND. See External Bypass (BPEXT) for more information.

8.4.4 Operation with CNTL Signal Control

According to the value in the ON_OFF_CONFIG register, The TPS544B20 and TPS544C20 devices can be

commanded to use the CNTL pin to enable or disable regulation, regardless of the state of the OPERATION

command. The minimum input high threshold for the CNTL signal is 2.1 V, and the maximum input low threshold

for the CNTL signal is 0.8 V. The CNTL pin can be configured as either active high or active low (inverted) logic.

8.4.5 Operation with OPERATION Control

According to the value in the ON_OFF_CONFIG register, these devices can be commanded to use the

OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

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Device Functional Modes (continued)

8.4.6 Operation with CNTL and OPERATION Control

According to the value in the ON_OFF_CONFIG register, these devices can be commanded to require both a

signal on the CNTL pin, and the OPERATION command to enable or disable regulation.

8.4.7 Operation with Output Margining

The OPERATION command can be used to toggle the device between three states:

•

Margin none

Margin low

Margin high

In the margin none state, the feedback reference, V_REF, is equal to the nominal 600-mV reference, plus any

offset defined by the VREF_TRIM command. In the margin low state, a negative offset defined by the

STEP_VREF_MARGIN_LOW command is applied to the feedback reference, moving the converter output

voltage down by an equivalent percentage. In the margin high state, a positive offset defined by the

STEP_VREF_MARGIN_HIGH command is applied to the feedback reference, moving the converter output

voltage up by an equivalent percentage. See the PMBus Output Voltage Adjustment section for more

information.

8.5 Programming

8.5.1 Supported PMBus Commands

The commands listed in the Table 5 section are implemented as described to conform to the PMBus 1.1

specification. It also shows default behavior and register values.

Table 5. Supported PMBus Commands and Default Values

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.1

COMMAND NAME

PMBus COMMAND DESCRIPTION

DEFAULT BEHAVIOR

Can be configured via

ON_OFF_CONFIG to be used to turn the Margin None.

01h

02h

OPERATION

output on and off with or without input

from the CTRL pin. Also used to turn on to enable regulation

and off margin high and low.

OPERATION is not used

00h

16h

Configures the combination of CNTL pin

input and OPERATION command for

turning output on and off.

ON_OFF_CONFIG

CNTL only. Active High

Clears all fault status registers to 0x00

and releases SMBALERT.

03h

10h

15h

16h

CLEAR_FAULTS

Write-only

n/a

00h

n/a

Allow writes to all

registers

WRITE_PROTECT

STORE_USER_ALL

RESTORE_USER_ALL

Used to control writing to the device.

Stores all current storable register

settings into EEPROM as new defaults.

Write-only

Restores all storable register settings

from EEPROM.

Provides a way for a host system to

determine key PMBus capabilities of the

device.

Read only. PMBus v1.1,

400 kHz, PEC enabled

19h

CAPABILITY

B0h

20h

35h

VOUT_MODE

VIN_ON

Read-only output mode indicator.

Linear, exponent = –9

4.25 V

17h

Sets value of input voltage at which the

device should start power conversion.

F011h

Sets value of input voltage at which the

device should stop power conversion.

36h

39h

VIN_OFF

4.0V

F010h

E000h

Can be set to null out offsets in the

current sensing circuit.

IOUT_CAL_OFFSET

0.0000 A

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Programming (continued)

Table 5. Supported PMBus Commands and Default Values (continued)

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.1

COMMAND NAME

PMBus COMMAND DESCRIPTION

DEFAULT BEHAVIOR

F84Eh

(TPS544C20)

F834h

39 A (TPS544C20)

26 A (TPS544B20)

Sets the value of the output current that

causes an overcurrent fault condition.

46h

47h

IOUT_OC_FAULT_LIMIT

(TPS544B20)

Sets response to output overcurrent and

IOUT_OC_FAULT_RESPONSE

undervoltage faults to latch-off or hiccup Shutdown and latch-off

mode.

07h

F8C3h

(TPS544C20)

F828h

30 A (TPS544C20)

20 A (TPS544B20)

Sets the value of the output current that

causes an overcurrent warning condition.

4Ah

IOUT_OC_WARN_LIMIT

(TPS544B20)

F814h ()

Sets the value of the sensed temperature

that causes an overtemperature fault

condition.

4Fh

51h

61h

OT_FAULT_LIMIT

OT_WARN_LIMIT

TON_RISE

150 °C

0096h

007Dh

E02Bh

Sets the value of the sensed temperature

that causes an overtemperature warning 125 °C

condition.

Sets the time from when the output starts

to rise until the voltage has entered the

regulation band.

2.7 ms

Returns one byte summarizing the most

critical faults.

78h

79h

7Ah

7Bh

STATUS_BYTE

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

Read only

Current status

Returns two bytes summarizing fault and

warning conditions.

Returns one byte detailing if an output

fault or warning has occurred

Retyrns one byte detailing if an

overcurrent fault or warning has occurred

Returns one byte detailing if a sensed

temperature fault or warning has

occurred.

7Dh

7Eh

80h

STATUS_TEMPERATURE

STATUS_CML

Read only

Current status

Returns one byte containing PMBus

serial communication faults.

Returns one byte detailing if internal

overtemperature or frequency detection

fault has occurred.

STATUS_MFR_SPECIFIC

8Bh

8Ch

READ_VOUT

READ_IOUT

Returns the output voltage in volts.

Returns the channel current in amps.

Read only

Current status

Returns the sensed temperature in

degrees Celsius.

8Eh

98h

D0h

D4h

READ_TEMPERATURE_2

PMBUS_REVISION

Read only

00h

Current status

11h

Returns PMBus revision to which the

device is compliant.

Two bytes dedicated as a user scratch

pad.

MFR_SPECIFIC_00

00h

VREF_TRIM

(MFR_SPECIFIC_04)

Used to apply a fixed offset voltage to

the reference voltage.

0.000 V

0000h

Sets the increase to the value of the

reference voltage for shifting the

reference higher.

STEP_VREF_MARGIN_HIGH

(MFR_SPECIFIC_05)

D5h

D6h

60 mV

001Eh

FFE2h

Sets the decrease to the value of the

reference voltage for shifting the

reference lower.

STEP_VREF_MARGIN_LOW

(MFR_SPECIFIC_06)

–60 mV

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Programming (continued)

Table 5. Supported PMBus Commands and Default Values (continued)

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.1

COMMAND NAME

PMBus COMMAND DESCRIPTION

DEFAULT BEHAVIOR

UV Fault: –16.8%

Sets the PGOOD and output

undervoltage and overvoltage limits as a

percent of nominal.

PGOOD (falling): –12.5%

PGOOD (rising): 12.5%

OV Fault: 16.8 %

PCT_VOUT_FAULT_PG_LIMIT

(MFR_SPECIFIC_07)

D7h

00h

TON_DELAY: 0ms

TOFF_DELAY: 0ms

SEQUENCE_TON_TOFF_DELAY

(MFR_SPECIFIC_08)

Sets the delays for turning the output on

and off as a ratio of TON_RISE.

D8h

E5h

00h

OPTIONS

(MFR_SPECIFIC_21)

Sets miscellaneous user selectable

options.

ADC is enabled.

Telemetry is enabled.

0004h

Auto ARA is enabled.

No SMBALERT sources

are masked

Used to mask which faults or warnings

assert SMBALERT, and enable Auto

ARA.

MASK_SMBALERT

(MFR_SPECIFIC_23)

E7h

FCh

0100h

0153h

(TPS544C20)

0143h

0153h (TPS544C20)

0143h (TPS544B20)

DEVICE_CODE

(MFR_SPECIFIC_44)

Returns a 12-bit unique identifier code

for the device and a 4-bit revision code.

(TPS544B20)

8.6 Register Maps

This family of devices supports the following commands from the PMBus 1.1 specification.

8.6.1 OPERATION (01h)

The OPERATION command turns the device output on or off in conjunction with input from the CNTL signal. It

also sets the output voltage to the upper or lower margin voltages. The unit stays in the commanded operating

mode until a subsequent OPERATION command or a change in the state of the CNTL pin instructs the device to

change to another mode.

COMMAND

Format

OPERATION

Unsigned binary

Bit Position

Access

7

r/w

ON

0

6

r

5

4

3

2

1

r

0

r

r/w

Function

X

0

Margin

X

Default Value

0

8.6.1.1 On

This bit is an enable command to the converter.

•

0: output switching is disabled. Both drivers placed in an off or low state.

1: output switching is enabled if the input voltage is above undervoltage lockout, OPERATION is configured

as a gating signal in ON_OFF_CONFIG, and no fault conditions exist.

8.6.1.2 Margin

If Margin Low is enabled, the feedback voltage is offset with the value from the STEP_VREF_MARGIN_LOW

command. If Margin High is enabled, the feedback voltage is offset with the value from the

STEP_VREF_MARGIN_HIGH command. (See PMBus specification for more information)

•

00XX: Margin Off

0101: Margin Low (Ignore on Fault)

0110: Margin Low (Act on Fault)

1001: Margin High (Ignore on Fault)

1010: Margin High (Act on Fault)

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NOTE

Because the PGOOD, OV and UV thresholds remain referenced to the nominal 600-mV

feedback reference, it is possible to use the Margin High, Margin Low or VREF_TRIM

options to set the reference voltage into a PGOOD or Undervoltage Fault based on the

ranges provided. When using the Ignore Fault option of the OPERATION command, these

faults are masked when entering Margin High or Margin Low, but they PGOOD or Under

Voltage Fault can be triggered when returning to Margin Off.

8.6.2 ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands

needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the

STORE_USER_ALL command.

COMMAND

Format

ON_OFF_CONFIG

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r/w

pu

1

3

r/w

cmd

0

2

r/w

cpr

1

0

r

r/w

pol

1

Function

X

cpa

0

Default Value

8.6.2.1 pu

The pu bit sets the default to either operate any time power is present or for power conversion to be controlled by

CNTL pin and PMBus OPERATION command. This bit is used in conjunction with the 'cp', 'cmd', and 'on' bits to

determine start up.

BIT VALUE

ACTION

0

Device powers up any time power is present regardless of state of the CNTL pin.

Device does not power up until commanded by the CNTL pin and OPERATION

command as programmed in bits [2:0] of the ON_OFF_CONFIG register.

1

8.6.2.2 cmd

The cmd bit controls how the device responds to the OPERATION command.

BIT VALUE

ACTION

0

1

Device ignores the “on” bit in the OPERATION command.

Device responds to the “on” bit in the OPERATION command.

8.6.2.3 cpr

The cpr bit sets the CNTL pin response. This bit is used in conjunction with the 'cmd', 'pu', and 'on' bits to

determine start up.

BIT VALUE

ACTION

Device ignores the CNTL pin. Power conversion is controlled only by the OPERATION

command.

0

1

Device requires the CNTL pin to be asserted to start the unit.

8.6.2.4 pol

The pol bit controls the polarity of the CNTL pin. For a change to become effective, the contents of the

ON_OFF_CONFIG register must be stored to non-volatile memory using the STORE_USER_ALL command and

the device power cycled. Simply writing a new value to this bit does not change the polarity of the CNTL pin.

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BIT VALUE

ACTION

0

1

CNTL pin is active low.

CNTL pin is active high.

8.6.2.5 cpa

The cpa bit sets the CNTL pin action when turning the controller off. This bit is read internally and cannot be

modified by the user.

BIT VALUE

ACTION

0

Turn off the output using the programmed delay.

8.6.3 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits

in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT

output if the device is asserting SMBALERT. The CLEAR_FAULTS command does not cause a unit that has

latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit is

immediately reset and the host notified by the usual means.

8.6.4 WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is

to provide protection against accidental changes. This command is not intended to provide protection against

deliberate or malicious changes to the device configuration or operation. All supported command parameters

may have their parameters read, regardless of the WRITE_PROTECT settings. Write protection also prevents

protected registers from being updated in the event of a RESTORE_USER_ALL. The contents of this register

can be stored to non-volatile memory using the STORE_USER_ALL command.

COMMAND

Format

WRITE_PROTECT

Unsigned binary

Bit Position

Access

7

r/w

bit7

0

6

r/w

bit6

0

5

r/w

bit5

0

4

X

3

X

2

X

1

X

0

X

Function

Default Value

8.6.4.1 bit5

8.6.4.2 bit6

8.6.4.3 bit7

BIT VALUE

ACTION

0

Enable all writes as permitted in bit6 or bit7

Disable all writes except the WRITE_PROTECT, OPERATION and ON_OFF_CONFIG.

(bit6 and bit7 must be 0 to be valid data)

1

BIT VALUE

ACTION

0

Enable all writes as permitted in bit5 or bit7

Disable all writes except for the WRITE_PROTECT, and OPERATION commands. (bit5

and bit7 must be 0 to be valid data)

1

BIT VALUE

ACTION

0

Enable all writes as permitted in bit5 or bit6

Disable all writes except for the WRITE_PROTECT command. (bit5 and bit6 must be 0

to be valid data)

1

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In any case, only one of the three bits may be set at any one time. Attempting to set more than one bit results in

an alert being generated and the cml bit is STATUS_WORD being set. An invalid setting of the

WRITE_PROTECT command results in no write protection.

8.6.5 STORE_USER_ALL (15h)

The STORE_USER_ALL command stores all of the current storable register settings in the EEPROM memory as

the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to

switch but ignores all fault conditions until the internal store process has completed.

EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the 'oth'

bit in the STATUS_CML registers.

The following registers can be stored to EEPROM memory using STORE_USER_ALL:

•

ON_OFF_CONFIG

WRITE_PROTECT

VIN_ON

VIN_OFF

IOUT_CAL_OFFSET

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

IOUT_OC_FAULT_RESPONSE

OT_FAULT_LIMIT

OT_WARN_LIMIT

TON_RISE

MFR_SPECIFIC_00

VREF_TRIM

STEP_VREF_MARGIN_HIGH

STEP_VREF_MARGIN_LOW

PCT_VOUT_FAULT_PG_LIMIT

SEQUENCE_TON_TOFF_DELAY

OPTIONS

MASK_SMBALERT

8.6.6 RESTORE_USER_ALL (16h)

The RESTORE_USER_ALL command restores all of the storable register settings from EEPROM memory.

Do not use this command while the device is actively switching, this causes the device to stop switching and the

output voltage to fall during the restore event. Depending on loading conditions, the output voltage could reach

an undervoltage level and trigger an undervoltage fault response if programmed to do so. The command can be

used while the device is switching, but it is not recommended as it results in a restart that could disrupt power

sequencing requirements in more complex systems. It is strongly recommended that the device be stopped

before issuing this command.

NOTE

A VIN_UV fault may be triggered when RESTORE_USER_ALL command is set. The

firmware workaround is accomplished by verifying that, upon completion of

a

RESTORE_USER_ALL command, the sole source asserting SMBALERT is the VIN_UV

bit in STATUS_BYTE. If so, issue a CLEAR_FAULTS command. Any other source

asserting

SMBALERT

under

these

circumstances

(i.e.

completion

of

RESTORE_USER_ALL) would indicate an actual fault condition.

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8.6.7 CAPABILITY (19h)

The CAPABILITY command provides a way for a host system to determine some key capabilities of this PMBus

device.

COMMAND

Format

CAPABILITY

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

3

r

2

r

1

r

0

r

ALRT

1

Function

PEC

1

SPD

Reserved

Default Value

0

1

0

The default values indicate that the device supports Packet Error Checking (PEC), a maximum bus speed of 400

kHz (SPD) and the SMBus Alert Response Protocol using SMBALERT.

8.6.8 VOUT_MODE (20h)

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of

a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the

Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the

linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the

values.

COMMAND

Bit Position

VOUT_MODE

7

r

6

5

r

4

r

3

r

2

1

r

0

r

Access

r

Mode

0

r

Exponent

1

Function

Default Value

0

1

0

1

8.6.8.1 Mode:

Value fixed at 000, linear mode.

8.6.8.2 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9.

8.6.9 VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all

other required startup conditions are met. Values are mapped to the nearest supported increment. Values

outside the supported range are treated as invalid data and cause the device set the CML bit in the

STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_ON remains

unchanged on an out-of-range write attempt. The contents of this register can be stored to non-volatile memory

using the STORE_USER_ALL command.

The supported VIN_ON values are shown in Table 6:

Table 6. Supported VIN_ON Values

VIN_ON Values (V)

4.25 (default)

4.5

5.75

7

4.75

6

5

6.25

7.5

9

5.25

6.5

8

5.5

6.75

8.25

9.5

12

7.25

8.75

10.5

13

8.5

10

9.25

11.5

15

11

12.5

14

16

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VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the CML bit

in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The

four most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

COMMAND

Format

VIN_ON

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

0

1

8.6.9.1 Exponent

–2 (dec), fixed.

8.6.9.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable with a default value of 17 (dec), corresponding to a default of 4.25 V.

8.6.10 VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are

mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers. The value of VIN_OFF remains unchanged during an out-of-range write attempt. The contents of this

register can be stored to non-volatile memory using the STORE_USER_ALL command.

The supported VIN_OFF values are shown in Table 7:

Table 7. Supported VIN_OFF Values

VIN_OFF Values (V)

4 (default)

5.25

4.25

5.5

4.5

5.75

7

4.75

6

5

6.25

7.5

6.5

6.75

8.25

9.75

12

7.25

8.75

10.75

14.75

8

8.5

9

9.25

10.25

13.75

11.25

15.75

11.75

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the cml bit in

STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The

4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

COMMAND

Format

VIN_OFF

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

0

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8.6.10.1 Exponent

–2 (dec), fixed.

8.6.10.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable with a default value of 16 (dec). This corresponds to a default value of

4.0 V.

8.6.11 IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the

IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is

0 A. The resolution of the argument for this command is 62.5 mA and the range is +3937.5 mA to -4000 mA.

Values written outside of this range alias into the supported range. This occurs because the read-only bits are

fixed. The exponent is always –4 and the 5 msb bits of the Mantissa are always equal to the sign bit. The

contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

COMMAND

Format

IOUT_CAL_OFFSET

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

1

r

0

r

7

r

6

r

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

8.6.11.1 Exponent

–4 (dec), fixed.

8.6.11.2 Mantissa

MSB is programmable with sign, next 4 bits are sign extend only.

Lower six bits are programmable with a default value of 0 (dec).

8.6.12 IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the

overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal

to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than

IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd)

bit in the STATUS_CML registers as well as assert SMBALERT. The contents of this register can be stored to

non-volatile memory using the STORE_USER_ALL command.

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:

COMMAND

Format

IOUT_OC_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

4

3

2

1

0

r

r/w

Function

Exponent

Mantissa

Default Value

See Below

8.6.12.1 Exponent

–1 (dec), fixed.

8.6.12.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable.

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The actual output current for a given mantissa and exponent is shown in Equation 5.

Mantissa

=

I_OUT(oc)= Mantissa´ 2^Exponent

2

(5)

The default values and allowable ranges for each device are summarized below:

OC_FAULT_LIMIT

DEVICE

UNIT

MIN

5

DEFAULT

MAX

45

TPS544C20

TPS544B20

39

26

A

5

30

8.6.13 IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an

IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also:

•

Sets the IOUT_OC bit in the STATUS_BYTE

Sets the IOUT or POUT bit in the STATUS_WORD

Sets the IOUT OC Fault bit in the STATUS_IOUT register

Notifies the PMBus host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_USER command.

COMMAND

Format

IOUT_OC_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r

6

r

5

r/w

4

r/w

3

r/w

2

r

1

r

0

r

Function

X

0

X

0

RS[2]

0

RS[1]

0

RS[0]

0

X

1

X

1

X

1

Default Value

8.6.13.1 RS[2:0]

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML.

8.6.14 IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-

current detector to indicate an over-current warning. When this current level is exceeded the device:

•

Sets the OTHER bit in the STATUS_BYTE

Sets the IOUT or POUT bit in the STATUS_WORD

Sets the IOUT overcurrent Warning (OCW) bit in the STATUS_IOUT register, and

Notifies the host by asserting SMBALERT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the

IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers as well as assert SMBALERT. The contents of this register can be stored to non-volatile memory using

the STORE_USER_ALL command.

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:

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COMMAND

IOUT_OC_WARN_LIMIT

Format

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

4

3

2

1

0

r

r/w

Function

Exponent

Mantissa

Default Value

See Below

8.6.14.1 Exponent

–1 (dec), fixed.

8.6.14.2 Mantissa

The upper four bits are fixed at 0.

Lower seven bits are programmable.

The actual output warning current level for a given mantissa and exponent is:

-°Æ¥©≥≥°

)

= -°Æ¥©≥≥° × 2^{%∏∞ØÆ•Æ¥}

=

/54 (/#7 ꢀ

2

(6)

The default values and allowable ranges for each device are summarized below:

OC_WARN_LIMIT

DEVICE

UNIT

MIN

4

DEFAULT

MAX

TPS544C20

TPS544B20

30

20

45

30

A

4

8.6.15 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-

temperature fault condition, when the sensed temperature from the external sensor exceeds this limit. Upon

triggering the over-temperature fault, the device takes the following actions:

•

Sets the TEMPERATURE bit in the STATUS_BYTE

Sets the OT Fault bit in the STATUS_TEMPERATURE

Notifies the host by asserting SMBALERT

Once the over-temperature fault is tripped, the output is latched off until the external sensed temperature falls

20°C from the OT_FAULT_LIMIT, at which point the output goes through a normal startup (soft-start).

The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT

less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the

invalid data (ivd) bit in the STATUS_CML registers as well as asserts SMBALERT. The contents of this register

can be stored to non-volatile memory using the STORE_USER_ALL command.

The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.

COMMAND

Format

OT_FAULT_LIMIT

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

6

5

r/w

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

0

Default Value

0

1

0

1

0

1

0

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8.6.15.1 Exponent

0 (dec), fixed.

8.6.15.2 Mantissa

The upper three bits are fixed at 0.

Lower eight bits are programmable with a default value of 150 (dec).

The default over-temperature fault setting is 150°C. Values can range from 120°C to 165°C in 1°C increments.

8.6.16 OT_WARN_LIMIT (51h)

The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-

temperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon

triggering the over-temperature warning, the device takes the following actions:

•

Sets the TEMPERATURE bit in the STATUS_BYTE

Sets the OT Warning bit in the STATUS_TEMPERATURE

Notifies the host by asserting SMBALERT

Once the over-temperature warning is tripped, the warning flag is latched until the external sensed temperature

falls 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT

greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the

invalid data (ivd) bit in the STATUS_CML registers as well as assert SMBALERT. The contents of this register

can be stored to non-volatile memory using the STORE_USER_ALL command.

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

COMMAND

Format

OT_WARN_LIMIT

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

6

5

r/w

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

1

Default Value

0

1

0

1

8.6.16.1 Exponent

0 (dec), fixed.

8.6.16.2 Mantissa

The upper three bits are fixed at 0.

Lower eight bits are programmable with a default value of 125 (dec).

The default over-temperature fault setting is 125°C. Values can range from 100°C to 140°C in 1°C increments.

8.6.17 TON_RISE (61h)

The TON_RISE command sets the time in ms, from when the reference starts to rise until the voltage has

entered the regulation band. It also determines the rate of the transition of the reference voltage (either due to

VREF_TRIM or STEP_VREF_MARGIN_x commands) when this transition is executed during the soft-start

period. There are several discrete settings that this command supports. Commanding a value other than one of

these values results in the nearest supported value being selected.

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The supported TON_RISE times over PMBus are shown in Table 8:

Table 8. Supported TON_RISE Values

TON_RISE VALUES (ms)

0.6

4.2

0.9

6.0

1.2

9.0

1.7

2.7 (default)

A value of 0 ms instructs the unit to bring its output voltage to the programmed regulation value as quickly as

possible. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL

command.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TON_RISE

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

6

5

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

1

Default Value

1

0

1

0

1

8.6.17.1 Exponent

–4 (dec), fixed.

8.6.17.2 Mantissa

The upper two bits are fixed at 0.

The lower eight bits are programmable with a default value of 43 (dec).

8.6.18 STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

COMMAND

Format

STATUS_BYTE

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

3

r

2

r

1

r

0

r

IOUT_OC

0

r

Function

X

0

OFF

0

VOUT_OV

0

VIN_UV

0

TEMPERATURE CML

NONE OF THE ABOVE

0

Default Value

0

A "1" in any of these bit positions indicates that:

OFF:

The device is not providing power to the output, regardless of the reason. In this family of devices,

this flag means that the converter is not enabled.

VOUT_OV:

An output overvoltage fault has occurred.

IOUT_OC:

An output over current fault has occurred.

VIN_UV:

An input undervoltage fault has occurred.

TEMPERATURE:

A temperature fault or warning has occurred. Check STATUS_TEMPERATURE.

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CML:

A Communications, Memory or Logic fault has occurred. Check STATUS_CML.

NONE OF THE ABOVE:

A fault or warning not listed in bit1 through bits 1-7 has occurred, for example an undervoltage

condition or an over current warning condition. Check other status registers.

8.6.19 STATUS_WORD (79h)

The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning

conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning

conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

COMMAND

Format

STATUS_WORD (low byte) = STATUS_BYTE

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

3

2

r

1

r

0

r

IOUT_OC

0

r

VIN_UV

0

r

Function

X

0

OFF

x

VOUT_OV

0

TEMPERATURE CML

NONE OF THE ABOVE

0

Default Value

0

A "1" in any of the low byte (STATUS_BYTE) bit positions indicates that:

OFF:

The device is not providing power to the output, regardless of the reason. In this family of devices

this flag means that the converter is not enabled.

VOUT_OV:

An output overvoltage fault has occurred.

IOUT_OC:

An output over current fault has occurred.

VIN_UV:

An input undervoltage fault has occurred.

TEMPERATURE:

A temperature fault or warning has occurred. Check STATUS_TEMPERATURE.

CML:

A Communications, Memory or Logic fault has occurred. Check STATUS_CML.

NONE OF THE ABOVE:

A fault or warning not listed in bits 1-7 has occurred. See other status registers.

COMMAND

Format

STATUS_WORD (high byte)

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

IOUT or

POUT

Function

VOUT

0

X

0

MFR

0

POWER_GOOD

0

X

0

X

0

X

0

Default Value

0

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A "1" in any of the high byte bit positions indicates that:

VOUT:

An output voltage fault or warning has occurred. Check STATUS_VOUT.

IOUT/POUT:

An output current warning or fault has occurred. The PMBus specification states that this warning

also applies to output power. This family of devices does not support output power warnings or

faults. Check STATUS_IOUT.

MFR:

An internal thermal shutdown (TSD) fault has occurred in the device. Check

STATUS_MFR_SPECIFIC.

POWER_GOOD:

The power good signal has not transitioned from high-to-low.

8.6.20 STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related

faults. The only bits of this register supported are:

•

VOUT_OV Fault

VOUT_UV Fault

COMMAND

STATUS_VOUT

Format

Unsigned binary

Bit Position

Access

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

VOUT OV Fault

0

X

0

X

0

VOUT UV Fault

X

0

X

0

X

0

X

0

Default Value

0

A "1" in any of these bit positions indicates that:

VOUT OV Fault:

The device has seen the output voltage rise above the output overvoltage threshold.

VOUT UV Fault:

The device has seen the output voltage fall below the output undervoltage threshold.

8.6.21 STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the output current related

faults. The only bits of this register supported are:

•

IOUT_OC Fault

IOUT_OC Warning

COMMAND

STATUS_IOUT

Format

Unsigned binary

Bit Position

Access

7

6

r

5

4

r

3

r

2

r

1

r

0

r

Function

IOUT_OC Fault

0

X

0

IOUT_OC Warning

0

X

0

X

0

X

0

X

0

X

0

Default Value

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A "1" in any of these bit positions indicates that:

IOUT_OC Fault:

The device has seen the output current rise above the level set by IOUT_OC_FAULT_LIMIT.

IOUT_OC Warn:

The device has seen the output current rise relating to the level set by IOUT_OC_WARN_LIMIT.

8.6.22 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external

temperature related faults. The only bits of this register supported are:

•

OT Fault

OT Warning

COMMAND

STATUS_TEMPERATURE

Format

Unsigned binary

Bit Position

Access

7

6

5

r

4

r

3

r

2

r

1

r

0

r

OT Fault

0

r

Function

OT Warning

0

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

OT Fault:

The measured external temperature has exceeded the level set by OT_FAULT_LIMIT.

OT Warning:

The measured external temperature has exceeded the level set by OT_WARN_LIMIT.

8.6.23 STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the converter’s

communication related faults. The bits of this register supported by the this family of devices are:

•

Invalid or Unsuppported Command

Invalid or Unsupported Data

Packet Error Check Failed

Memory Fault Detected

Other Communication Fault.

COMMAND

STATUS_CML

Format

Bit Position

Unsigned binary

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Access

Invalid or

Unsupported

Command

Invalid or

Unsupported

Data

Other

Communication

Fault

Packet Error

Check Failed

Memory Fault

Detected

Function

X

0

X

0

X

0

Default Value

0

A "1" in any of these bit positions indicates that:

Invalid or Unsupported Command:

An invalid or unsupported command has been received.

Invalid or Unsupported Data

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Invalid or unsupported data has been received

Packet Error Check Failed

A packet has failed the CRC checksum error check.

Memory Fault Detected

A fault has been detected with the internal memory.

Other Communication Fault

Some other communication fault or error has occurred

8.6.24 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturer-

specific faults or warnings.

COMMAND

Format

STATUS_MFR_SPECIFIC

Unsigned binary

Bit Position

Access

7

6

r

5

r

4

3

r

2

r

1

r

0

r

OTFI

0

r

IVFREQ

0

Function

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

OTFI:

The internal temperature is above the thermal shutdown (TSD) fault threshold

IVFREQ:

The switching frequency detection circuit is not resolving to a valid selection based on the RT

resistor.

8.6.25 READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage

of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the

load is not accounted for. The data format is as shown below:

COMMAND

Format

READ_VOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Mantissa

0

Default Value

0

The setting of the VOUT_MODE affects the results of this command as well. In this family of devices,

VOUT_MODE is set to linear mode with an exponent of –9 and cannot be altered. The output voltage calculation

is shown in Equation 7.

Exponent

V

= Mantissa´ 2

OUT

(7)

8.6.26 READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current

of the controller. The average output current is sensed according to the method described in Low-Side MOSFET

Current Sensing and Overcurrent Protection. The data format is as shown below:

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COMMAND

Format

READ_IOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

1

r

Function

Mantissa

0

Default Value

1

0

The device scales the output current before it reaches the internal analog to digital converter so that resolution of

the output current read is 62.5 mA. The maximum value that can be reported is 64 A. The user must set the

IOUT_CAL_OFFSET parameter correctly in order to obtain accurate results. Calculate the output current using

Equation 8.

Exponent

I

= Mantissa´ 2

OUT

(8)

8.6.26.1 Exponent

Fixed at -4.

8.6.26.2 Mantissa

The lower 10 bits are the result of the ADC conversion of the average output current, as indicated by the output

of the internal current sense amplifier. The 11th bit is fixed at 0 because only positive numbers are considered

valid. Any computed negative current is reported as 0 A.

8.6.27 READ_TEMPERATURE_2 (8Eh)

The READ_TEMPERATURE_2 command returns the external temperature in degrees Celsius of the current

channel.

COMMAND

Format

READ_TEMPERATURE_2

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

0

r

Function

Mantissa

0

Default Value

0

1

0

1

8.6.27.1 Exponent

0 (dec), fixed.

8.6.27.2 Mantissa

The lower 11 bits are the result of the ADC conversion of the external temperature. The default reading is 25

(dec) corresponding to a temperature of 25°C.

8.6.28 PMBUS_REVISION (98h)

The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that these devices are

compatible with the 1.1 revision of the PMBus specification.

COMMAND

Format

PMBUS_REVISION

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Default Value

0

1

0

1

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8.6.29 MFR_SPECIFIC_00 (D0h)

The MFR_SPECIFIC_00 register is dedicated as a user scratch pad.

COMMAND

Format

MFR_SPECIFIC_00

Unsigned binary

Bit Position

Access

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

User scratch pad

Default Value

0

The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

8.6.30 VREF_TRIM (MFR_SPECIFIC_04) (D4h)

The VREF_TRIM command applies a fixed offset voltage to the reference voltage. It is most typically used to trim

the output voltage at the time the PMBus device is assembled into the final application design. The contents of

this register can be stored to non-volatile memory using the STORE_USER_ALL command.

the settings of the VOUT_MODE command determine the effect of VREF_TRIM command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –9 (decimal).

6_{2%& Ø¶¶≥•¥}= 62%&_42)- × ꢀ ≠6

:

;

(9)

The maximum trim ranges between –20% to +10% of the nominal reference voltage (600 mV) in 2 mV steps.

Permissible values range from –120 mV to +60 mV. If a value outside this range is given with this command, the

device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts

SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible

reference voltage adjustment range is –180 mV to +60 mV (-30% to +10%). If a value outside this range is given

with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of

the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is

executed during the soft-start period. Any transition in the reference voltage after soft-start is complete occurs at

the slew rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the

reference by 10%, occurs in approximately 900 µs.

COMMAND

Format

VREF_TRIM

Linear, two’s complement binary

Bit Position

Access

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default

Value

0

8.6.31 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)

The STEP_VREF_MARGIN_HIGH command sets the target voltage which the reference voltage changes to

when the OPERATION command is set to "Margin High". The contents of this register can be stored to non-

volatile memory using the STORE_USER_ALL command.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –9 (decimal). The actual reference voltage commanded by a

margin high command can be found by:

6_{2%& -(}= ꢀ34%0_62%&_-!2')._()'( + 62%&_42)-ꢁ × ꢂ ≠6

:

;

(10)

46

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ZHCSCI5B –MAY 2014–REVISED JULY 2016

The margin high range is between 0% and 10% of the nominal reference voltage (600 mV) in 2-mV steps.

Permissible values range from 0 mV to 60 mV. If a value outside this range is given with this command, the

device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts

SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible

reference voltage adjustment range is –180 mV to 60 mV (-30% to 10%). If a value outside this range is given

with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of

the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is

executed during soft-start. Any transition in the reference voltage after soft-start is complete occurs at the slew

rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the reference by

10%, occurs in approximately 900 µs.

COMMAND

Format

STEP_VREF_MARGIN_HIGH

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

The default value of STEP_VREF_MARGIN_HIGH is 30 (dec), corresponding to a default margin high voltage of

60 mV (+10%) .

8.6.32 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)

The STEP_VREF_MARGIN_LOW command sets the target voltage which the reference voltage changes to

when the OPERATION command is set to Margin Low. The contents of this register can be stored to non-volatile

memory using the STORE_USER_ALL command.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –9 (decimal). Equation 11 shows the actual output voltage

commanded by a margin high command.

6_{2%& -,}= (34%0_62%&_-!2')._,/7 + 62%&_42)-ꢀ × ꢁ ≠6

:

;

(11)

The margin low ranges between –20% and 0% of the nominal reference voltage (600 mV) in 2-mV steps.

Permissible values range from –120 mV to 0 mV. If a value outside this range is given with this command, the

device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts

SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible

reference voltage adjustment range is –180 mV to 60 mV (–30% to +10%). If a value outside this range is given

with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of

the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is

executed during the soft-start period. Any transition in the reference voltage after soft-start is complete occurs at

the slew rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the

reference by 10%, occurs in approximately 900 µs.

COMMAND

Format

STEP_VREF_MARGIN_LOW

Linear, two's complement binary

Bit Position

Access

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

1

0

1

0

47

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The default value of STEP_VREF_MARGIN_LOW is –30 (dec), corresponding to a default margin low voltage of

–60 mV (–10%).

8.6.33 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)

The PCT_VOUT_FAULT_PG_LIMIT command is used to set the PGOOD, VOUT_UNDER_VOLTAGE (UV) and

VOUT_OVER_VOLTAGE (OV) limits as a percentage of nominal.

The PCT_VOUT_FAULT_PG_LIMIT takes a one byte data word formatted as shown below:

COMMAND

PCT_VOUT_FAULT_PG_LIMIT

Format

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

0

r/w

PCT_MSB

0

r/w

PCT_LSB

0

Function

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

The PGOOD, VOUT_UNDER_VOLTAGE (UV) and VOUT_OVER_VOLTAGE (OV) settings are shown in

Table 9, as a percentage of nominal reference voltage on the FB pin.

Table 9. Protection Settings (typical)

PCT_MSB

PCT_LSB

UV

PGL LOW

-12.5%

-7.0%

PGH HIGH

12.5%

7.0%

OV

0

1

0

1

0

1

-16.8%

-12.0%

-28.0%

-42.0%

16.8%

12.0%

-22.0%

-36.0%

7.0%

The PGOOD pin may trip if the output voltage is too high (using PGH high) or too low (using PGL low).

Additionally, the PGOOD pin has hysteresis.

Additionally, when output overvoltage (OV) is tripped, the output must lower below the PGH high threshold minus

the hysteresis, before PGOOD and OV are reset. Likewise, when output undervoltage (UV) is tripped, the output

must rise above the PGOOD high threshold plus the hysteresis, before PGOOD and UV are reset.

8.6.34 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)

The SEQUENCE_TON_TOFF_DELAY command is used to set the delay for turning on the device and turning

off the device as a ratio of TON_RISE.

The SEQUENCE_TON_TOFF_DELAY takes a one byte data word formatted as shown below:

COMMAND

SEQUENCE_TON_TOFF_DELAY

Format

Unsigned binary

Bit Position

Access

7

6

5

4

r

3

2

1

0

r

r/w

Function

TON_DELAY

0

X

0

TOFF_DELAY

0

X

0

Default Value

0

TON_DELAY:

This parameter selects the delay from when the output is enabled until soft-start beings, as an

integer multiple of the TON_RISE time. The default value is 0. Values can range from 0 to 7 in

increments of 1. When TON_DELAY = 0, the device imposes a minimum delay of 50 µs.

TOFF_DELAY:

This parameter selects the delay from when the output is disabled until the output stops switching,

as an integer multiple of the TON_RISE time. The default value is 0. Values can range from 0 to 7 in

increments of 1.

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8.6.35 OPTIONS (MFR_SPECIFIC_21) (E5h)

The OPTIONS register can be used for setting user selectable options, as shown below.

COMMAND

Format

OPTIONS

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

r

3

r

2

1

r

0

r

r/w

Function

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

1

X

1

X

1

X

0

EN_ADC_CNTL

1

X

0

X

0

Default Value

The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

A “1” in any of these bit positions indicates that:

EN_ADC_CNTL:

Enables ADC operation used for voltage, current and temperature monitoring.

NOTE

The EN_ADC_CNTL bit must be set in order to enable output voltage, current and

temperature telemetry. When the EN_ADC_CNTL bit is zero, the READ_VOUT,

READ_IOUT and READ_TEMPERATURE_2 registers do not update continuously, and

retain their previous values from the last time EN_ADC_CNTL was set.

8.6.36 MASK_SMBALERT (MFR_SPECIFIC_23) (E7h)

The MASK SMBALERT command may be used to prevent a warning or fault condition from asserting

SMBALERT.

COMMAND

MASK_SMBALERT (High Byte)

Format

Unsigned Binary

Bit Position

Access

7

r/w

6

r/w

5

4

r/w

3

r/w

2

r/w

1

r/w

0

r/w

mSMBTO

0

r/w

Auto_ARA

1

Function

mOTFI

0

mPRTCL

0

mIVC

0

mIVD

0

mPEC

0

mMEM

0

Default Value

COMMAND

MASK_SMBALERT (Low Byte)

Format

Unsigned binary

Bit Position

Access

7

6

5

r/w

4

r/w

3

r/w

2

r/w

1

0

r/w

mVIN_UV

0

Function

mOTF

mOTW

mOCF

0

mOCW

0

mOVF

0

mUVF

0

mPGOOD

0

Default Value

0

8.6.36.1 mOTFI

This bit controls whether an internal overtemperature fault (OTFI) asserts SMBALERT.

•

0: OTFI (STATUS_MFR_SPECIFIC[7]) asserts SMBALERT.

1: OTFI does not assert SMBALERT.

8.6.36.2 mPRTCL

This bit controls whether an SMBus Protocol Error causes SMBALERT to assert.

•

0: SMBus Protocol Errors assert SMBALERT.

1: SMBus Protocol Errors do not assert SMBALERT.

49

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8.6.36.3 mSMBTO

This bit controls whether an SMBus Timeout causes SMBALERT to assert.

•

0: SMBus Timeout asserts SMBALERT.

1: SMBus Timeout does not assert SMBALERT.

8.6.36.4 mIVC

This bit controls whether an invalid command (IVC) causes SMBALERT to assert.

•

0: Issuing an invalid command asserts SMBALERT.

1: Issuing an invalid command does not assert SMBALERT.

8.6.36.5 mIVD

This bit controls whether an invalid or unsupported data (IVD) causes SMBALERT to assert.

•

0: Issuing invalid or unsupported data asserts SMBALERT.

1: Issuing invalid or unsupported data does not assert SMBALERT.

8.6.36.6 mPEC

This bit controls whether an invalid packet error check (PEC) byte causes SMBALERT to assert.

•

0: Invalid PEC byte asserts SMBALERT.

1: Invalid PEC byte does not assert SMBALERT.

8.6.36.7 mMEM

This bit controls whether a memory error (MEM) causes SMBALERT to assert.

•

0: Memory error (MEM) asserts SMBALERT.

1: Memory error (MEM) does not assert SMBALERT.

8.6.36.8 Auto_ARA

This bit controls whether the Auto ARA Response is enabled.

•

0: Auto ARA is disabled. Host must take all action necessary to clear SMBALERT

1: Auto ARA is enabled. The device releases SMBALERT after successfully responding to an ARA from the

host.

8.6.36.9 mOTF

This bit controls whether an overtemperature fault (OTF) causes SMBALERT to assert.

•

0: Overtemperature fault (OTF) asserts SMBALERT.

1: Overtemperature fault does not assert SMBALERT.

8.6.36.10 mOTW

This bit controls whether an overtemperature warning (OTW) causes SMBALERT to assert.

•

0: Overtemperature warning (OTW) asserts SMBALERT.

1: Overtemperature warning (OTW) does not assert SMBALERT.

8.6.36.11 mOCF

This bit controls whether an overcurrent fault (OCF) causes SMBALERT to assert.

•

0: Overcurrent fault (OCF) asserts SMBALERT to assert.

1: Overcurrent fault (OCF) does not assert SMBALERT.

8.6.36.12 mOCW

This bit controls whether an overcurrent warning (OCW) causes SMBALERT to assert.

•

0: Overcurrent warning (OCW) asserts SMBALERT.

1: Overcurrent warning (OCW) does not assert SMBALERT.

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8.6.36.13 mOVF

This bit controls whether an output overvoltage (OVF) causes SMBALERT to assert.

•

0: Output overvoltage fault (OVF) causes SMBALERT to assert.

1: Mask SMBALERT assertion due to STATUS_VOUT[7].

8.6.36.14 mUVF

This bit controls whether an output undervoltage (UVF) causes SMBALERT to assert.

•

0: Output undervoltage fault (UVF) asserts SMBALERT.

1: Output undervoltage fault does not assert SMBALERT.

8.6.36.15 mPGOOD

This bit controls whether a PGOOD transition from high-to-low causes SMBALERT to assert.

•

0: PGOOD transition from high-to-low asserts SMBALERT.

1: PGOOD transition from high to low does not assert SMBALERT.

8.6.36.16 mVIN_UV

This bit controls whether an input undervoltage fault (VIN_UV) causes SMBALERT to assert.

•

0: Input undervoltage fault (VIN_UV) asserts SMBALERT.

1: Input undervoltage fault (VIN_UV) does not assert SMBALERT.

8.6.37 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)

The DEVICE_CODE command returns a two byte unsigned binary 12-bit device identifier code and 4-bit revision

code in the following format.

COMMAND

Format

MFR_SPECIFIC_44

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Identifier Code

Revision Code

Default Value

See Below.

This command provides similar information to the DEVICE_ID command but for devices that do not support block

read and write functions.

The fixed, read-only values for each device are summarized below:

DEVICE

IDENTIFIER CODE

REVISION CODE

REGISTER VALUE

0153h

TPS544C20

TPS544B20

015h

014h

3h

0143h

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9 Applications and Implementation

9.1 Application Information

The TPS544B20 and TPS544C20 devices are highly-integrated synchronous step-down DC-DC converters.

These devices are used to convert a higher DC input voltage to a lower DC output voltage, with a maximum

output current of 20 A and 30 A respectively.

9.2 Typical Application

Use the following design procedure to select key component values for this family of devices, and set the

appropriate behavioral options according to the PMBus protocol.

V_IN

R_VDD

C_I6

C_I7

V_OUTS+

V_OUTS-

C_I3

C_I4

C_I5

C_I1

C_I2

4.7 nF

0 Ω

22 mF

100 mF 100 mF

22 mF

C_VDD

1.0 mF

GND

U1

TPS544C20RVF

GND

C_B

0.1 mF

R_B

0 Q

V_OUTS+

10 Ω

R_Bias

4.99 kΩ

R1

10 kΩ

R_SP

7

8

33

34

35

L₁

BOOT

SW

DIFFO

FB

V_OUT

C2

410 nH

9

SW

COMP

MODE

CNTL

BP3

C_O1

C_O2

C_O4

22 mF

C_O3

22 mF

C_SB

C_O5

22 mF

10

11

12

8.2 nF

220 mF

39

1

1 nF

220 mF

SW

R_SB

SW

R_SN

10 Ω

3 Ω

27

3

SW

V_OUTS-

30

GND

ADDR0

BPEXT

SMBALERT

CLK

GND

6

5

2

SMBALERT

CLK

ADDR1

RT

R_T

38.3 kΩ

40

38

28

PMBus

Interface

C_B3

0.1 mF

4

R_A0

38.3 kΩ

R_A1

AGND

BP6

DATA

36

37

38.3 kΩ

PGOOD

TSNS

PGOOD

26

PGND

AGND

C_T

1 nF

Q_T

C_B6

4.7 mF

AGND

GND

Figure 32. TPS544C20 4.5-V to 18-V Input, 1.8-V Output, 30-A Converter

9.2.1 Design Requirements

For this design example, use the following input parameters.

Table 10. Design Example Specifications

PARAMETER

Input voltage

TEST CONDITION

MIN

TYP

MAX UNIT

V_I

4.5

12.0

18.0

0.4

V

V_I(ripple)

V_O

Input ripple voltage

Output voltage

I_OUT= 30 A

1.8

Line regulation

4.5 V ≤ V_I≤ 18 V

0 V ≤ I_O≤ 30 A

I_O= 30 A

0.5%

18

Load regulation

V_(PP)

Output ripple voltage

Transient response overshoot

mV

V_(OVER)

I_(STEP)= 10 A

36

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Typical Application (continued)

Table 10. Design Example Specifications (continued)

PARAMETER

Transient response undershoot

Output current

TEST CONDITION

I_(STEP)= 10 A

MIN

-36

0

TYP

MAX UNIT

V_(UNDER)

mV

I_O

5 V ≤ V_I≤ 18 V

20

2.7

30

A

ms

A

t_SS

I_OC

η

Soft-start time

V_I= 12 V

Overcurrent trip point

Efficiency

40

I_O= 20 A, V_I= 12 V

90%

500

f_SW

Switching frequency

kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Switching Frequency Selection

There is a trade-off between higher and lower switching frequencies. Higher switching frequencies may produce

smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply

that switches at a lower frequency. However, the higher switching frequency produce higher switch losses, which

decrease efficiency and impact thermal performance. In this design, a moderate switching frequency of 500 kHz

achieves both a balance between a small solution size and high-efficiency operation. With the frequency

selected, use Table 2 to select the timing resistor. For a frequency of 500 kHz R_RTis 38.2 kΩ.

9.2.2.2 Inductor Selection

To calculate the value of the output inductor, use Equation 12. The coefficient K_INDrepresents the amount of

peak-to-peak inductor ripple current relative to the maximum output current. The output capacitor filters the

inductor ripple current; therefore, choosing a high inductor ripple current impacts the selection of the output

capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor

ripple current. To achieve balanced performance, maintain a K_INDcoefficient between 0.3 and 0.4. Using this

target ripple current, the required inductor size can be calculated as shown in Equation 12.

6_/54

_{).(≠°∏ ꢀ}× ¶₃₇

6 F 6_/54

1ꢁ8 6 × (18 6 F 1ꢁ8 6ꢀ

).

,1 =

×

=

= ꢄꢅ0 Æꢃ

6

)

/54 ≠°∏

_;× +_).$18 6 × ꢂ00 ´ꢃ∫ × ꢄ0 ! × 0ꢁꢄ

:

(12)

Selecting K_IND= 0.3, the target inductance L₁= 360 nH. Using the next standard value, the 320 nH Pulse (brand)

PG077.321NL is chosen in this application for its high current rating, low DCR, and small size. The inductor

ripple current, RMS current, and peak current can be calculated using Equation 13, Equation 14 and

Equation 15. These values should be used to select an inductor with approximately the target inductance value,

and current ratings that allow normal operation with some margin.

6

_;F 6_/54

6_/54

1ꢁ8 6 × (18 6 F 1ꢁ8 6ꢀ

:

). ≠°∏

)

=

×

=

= 1ꢃꢁ1 !

2)00,%

6

_{).(≠°∏ ꢀ}× ¶₃₇

,1

18 6 × ꢂꢃꢃ ´ꢄ∫ × ꢅꢆꢃ Æꢄ

(13)

1

2

¨

:

;

:

;

)

=

)

+

)

=

3ꢂ !

+

1ꢂ. 1 ! = 3ꢂ.1ꢃ !

,(≤≠≥ ꢀ

ꢁ)00,%

/54 (≠°∏ ꢀ

12

(14)

(15)

1

)

= )_/54+ )_ꢀ)00,%= 3ꢁ ! + × 1ꢁ.1! = 3ꢂ.1 !

, ∞•°´

2

The Pulse PG077.321NL is rated for 45 A RMS current, and 48-A saturation. Using this inductor, the ripple

current I_RIPPLE= 10.1 A, the RMS inductor current I_L(rms)= 30.14 A, and peak inductor current I_L(peak)= 35 A.

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9.2.2.3 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

affects three criteria:

•

how the regulator responds to a load transition

the output voltage ripple

the minimum output capacitance needed to maintain stable D-CAP2 mode control

The output capacitance needs to be selected based on the most stringent of these three criteria.

9.2.2.3.1 Response to a Load Transition

The desired response to a load transition is the first criterion. The output capacitor must supply the load with the

required current when not immediately provided by the regulator. When the output capacitor supplies load

current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient.

These devices use Adaptive Constant On-Time (COT) control. During a transient, the ON-time remains

unchanged from normal operation, but the off-time shortens to allow a rapid increase in the inductor current in

order to meet the demands of the load transition. To estimate the time required to respond to a load increase,

calculate the number of switching cycles required to change the inductor current using Equation 16.

)

1ꢀ !

42!.

#

£π£¨•≥

N

=

= 1

)

1ꢀꢁ1 !

2)00,%

(16)

And estimate the time needed to produce that number of cycles during a transient as Equation 17:

#

6_/54

1

1ꢂ8 6

ꢃꢂꢁ 6

£π£¨•

4_42!.3

N

F1 +

G =

l1 +

p = 1ꢂꢃ J≥

ꢀ × ¶₃₇

6

ꢀ × ꢁ00 ´(∫

:

;

). ≠©Æ

(17)

The output capacitor must support the full change in output current for half of the time, so the minimum output

capacitance can be estimated by Equation 18:

)

× 4_42!.3

10 ! × 1ꢁꢂ ꢃ≥

ꢀ × ꢄꢅ ≠6

42!.

#

=

= 19ꢄ ꢃ&

µÆ§•≤≥®ØØ¥

ꢀ × 6_5Æ§•≤

(18)

The output capacitor must also absorb the full change in output current for half of the time needed to remove the

excess current from the inductor during a rapid load decrease. This minimum output capacitance can be

estimated using Equation 19:

ꢀ

:

)

;

:

;

× ,1

10 ! × 3ꢀ0 Æ(

42!.

#

=

= ꢃ9ꢃ J&

Ø∂•≤≥®ØØ¥

6_/54× 6_/6%2

1ꢁ8 6 × 3ꢂ ≠6

(19)

In order to meet the transient response requirements, the output capacitance must be greater than the larger of

C_undershootand C_overshoot

.

In this case, the highest minimum output capacitance (C_OUT(min)) to meet the response to a load transition is the

overshoot requirement, which dictates the minimum output capacitance. Therefore, using Equation 19, the

minimum output capacitance required to meet the transient requirement is 494 µF.

9.2.2.3.2 Output Voltage Ripple

The output voltage ripple is the second criterion. Equation 20 calculates the minimum output capacitance

required to meet the output voltage ripple specification. This criterion is the requirement when the impedance of

the output capacitance is dominated by ESR.

1

)

1ꢀ.1 !

2)00,%

#

=

×

=

= 1ꢂꢀ J&

≤©∞∞¨•

8 × ꢁꢀꢀ ´(∫ × 18 ≠6

:

;

(20)

In this case, the maximum output voltage ripple is 18 mV. Under this requirement, the minimum output

capacitance for ripple (as calculated in Equation 20) yields 140 μF. Because this capacitance value is smaller

than the output capacitance required to meet the transient response, select the output capacitance value based

on the transient requirement. For this application, two 220-µF, low-ESR polymer bulk capacitors, three 47-µF

capacitors and three 22-µF ceramic capacitors are selected to meet the transient specification with at least 80%

margin. Therefore C_OUTequals 647 µF.

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With the target output capacitance value chosen, Equation 21 calculates the maximum ESR the output capacitor

bank can have to meet the output voltage ripple specification. Equation 21 indicates the ESR should be less than

1.4 mΩ. The six ceramic capacitors each contribute approximately 2 mΩ, making the effective ESR of the output

capacitor bank approximately 0.33 mΩ, meeting the specification with sufficient margin.

)

37

1ꢂ.1 !

2)00,%

ꢁ × ¶ × #_/54

6_{/54 ≤©∞∞¨•}

ꢀ

1ꢁ ≠6 ꢀ

ꢁ × ꢃꢂꢂ ´(∫ × ꢄꢅꢆ J&

%32_-!8

=

= 1.ꢅ ≠3

)

1ꢂ.1 !

2)00,%

(21)

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases the

minimum required capacitance value. Capacitors generally have limits to the amount of ripple current they can

handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current

must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple

current. Equation 22 can be used to calculate the RMS ripple current the output capacitor needs to support. For

this application, Equation 22 yields 2.28 A.

6_/54× k6

_;F 6_/54o

:

;

1ꢁ8 6 × 18 6 F 1ꢁ8 6

12 × 18 6 × ꢂ20 Æꢃ × ꢄ00 ´ꢃ∫

¾

:

). ≠°∏

)

=

= 2ꢁ92 !

#/(≤≠≥ ꢀ

12 × 6

_;× ,1 × ¶₃₇

¾

:

). ≠°∏

(22)

9.2.2.4 D-CAP Mode and D-CAP2 Mode Stability

D-CAP mode control requires that the ESR ripple at the FB pin be at least 15 mV (or 2.5%) of the output voltage

and the ESR-zero frequency of the output capacitor is less than 1/4 the switching frequency. Because this design

requires output voltage ripple less than 2.5% of the output voltage and uses low-ESR, specialty polymer, and

ceramic output capacitors, this design uses D-CAP2 mode control. Because D-CAP2 mode control uses an

internally generated ramp to emulate the ESR of the output capacitor, D-CAP2 mode requires sufficient output

capacitance to maintain an effective ESR-zero frequency less than 1/4 of the nominal switching frequency with

this emulated ESR. The minimum capacitance for stability can be calculated in Equation 23 using τ_Iemfrom

Table 11:

2 × 6_≤•¶× R_)•≠

2 × ꢀ00 ≠6 × ꢁꢀ µ≥

#

=

= 100 J&

≥¥°¢©¨©¥π

N × 6_/54× ,1 × ¶₃₇ꢂ.1ꢃ × 1.8 6 × ꢂ20 Æ( × ꢄ00 ´(∫

(23)

Table 11. D-CAP2 Mode Current Emulation Time

Constants

NOMINAL FREQUENCY (kHz)

τ_Iem(µs)

104

98

250

300

400

500

650

750

850

1000

87

76

60

52

44

33

9.2.2.5 Input Capacitor Selection

The TPS544B20 and TPS544C20 devices require a capacitor with these features:

•

high-quality

ceramic

type X5R or X7R

input decoupling feature

a value of 0.1 μF to 1.0 μF of effective capacitance on the VDD pin, relative to GND

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The power stage input decoupling capacitance (effective capacitance at the VIN and GND pins) must be

sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while

providing minimal input voltage ripple as a result. This effective capacitance includes any DC bias effects. The

voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also

have a ripple current rating greater than the maximum input current ripple to the device during full load. The input

ripple current can be calculated using Equation 24.

:

;

6_/54

k

6

_;F 6_/54o

1ꢁ8 6

ꢂꢁꢃ 6

ꢂꢁꢃ 6 F 1ꢁ8 6

:

). ≠©Æ

¨

)

= )

;

×

/54 (≠°∏ ꢀ

×

= 30 ! ×

×

= 1ꢂꢁ7 !≤≠≥

:

#). ≤≠≥

6

ꢂꢁꢃ 6

:

;

:

;

). ≠©Æ

(24)

The minimum input capacitance and ESR values for a given input voltage ripple specification, V_IN(ripple), are

shown in Equation 25 and Equation 26. The input ripple is composed of a capacitive portion, V_RIPPLE(cap), and a

resistive portion, V_RIPPLE(esr)

.

)

_{/54 (≠°∏ ꢀ}× 6_/54

ꢁ0 ! × 1ꢂ8 6

#

=

;

=

= ꢅ0 J&

:

). ≠©Æ

6

_;× 6

_;× ¶₃₇100 ≠6 × 18 6 × ꢃ00 ´ꢄ∫

:

). ≠°∏

:

≤©∞∞¨• £°∞

(25)

(26)

6_2)00,%

ꢁꢂ1 6

%32

%32_{#). ≠°∏}

=

= ꢀꢂ8 ≠3

1

ꢀ

1

)

+ )_2)00,%

ꢃꢁ ! + × 1ꢁꢂ1 !

ꢀ

/54 ≠°∏

The value of a ceramic capacitor varies significantly with temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectric capacitors are usually selected for power regulator

capacitors because they have a high capacitance-to-volume ratio and are fairly stable during temperature

changes. The input capacitor must also be selected with the DC bias taken into account. To support the

maximum input voltage, this design requires a ceramic capacitor with a rating of at least 25 V. Allow 0.1-V input

ripple for V_RIPPLE(cap), and 0.3-V input ripple for V_RIPPLE(esr). Using Equation 25 and Equation 26, the minimum

input capacitance for this design is 60 µF, and the maximum ESR is 2.8 mΩ. Four 22-μF, 25-V ceramic

capacitors and two additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the power

stage. For the VDD pin, one 1.0-μF, 25-V ceramic capacitor was selected. The input voltage (VIN) and power

input voltage (PVIN) pins must be tied together. The input capacitance value determines the input ripple voltage

of the regulator. Using the design example values, I_OUT(max)= 30 A, C_IN= 288 μF, f_SW= 500 kHz, yields a

maximum RMS input ripple current of 14.7 Arms.

9.2.2.6 Bootstrap Capacitor and Resistor Selection

A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper

operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor

should have voltage rating of 25 V or higher. To reduce the dV/dt of the rising edge of the SW node, reduce

ringing and EMI, a resistor R_BOOTup to 5 Ω can be placed in series with the bootstrap capacitor.

9.2.2.7 BP6, BP3 and BPEXT

This design does not include an auxiliary 5-V supply, so BPEXT is terminated to GND. According to the

recommendations in , BP3 is bypassed to AGND with 100 nF of capacitance, and BP6 is bypassed to GND with

4.7-µF of capacitance. In order for the regulator to function properly, it is important that these capacitors be

located close to the TPS544C20, with low-impedance return paths to AGND or GND as appropriate. See

Figure 45 for more information.

9.2.2.8 R-C Snubber and VIN Pin High-Frequency Bypass

Although it is possible to operate the TPS544C20 within absolute maximum ratings without including any ringing

reduction techniques, some designs may require external components to further reduce ringing levels. This

example uses two approaches:

•

a high frequency power stage bypass capacitor on the VIN pins

an R-C snubber between the SW and GND

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Including a high-frequency bypass capacitor is a lossless ringing reduction technique which helps minimizes the

outboard parasitic inductances in the power stage. These capacitors store energy during the low-side MOSFET

on-time, and discharge once the high-side MOSFET is turned on. For this example a 4.7-nF, 25-V, 0402 sized

high-frequency capacitor is selected. The placement of this capacitor (shown in Figure 46) is critical to its

effectiveness.

Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF

capacitor and a 3-Ω resistor are chosen. In this example an 0805 resistor is chosen, which is rated for 0.125 W,

nearly twice the estimated power dissipation. Figure 33 and Figure 34 show the effect of the R-C snubber on the

rising edge of the SW pin. See SLUP100 for more information about snubber circuits.

V_IN

SW

V_IN= 12 V

I_OUT= 20 A

Snubber = Open

V_IN= 12 V

I_OUT= 20 A

Snubber = 1nF + 3Ω

Figure 34. SW Rising Edge

Figure 33. SW Rising Edge

9.2.2.9 Temperature Sensor

This application design uses a surface-mount MMBT3904SL for the temperature sensor, Q_T. In this example, the

sensor monitors the PCB temperature where it is generally the highest, next to the power inductor. Placement of

the temperature sensor and routing back to the TSNS pin are critical design features to reduce noise its

temperature measurements. In this example, the temperature sensor is placed on the V_OUTside of the power

inductor to avoid switching noise from the SW plane, and routed back to the TSNS and AGND pin. Additionally, a

330-pF capacitor, C_T, is placed from TSNS to AGND near the TSNS pin.

Disable external temperature sensing by terminating TSNS to AGND with a 0-Ω resistor. This termination forces

the temperature readings to –40 °C, and prevents external over-temperature fault trips.

9.2.2.10 Key PMBus Parameter Selection

Several of the key design parameters for the TPS544B20 and TPS544C20 device can be configured according

to the PMBus protocol, and stored to its non-volatile memory (NVM) for future use.

9.2.2.10.1 Enable, UVLO and Sequencing

Use the ON_OFF_CONFIG (02h) command to select the turn-on behavior of the converter. For this example, the

CNTL pin was used to enable or disable the converter, regardless of the state of OPERATION (01h), as long as

input voltage is present, and above the UVLO threshold.

The minimum input voltage, V_IN(min), for this example is 4.5 V. The VIN_ON command was set to 4.25 V, and the

VIN_OFF command was set to 4.0 V, giving 250 mV of hysteresis. If VIN falls below VIN_OFF, power conversion

stops, until it is raised above VIN_ON.

This example lacks specific turn-on or turn-off delay requirements, so SEQUENCE_TON_TOFF_DELAY was

used to set both the turn-on and turn-off delays to 0 × the soft-start time, the delay between enabling power

conversion, and the rise of the output voltage is approximately 400 µs. See the Soft-Start section for more

information.

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9.2.2.10.2 Soft-Start Time

The TON_RISE command sets the soft-start time. When selecting the soft-start time, consider the charging

current for the output capacitors. In some applications (for example those with large amounts of output

capacitance) this current can lead to problems with nuisance tripping of the overcurrent protection circuitry. To

avoid nuisance tripping, the output capacitor charging current should be included when choosing a soft-start

time, and overcurrent threshold. The capacitor charging current can be calculated using Equation 27.

6_/54× #_/541.8 6 × ꢀꢁ7 J&

)

#!0

=

= ꢁꢂ2 ≠!

¥

2.7 ≠≥

33

(27)

After calculating the charging current, the overcurrent threshold can then be calibrated to the sum of the

maximum load current and the output capacitor charging current plus some margin.

In this example, the soft-start time is arbitrarily selected to be the default value, 2.7 ms. In this case, the charging

current, I_CAP= 337 mA.

9.2.2.10.3 Overcurrent Threshold and Response

The IOUT_OC_FAULT_LIMIT command sets the overcurrent threshold. The current limit should be set to the

maximum load current, plus the output capacitor charging current during start-up, plus some margin for load

transitions and component variation. The amount of margin required depends on the individual application, but a

suggested starting point is 30%. More or less may be required. For this application, the maximum load current is

30 A, the output capacitor charging current is 337 mA. This design uses the factory default overcurrent threshold

of 39 A.

The IOUT_OC_FAULT_RESPONSE command sets the desired response to an overcurrent event. In this

example, the converter is configured to latch-off in the event of an overcurrent. TPS544C20 device can also be

configured to hiccup, (continuously restart waiting for a 7 x soft-start time-out between re-trials. )

9.2.2.10.4 Power Good, Output Overvoltage and Undervoltage Protection

The PCT_VOUT_FAULT_PG_LIMIT command configures the PGOOD, and regulation windows. This example

includes a moderate threshold setting. The resulting power good window is ±12.5%, and the resulting

overvoltage and undervoltage window is ±16.8%. More or less aggressive protection levels can be selected

according to the PMBus protocol.

58

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

9.2.2.11 Output Voltage Setting and Frequency Compensation Selection

A feedback divider from DIFFO to AGND sets the output voltage. This design arbitrarily selects an R1 value of

20 kΩ. Using R1 and the desired output voltage, and calculate R_BIASusing Equation 28 to be 10 kΩ.

6_&"

0.ꢀ 6

2_"©°≥

=

× 21 =

× ꢁ0 ´3 = 10 ´3

6_/54- 6_&"

1.8 6 - 0.ꢀ 6

(28)

The TPS544B20 and TPS544C20 devices use D-CAP2 mode control with a transconductance error amplifier to

eliminate the output voltage error introduced by valley voltage regulation. To stabilize the error amplifer, TI

recommends a 10-nF capacitor from COMP to AGND. To improve transient response and increase phase

margin, a series resistor, R_COMP, can be added. When using R_COMP, add a 1.0-nF capacitor from COMP to AGND

to limit the error amplifier gain at high frequency. Use Equation 29 to calculate the value of R_COMP

.

6_/54× ,1

#

1.8 6 × 3ꢀꢁ Æ( ꢂꢃ7 J&

× = ꢀ.ꢃꢄ ´3

/54

2_#/-0= 3 ×

×

= 3 ×

6_≤•¶× R_)•≠

#

ꢁ.ꢂꢁꢁ 6 × 7ꢂ J≥ 1ꢁ Æ&

#/-0

(29)

Alternatively, for output voltages 1.2 V and higher, a feedforward capacitor, C1, can be added in parallel with R1

from DIFFO to FB to provide similar improvement to transient response and phase margin. Use Equation 30 to

calculate the value of C1.

6_/54× ,1

#

1.8 6 × 3ꢀ0 Æ( ꢁꢂ7 J&

× = ꢂ09 ∞&

/54

#₁=

×

=

6_≤•¶× R_)•≠

21

0.ꢁ00 6 × 7ꢁ J≥ ꢀ0 ´3

(30)

The resulting design example frequency compensation values are:

•

R1 = 20 kΩ

R_BIAS= 10 kΩ

C1 = 420 pF

59

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

9.2.3 Application Curves

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

Output Voltage

0.6 V

1.0 V

1.8 V

3.3 V

0.8 V

1.2 V

2.5 V

0.6 V

1.0 V

1.8 V

3.3 V

0.8 V

1.2 V

2.5 V

0

5

10

15

Load Current (A)

20

25

30

0

5

10

15

Load Current (A)

20

25

30

C003

V_IN= 5 V

L = 410 nH

f_SW= 500 kHz

T_A= 25 °C

V_IN= 12 V

f_SW= 500 kHz

T_A= 25 °C

Snubber = Open

R_BOOT= 0 Ω

L = 410 nH

Snubber = Open

R_BOOT= 0 Ω

R_DCR= 0.3 mΩ

Figure 35. Power Efficiency vs. Load Current

Figure 36. Power Efficiency, V_IN= 12 V

1.818

1.812

1.806

1.800

1.794

1.788

1.782

Input Voltage

5V

8 V

12 V

18 V

15 V

0

5

10

15

20

25

30

Load Current (A)

C005

V_IN= 12 V

I_OUT= 20 A

V_IN= 12 V

Figure 38. Startup from CNTL

Figure 37. Load Regulation

V_IN= 12 V

I_OUT= 20 A

V_IN= 12 V

I_OUT= 20 A

t_RISE= 2.0 µs

Figure 39. Shutdown from CNTL

Figure 40. Load Transition 10-A to 20-A

60

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

V_IN= 12 V

I_OUT= 20 A

t_FALL= 2.0 µs

V_IN= 12 V

I_OUT= 20 A

Figure 41. Load Transition 20-A to 10-A

Figure 42. DC Ripple

Natural Convection

V_IN= 12 V

I_OUT= 20 A

f_SW= 500 kHz

V_IN= 12 V

I_OUT= 0 A

V_PRE-BIAS= 900 mV

Figure 44. Thermal Image

Figure 43. 50% Pre-Biased Start-Up

10 Power Supply Recommendations

These devices operate from an input voltage supply between 4.5 V and 18 V. These devices are not designed

for split-rail operation. The VIN and VDD pins must be the same voltage for accurate high-side short circuit

protection. Proper bypassing of input supplies and internal regulators is also critical for noise performance, as is

PCB layout and grounding scheme. See the recommendations in the Layout section.

61

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following layout recommendations will help guide

you through a good layout of the TPS544B20 and TPS544C20 Devices. Figure 45 shows the recommended

PCB layout configuration for additional reference.

•

As with any switching regulator, there are several signal paths that conduct fast switching voltages or

currents. Minimize the loop area formed by these paths and their bypass connections.

•

Bypass the VIN pins to GND with a low-impedance path. Power-stage input bypass capacitors should be as

close as physically possible to the VIN and GND pins. Additionally, a high-frequency bypass capacitor on the

VIN pins can help to reduce switching spikes. See Figure 46 for placement recommendation.

•

The AGNDSNS pin must be kelvin connected to the AGND pin, with a low-noise, low-impedance path to

ensure accurate current monitoring. This connection must be made on an internal or bottom layer. It should

not segment the thermal tab copper area. This connection serves as the only connection between AGND and

GND for this device.

Signal components should be terminated or bypassed to a separate analog ground (AGND) copper area,

which is isolated from fast switching voltage and current paths. This copper area should not be connected to

the thermal tab, or to an internal ground plane, and should be reserved for this regulator only.

•

Minimize the SW copper area for best noise performance. Route sensitive traces away from SW and BOOT,

as these nets contain fast switching voltages, and lend easily to capacitive coupling.

Snubber component placement is critical to its effectiveness of ringing reduction. These components should

be on the same layer as the devices, and be kept as close as possible to the SW and GND copper areas.

Keep signal components and regulator bypass capacitors local to the device, and place them as close as

possible to the pins to which they are connected. These components include the feedback resistors,

frequency compensation, the R_RTresistor, ADDR0 and ADDR1 resistors, as well as bypass capacitors for

BP3, BP6, VDD, and optionally BPEXT.

•

The VIN and VDD pins must be the same voltage for accurate short circuit protection, but high frequency

switching noise on the VDD pin can degrade performance. VDD should be connected to VIN through a trace

from the input copper area. To avoid high frequency noise on VDD, TI recommends keeping the VDD to VIN

connection as short as possible to keep the parasitic inductance low. Optionally form a small low-pass R-C

between VIN and VDD, with the VDD bypass capacitor (0.1 µF to 1.0 µF) and a 0-Ω to 2-Ω resistor between

VIN and VDD. See Figure 45.

The VDD bypass capacitor can conduct high frequency switching currents. Thus in practice, TI recommends

grounding the VDD bypass capacitor to GND or AGNDSNS rather than AGND. If AGNDSNS is used, to avoid

injecting noise into the regulation path, it is important to route the ground return of the bypass capacitor to

AGNDSNS through a dedicated trace to avoid sharing a path to AGND between the VDD capacitor and the

FB to AGND (R_bias) resistor and COMP to AGND (C_comp) capacitor.

•

The TPS544B20 and TPS544C20 devices have several pins which require good local bypassing. Place

bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground. Poor

bypassing on VDD, BP3 and BP6 can degrade the performance of the regulator.

Route the VOUTS+ and VOUTS– lines from the output capacitor bank at the load back to the device pins as

a tightly coupled differential pair. It is critical that these traces be kept away from switching or noisy areas

which can add differential-mode noise.

Routing of the temperature sensor traces is critical to the noise performance of temperature monitoring. Keep

these traces away from switching areas or high current paths on the layout. It is also recommended to use a

small 1-nF capacitor from TSNS to AGND to improve the noise performance of temperature readings.

62

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

11.2 Layout Example

(Not to scale)

GND

AGND

C

AGND

VIN

C

R

C

DIFFO

FB

GND

C

GND

COMP

PGOOD

TSNS

AGND

MODE

RT

C

R

C

R

Thermal Tab

C

GND

R

GND

AGNDS

NS

C

R

C

Route to VOUTS+

and VOUTS- as a

differential pair

SW

R

C

AGND is not connected to the

thermal tab or internal ground

plane. Kelvin connect to

R

VOUT

AGNDSNS on another layer

L

PMBus

Communication

QT

Minimize SW area. Keep

sensitive traces away from SW

and BOOT

Bottom-side

component

Figure 45. PCB Layout Recommendation

Vias connect

multiple VIN layers

TPS544B20/C20

No GND plane under SW node

2.2 nF to 4.7 nF 0402 VIN to

GND capacitor(s)

Multiple vias connect to

wide ground plane(s)

underneath VIN pins

Figure 46. High-Frequency Bypass Capacitor Placement

63

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

Layout Example (continued)

11.2.1 Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the

reflow process can affect electrical performance. Figure 47 shows the recommended reflow oven thermal profile.

Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.

t_P

T_P

T_L

T_S(max)

T_S(min)

t_L

r_RAMP(up)

r_RAMP(down)

t_S

t_25P

Time (s)

25

Figure 47. Recommended Reflow Oven Thermal Profile

Table 12. Recommended Thermal Profile Parameters

PARAMETER

MIN

TYP

MAX

UNIT

RAMP UP AND RAMP DOWN

r_RAMP(up)

Average ramp-up rate, T_S(max)to T_P

Average ramp-down rate, T_Pto T_S(max)

3

6

°C/s

r_RAMP(down)

PRE-HEAT

T_S

Pre-Heat temperature

150

60

200

180

°C

s

t_S

Pre-heat time, T_S(min)to T_S(max)

REFLOW

T_L

T_P

t_L

Liquidus temperature

217

°C

s

Peak temperature

260

150

40

Time maintained above liquidus temperature, T_L

Time maintained within 5 °C of peak temperature, T_P

Total time from 25 °C to peak temperature, T_P

60

20

t_P

s

t_25P

480

s

64

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 德州仪器 (TI) Fusion Digital Power™设计人员

TPS544B20 和 TPS544C20 器件由德州仪器 (TI) 数字电源设计工具 (Digital Power Designer) 完全支持。Fusion

Digital Power Designer 是一款图形用户界面 (GUI)，此界面可根据 PMBus 接口协议，经由德州仪器 (TI) USB 到

通用输入输出接口 (GPIO) 适配器来配置和监视 TPS544B20 和 TPS544C20 器件。

单击此链接下载德州仪器 (TI) Fusion Digital Power Designer 软件包。

图 48. 使用 Fusion Digital Power Designer 进行器件监控

65

TPS544B20, TPS544C20

ZHCSCI5B –MAY 2014–REVISED JULY 2016

www.ti.com.cn

图 49. 使用 Fusion Digital Power Designer 进行器件配置

12.1.2 器件命名规则

总线占用在共用通信总线上的长时间器件运行防止此共用总线上其他器件的正常通信时出现。

12.2 相关链接

下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的

快速链接。

表 13. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

TPS544B20

TPS544C20

12.3 商标

SWIFT, NexFET, D-CAP, D-CAP2, Fusion Digital Power, E2E are trademarks of Texas Instruments.

PMBus is a trademark of SMIF, Inc..

All other trademarks are the property of their respective owners.

66

TPS544B20, TPS544C20

www.ti.com.cn

ZHCSCI5B –MAY 2014–REVISED JULY 2016

12.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且

不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

67

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Sep-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS544B20RVFR

TPS544B20RVFT

TPS544C20RVFR

TPS544C20RVFT

LQFN-

CLIP

RVF

40

2500

250

330.0

180.0

330.0

180.0

16.4

5.35

7.35

1.7

8.0

16.0

Q1

LQFN-

CLIP

LQFN-

CLIP

2500

250

LQFN-

CLIP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Sep-2017

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS544B20RVFR

TPS544B20RVFT

TPS544C20RVFR

TPS544C20RVFT

LQFN-CLIP

RVF

40

2500

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

38.0

35.0

38.0

35.0

2500

250

Pack Materials-Page 2

PACKAGE OUTLINE

RVF0040A

LQFN-CLIP - 1.52 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

A

B

PIN 1 INDEX AREA

7.1

6.9

C

1.52

1.32

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.3 0.1

EXPOSED

THERMAL PAD

36X 0.5

13

20

12

21

41

SYMM

2X

5.3 0.1

5.5

32

1

0.3

40X

0.2

40

33

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

40X

4222989/B 10/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220.

www.ti.com

EXAMPLE BOARD LAYOUT

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.3)

6X (1.4)

40

33

40X (0.6)

1

32

40X (0.25)

2X

(1.12)

36X (0.5)

6X

(1.28)

(6.8)

(5.3)

41

SYMM

(R0.05) TYP

(

0.2) TYP

VIA

12

21

13

20

SYMM

(4.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222989/B 10/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.815) TYP

40

33

40X (0.6)

1

41

32

40X (0.25)

(1.28)

TYP

36X (0.5)

(0.64)

TYP

SYMM

(6.8)

(R0.05) TYP

8X

(1.08)

12

21

METAL

TYP

20

13

8X (1.43)

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

71% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4222989/B 10/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

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型号：	TPS544B20RVFT
厂家：	TEXAS INSTRUMENTS
描述：	具有 PMBus 编程功能和监控的 4.5V 至 18V、20A 同步 SWIFT™ 降压转换器 \| RVF \| 40 \| -40 to 125 监控开关输出元件转换器
文件：	总76页 (文件大小：3393K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS544B20RVFT [TI]

相关型号：

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TPS544B25RVFT

TPS544C20

TPS544C20RVFR

TPS544C20RVFT

TPS544C25

TPS544C25RVFR

TPS544C25RVFT

TPS544C26

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