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TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

TPS544x25 4.5V 至 18V、20A 和 30A SWIFT™

同步降压控制器（具有 PMBus™和频率同步功能）

1 特性

3 说明

1

•

符合 PMBus 1.2 标准的转换器：20A 和 30A

TPS544x25 器件是采用 5mm × 7mm 封装且符合

PMBus 1.2 规范的非隔离式直流/直流转换器，具有集

成的 FET，能够在高频下运行并输出 20A 或 30A 的电

流。集成式 NexFET™功率级和经优化的驱动器提供的

高频、低损耗开关支持密度极高的电源解决方案。

PMBus 接口通过 VOUT_COMMAND 支持 AVS 功

能，同时支持灵活的转换器配置以及关键参数（包括输

出电压、电流和可选的外部温度）监控功能。对故障状

况的响应可设置为重新启动、锁存或忽略，具体取决于

系统要求。

输入电压范围：4.5V 至 18V

输出电压范围：0.5V 至 5.5V

5mm × 7mm LQFN 封装

单个散热焊盘

集成 5.5mΩ 和 2.0mΩ 堆叠 NexFET™功率级

用于通过 PMBus 进行自适应电压调节 (AVS) 和裕

量调节的 500mV 至 1500mV 基准

•

电压不低于 600mV 时的精度为 0.5%

无损低侧金属氧化物半导体场效应晶体管

(MOSFET) 电流感测

器件信息

•

具有输入前馈功能的电压模式控制

差分远程感应

器件名称

封装

封装尺寸

TPS544B25RVFT

TPS544C25RVFT

LQFN (40)

5.00mm x 7.00mm

单启动至预偏置输出

输出电压和输出电流报告

使用 2N3904 时的外部温度监视晶体管

可通过 PMBus 接口进行编程

.

–

VOUT_COMMAND 和 AVS VOUT 转换率

具有热补偿功能的过流保护

UVLO、软启动和软停止

PGOOD、OV、UV、OT 电平

故障响应

效率

100

95

90

85

80

75

70

65

60

接通和关闭延迟

•

热关断

引脚配置适用的开关频率：200kHz 至 1MHz

与外部时钟频率同步

封装兼容 20A、30A 转换器

V

= 0.5

= 1.0

= 1.5

= 2.5

= 3.3

OUT

2 应用范围

•

测试和测量仪器

以太网交换机、光交换机、路由器、基站

服务器

0

4

8

12

16

20

24

28

32

Load Current (A)

No Snubber

企业级存储固态硬盘 (SSD)

高密度电源解决方案

V

= 12 V

L = 470 nH

= 0 Ω

IN

f

= 500 kHz

R

= 0.3mΩ

R

BOOT

SW

DCR

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSC81

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

8.5 Supported PMBus Commands ............................... 36

8.6 Register Maps......................................................... 39

Applications and Implementation ...................... 77

9.1 Application Information............................................ 77

9.2 Typical Applications ................................................ 77

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 12

Detailed Description ............................................ 18

8.1 Overview ................................................................. 18

8.2 Functional Block Diagram ....................................... 18

8.3 Feature Description................................................. 19

8.4 Device Functional Modes........................................ 36

9

10 Power Supply Recommendations ..................... 86

11 Layout................................................................... 87

11.1 Layout Guidelines ................................................. 87

11.2 Layout Example .................................................... 88

12 器件和文档支持 ..................................................... 90

12.1 器件支持 ............................................................... 90

12.2 相关链接................................................................ 91

12.3 社区资源................................................................ 91

12.4 商标....................................................................... 91

12.5 静电放电警告......................................................... 92

12.6 Glossary................................................................ 92

13 机械、封装和可订购信息....................................... 92

8

4 修订历史记录

日期

修订版本

注意

2015 年 5 月

*

初始发行版。

2

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

5 Device Comparison Table

DEVICE NAME

CURRENT OPTION (A)

TPS544B25RVFR

TPS544B25RVFT

TPS544C25RVFR

TPS544C25RVFT

20

30

6 Pin Configuration and Functions

RVF Package

40-Pin LQFN

(Top View)

40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

CNTL

ADDR1

ADDR0

DATA

1

2

3

4

5

6

7

8

9

VOUTSt

VOUTS+

VSET

VDD

CLK

BP6

BP3

SMBALERT

BOOT

PGND

25

24

23

SW

VIN

SW 10

SW

22

21

11

SW 12

VIN

Thermal Tab

13 14 15 16 17 18 19 20

Pin Functions

NAME

ADDR0

ADDR1

AGND

NO.

3

DESCRIPTION

Sets low-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.

Sets high-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.

Analog ground return for controller device. Connect to GND at the thermal tab.

2

38

Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a

minimum of 2.2 µF to AGND. BP3 is not designed to power external circuit.

BP3

27

Output of the 6.5-V on-board regulator. This regulator powers the driver stage of the controller and should

be bypassed with a minimum of 2.2 µF to GND. TI recommends using an additional 100-nF typical bypass

capacitor for reduce ripple on BP6.

BP6

28

Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the

SW pin.

BOOT

CLK

7

5

1

PMBus CLK pin. See Supported PMBus Commands section.

PMBus CNTL pin. See Supported PMBus Commands section. The CNTL pin has an internal pull-up and

floats high when left floating.

CNTL

3

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Pin Functions (continued)

NAME

COMP

DATA

DIFFO

FB

NO.

35

4

DESCRIPTION

Output of the error amplifier. Connect compensator network from this pin to the FB pin.

PMBus DATA pin. See Supported PMBus Commands section.

Output of the differential remote sense amplifier.

33

34

13

14

15

16

17

18

19

20

26

Feedback pin for the control loop. Negative input of the error amplifier.

GND

Power stage ground return.

PGND

Power ground return for controller device. Connect to GND at the thermal tab.

Power good output. Open drain output that floats up when the device is operating and in regulation. Any

fault condition causes this pin to pull low. Please refer to Table 6 for the possible sources to pull down

PGOOD pin.

PGOOD

36

Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency.

Do not leave this pin floating.

RT

40

SMBALERT

6

8

SMBus alert pin. See SMBus specification.

9

Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this

group of pins.

SW

10

11

12

For switching frequency synchronization or output voltage reset. The SYNC function allows synchronizing

the oscillator to an external source that is either slower of faster than the nominal free running oscillator

frequency. To use the SYNC function, VSET pin should be pulled up to BP3 or set the FORCE_SYNC bit

in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) if VSET function is used; if

synchronization is not required, pull the SYNC pin to BP3. If the VSET pin is connected to AGND through a

valid resistor to configure default output voltage, SYNC/RESET_B is configured as RESET_B function

when FORCE_SYNC is not set. Then the logic low on the SYNC/RESET_B pin restores the output voltage

to default value set by VSET without power cycling. When SYNC/RESET_B is configured as RESET_B

function, there is an internal 200kΩ pull-up resistor to BP3.

SYNC/RESET_B

39

External temperature sense signal input or alternatively used to set default soft-start time by connecting a

resistor from this pin to AGND. Do not leave this pin floating. Disable TSNS by pulling TSNS to AGND and

unsetting SS_DET_DIS in OPTIONS (MFR_SPECIFIC_21) (E5h) in applications where neither is needed.

TSNS/SS

VDD

37

29

Input power to the controller. Connect a low impedance bypass with a minimum of 1 µF to AGND. The

VDD voltage is also used for input feed-forward. VIN and VDD must be the same potential for accurate

short circuit protection.

21

22

23

24

25

VIN

Input power to the power stage. Low impedance bypassing of these pins to GND is critical.

Load voltage sensing, positive side. This sensing provides remote sensing for the PMBus interface

reporting and the voltage control loop.

VOUTS+

VOUTS–

31

32

Load voltage sensing, negative or common side. This sensing provides remote sensing for the PMBus

interface reporting and the voltage control loop.

Optionally configures default output voltage setting by connecting a resistor from this pin to AGND. See Set

Default Output Voltage by VSET for details. If VSET is not used, pull this pin up to BP3. Do not leave this

pin floating.

VSET

30

Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper

operation.

Thermal tab

4

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

–5

MAX

18

19

25

37

7

UNIT

VIN, VDD

VIN, VDD <2 ms transient

VIN – SW (VIN to SW differential)

VIN – SW (VIN to SW differential, <10 ns transient due to SW ringing)

BOOT

–0.3

–1

Input voltage range

V

BOOT – SW (BOOT to SW differential)

BOOT – SW (BOOT to SW differential, <10 ns transient)

7.5

5.5

3.6

7

CLK, DATA

VSET, ADDR0, ADDR1, TSNS/SS

FB, SYNC/RESET_B, CNTL, VOUTS–, VOUTS+, RT

SW

25

7

SW <100 ns transient

BP6, COMP, DIFFO, PGOOD

SMBALERT

–5

Output voltage range

–0.3

–40

–55

V

5.5

3.6

150

BP3

Operating junction temperature range, T_J

Storage temperature range, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

TYP

12

MAX

18

UNIT

V

V_DD

V_IN

T_J

Controller input voltage

Power stage input voltage

Junction temperature

4.5

12

18

V

–40

125

°C

5

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

7.4 Thermal Information

TPS544x25

PQFN (RVF)

40 PINS

27.4

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.3

4.2

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.4

ψ_JB

4.2

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

7.5 Electrical Characteristics

T_J= –40°C to 125°C, V_VIN= V_VDD= 12 V, R_RT= 40.2 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

V_VDD

V_VIN

Input supply voltage range

Power stage voltage range

Input operating current

4.5

18

12

V

I_VDD

Not switching

9.5

4.5

mA

UVLO

Factory default setting

V

VIN_ON

Input turn on voltage

Input turn off voltage

Programmable range, 15 different settings

Accuracy

4.25

–5%

7.75

5%

Factory default setting

4

VIN_OFF

Programmable range, 15 different settings

Accuracy

4

7.5

5%

–5%

ERROR AMPLIFIER AND FEEDBACK VOLTAGE

Default setting

Setpoint range⁽¹⁾

940.5

0.5

950

959.5

1.5

mV

V

V_FB

Feedback pin voltage

V_FB= 600 mV, 0°C ≤ T_J≤ 85°C⁽²⁾

0.6 V ≤ V_FB≤ 1.5 V⁽¹⁾

0.5 V ≤ V_FB< 0.6 V⁽¹⁾

–0.5%

–1.0%

–1.5%

80

0.5%

1.0%

1.5%

Feedback pin voltage

accuracy

V_FB(ACC)

%

A_OL

G_BWP

I_FB

Open-loop gain⁽¹⁾

Gain bandwidth product⁽¹⁾

FB pin input bias current

Sourcing

dB

MHz

nA

15

V_FB= 0.95 V

V_FB= 0 V

–75

1

75

12

I_COMP

mA

Sinking

V_FB= 1.2 V

1

VSET

I_Vset

VSET pin current

9.5

10.5

950

µA

mV

V

V_Vset

Initial VOUT setting

VSET disable threshold

R_Vset= 34.8 kΩ

V_Vset(dis)

OSCILLATOR

2.41

Adjustment range⁽²⁾

Switching frequency

Ramp peak-to-peak⁽¹⁾

Valley voltage⁽¹⁾

200

425

1000

575

kHz

F_SW

R_RT= 40.2 kΩ

500

V_VDD/8.5

0.75

V_RMP

V_VDD/9.3

V_VDD/7.6

V

V_VLY

SYNCHRONIZATION

V_IH(sync)

High-level input voltage

Low-level input voltage

2.0

V

V_IL(sync)

0.80

100

Sync input minimum pulse

width

T_pw(sync)

f_SYNC

ns

Synchronization frequency

200

1200

20%

kHz

SYNC pin frequency range

Δf_SYNC

-20%

from free running frequency⁽¹⁾

RESET_B

3.3-V and 5-V logic

2.1

1.2

V_IH(reset)

High-level input voltage⁽¹⁾

Low-level input voltage

1.8-V logic (factory default)

3.3-V and 5-V logic

V

0.8

0.5

V_IL(reset)

1.8-V logic (factory default)

Minimum RESET_B pulse

width

t_PW(reset)

R_VSET= 34.8 kΩ

200

ns

Output voltage after reset

triggered

V_{vout_command(reset)}

950

mV

(1) Specified by design. Not production tested.

(2) The parameter covers 4.5 V to 18 V of VDD.

7

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_VIN= V_VDD= 12 V, R_RT= 40.2 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BP6 REGULATOR

V_BP6

Regulator output voltage

Regulator dropout voltage

I_BP6= 10 mA

5.85

50

6.4

6.9

V

V_BP6(do)

V_VIN– V_BP6, V_VDD= 4.5 V, I_BP6= 25 mA

V_VDD= 12 V

200

400

mV

Regulator short-circuit

current⁽¹⁾

Regulator UVLO voltage⁽¹⁾

I_BP6SC

150

3.73

320

mA

V

V_BP6UV

Regulator UVLO voltage

hysteresis⁽¹⁾

V_BP6UV(hyst)

mV

BOOTSTRAP

V_BOOT(drop)

Bootstrap voltage drop

I_BOOT= 5 mA

125

3.4

mV

BP3 REGULATOR

V_BP3

3-V regulator output voltage

V_VDD≥ 4.5 V, I_BP3= 5 mA

3.0

3.2

35

V

3-V regulator short-circuit

current⁽¹⁾

I_BP3SC

mA

PWM

Minimum controllable pulse

width⁽¹⁾

t_ON(min)

100

ns

SOFT-START

Factory default setting

5

100

0

ms

%

Programmable range, 16 discrete

settings⁽¹⁾⁽³⁾

TON_RISE

Soft-start time

0

100

10

Accuracy, TON_RISE = 1 ms

Factory default setting

-10

ms

TON_MAX_FAULT_ Upper limit on the time to

Programmable range, 16 discrete

settings⁽¹⁾⁽⁴⁾

Accuracy⁽¹⁾

0

100

10

LIMIT

power up the output

–10

%

ms

%

Factory default setting

Programmable range, 16 discrete settings⁽¹⁾

Accuracy⁽¹⁾

TON_DELAY

Turn-on delay

0

100

10

–10

SOFT-STOP

Factory default setting⁽⁵⁾

0

ms

Programmable range, 16 discrete

settings⁽¹⁾⁽⁵⁾

TOFF_FALL

Soft-stop time

Turn-off delay

0

100

10

Accuracy, TOFF_FALL = 1 ms

Factory default setting

–10

%

ms

%

TOFF_DELAY

Programmable range, 16 discrete settings⁽¹⁾

Accuracy⁽¹⁾

0

100

10

–10

SS PIN FOR INITIAL SOFT-START PROGRAMMING

I_SS

SS pin current

9.5

10.5

12

µA

V

V_SS(ivlow)

V_SS(ivhigh)

SS pin invalid low voltage

SS pin invalid high voltage

0.03

2.40

(3) The setting of TON_RISE of 0 ms means the unit to bring its output voltage to the programmed regulation value as quickly as possible,

which results in an effective TON_RISE time of 1 ms (fastest time supported).

(4) The setting of TON_MAX_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT of 0 means disabling TON_MAX_FAULT and

VOUT_UV_FAULT response and reporting, respectively.

(5) The setting of TOFF_FALL of 0 ms means the unit to bring its output voltage down to 0 as quickly as possible, which results in an

effective TOFF_FALL time of 1 ms (fastest time supported).

8

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_VIN= V_VDD= 12 V, R_RT= 40.2 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REMOTE SENSE AMPLIFIER

(V_OUTS+– V_OUTS–) = 0.6 V

–5

–7

5

7

Error voltage from DIFFO to

V_DIFFO(err)

(V_OUTS+– V_OUTS–) = 1.2 V

(V_OUTS+– V_OUTS–) = 3.0 V

mV

(V_OUTS+– V_OUTS–

)

–15

0.995

2

15

A_RSA

Differential gain

1.005

V/V

BW_RSA

Closed-loop bandwidth⁽¹⁾

MHz

Maximum DIFFO output

voltage

V_DIFFO(max)

V_BP6–0.2

V

DIFFO sourcing current

DIFFO sinking current

1

I_DIFFO

mA

POWER STAGE

High-side power device on-

resistance

R_HS

V

_VDD≥ 12 V, T_J= 25°C

5.5

2.0

mΩ

Low-side power device on-

resistance

V_VDD≥ 12 V, (BOOT - SW) = 6.5 V, T_J

=

R_LS

25°C

CURRENT SENSE AMPLIFIER

Minimum LDRV pulse width

t_LS(minCS)

for valid overcurrent and

current mornitoring⁽¹⁾

400

ns

LOW-SIDE CURRENT LIMIT PROTECTION

Off time between restart

7 ×

TON_RISE

t_OFF(OC)

ms

attempts⁽¹⁾

Factory default setting

Programmable range

Factory default setting

Programmable range

Factory default setting

Programmable range

Factory default setting

Programmable range

36

24

34

22

TPS544C25

TPS544B25

TPS544C25

TPS544B25

5

4

40

36

IOUT_OC_FAULT_ Output current overcurrent

LIMIT

fault threshold

A

39.5

IOUT_OC_WARN_

LIMIT

Output current overcurrent

warning threshold

4

35.5

Output current overcurrent

fault accuracy

I

_OUT≥ 20 A

–10%

+10%

I_OC(acc)

Output current overcurrent

warning accuracy

I

_OUT≥ 20 A⁽¹⁾

–10%

+10%

HIGH-SIDE SHORT CIRCUIT PROTECTION

High-side short-circuit

protection peak current

threshold

TPS544C25

TPS544B25

40

33

75

66

I_HSOC

A

POWER GOOD (PGOOD) AND OVERVOLTAGE/UNDERVOLTAGE WARNING

PGOOD and over/under

V_PG(hyst)

votlage warning threshold

hysteresis at DIFFO pin

VOUT_SCALE_LOOP = 1.0

15

30

75

mV

R_PGOOD

PGOOD pull-down resistance V_DIFFO= 0 V, I_PGOOD= 5 mA

PGOOD pin leakage current V_PGOOD= 5 V

45

60

15

Ω

I_PGOOD(lk)

µA

VOUT_SCALE_LOOP = 1.0, factory default

setting

1165

527

600

350

1201

1237

1797

650

VOUT_OV_WARN_ Overvoltage warning threshold

LIMIT at DIFFO pin

VOUT_SCALE_LOOP = 1.0, programmable

range⁽¹⁾

VOUT_SCALE_LOOP = 1.0, factory default

setting

631

mV

VOUT_UV_WARN_ Undervoltage warning

LIMIT

threshold at DIFFO pin

VOUT_SCALE_LOOP = 1.0, programmable

range⁽¹⁾

1428

Over/under votlage warning

V_{UVOV(warnhyst)}

threshold hysteresis at DIFFO VOUT_SCALE_LOOP = 1.0⁽¹⁾

15

75

9

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_VIN= V_VDD= 12 V, R_RT= 40.2 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

OUTPUT OVERVOLTAGE AND UNDERVOLTAGE FAULT PROTECTION

VOUT_SCALE_LOOP = 1.0, factory default

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1243

529

550

346

1281

1330

1799

610

setting

VOUT_OV_FAULT_ Overvoltage fault threshold at

LIMIT DIFFO pin

VOUT_SCALE_LOOP = 1.0, programmable

range⁽¹⁾

VOUT_SCALE_LOOP = 1.0, factory default

setting

594

mV

VOUT_UV_FAULT_ Undervoltage fault threshold at

LIMIT

DIFFO pin

VOUT_SCALE_LOOP = 1.0, programmable

range⁽¹⁾⁽⁴⁾

1426

Over/under votlage fault

V_{UVOV(flthyst)}

threshold hysteresis at DIFFO VOUT_SCALE_LOOP = 1.0⁽¹⁾

15

75

OUTPUT VOLTAGE TRIMMING

Factory default setting

1.0

VOUT_

TRANSITION_

RATE

mV/µs

Output voltage transition rate

Programmable range, 8 discrete settings

Accuracy

0.067

–10%

1.5

10%

Factory default setting

1

VOUT_SCALE_

LOOP

Feedback loop scaling factor

Programmable range, 3 discrete settings

Factor default setting

0.25

1

486

VOUT_SCALE_LOOP = 1.0, programmable

range⁽¹⁾

256

512

768

1536

3072

Output voltage programmable

register value, multiply by 2^-9

to get output voltage

VOUT_COMMAND

VOUT_SCALE_LOOP = 0.5, programmable

range⁽¹⁾

VOUT_SCALE_LOOP = 0.25, programmable

range⁽¹⁾

1024

TEMPERATURE SENSE AND THERMAL SHUTDOWN

Junction thermal shutdown

T_SD

135

15

0

145

20

155

25

temperature⁽¹⁾

°C

V

Junction thermal shutdown

T_HYST

hysteresis⁽¹⁾

Voltage range on TSNS/SS

V_TSNS

1.00

pin⁽¹⁾

Factory default setting

Programmable range

Factory default setting

Programmable range

125

100

External overtemperature fault

OT_FAULT_LIMIT

limit⁽¹⁾

120

165

External overtemperature

OT_WARN_LIMIT

°C

warning limit⁽¹⁾

100

15

140

25

External overtemperature

T_OT(hys)

20

fault, warning hysteresis⁽¹⁾

MEASUREMENT SYSTEM

Output voltage measurement

range

M_VOUT(rng)

0.5

5.8

V

Output voltage measurement

M_VOUT(acc)

accuracy

–2.0%

2.0%

Output voltage measurement

M_VOUT(lsb)

1.953

mV

A

bit resolution⁽¹⁾

Output current measurement

range

M_IOUT(rng)

0

40

I

_OUT≥ 20 A

–15%

–3

15%

3

Output current measurement

accuracy

M_IOUT(acc)

3 A ≤ I_OUT< 20 A⁽¹⁾

A

Output current measurement

bit resolution⁽¹⁾

M_IOUT(lsb)

M_TSNS(rng)

M_TSNS(acc)

M_TSNS(lsb)

62.5

mA

External temperature sense

range⁽¹⁾

–40

–5

165

5

External temperature sense

accuracy⁽¹⁾

-40°C ≤ T_J(sensor)≤ 165°C

°C

External temperature sense bit

resolution⁽¹⁾

1

10

TPS544C25, TPS544B25

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ZHCSDR8 –MAY 2015

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_VIN= V_VDD= 12 V, R_RT= 40.2 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PMBus INTERFACE ADDRESSING

I_ADD

Address pin bias current

9.5

10.5

12

µA

V

V_ADD(ivlow)

Address pin illegal low voltage

0.05

Address pin illegal high

voltage

V_ADD(ivhigh)

2.40

PMBus™ INTERFACE

3.3-V/5-V logic

2.1

1.2

Input high voltage, CLK,

DATA, CNTL

V_IH

V

1.8-V logic (factory default)

3.3-V/5-V logic

0.8

0.5

Input low voltage, CLK, DATA,

CNTL

V_IL

V

1.8-V logic (factory default)

Input high level current, CLK,

DATA

I_IH

-10

10

µA

Input low level current, CLK,

DATA

I_IL

-10

5

10

µA

V

I_CNTL

V_OL

CNTL pin pull-up current

Output low level voltage,

DATA, SMBALERT

V_DD> 4.5 V, input current to DATA,

SMBALERT = 4mA

0.4

Output high level open drain

leakage current, DATA,

SMBALERT

I_OH

Voltage on DATA, SMBALERT = 5.5V

-10

10

µA

Output low level open drain

leakage current, DATA,

SMBALERT

I_OL

Voltage on DATA, SMBALERT = 0.4V

Slave mode

4.0

10

mA

PMBus operating frequency

range

I_PMB

400

kHz

11

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

7.6 Typical Characteristics

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V_OUT= 0.5 V

V_OUT= 1.0 V

V_OUT= 1.5 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 0.5 V

V_OUT= 1.0 V

V_OUT= 1.5 V

V_OUT= 2.5 V

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Load Current (A)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Load Current (A)

D001

V_IN= 5 V

f_SW= 500 kHz

L = 470 nH

No Snubber

V_IN= 12 V

f_SW= 500 kHz

L = 470 nH

No Snubber

R_DCR= 0.3 mΩ

R_BOOT= 0 Ω

R_DCR= 0.3 mΩ

R_BOOT= 0 Ω

Figure 1. Efficiency vs. Output Current

Figure 2. Efficiency vs. Output Current

3

2.8

2.6

2.4

2.2

2

8.5

8

V_DD= 4.5 V

V_DD= 12 V

V_DD= 18 V

V_DD= 4.5 V

V_DD= 12 V

V_DD= 18 V

7.5

7

6.5

6

5.5

5

1.8

1.6

4.5

4

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

Figure 3. Low-Side MOSFET On-Resistance (R_DS(on)

)

Figure 4. High-Side MOSFET On-Resistance (R_DS(on)

)

vs. Junction Temperature

601

952

951.5

951

600.5

600

950.5

950

599.5

599

949.5

949

948.5

948

598.5

598

947.5

947

V_DD= 4.5 V

V_DD= 12 V

V_DD= 18 V

V_DD= 4.5 V

V_DD= 12 V

V_DD= 18 V

597.5

597

946.5

946

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

V_FB= 600 mV

V_FB= 950 mV

Figure 5. Feedback Voltage vs. Junction Temperature

Figure 6. Feedback Voltage vs. Junction Temperature

12

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www.ti.com.cn

ZHCSDR8 –MAY 2015

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

12

11.5

11

1.01

1.0075

1.005

1.0025

1

10.5

10

9.5

9

0.9975

0.995

0.9925

0.99

8.5

8

7.5

7

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

Figure 7. Normalized Switching Frequency

vs. Junction Temperature

Figure 8. Non-Switching Input Current (I_VDD

)

vs. Junction Temperature

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

6.1

6

3.4

3.35

3.3

3.25

3.2

3.15

3.1

3.05

3

5.9

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

I_BP6= 10 mA

V_VIN= V_VDD= 12 V

I_BP3= 5 mA

V_VIN= V_VDD= 12 V

Figure 9. BP6 Voltage vs. Junction Temperature

Figure 10. BP3 Voltage vs. Junction Temperature

4.6

4.55

4.5

100

90

80

70

60

50

40

30

20

10

0

4.45

4.4

4.35

4.3

-40

-20

0

20

40

60

80

100 120 140

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

VIN_ON = 4.5 V

Figure 11. PGOOD Pull-Down Resistance

vs. Junction Temperature

Figure 12. Turn-On Voltage vs. Junction Temperature

13

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

4.2

4.15

4.1

2

1.5

1

4.05

4

0.5

0

3.95

3.9

-0.5

-1

3.85

3.8

-1.5

-2

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40

-20

0

20

40

60

80

100 120 140

Junction Temperature (èC)

D001

VIN_OFF = 4.0 V

I_OUT= 20 A

V_VIN= V_VDD= 12 V

Figure 13. Turn-Off Voltage vs. Junction Temperature

Figure 14. READ_IOUT Accuracy vs. Junction Temperature

0.25

70

60

50

40

30

20

0

-0.25

-0.5

-0.75

-1

10

TPS544C25

TPS544B25

0

-40

-20

0

20

40

60

80

100 120 140

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

V_VIN= V_VDD= 12 V

BOOT - SW = 6.5 V

V_VIN= V_VDD= 12 V

Figure 15. READ_VOUT Accuracy vs. Junction Temperature

Figure 16. High-Side Overcurrent Protection

vs. Junction Temperature

4

3.5

3

2.5

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

40

35

30

25

20

15

10

5

TPS544C25

TPS544B25

-3.5

-4

-40 -25 -10

0

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

JunctionTemperature (°C)

Junction Temperature (èC)

D001

OCF = 20 A

V_VIN= V_VDD= 12 V

OCF = 36 A

OCF = 24 A

(TPS544C25)

(TPS544B25)

Figure 17. Overcurrent Fault Protection (OCF) Accuracy

vs. Junction Temperature

Figure 18. Overcurrent Fault Protection (OCF)

vs. Junction Temperature

14

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ZHCSDR8 –MAY 2015

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 5 V

V_OUT= 1.0 V

f_SW= 1 MHz

V_IN= 5 V

V_OUT= 1.0 V

f_SW= 300 kHz

Figure 19. Safe Operating Area

Figure 20. Safe Operating Area

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 5 V

V_OUT= 1.0 V

f_SW= 500 kHz

V_IN= 5 V

V_OUT= 1.5 V

f_SW= 300 kHz

Figure 21. Safe Operating Area

Figure 22. Safe Operating Area

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

2

4

6

8

10 12 14 16 18 20 22 24 26 28

Output Current (A)

D001

V_IN= 5 V

V_OUT= 1.5 V

f_SW= 500 kHz

V_IN= 5 V

V_OUT= 3.3 V

f_SW= 300 kHz

Figure 23. Safe Operating Area

Figure 24. Safe Operating Area

15

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28

Output Current (A)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 5 V

V_OUT= 3.3 V

f_SW= 500 kHz

V_IN= 12 V

V_OUT= 1.0 V

f_SW= 300 kHz

Figure 25. Safe Operating Area

Figure 26. Safe Operating Area

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 12 V

V_OUT= 1.0 V

f_SW= 500 kHz

V_IN= 12 V

V_OUT= 1.5 V

f_SW= 300 kHz

Figure 27. Safe Operating Area

Figure 28. Safe Operating Area

120

100

80

60

40

20

0

120

100

80

60

40

20

0

400 LFM

200 LFM

100 LFM

Natural convection

400 LFM

200 LFM

100 LFM

Natural convection

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 300 kHz

V_IN= 12 V

V_OUT= 1.5 V

f_SW= 500 kHz

Figure 30. Safe Operating Area

Figure 29. Safe Operating Area

16

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

Typical Characteristics (continued)

V_IN= V_DD= 12 V, T_A= 25 ºC, R_RT= 40.2 kΩ (unless otherwise specified). Safe operating area curves were measured using a

Texas Instruments Evaluation Module.

120

100

80

60

40

400 LFM

200 LFM

100 LFM

Natural convection

20

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Output Current (A)

D001

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

Figure 31. Safe Operating Area

17

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS544x25 devices are PMBus 1.2 compliant 20-A and 30-A, high-performance, synchronous buck

converters with two integrated N-channel NexFET™ power MOSFETs, enabling high power density and minimal

PCB area. These devices implement the industry standard fixed switching frequency, voltage-mode control with

input feed-forward topology that responds instantly to input voltage change. These devices can be synchronized

to the external clock to eliminate beat noise and reduce EMI/EMC. The integrated PMBus interface capability

provides precise current, voltage and on-board temperature monitoring, as well as many user-programmable

configuration options including Adaptive Voltage Scaling (AVS) through standard VOUT_COMMAND.

8.2 Functional Block Diagram

VDD

BP6

BP3

BOOT

VIN

SW

Linear

Regulators

HSFET

LSFET

Driver

Control

Anti-Cross-

Conduction

BP6

RT

Pre-Bias

Oscillator

SYNC/RESET_B

Ramp

PWM

GND

CLK

S

R

Q

OC Event

Average I_OUT

RESET_VOUT

+

Current

Sense,

OC Detection

COMP

FB

Error Amplifier

Fault

VREF for

Soft-Start and

+

DATA

OC Threshold

Reference

DAC

VOUT_COMMAND

SMBALERT

CNTL

PMBus Engine

VSET

ADC, PMBus Commands,

IC Interface, EEPROM

V_OUTSense

OV/UV Detection

ADDR0

ADDR1

PGOOD

PGND

DIFFO

AGND

750 kW

Temperature

Sensing

VOUTS+

VOUTSœ TSNS/SS

18

TPS544C25, TPS544B25

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ZHCSDR8 –MAY 2015

8.3 Feature Description

8.3.1 Linear Regulators BP3 and BP6

The TPS544x25 devices have two on-board linear regulators to provide suitable power for the internal circuitry of

the device. Externally bypass pins BP3 and BP6 for the converter to function properly. BP3 requires a minimum

of 2.2 µF of capacitance connected to AGND. BP6 requires a minimum 2.2 µF of capacitance connected to

GND. TI recommends using a 4.7-µF capacitor and an additional 100-nF to reduce the ripple on the BP6 pin.

NOTE

Place bypass capacitors as close as possible to the device pins, with a minimum return

loop back to ground and the return loop should be kept away from fast switching voltage

and main current path. Refer to Layout for details. Poor bypassing can degrade the

performance of the regulator.

The use of the internal regulators to power other circuits are not recommended because the loads placed on the

regulators might adversely affect operation of the controller.

8.3.2 Input Undervoltage Lockout (UVLO)

The TPS544x25 devices provide flexible user adjustment of the undervoltage lockout threshold and hysteresis.

Two PMBus commands, VIN_ON (35h) and VIN_OFF (36h) allow the user to set these input voltage turn-on and

turn-off thresholds independently, with a minimum of 4-V turn-off to a maximum 7.75-V turn-on. See the

command descriptions for more details.

8.3.3 Turn-On and Turn-Off Delay and Sequencing

The TPS544x25 devices provide many sequencing options. Using the ON_OFF_CONFIG command, the device

can be configured to start up whenever the input voltage is above the undervoltage lockout (UVLO) threshold, or

to additionally require a signal on the CNTL pin and/or receive an update to the OPERATION command via the

PMBus interface . When the gating signal as specified by ON_OFF_CONFIG is asserted, a programmable turn-

on delay can be set with TON_DELAY to delay the start of regulation. Similarly, a programmable turn-off delay

can be set with TOFF_DELAY to delay the stop of regulation once the gating signal is de-asserted. Delay times

are specified in ms, from 0 to 100 ms.

Figure 32 shows control of the start-up and shutdown operations of the device, when the device is configured to

respond to both CNTL and the OPERATION command. The device can also be configured to use either the

CNTL signal, or the OPERATION command independently, or convert power whenever sufficient input voltage is

present.

TON_DELAY

TOFF_DELAY

TON_RISE

TOFF_FALL

VIN

OFF

ON

OFF

OPERATION[7]

CNTL

V

OUT

Time

Figure 32. Turn-On Controlled By Both Operation⁽¹⁾and Control

(1)

8.3.4 Voltage Reference

A reference DAC (digital-to-analog converter) with 500 mV to 1500 mV range and 2^-9V (1.953 mV) resolution

connects to the non-inverting input of the error amplifier. The tight tolerance on the reference voltage allows the

user to design power supply with very high DC accuracy.

(1) Bit 7 of OPERATION is used to control power conversion.

19

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Feature Description (continued)

8.3.5 Differential Remote Sense

The TPS544x25 devices implement a differential remote sense amplifier to provide excellent load regulation by

cancelling IR-drop in high current applications. The VOUTS+ and VOUTS– pins should be kelvin-connected to

the output capacitor bank directly at the load, and routed back to the device as a tightly coupled differential pair.

Ensure that these traces are isolated from fast switching signals and high current paths on the final PCB layout,

as these can add differential-mode noise. Optionally, use a small coupling capacitor (1-nF typical) between the

VOUTS+ and VOUTS– pins to improve noise immunity. The output of the differential remote sense amplifier

(DIFFO) is used for output voltage setting and error amplifier frequency compensation local to the device as

shown in Figure 33.

Additionally, the voltage at the DIFFO pin is digitized, averaged to reduce measurement noise and continually

stored in the READ_VOUT register, enabling output voltage telemetry.

R2

C1

VOUTS+

DIFFO

FB

R1

+

VOUTSt

COMP

R3

C2

+

C3

V_REF

To PWM

R_BIAS

Figure 33. Output Voltage Setting

8.3.6 Set Output Voltage and Adapative Voltage Scaling (AVS)

A voltage divider from the DIFFO pin to the FB pin is typically required to set the nominal output voltage like the

one formed by R1 and R_BIASresistors shown in Figure 33. To allow PMBus devices to map between the

commanded voltage and the voltage at the control circuit input (V_OUTdivided down to match a reference voltage),

the device uses the VOUT_SCALE_LOOP command.

VREF = VOUT_COMMAND × VOUT_MODE × VOUT_SCALE_LOOP (V)

where

•

VOUT_SCALE_LOOP = R_BIAS/(R_BIAS+R1) (as shown in Figure 33)

(1)

(2)

VOUT = VOUT_COMMAND × VOUT_MODE = VOUT_COMMAND × 2^-9V.

The output voltage can be set and adjusted dynamically using the VOUT_COMMAND through the PMBus

interface. See the PMBus command description for full details on the implementation.

NOTE

•

The VOUT_SCALE_LOOP is limited to only 3 possible options: 1 (default, no bottom

resistor required for the divider), 0.5, and 0.25.

When VOUT_SCALE_LOOP = 1 (default), no bottom resistor R_BIASis needed. The

reference voltage is equal to the output voltage, which allows tighter system DC

accuracy by removing the resistor divider tolerance.

•

It is required that the user make sure the divider ratio R_BIAS/( R_BIAS+R1) matches the

programed VOUT_SCALE_LOOP and the user should program VOUT_SCALE_LOOP

prior to any other VOUT related commands in order for the proper range checking to

work and to avoid Invalid Data and output overvoltage and undervoltage scenarios.

20

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ZHCSDR8 –MAY 2015

Feature Description (continued)

The range of valid VOUT_COMMAND values is dependent upon the configured VOUT_SCALE_LOOP as shows

in Table 1.

Table 1. FB Resistor Divider Ratio and VOUT_COMMAND Data Valid Range

OUTPUT VOLTAGE

RANGE (V)

VOUT_COMMAND

DATA VALID RANGE

RESISTOR DIVIDER

R_BIAS: R1 (IN

VOUT_SCALE_LOOP

Figure 33)

MIN

0.5

1

MAX

MIN

256

MAX

1

Unnecessary

1.5

3

768

1536

3072

0.5

1:1

1:3

512

0.25

2

6

1024

There are several commands that are used in commanding the output voltage of a device with a PMBus

interface. These include:

•

VOUT_MODE

VOUT_COMMAND

VOUT_MAX

MFR_VOUT_MIN

VOUT_SCALE_LOOP

VOUT_OV_FAULT_LIMIT

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

Figure 34 shows how the output voltage related commands are applied. The TPS544x25 devices implement

relational check to make sure the VOUT_COMMAND is not programmed to exceed the VOUT_MAX,

MFR_VOUT_MIN, VOUT_OV_WARN_LIMIT , and VOUT_UV_WARN_LIMIT. The VOUT_OV_WARN_LIMIT

should also be smaller than VOUT_OV_FAULT_LIMIT and the VOUT_UV_WARN_LIMIT should be greater than

VOUT_UV_FAULT_LIMIT. Violation of these relational check rules will set corresponding status bits and trigger

SMBALERT. See the PMBus command description for full details.

In order for the relational checking to operate properly and to avoid error flagging, the VOUT_SCALE_LOOP

should be changed first, if needed. Any changes to other registers should be made such that the values in all the

registers conform to the limits for the current VOUT_SCALE_LOOP setting.

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Slew Rate Control for

Margining and AVS

Range 0.067 to 1 mV/us

8 Discrete Settings

Range: 1 ms to 100 ms Range: 1 ms to 100 ms

TOFF_FALL

Digital Controlled Fall

TON_RISE

Digital Soft Start

VOUT_TRANS_RATE

Resistor divider may

or may not be used

on FB

FB

Range: 0 ms to 100 ms for both

16 discrete settings

V_REFRange:

0 V to 1.5 V for

2-mV resolution

Slew

Rate

Decode

TON_DELAY

TOFF_DELAY

Default: 0.95 V.

EEPROM backup.

Default overridden

by R_SETresistor.

on V_REF

Pull up to BP3

when not used.

VSET

Step Control

+

Range

Limit

COMP

DAC

+

ADC

VOUT_COMMAND

V_REF

Relational Check

VOUT_COMMAND with:

R_SET

VOUT_MAX

Default: 1.5 V

Default: 0.5 V

VOUT_SCALE_LOOP

MFR_VOUT_MIN

Possible values:

0.25, 0.5, 1.0

Default: 1.0

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

Default: 1.201 V

Default: 0.631 V

Figure 34. Conceptual View Of How Output Voltage Related Commands Are Applied

8.3.6.1 Increasing the Output Voltage

The order below is optimum for programming the output voltage upwards (not all commands may be necessary).

•

(40h) VOUT_OV_FAULT_LIMIT

(42h) VOUT_OV_WARN_LIMIT

(24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT is

irrelevant. Just set VOUT_MAX prior to VOUT_COMMAND)

•

(21h) VOUT_COMMAND

(A4h) MFR_VOUT_MIN (ordering with respect to VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT is

irrelevant. Just set MFR_VOUT_MIN after VOUT_COMMAND)

•

(43h) VOUT_UV_WARN_LIMIT

(44h) VOUT_UV_FAULT_LIMIT

8.3.6.2 Decreasing the Output Voltage

The order below is optimum for programming the output voltage downwards (not all commands may be

necessary).

•

(44h) VOUT_UV_FAULT_LIMIT

(43h) VOUT_UV_WARN_LIMIT

(A4h) MFR_VOUT_MIN (ordering with respect to VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT is

irrelevant. Just set MFR_VOUT_MIN prior to VOUT_COMMAND)

•

(21h) VOUT_COMMAND

(24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT is

irrelevant. Just set VOUT_MAX after VOUT_COMMAND)

•

(42h) VOUT_OV_WARN_LIMIT

(40h) VOUT_OV_FAULT_LIMIT

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8.3.6.3 Set Default Output Voltage by VSET

In order to power up the converter to a default VOUT_COMMAND rather than that stored in EEPROM without

reprogramming, the initial boot-up output voltage can also be set by the resistor connected from VSET pin to

AGND. The E48 series resistors with no worse than 1% tolerance suggested for setting the output votlage are

shown in Table 2. VOUT_SCALE_LOOP can be set only at a value of 1 (no bottom resistor is needed in the

feedback resistor divider) if the VSET pin is used. If VSET pin is not used, pull it up to BP3. If TPS544x25

devices re-start after losing power completely, the VOUT_COMMAND value set by external resistor overwrites

any value stored from previous VOUT_COMMAND operation.

Table 2. VSET Resistors for Boot-up VOUT_COMMAND Value

BOOT-UP DEFAULT

VOUT_COMMAND (V)

RESISTOR VALUE

(kΩ)

0.95

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.20

Short to AGND

8.66

15.4

23.7

34.8

51.1

78.7

121

187

VOUT_COMMAND value

stored in EEPROM

(VSET pin pulled up to BP3)⁽¹⁾

(1) sets iv_vset bit in STATUS_MFR_SPECIFIC (80h)

If the resistor connected from VSET pin to AGND is used to set the output voltage, the SYNC/RESET_B pin is

configured as RESET_B pin on default. Reset the output voltage to the boot-up voltage when SYNC/RESET_B is

logic low. See Reset VOUT for more details.

If the VSET pin voltage higher than the VSET disable threshold (2.41 V minimum), the VSET function is disabled,

the boot-up default VOUT_COMMAND are restored from the internal EEPROM of the TPS544x25 devices.

When VSET is not used, the SYNC/RESET_B pin is configured as SYNC pin on default and the switching

frequency synchronizes to the external clock applied to SYNC/RESET_B pin. In order to use both VSET and

SYNC function, the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) should

be set to 1. The aforementioned interaction between VSET and SYNC/RESET_B pin funcationality is listed in

Table 3. See Switching Frequency and Synchronization for more details.

The VSET pin configuration also affects the PMBus logic threshold in the TPS544x25 devices. See OPTIONS

(MFR_SPECIFIC_21) (E5h) for details.

Table 3. Interaction between VSET and SYNC/RSET_B Pin Funcationality

VSET Used⁽¹⁾

FORCE_SYNC

SYNC/RSET_B FUNCTIONALITY

No

0

1

0

1

SYNC

Yes

RESET_B

SYNC

(1) VSET pin voltage < 2.41 V

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8.3.7 Reset VOUT

Without power cycling, the VOUT_COMMAND value and the corresponding output voltage can be reset to the

default value set by VSET. To reset VOUT_COMMAND, the VSET pin should be used in combination with

SYNC/RESET_B pin. The default VOUT_COMMAND value is set by the resistor connected between VSET and

AGND and latched when the TPS544x25 devices are powered up from VDD. When the SYNC/RESET_B pin is

pulled low, the digital core sets VOUT_COMMAND value back to the default value. The Figure 35 shows the

timing diagram for resetting the output voltage. When RESET_B is asserted low, after a short delay (less than 2

µs), the output voltage begins transitioning from its current value to the default value configured by VSET per the

slew-rate set in VOUT_TRANSITION_RATE. The VOUT_COMMAND value is not updated to any

VOUT_COMMAND programming while SYNC/RESET_B is held low.

V

SYNC/RESET_B

Pre-AVS V

OUT

V

OUT

Default V

SET .

(B)

(A)

Response Delay

Time

(A) VOUT_COMMAND adjustment through the PMBus interface ;

(B) Reset back to default VOUT_COMMAND value determined by VSET resistor at power up. The slew rate is

defined by VOUT_TRANSITION_RATE.

Figure 35. Output Voltage Reset

8.3.8 Switching Frequency and Synchronization

A resistor from the RT pin to AGND sets the switching frequency. Equation 3 calculates the R_RTresistor value.

ꢀ.01 × 10¹⁰

2₂₄

=

¶

37

where

•

R_RTis the timing resistor in Ω

f_SWis the switching frequency in Hz

(3)

The TPS544x25 devices are designed to operate between 200 kHz and 1 MHz.

The TPS544x25 devices can also synchronize to an external clock which is ±20% of the free-running frequency.

The external clock should be applied to the SYNC/RESET_B pin. A sudden change in synchronization clock

frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output

voltage.

If a resistor is connected from VSET pin to AGND to program the initial boot-up voltage, the clock

synchronization function is disabled on default, the SYNC/RESET_B pin is configured to RESET function which

can reset VOUT when SYNC/RESET_B is logic low.

In order to use both VSET and SYNC function, the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS

(MFR_SPECIFIC_32) (F0h) should be set to 1, as shown in Table 3. While the output in regulation and an

external clock being applied to SYNC/RESET_B pin, set the FORCE_SYNC bit on the fly causes a sudden

change in switching frequency and results in an overshoot or undershoot on the output voltage.

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8.3.9 Soft-Start and TON_RISE Command

To control the inrush current needed to charge the output capacitor bank during start up, the TPS544x25 devices

implement a soft-start time. When the device is enabled, the feedback reference voltage, V_REF, ramps from 0 V

to the final level defined by VOUT_COMMAND and VOUT_SCALE_LOOP at a slew rate defined by the

TON_RISE command. The rise times specified are defined by the slew rate needed to ramp the reference

voltage from 0 V to its final value at each given rise time.

The actual rise time of the converter output is slightly less than the rise time defined by TON_RISE. This

difference occurs because switching does not occur until the error amplifier output reaches the valley of the PWM

ramp. During soft-start, the error amplifier output voltage starts at 0 V, and must reach the valley of the PWM

ramp, 0.75 V typical, before switching can begin. As soons as it reaches the valley of the PWM ramp, the

converter output voltage rises quickly until the feedback voltage, V_FB, reaches the reference voltage V_REF, from

which point they track through the end of the soft-start period.

t

ON(rise)

ON(delay)

CNTL

V

REF

V

OUT

COMP slews up

to PWM ramp

PWM Ramp

COMP

Time

Figure 36. Soft-Start Timing

The TPS544x25 devices support several soft-start times between 1 ms and 100 ms selected by the TON_RISE

command. The value of TON_RISE can be set through the PMBus interface or alternatively by the resistor

connected from TSNS/SS pin to AGND. To use the TSNS/SS pin for TON_RISE setting, the SS_DET_DIS bit in

OPTIONS (MFR_SPECIFIC_21) (E5h) register should be set to 0 to enable the soft-start time detection.

Table 4. TSNS/SS Pin Configuration

SS_DET_DIS

TSNS/SS FUNCTIONALITY

0

1

SS

TSNS

The E48 series resistors with no worse than 1% tolerance suggested for TON_RISE setting are shown in

Table 5. Issuing TON_RISE command after start-up overwrites the TON_RISE value set by external resistor. If

TPS544x25 re-starts after losing power completely, the TON_RISE value set by external resistor overwrites any

value stored from previous TON_RISE operation.

Table 5. Soft-Start Resistors

RESISTOR VALUE

TON_RISE (ms)

(kΩ)

Short to AGND (sets iv_ss bit in

STATUS_MFR_SPECIFIC (80h))

5

1

2

8.25

14.7

22.6

34.8

51.1

78.7

3

5

7

10

25

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Table 5. Soft-Start Resistors (continued)

RESISTOR VALUE

TON_RISE (ms)

(kΩ)

121

187

27

52

TSNS/SS pin pulled up to BP3 (sets iv_ss bit in

STATUS_MFR_SPECIFIC (80h))

5

8.3.10 Pre-Biased Output Start-Up

The TPS544x25 devices prevent current from being discharged from the output during start-up, when a pre-

biased output condition exists. No SW pulses occur until the internal soft-start voltage rises above the error

amplifier input voltage (FB pin), if the output is pre-biased. As soon as the soft-start voltage exceeds the error

amplifier input, and SW pulses start, the device limits synchronous rectification after each SW pulse with a

narrow on-time. The low-side MOSFET on-time slowly increases on a cycle-by-cycle basis until 128 pulses have

been generated and the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach

prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-

regulation sequences are smooth and monotonic. These devices respond to a pre-biased output over-voltage

condition immediately upon VDD powered up and BP6 regulator voltage above its own UVLO of 3.73 V typical.

8.3.11 Soft-Stop and TOFF_FALL Command

As shown in Figure 32, the TPS544x25 devices implement TOFF_FALL command to define the time for the

output voltage to drop from regulation to 0. There might be negative current in the TPS544x25 devices during the

TOFF_FALL time in order to discharge the output voltage. The setting of TOFF_FALL of 0 ms means the unit to

bring its output voltage down to 0 as quickly as possible, which results in an effective TOFF_FALL time of 1 ms

(fastest time supported). This feature can be disabled in ON_OFF_CONFIG for the turn-off controlled by CNTL

pin or bit 6 of OPERATION if the regulator is turned off by OPERATION command, in that case, both high-side

and low-side FET drivers are turned off immediately and the output voltage will be discharged by the load.

8.3.12 Current Monitoring and Low-Side MOSFET Overcurrent Protection

The TPS544x25 devices sense average output current using an internal sense FET. A sense FET conducts a

scaled-down version of the power-stage current. Sampling this current in the middle of the low-side drive signal

determines the average output current. This architecture achieves excellent current monitoring and better

overcurrent threshold accuracy than inductor DCR current sensing with minimal temperature variation and no

dependence on power loss in a higher DCR inductor. Use the IOUT_CAL_OFFSET command to improve current

sensing and overcurrent accuracy by removing board layout-related systematic errors post assembly. The

devices continually digitize the sensed output current, and average it to reduce measurement noise. The devices

then store the current value in the read-only READ_IOUT register, enabling output current telemetry.

26

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VDD

VIN

Terminate

PWM Pulse

PWM

Logic

+

HFET

Peak Current

Comparator

HDRV

Three

Consecutive

Cycle

SW

HSOC

LSOC

Current Sense

Amplifier

Counter

LFET

+

OCF/OCW

Comparators

SenseFET

Average

Current

IOUT_OC_

FAULT_RESPONSE

Sensing

Hiccup/

Latch-off

LDRV

OCF/OCW

IOUT_CAL_

OFFSET

Thresholds

OCW

OCF

READ_IOUT

STATUS_IOUT

SMBALERT

PMBus Engine

AGND

PGND

GND

Figure 37. SenseFET Average Current Sensing and Overcurrent Protection

The TPS544x25 devices also implement low-side MOSFET overcurrent protection with programmable fault and

warning thresholds. The IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands set the low-side

overcurrent thresholds.

As shown in Figure 37, if an overcurrent event is detected in a given switching cycle, the device increments an

overcurrent counter. When the device detects three consecutive overcurrent (either high-side or low-side) events,

the converter responds, flagging the appropriate status registers, triggering SMBALERT if it is not masked, and

entering either continuous restart hiccup, or latch-off according to the IOUT_OC_FAULT_RESPONSE command.

In continuous restart hiccup mode, the devices implement a seven soft-start cycle time-out, followed by a normal

soft-start attempt. When the overcurrent fault clears, normal operation resumes, otherwise, the device detects

overcurrent and the process repeats. The IOUT_OC_FAULT_RESPONSE can also be set to ignore the OC fault

for debug purpose. The fault response scheme is summarized in Table 6.

8.3.13 High-Side MOSFET Short-Circuit Protection

The TPS544x25 devices also implement a fixed high-side MOSFET overcurrent (HSOC) protection to limit peak

current, and prevent inductor saturation in the event of a short circuit. The devices detect an overcurrent event by

sensing the voltage drop across the high-side MOSFET when it is on. If the peak current reaches the I_HOSClevel

on any given cycle, the cycle terminates to prevent the current from increasing any further. High-side MOSFET

overcurrent events are counted using the method shown in Figure 37. If the devices detect three consecutive

overcurrent events (high-side or low-side), the converter responds, by flagging the appropriate status registers;

triggering SMBALERT if it is not masked; and entering either continuous restart hiccup, or latch-off according to

the IOUT_OC_FAULT_RESPONSE command. For accurate high-side MOSFET overcurrent protection, the VIN

and VDD pins must be the same potential; split rail operation is not supported. The

IOUT_OC_FAULT_RESPONSE can also be set to ignore the OC fault for debug purpose. When the

IOUT_OC_FAULT_RESPONSE is set to ignore, the device continues to have cycle-by-cycle HSOC protection.

The fault response scheme is summarized in Table 6.

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8.3.14 Over-Temperature Protection

An internal temperature sensor protects theTPS544x25 devices from thermal runaway. The internal thermal

shutdown threshold, T_SD, is fixed at 145°C typical. When the devices sense a temperature above T_SD, an over-

temperature fault internal (OTFI) bit in STATUS_MFR_SPECIFIC is flagged, and power conversion stops until

the sensed junction temperature falls by the thermal shutdown hysteresis amount, T_HYST, (20°C typical). The

SMBALERT will be triggered if it is not masked.

The TPS544x25 devices also provide programmable external over-temperature fault and warning thresholds

using measurements from an external temperature sensor connected on the TSNS/SS pin as shown in

Figure 38. The temperature sensor circuit applies two bias currents to an external NPN transistor, and measures

ΔV_BEto infer the junction temperature of the sensor. The TPS544x25 devices are designed to use a standard

2N3904 NPN transistor as a temperature sensor. Other sensors may be used, but the devices assume an

ideality factor, n, of 1.008 for use with the 2N3904 transistor. The devices then digitize the result and compare it

to the user-configured over-temperature fault and warning thresholds. When an external over-temperature fault

(OTF) is detected, power conversion stops until the sensed temperature falls by 20°C. The

READ_TEMPERATURE_2 (8Eh) register is continually updated with the digitized temperature measurement,

enabling temperature telemetry. The OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) commands set over-

temperature fault and warning thresholds via the PMBus interface. When an overtemperature event is detected,

the device sets the appropriate flags in STATUS_TEMPERATURE (7Dh) and triggers SMBALERT if it is not

masked.

TI recommends including a 1-nF capacitor between the TSNS/SS pin and AGND to reduce temperature

measurement noise. Optionally, external temperature sensing can be disabled by terminating TSNS/SS to AGND

with a 0-Ω resistor. This termination forces the external temperature measurement to –40°C, and prevents

external over-temperature faults tripping. The internal temperature sensor, and internal over-temperature fault

remain enabled regardless of the TSNS/SS pin termination.

NOTE

The READ_TEMPERATURE_2 (8Eh) value remains at 25°C when SS_DET_DIS in

OPTIONS (MFR_SPECIFIC_21) (E5h) is set to 0 since the TSNS/SS pin is configured to

set TON_RISE time and not used for external temperature sensing (see Table 4).

The device response upon over-temperature fault can be set to Latch-off, Restart and Ignore in

OT_FAULT_RESPONSE. The fault response scheme is summarized in Table 6.

Internal Temp

OT Fault Internal

+

Sensor

Thermal

Shutdown

145°C

OT_FAULT_RESPONSE

OT_FAULT_LIMIT

OT_WARN_LIMIT

OT

Fault

READ_TEMPERATURE_2

STATUS_TEMPERATURE

STATUS_MFR_SPECIFIC

SMBALERT

TSNS/SS

Sampling and

Temperature

Conversion

∆V_BE

Measurement

PMBus Engine

C_T

Q_T

Figure 38. Over-Temperature Protection

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8.3.15 Output Overvoltage and Undervoltage Protection

The TPS544x25 devices include both output overvoltage protection and output undervoltage protection

capability. The devices compare the DIFFO pin voltage to internal selectable pre-set voltages, as defined by the

VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT command . As the output voltage rises or falls from the

nominal voltage, the DIFFO voltage tracks the output voltage.

If the DIFFO pin voltage rises above the output overvoltage protection threshold VOUT_OV_FAULT_LIMIT, the

device terminates normal switching and turns on the low-side MOSFET to discharge the output capacitor and

prevent further increases in the output voltage. The device also declares an OV fault, flagging the appropriate

status registers, triggering SMBALERT if it is not masked. Then the device enters continuous restart hiccup, or

latch-off according to the VOUT_OV_FAULT_RESPONSE command. The TPS544x25 devices respond to the

output over-voltage condition immediately upon VDD powered up and BP6 regulator voltage above its own

UVLO of 3.73 V typical. The VOUT_OV_FAULT_RESPONSE can also be set to ignore the output overvotlage

fault and continue without interruption. Under this configuration, the control loop continues to respond and adjust

PWM duty cycle in order to keep output voltage within regulation.

If the DIFFO pin voltage falls below the undervoltage protection level defined by VOUT_UV_FAULT_LIMIT after

soft-start has completed, the device terminates normal switching and forces both the high-side and low-side

MOSFETs off, and awaits an external reset or begins a hiccup time-out delay prior to restart, depending on the

value of the VOUT_UV_FAULT_RESPONSE command. The device also declares a UV fault, flagging the

appropriate status registers, triggering SMBALERT if it is not masked. The VOUT_UV_FAULT_RESPONSE can

also be set to ignore the output undervotlage fault and continue without interruption for debug purpose.

The fault response scheme is summarized in Table 6.

8.3.16 TON_MAX Fault

The TON_MAX_FAULT_LIMIT command sets an upper limit, in ms, on how long the unit can attempt to power

up the output without reaching the output undervoltage fault limit. The TPS544x25 devices differentiate a startup

UV fault and

a

regulation UV fault by implementing the TON_MAX_FAULT_LIMIT

.

The

TON_MAX_FAULT_LIMIT can allow the TPS544x25 devices more time than the soft-start time defined by

TON_RISE to come into regulation and the UV detection is essentially delayed up to the

TON_MAX_FAULT_LIMIT time. Refer to PMBus command section TON_MAX_FAULT_LIMIT for more details.

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8.3.17 Power Good (PGOOD) Indicator

When the output voltage remains within the PGOOD window after the start-up period, PGOOD as an open-drain

output is released, and rises to an externally supplied logic level. The PGOOD window is defined by

VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT, which can be programmed through the PMBus

interface, as shown in Figure 39. The PGOOD hystersis window scales with respect to VOUT_SCALE_LOOP,

i.e. the OVW and UVW hystersis window of VOUT_SCALE_LOOP

= 0.5 is twice the size of

VOUT_SCALE_LOOP = 1 and just half of the size of VOUT_SCALE_LOOP = 0.25. The The PGOOD pin pulls

low upon any fault condition on default. Please refer to Table 6 for the possible sources to pull down PGOOD

pin.

The PGOOD signal can be connected to the CNTL pin of another device to provide additional controlled turn-on

and turn-off sequencing.

OV Fault

OV Warn

OVW

Hysteresis

VOUT_COMMAND

UV Warn

(@DIFFO)

UV Fault

UVW

Hysteresis

V

OUT

PGOOD

(non-latch)

Time

(1) V_OUTis measured at the DIFFO pin.

Figure 39. PGOOD Threshold and Hysteresis

NOTE

Pulling PGOOD pin high before the TPS544x25 devices gets input power could cause

PGOOD pin going high due to the limited pull-down capability in un-powered condition. If

this is not desired, increase the pull-up resistance or reduce the external pull-up supply

voltage.

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8.3.19 Switching Node

The SW pin connects to the switching node of the power conversion stage and acts as the return path for the

high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally

traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the

output capacitance (C_OSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100

MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the

input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the

pin.

In many cases, a series resistor and capacitor snubber network connected from the switching node to GND can

be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network

components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin

exceeds the limit, then include snubber components. See SLUP100 for more information about snubber circuits

design.

Placing a BOOT resistor in series with the BOOT capacitor slows down the turn-on of the high-side FET and can

help to reduce the peak ringing at the switching node as well.

8.3.20 PMBus General Description

Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power

Management Protocol Specification, Part 1, revision 1.2 available at http://pmbus.org. The TPS544x25 devices

support both the 100-kHz and 400-kHz bus timing requirements. The devices do not stretch pulses when

communicating with the master device.

Communication over the PMBus interface can support the Packet Error Checking (PEC) scheme if desired. If the

master supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before

a STOP, the PEC is not used.

The devices support a subset of the commands in the PMBus 1.2 Power Management Protocol Specification.

See Supported PMBus Commands for more information

The devices also support the SMBALERT response protocol. The SMBALERT response protocol is a mechanism

by which a slave device (such as the TPS544x25 devices ) can alert the bus master that it is available for

communication. The master processes this event and simultaneously accesses all slaves on the bus (that

support the protocol) through the alert response address (ARA). Only the slave that caused the alert

acknowledges this request. The host performs a modified receive byte operation to ascertain the slave address.

At this point, the master can use the PMBus status commands to query the slave that caused the alert. By

default these devices implement the auto alert response, a manufacturer specific improvement to the

SMBALERT response protocol, intended to mitigate the issue of bus hogging. See Auto ARA Response for more

information. For more information on the SMBus alert response protocol, see the System Management Bus

(SMBus) specification.

The devices contain non-volatile memory that stores configuration settings and scale factors. However, the

device does not save the settings programmed into this non-volatile memory. The STORE_DEFAULT_ALL (11h)

command must be used to commit the current settings to non-volatile memory as device defaults. The settings

that are capable of being stored in non-volatile memory are noted in their detailed descriptions.

8.3.21 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus.

The TPS544x25 devices each have 64 possible addresses (0 through 63 in decimal) that can be assigned by

connecting resistors from the ADDR0 and ADDR1 pins to AGND. The address is set in the form of two octal (0-

7) digits, one digit for each pin. ADDR1 is the high order digit and ADDR0 is the low-order digit. These address

selection resistors must be 1% tolerance or better. Using resistors other than the recommended values can result

in devices responding to adjacent addresses.

The E48 series resistors with no worse than 1% tolerance suggested for each digit value are shown in Table 7.

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Table 7. Required Address

Resistors

DIGIT

RESISTOR VALUE (kΩ)

0

1

2

3

4

5

6

7

8.66

15.4

23.7

34.8

51.1

78.7

121

187

The TPS544x25 devices also detect values that are out of range on the ADDR0 and ADDR1 pins. If the device

detects that either pin has an out-of-range resistance connected to it, the device continues to respond to PMBus

interface commands, but does so at address 127 decimal, which is outside of the possible programmed

addresses. It is possible but not recommended to use the device in this condition, especially if other devices are

present on the bus or if another device could possibly occupy the 127 decimal address.

Certain addresses in the I²C address space are reserved for special functions and it is possible to set the

address of the devices to respond to these addresses. The user is responsible for knowing which of these

reserved addresses are in use in a system and for setting the address of the devices accordingly so as not to

interfere with other system operations. The devices can be set to respond to the global call address or 0. It is

recommended not to set the devices to this address unless the user is certain that no other devices respond to

this address and that the overall bus is not affected by having such an address present.

8.3.22 PMBus Connections

The TPS544x25 devices support both the 100-kHz and 400-kHz bus speeds, 1.8-V or 3.3-V and 5-V PMBus

interface logic level. See the PMBus Interface section of the Electrical Characteristics and PMBus command

OPTIONS (MFR_SPECIFIC_21) (E5h) for more information.

8.3.23 Auto ARA (Alert Response Address) Response

By default, the TPS544x25 devices implement the auto alert response, a manufacturer specific improvement to

the standard SMBALERT response protocol defined in the SMBus specification. The auto alert response is

designed to prevent SMBALERT monopolizing in the case of a persistent fault condition on the bus. The user

can choose to disable the auto ARA response, and use the standard SMBALERT response as defined in the

SMBus specification, by using bit EN_AUTO_ARA of the OPTIONS (MFR_SPECIFIC_21) (E5h) register.

In the case of a fault condition, the slave device experiencing the fault pulls down the shared SMBALERT line, to

alert the host that a fault condition has occurred. To establish which slave device has experienced the fault, the

host issues a modified receive byte operation to the alert response address (ARA), to which only the slave

pulling down on SMBALERT should respond. The SMBus protocol provides a method for address arbitration in

the case that multiple slaves on the same bus are experiencing fault conditions. Once the host has established

the address of the offending device, it must take any necessary action to release the SMBALERT line. For more

information on the standard SMBus alert response protocol, see the System Management Bus (SMBus)

specification.

In the case of a non-persistent fault (a single-time event, such as an invalid command or data byte), the host can

ascertain the address of the slave experiencing a fault using the standard ARA response, and simply issue

CLEAR_FAULTS (03h) to release the SMBALERT line, and resume normal operation. However, in the case of a

persistent fault (one which remains active for some time, such as a short-circuit, or thermal shutdown), once the

device issues a CLEAR_FAULTS (03h) command, the fault immediately re-triggers, and SMBALERT continues

to be pulled low. In this case, the device holds low the SMBALERT line until the host masks the SMBALERT line

using SMBALERT_MASK and then issues the CLEAR_FAULTS (03h) command. Because the SMBALERT line

remains low, the host cannot be alerted to other fault conditions on the bus until it clears SMBALERT. Figure 40

and Figure 41 illustrate this response.

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SMBALERT is not released until CLEAR_FAULTS

is issued by the host

SMBALERT

STATUS_CML

DATA

No Faults

Invalid Command

No Faults

PAGE

HOST

ARA Slave Address

HOST SLAVE

CLEAR_FAULT

HOST

Figure 40. Example Standard ARA Response to Non-Persistent Fault

SMBALERT is low until host masks fault, and issues CLEAR_FAULTS

if the fault condition persists

SMBALERT

STATUS_IOUT

DATA

No Faults

OC FAULT

ARA Slave Address

HOST SLAVE

MASK_SMBALERT

HOST

CLEAR_FAULTS

HOST

Short

Circuit

Figure 41. Example Standard ARA Response to a Persistent Fault

In order to mitigate the problem of SMBALERT bus hogging described previously, the devices implement the

Auto ARA response. When Auto ARA is enabled, the devices releases SMBALERT automatically after

successfully responding to access from the host at the alert response address. In this case, even when the

device is experiencing a persistent fault, it does not hold the SMBALERT line low following successful notification

of the host, and the host can be alerted to other faults on the bus in the normal manner. Examples of the auto

ARA response are illustrated in Figure 42 and Figure 43.

SMBALERT is

released when slave

successfully responds to ARA

SMBALERT

STATUS_CML

DATA

No Faults

Invalid Command

No Faults

PAGE

HOST

ARA Slave Address

HOST SLAVE

CLEAR_FAULT

HOST

Figure 42. Example Auto ARA Response to Non-Persistent Fault

Host must mask SMBALERT or it will re-assert when

CLEAR_FAULTS is issued, if the fault condition persists

SMBALERT is

released when slave

SMBALERT

STATUS_IOUT

DATA

successfully responds to ARA

No Faults

OC FAULT

ARA Slave Address

HOST SLAVE

MASK_SMBALERT

HOST

CLEAR_FAULTS

HOST

Short

Circuit

Figure 43. Example Auto ARA Response to Persistent Fault

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8.4 Device Functional Modes

8.4.1 Continuous Conduction Mode

The TPS544x25 devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the

output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly increased to prevent

excessive current sinking in the event the device is started with a pre-biased output. Following the first 128 clock

cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.

8.4.2 Operation with CNTL Signal Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to use the

CNTL pin to enable or disable regulation, regardless of the state of the OPERATION command. The CNTL pin

can be configured as either active high or active low (inverted) logic.

8.4.3 Operation with OPERATION Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to use the

OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

8.4.4 Operation with CNTL and OPERATION Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to require

both a signal on the CNTL pin, and the OPERATION command to enable or disable regulation.

8.5 Supported PMBus Commands

The commands listed in Table 8 are implemented as described to conform to the PMBus 1.2 specification.

Default behavior and register values are also shown.

Table 8. Supported PMBus Commands and Default Values

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.2

COMMAND NAME

PMBus COMMAND

DESCRIPTION

DEFAULT BEHAVIOR

NVM

Can be configured via

ON_OFF_CONFIG to be used to OPERATION is not used to

turn the output on and off with or enable regulation

without input from the CTRL pin.

01h

OPERATION

00h

No

Configures the combination of

CNTL pin input and OPERATION

command for turning output on

and off.

02h

03h

10h

ON_OFF_CONFIG

CLEAR_FAULTS

WRITE_PROTECT

CNTL only. Active High

16h

n/a

Yes

No

Clears all fault status registers to

Write-only

0x00 and releases SMBALERT.

Used to control writing to the

volaile operating memory

Allow writes to all registers

(PMBus and restore from

00h

Yes

EEPROM).

Stores all current storable

register settings into EEPROM as Write-only

new defaults.

11h

12h

19h

STORE_DEFAULT_ALL

RESTORE_DEFAULT_ALL

CAPABILITY

n/a

No

Restores all storable register

Write-only

settings from EEPROM.

Provides a way for a host system

Read only. PMBus v1.2,

to determine key PMBus

400 kHz, PEC enabled

B0h

capabilities of the device.

1Bh

20h

21h

SMBALERT_MASK

VOUT_MODE

Mask Warn or Fault status bits

Read-only output mode indicator. Linear, exponent = –9

Default Regulation Setpoint 950mV

Mask PGOODz only

n/a

17h

Yes

No

VOUT_COMMAND

01E6h

Yes

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Supported PMBus Commands (continued)

Table 8. Supported PMBus Commands and Default Values (continued)

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.2

COMMAND NAME

PMBus COMMAND

DESCRIPTION

DEFAULT BEHAVIOR

NVM

Sets the maximum output

voltage. VOUT_MAX imposes a

higher bound to any attempted

V_OUTsetting from

24h

VOUT_MAX

1.5V

0300h

No

VOUT_COMMAND and VSET

pin default.

Sets the rate at which the output

should change voltage.

27h

29h

VOUT_TRANSITION_RATE

VOUT_SCALE_LOOP

1 mV/us

1

D03Ch

F004h

No

Sets output sense scaling ratio

for main control loop.

Yes

Sets value of input voltage at

which the device should start

power conversion.

35h

36h

VIN_ON

4.5 V

4.0V

F012h

F010h

Yes

Sets value of input voltage at

which the device should stop

power conversion.

VIN_OFF

Can be set to null out offsets in

the current sensing circuit.

39h

40h

41h

42h

43h

44h

45h

IOUT_CAL_OFFSET

0.0000 A

1.281 V

Restart

1.201 V

0.631 V

0.594 V

Restart

E000h

0290h

BFh

Yes

No

Sets output overvoltage fault

threshold.

VOUT_OV_FAULT_LIMIT

VOUT_OV_FAULT_RESPONSE

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

VOUT_UV_FAULT_RESPONSE

Sets output overvoltage fault

response.

Sets output overvoltage warning

threshold.

0267h

0143h

0130h

BFh

Sets output undervoltage warning

threshold.

No

Sets output undervoltage fault

threshold.

Yes

Sets output undervoltage fault

response.

Sets the value of the output

current that causes an

overcurrent fault condition.

36 A (TPS544C25)

24 A (TPS544B25)

F848h

F830h

46h

47h

4Ah

4Fh

50h

IOUT_OC_FAULT_LIMIT

Yes

No

Sets response to output

IOUT_OC_FAULT_RESPONSE overcurrent faults to latch-off,

hiccup mode or ignore.

Restart

BFh

Sets the value of the output

current that causes an

overcurrent warning condition.

34 A (TPS544C25)

22 A (TPS544B25)

F844h

F82Ch

IOUT_OC_WARN_LIMIT

OT_FAULT_LIMIT

Sets the value of the sensed

temperature that causes an

overtemperature fault condition.

125 °C

Restart

007Dh

BFh

Yes

Sets response to over

temperature faults to latch-off,

hiccup mode or ignore.

OT_FAULT_RESPONSE

Sets the value of the sensed

temperature that causes an

overtemperature warning

condition.

51h

60h

61h

OT_WARN_LIMIT

TON_DELAY

TON_RISE

100 °C

0 ms

0064h

0000h

0005h

No

Yes

Sets the turn-on delay.

Sets the time from when the

output starts to rise until the

voltage has entered the

regulation band.

5 ms

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Supported PMBus Commands (continued)

Table 8. Supported PMBus Commands and Default Values (continued)

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.2

PMBus COMMAND

DESCRIPTION

DEFAULT BEHAVIOR

NVM

COMMAND NAME

TON_MAX_FAULT_LIMIT

TON_MAX_FAULT_RESPONSE

Sets an UPPER limt in

milliseconds, on how long the

unit can attempt to power up the

output without reaching the

output undervoltage fault limit.

The time begins counting as the

device enters the soft-start

period.

62h

63h

100 ms

0064h

BFh

No

Sets the soft start timeout fault

response.

Restart

Yes

64h

65h

TOFF_DELAY

TOFF_FALL

Sets the turn-off delay.

0 ms

0000h

Yes

Sets the soft stop fall time.

Returns one byte summarizing

the most critical faults.

78h

79h

STATUS_BYTE

STATUS_WORD

Read only

Current status

No

Returns two bytes summarizing

fault and warning conditions.

Returns one byte detailing if an

output fault or warning has

occurred

7Ah

7Bh

7Ch

7Dh

7Eh

STATUS_VOUT

Read only

Current status

No

Retyrns one byte detailing if an

overcurrent fault or warning has

occurred

STATUS_IOUT

Returns one byte of information

relating to the status of the

converter's input related faults.

STATUS_INPUT

STATUS_TEMPERATURE

STATUS_CML

Returns one byte detailing if a

sensed temperature fault or

warning has occurred.

Returns one byte containing

PMBus serial communication

faults.

Returns one byte detailing if

internal overtemperature or

address detection fault has

occurred.

80h

STATUS_MFR_SPECIFIC

Read only

Current status

No

Returns the output voltage in

volts.

8Bh

8Ch

READ_VOUT

READ_IOUT

Read only

Current status

No

Returns the output current in

amps.

Read-only, 25 C

whenSS_DET_DIS in

OPTIONS

(MFR_SPECIFIC_21) (E5h)

= 0.

Returns the sensed temperature

in degrees Celsius.

8Eh

98h

READ_TEMPERATURE_2

PMBUS_REVISION

0019h

12h

No

Returns PMBus revision to which

the device is compliant.

Read only

0.5 V

Sets the minimum output voltage.

MFR_VOUT_MIN imposes a

lower bound to any attempted

V_OUTsetting from

A4h

MFR_VOUT_MIN

0100h

No

VOUT_COMMAND and VSET

pin default.

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Supported PMBus Commands (continued)

Table 8. Supported PMBus Commands and Default Values (continued)

DEFAULT

REGISTER

VALUE

CMD

CODE

PMBus 1.2

COMMAND NAME

PMBus COMMAND

DESCRIPTION

DEFAULT BEHAVIOR

NVM

This Read-only Block Read

command returns a single word

(16 bits) with the unique Device

Code identifier for each device

for which this IC can be

configured. The BYTE_COUNT

field in the Block Read command

is 2 (indicating 2 bytes follow):

Low Byte first, then High Byte.

TPS544C25

0027h

ADh

IC_DEVICE_ID

No

TPS544B25

0028h

This Read-only Block Read

command returns a single word

(16 bits) with the unique Device

revision identifier. The

BYTE_COUNT field in the Block

Read command is 2 (indicating 2

bytes follow): Low Byte first, then

High Byte.

AEh

D0h

IC_DEVICE_REV

Read only

0000h

No

MFR_SPECIFIC_00

User scratch pad.

Yes

Sets user selectable options.

Options register: Disable SS

detection, Enable Auto Alert

Response Address response

(ARA), ADC averaging, Enable

Data limit override, Enable ADC,

Enable Vout Scan Mode, Enable

auto PMBus rail logic level

detection and Force PMBus rail

logic level.

Enable SS detection, auto

ARA, ADC conversion,

PMBus auto detection, 8x

average for V/I/T reporting,

and force 1.8V logic

E5h

OPTIONS (MFR_SPECIFIC_21)

00C7h

Yes

The SYNC/RESET_B pin

operates as RESET_B if

VSET detection is valid;

default trim for HS OC; for

OVP response, the LS FET

latches on when an OV

fault is detected, and turns

off as soon as the sensed

output (at DIFFO pin) drops

below the UV fault

Sets miscellaneous user

MISC_CONFIG_OPTIONS

(MFR_SPECIFIC_32)

selectable options. Options

register: Force SYNC, HSOC

user trim, OVP response options.

F0h

0001h

Yes

threshold.

8.6 Register Maps

This family of devices supports the following commands from the PMBus 1.2 specification.

Register Access Legend:

•

r- read

w - write

superscript E – the bit is backed up with Non-volatile EEPROM

8.6.1 OPERATION (01h)

The OPERATION command turns the device output on or off in conjunction with input from the CNTL signal. It is

also used to set the output voltage to the upper or lower margin voltages. The unit stays in the commanded

operating mode until a subsequent OPERATION command or a change in the state of the CNTL pin instructs the

device to change to another mode.

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COMMAND

Format

OPERATION

Unsigned binary

Bit Position

Access

7

r/w

ON

0

6

r/w

OFF

0

5

r

4

r

3

r

2

r

1

r

0

r

Function

X

Default Value

8.6.1.1 On

This bit is an enable command to the converter.

•

0: output switching is disabled. Both drivers placed in an off or low state.

1: output switching is enabled if the input voltage is above undervoltage lockout, OPERATION is configured

as a gating signal in ON_OFF_CONFIG, and no fault conditions exist.

8.6.1.2 Off

This bit sets the turn-off behavior when commanding the unit to turn off via OPERATION[7] ( the “ On“ bit).

•

0: Immediately turn off the output (not honoring the programmed turn-off delay (TOFF_DELAY) and ramp

down (TOFF_FALL)) when commanded off via OPERATION[7] ( the “ On“ bit).

•

1: Use the programmed turn-off delay (TOFF_DELAY) and ramp down (TOFF_FALL) when commanded off

via OPERATION[7] – aka “soft off”.

NOTE

The device ignores any values written to read-only bits. Additionally, both “on” and “off”

bits being set at the same time is not allowed and considered invalid data per section 12.1

of the PMBus Specification Part II; any attempt to do so causes the device to set the ’cml’

bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and triggers

SMBALERT signal.

8.6.2 ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands

needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL (11h) command. The default value in ON_OFF_CONFIG register is to have the device

power up by CNTL pin only with the active high polarity and use the programmed turn-off delay (TOFF_DELAY)

and ramp down (TOFF_FALL) for powering off the converter.

COMMAND

Format

ON_OFF_CONFIG

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r/w^E

pu

1

3

2

r/w^E

cpr

1

r/w^E

pol

1

0

r/w^E

cpa

0

r/w^E

cmd

0

Function

X

Default Value

8.6.2.1 pu

The pu bit sets the default to either operate any time power is present or for power conversion to be controlled by

CNTL pin and PMBus OPERATION command. This bit is used in conjunction with the 'cpr', 'cmd', and 'on' bits to

determine start up.

BIT VALUE

ACTION

0

Device powers up any time power is present regardless of state of the CNTL pin.

Device does not power up until commanded by the CNTL pin and/or OPERATION

command as programmed in bits [3:0] of the ON_OFF_CONFIG register.

1

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8.6.2.2 cmd

The cmd bit controls how the device responds to the OPERATION command. This bit is used in conjunction with

the 'cpr', 'pu', and 'on' bits to determine start up.

BIT VALUE

ACTION

0

1

Device ignores the “on” bit in the OPERATION command.

Device responds to the “on” bit in the OPERATION command.

8.6.2.3 cpr

The cpr bit sets the CNTL pin response. This bit is used in conjunction with the 'cmd', 'pu', and 'on' bits to

determine start up.

BIT VALUE

ACTION

Device ignores the CNTL pin. Power conversion is controlled only by the OPERATION

command.

0

1

Device requires the CNTL pin to be asserted to start the unit.

8.6.2.4 pol

The pol bit controls the polarity of the CNTL pin. For a change to become effective, the contents of the

ON_OFF_CONFIG register must be stored to non-volatile memory using the STORE_DEFAULT_ALL command

and the device power cycled. Simply writing a new value to this bit does not change the polarity of the CNTL pin.

BIT VALUE

ACTION

0

1

CNTL pin is active low.

CNTL pin is active high.

8.6.2.5 cpa

The cpa bit sets the CNTL pin action when turning the converter off.

BIT VALUE

ACTION

0

Use the programmed turn-off delay (TOFF_DELAY) and ramp down (TOFF_FALL).

Immediately turn off the output (not honoring the programmed turn-off delay

(TOFF_DELAY) and ramp down (TOFF_FALL)).

1

8.6.3 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits

in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT

signal output if the device is asserting the SMBALERT signal. The CLEAR_FAULTS command does not cause a

unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault

bit is immediately reset and the host notified by the usual means.

NOTE

•

To get a reliable clear fault result, the clear_fault command should be issued (8 ×

TON_RISE + TON_DELAY) after the switcher shuts down.

In the case of OV fault with “latch off” response, the LS FET latches on when the fault

is detected. If the OV_RESP_SEL bit in (F0h) MFR_SPECIFIC_32 is set to 1, then the

LS FET releases when the output voltage falls below the VOUT_UV_FAULT_LIMIT.

Otherwise, it remains on until the CLEAR_FAULTS command is issued. The CLEAR

FAULTS command causes the LS FET to turn off.

•

To clear an OV fault, two CLEAR_FAULTS commands need to be issued and the OVF

cannot be cleared the first time, but the second time.

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8.6.4 WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is

to provide protection against accidental changes. This command is not intended to provide protection against

deliberate or malicious changes to the device configuration or operation. All supported command parameters

may have their parameters read, regardless of the WRITE_PROTECT settings. Write protection also prevents

protected registers from being updated in the event of a RESTORE_DEFAULT_ALL. The contents of this register

can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

COMMAND

Format

WRITE_PROTECT

Unsigned binary

Bit Position

Access

7

r/w^E

bit7

0

6

r/w^E

bit6

0

5

r/w^E

bit5

0

4

X

3

X

2

X

1

X

0

X

Function

Default Value

8.6.4.1 bit5

8.6.4.2 bit6

8.6.4.3 bit7

BIT VALUE

ACTION

0

Enable all writes as permitted in bit6 or bit7

Disable all writes except the WRITE_PROTECT, OPERATION, ON_OFF_CONFIG,

and VOUT_COMMAND. (bit6 and bit7 must be 0 to be valid data)

1

BIT VALUE

ACTION

0

Enable all writes as permitted in bit5 or bit7

Disable all writes except for the WRITE_PROTECT, and OPERATION commands. (bit5

and bit7 must be 0 to be valid data)

1

BIT VALUE

ACTION

0

Enable all writes as permitted in bit5 or bit6

Disable all writes except for the WRITE_PROTECT command. (bit5 and bit6 must be 0

to be valid data)

1

In any case, only one of the three bits may be set at any one time. Attempting to set more than one bit results in

an alert being generated and the cml bit is STATUS_WORD being set. An invalid setting of the

WRITE_PROTECT command results in no write protection.

Data Byte

ACTION

Value

1000 0000

0100 0000

Disables all WRITES except to the WRITE_PROTECT command.

Disables all WRITES except to the WRITE_PROTECT, and OPERATION commands.

Disables all WRITES except to the WRITE_PROTECT, OPERATION,

ON_OFF_CONFIG, and VOUT_COMMAND commands.

0010 0000

8.6.5 STORE_DEFAULT_ALL (11h)

The STORE_DEFAULT_ALL command stores all of the current storable register settings in the EEPROM

memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to

switch but ignores all fault conditions until the internal store process has completed. Issuing

STORE_DEFAULT_ALL also causes the device to be unresponsive via PMBus for a period of ~100ms.

EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the

'mem' bit in the STATUS_CML registers.

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8.6.6 RESTORE_DEFAULT_ALL (12h)

The RESTORE_DEFAULT_ALL command restores all of the storable register settings from EEPROM memory to

those registers which are unprotected according to current setting of WRITE_PROTECT. Issuing

STORE_DEFAULT_ALL also causes the device to be unresponsive via PMBus for a period of ~100ms.

NOTE

Do not use this command while the device is actively switching, this causes the device to

stop switching and the output voltage to fall during the restore event. Depending on

loading conditions, the output voltage could reach an undervoltage level and trigger an

undervoltage fault response if programmed to do so. The command can be used while the

device is switching, but it is not recommended as it results in a restart that could disrupt

power sequencing requirements in more complex systems. It is strongly recommended

that the device be stopped before issuing this command.

8.6.7 CAPABILITY (19h)

The CAPABILITY command provides a way for a host system to determine some key capabilities of this PMBus

device.

COMMAND

Format

CAPABILITY

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

3

r

2

r

1

r

0

r

ALRT

1

Function

PEC

1

SPD

Reserved

Default Value

0

1

0

The default values indicate that the device supports Packet Error Checking (PEC), a maximum bus speed of 400

kHz (SPD) and the SMBus Alert Response Protocol using SMBALERT.

8.6.8 SMBALERT_MASK (1Bh)

The SMBALERT_MASK command may be used to prevent a warning or fault condition from asserting the

SMBALERT signal.

NOTE

The command uses the SMBus Write Word command protocol to overlay a “mask byte”

with an associated/designated status register. It uses the SMBus Block Write/Block Read

protocol – with a block size = 1, to read the mask settings for any given status register. If

the host in the Block_Count field of the Block Write portion sends a block size unequal to

1 the device returns a NACK. The device always returns a Block Count of 1 upon reads of

SMBALERT_MASK.

The bits in the mask byte align with the bits in the corresponding status register. For example, if the

STATUS_TEMPERATURE command were sent with the mask byte 01000000b, then an Over Temperature

Warning condition would be blocked from asserting SMBALERT. Please refer to the PMBus v1.2 specification -

section 15.38 (SMBALERT_MASK Command) and the SMBus specification Block Write/Block Read protocol for

further details.

There are 19 maskable SMBALERT sources in the TPS544x25. Each of these 19 status conditions has an

associated EEPROM backed mask bit. These sources are represnted and identified in the status register

command descriptions by a particular status bit denoted as having EEPROM backup (e.g. a bit access of r/w^E).

Writes and reads to SMBALERT_MASK command code accepts only the following as valid STATUS_x

command codes:

•

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

STATUS_INPUT

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•

STATUS_TEMPERATURE

STATUS_CML

STATUS_MFR_SPECIFIC

Attempting to write a mask byte for any STATUS_X command code other than this list causes the device to set

the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and triggers SMBALERT.

Attempting to read a mask byte for any STATUS_x command code other than this list returns 00h for the mask

byte. Refer to these individual command descriptions for further details on their specific smbalert masking

capabilities.

There is

1

unique status bit in the TPS544x25 that warrants special clarification: PGOOD_Z

(STATUS_WORD[10]) is maskable as an SMBALERT source via SMBALERT_MASK commands to

STATUS_WORD. If the user wants to write, or read, the mask bit for PGOOD_Z, they must put ‘79h’ in the

STATUS_x COMMAND_CODE field of the SMBALERT_MASK command. PGOOD_Z SMBALERT_MASK bit

default to 1.

8.6.9 VOUT_MODE (20h)

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of

a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the

Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the

linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the

values.

COMMAND

Bit Position

VOUT_MODE

7

r

6

5

r

4

r

3

r

2

1

r

0

r

Access

r

Mode

0

r

Exponent

1

Function

Default Value

0

1

0

1

8.6.9.1 Mode:

Value fixed at 000, linear mode.

8.6.9.2 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count).

8.6.10 VOUT_COMMAND (21h)

The VOUT_COMMAND command sets the output voltage in volts. The contents of this register can be stored to

non-volatile memory using the STORE_DEFAULT_ALL command. The exponent is set be VOUT_MODE at –9

(equivalent of 1.953 mV/count). The programmed the output voltage is computed as:

V_OUT= VOUT_COMMAND × VOUT_MODE (V) = VOUT_COMMAND × 2^–9(V)

(4)

The range of valid VOUT_COMMAND values is dependent upon the configured VOUT_SCALE_LOOP (29h) as

follows:

VOUT_SCALE_L

Vout Range (volts)

VOUT_COMMAND data valid range

OOP

1

0.5 – 1.5

1 – 3

256 - 768

512 - 1536

1024 - 3072

0.5

0.25

2 – 6

There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:

•

The first case is if the value programmed to VOUT_COMMAND exceeds the value stored in either

MFR_VOUT_MIN (A4h) or VOUT_MAX (24h). In this case, VOUT_COMMAND is set to the appropriate

MFR_VOUT_MIN or VOUT_MAX value (which ever was violated). See the command descriptions for

MFR_VOUT_MIN (A4h) or VOUT_MAX (24h) for the specific status bits set in either case.

•

The second case is if VOUT_COMMAND is attempted to be programmed outside the OV and UV warn limits.

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In this case, the VOUT_COMMAND value remains unchanged. Specifically, the following relationships must

be maintained:

•

VOUT_COMMAND < VOUT_OV_WARN_LIMIT

VOUT_COMMAND > VOUT_UV_WARN_LIMIT

In this second case where VOUT_COMMAND is attempted to be programmed outside the OV or UV Warn limits,

it causes the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and

triggers SMBALERT signal.

When using the VSET function, at initial power-up. the Mantissa value decoded according to the appropriate

VSET resistor is written into the VOUT_COMMAND register as the initial default. Note this overwrites any value

restored from EEPROM when the device VDD is powered up.

COMMAND

Format

VOUT_COMMAND

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r/w^Er/w^Er/w^Er/w^E

r/w^E

Mantissa

1

Function

Default Value

0

1

0

1

0

8.6.10.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.10.2 Mantissa

This is the Mantissa for the linear format. Default value is: 0000 0001 1110 0110 (bin) 486 (dec) (equivalent Vout

default = 0.95V).

8.6.11 VOUT_MAX (24h)

The VOUT_MAX command sets the maximum output voltage. The purpose is to protect the device(s) on the

output rail supplied by this device from a higher than acceptable output voltage. VOUT_MAX imposes an upper

bound to any attempted output voltage setting:

a) programmed VOUT_COMMAND

b) VSET pin default

If any attempt is made to program the output voltage (using the VOUT_COMMAND ) in excess of the value in

VOUT_MAX, the device also:

•

Clamps the output voltage at the programmed VOUT_MAX value

Sets the OTH (other) bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the VOUT_MAX_Warning bit in the STATUS_VOUTregister

Notifies the host via the SMBALERT pin

The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed output voltage is

computed as:

MAXIMUM VOUT allowed = VOUT_MAX × VOUT_MODE (V) = VOUT_MAX × 2^–9(V)

(5)

There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:

•

If the commanded VOUT_MAX is outside the valid data range for the VOUT_SCALE_LOOP configured, but,

is still relationally correct (above VOUT_COMMAND). In this case, that value is not accepted; but,

VOUT_MAX is set to the highest allowed value.

•

The second case is the opposite, where the attempted write value is within the absolute range of

VOUT_MAX; but, is not relationally correct (it is below VOUT_COMMAND). In this case, VOUT_MAX remains

unchanged.

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Both cases equally cause the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the

STATUS_CML registers, and triggers SMBALERT signal.

COMMAND

Format

VOUT_MAX

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

Mantissa

8.6.11.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95 mV/count, specified in

VOUT_MODE command).

8.6.11.2 Mantissa

The range of valid VOUT_MAX values is dependent upon the configured (29h) VOUT_SCALE_LOOP as follows.

If VOUT_SCALE_LOOP = 1:

•

default: 0000 0011 0000 0000 (bin) 768 (dec) (equivalent output voltage default = 1.5V)

Minimum : 0000 0001 0001 1010 (bin) 282 (dec) (equivalent VOUT_MAX = 0.55V)

Maximum: 0000 0011 0000 0000 (bin) 768 (dec) (equivalent VOUT_MAX = 1.5V)

If VOUT_SCALE_LOOP = 0.5:

•

default: 0000 0110 0000 0000 (bin) 1536 (dec) (equivalent output voltage default = 3V)

Minimum : 0000 0010 0011 0100 (bin) 564 (dec) (equivalent VOUT_MAX = 1.1V)

Maximum: 0000 0110 0000 0000 (bin) 1536 (dec) (equivalent VOUT_MAX = 3V)

If VOUT_SCALE_LOOP = 0.25:

•

default: 0000 1100 0000 0000 (bin) 3072 (dec) (equivalent output voltage default = 6V)

Minimum : 0000 0100 0110 1000 (bin) 1128 (dec) (equivalent VOUT_MAX = 2.2V)

Maximum: 0000 1100 0000 0000 (bin) 3072 (dec) (equivalent VOUT_MAX = 6V)

8.6.12 VOUT_TRANSITION_RATE (27h)

The VOUT_TRANSITION_RATE command sets the rate of change in mV/µs of any output voltage change

during normal operation (also includes vout changes in TOFF_DELAY state. In contrast Soft Start transition rate

is controlled by TON_RISE and the TOFF_FALL transition rate is controlled by TOFF_FALL command).

Only 8 fixed output voltage transition rates are available in the device. As such, the range of programmed

vout_transition rates are sub-divided into 8 “buckets” that then selects one of the 8 fixed V_OUTtransition rates.

Programmed values are rounded to the nearest “bucket/transition rate” as outlined in the table below.

COMMAND

Format

VOUT_TRANSITION_RATE

Linear, two’s complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

r/w

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

1

Default Value

1

0

1

0

8.6.12.1 Exponent

default: 11010 (bin) -6 (dec) (0.015625)

These default settings are not programmable.

8.6.12.2 Mantissa

default: 000 0011 1100 (bin) 60 (dec) (equivalent VOUT_TRANSITION_RATE = 1mV/µs)

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NOTE

It is possible to use VOUT_TRANSITION_RATE to slew Vref faster than the voltage loop

can track. This causes a control related overshoot/undershoot response on the output

voltage.

VOUT_TRANSITI

VOUT_TRANSITION Mantissa (d)

ON rate (mV/µs)

Greater than

Less than or equal to

0.067

0.1

5

7

0.143

0.222

0.333

0.5

7

12

17

25

47

79

12

17

25

47

79

1

1.5

8.6.13 VOUT_SCALE_LOOP (29h)

VOUT_SCALE_LOOP is equal to the feedback resistor ratio ( R_BIAS/( R_BIAS+R1) in the configuration shown in

Figure 33). It is limited to only 3 possible options/ratios: 1 (default, no R_BIASneeded), 0.5, and 0.25. Attempting to

write a value unequal to one of these three options cause the device to set the ’cml’ bit in the STATUS_BYTE,

and the ‘ivd’ bit in the STATUS_CML registers. Additionally, SMBALERT is asserted and the value of

VOUT_SCALE_LOOP remains unchanged. The contents of this register can be stored to non-volatile memory

using the STORE_DEFAULT_ALL command.

NOTE

Construct the feedback resistor ratio appropriately (see Table 1).

Program the VOUT_SCALE_LOOP setting before the output is turned on.

In order for the range checking to work properly and to avoid Invalid Data scenarios:

•

VOUT_SCALE_LOOP should be changed first, if needed.

Any changes to these registers should be made such that:

–

The values in all the registers conform to the limits for the current VOUT_SCALE_LOOP setting

The order below is optimum for programming the output voltage upwards (not all commands may be

necessary)

–

(40h) VOUT_OV_FAULT_LIMIT

(42h) VOUT_OV_WARN_LIMIT

(24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT

is irrelevant. Just set VOUT_MAX prior to VOUT_COMMAND)

–

(21h) VOUT_COMMAND

(A4h)

MFR_VOUT_MIN

(ordering

with

respect

to

VOUT_UV_FAULT_LIMIT

and

VOUT_UV_WARN_LIMIT is irrelevant. Just set MFR_VOUT_MIN after VOUT_COMMAND)

–

(43h) VOUT_UV_WARN_LIMIT

(44h) VOUT_UV_FAULT_LIMIT

–

The order below is optimum for programming the output voltage downwards (not all commands may be

necessary)

–

(44h) VOUT_UV_FAULT_LIMIT

(43h) VOUT_UV_WARN_LIMIT

(A4h)

MFR_VOUT_MIN

(ordering

with

respect

to

VOUT_UV_FAULT_LIMIT

and

VOUT_UV_WARN_LIMIT is irrelevant. Simply set MFR_VOUT_MIN prior to VOUT_COMMAND)

–

(21h) VOUT_COMMAND

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–

(24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT

is irrelevant. Simply set VOUT_MAX after VOUT_COMMAND)

–

(42h) VOUT_OV_WARN_LIMIT

(40h) VOUT_OV_FAULT_LIMIT

COMMAND

Format

VOUT_SCALE_LOOP

Linear, two’s complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

1

r

Mantissa

0

Function

Default Value

1

0

1

0

8.6.13.1 Exponent

default: 11110 (bin) -2 (dec) (equivalent LSB=0.25)

These default settings are not programmable.

8.6.13.2 Mantissa

default: 000 0000 0100 (bin) 4 (dec) (equivalent VOUT_SCALE_LOOP voltage = 1)

For VOUT_SCALE_LOOP = 1.00, mantissa = 004h. (4 × 2^–2= 1.00)

For VOUT_SCALE_LOOP = 0.50, mantissa = 002h. (2 × 2^–2= 0.50)

For VOUT_SCALE_LOOP = 0.25, mantissa = 001h. (1 × 2^–2= 0.25)

8.6.14 VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all

other required startup conditions are met. Values are mapped to the nearest supported increment. Values

outside the supported range are treated as invalid data and cause the device set the CML bit in the

STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers, and trigger SMBALERT signal. The

value of VIN_ON remains unchanged on an out-of-range write attempt. The contents of this register can be

stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The supported VIN_ON values are shown in Table 9:

Table 9. Supported VIN_ON Values

VIN_ON Values (V)

4.25

5.5

4.5 (default)

4.75

6

5

5.25

6.5

5.75

7

6.25

7.5

6.75

7.25

7.75

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON results in the new value being rejected, SMBALERT signal being asserted along with the

CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The

four most significant bits of the mantissa are fixed, while the lower 4 bits may be altered.

COMMAND

Format

VIN_ON

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

1

r

Mantissa

0

Function

Default Value

1

0

1

0

1

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8.6.14.1 Exponent

default: 11110 (bin) -2 (dec) (equivalent LSB=0.25V)

These default settings are not programmable.

8.6.14.2 Mantissa

default: 000 0001 0010 (bin) 18 (dec) (equivalent VIN_ON voltage = 4.5V)

Minimum : 000 0001 0001 (bin) 17 (dec) (equivalent VIN_ON voltage = 4.25V)

Maximum: 000 0001 1111 (bin) 31 (dec) (equivalent VIN_ON voltage = 7.75V)

8.6.15 VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are

mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers, and trigger SMBALERT signal. The value of VIN_OFF remains unchanged during an out-of-range write

attempt. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL

command.

The supported VIN_OFF values are shown in Table 10:

Table 10. Supported VIN_OFF Values

VIN_OFF Values (V)

4 (default)

5.25

4.25

5.5

4.5

5.75

7

4.75

6

5

6.25

7.5

6.5

6.75

7.25

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the cml bit in

STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The

4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

COMMAND

Format

VIN_OFF

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

1

r

Mantissa

0

Function

Default Value

1

0

1

0

8.6.15.1 Exponent

default: 11110 (bin) -2 (dec) (equivalent LSB=0.25V)

These default settings are not programmable.

8.6.15.2 Mantissa

default: 000 0001 0000 (bin) 16 (dec) (equivalent VIN_OFF voltage = 4.0V)

Minimum : 000 0001 0000 (bin) 16 (dec) (equivalent VIN_OFF voltage = 4.0V)

Maximum: 000 0001 1110 (bin) 30 (dec) (equivalent VIN_OFF voltage = 7.50V)

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8.6.16 IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the

IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is

0 A. The resolution of the argument for this command is 62.5 mA and the range is +3.9375 A to -4.0 A. Values

written outside of this range alias into the supported range. This occurs because the read-only bits are fixed. The

exponent is always –4 and the 5 msb bits of the Mantissa are always equal to the sign bit. The contents of this

register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

COMMAND

Format

IOUT_CAL_OFFSET

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r/w^E

1

r

0

r

7

r

6

r

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

1

Function

Mantissa

0

Default Value

1

0

8.6.16.1 Exponent

default: 11100 (bin) -4 (dec) (lsb=62.5mA)

These default settings are not programmable.

8.6.16.2 Mantissa

MSB is programmable with sign, next 4 bits are sign extend only.

Lower six bits are programmable with a default value of 0 (dec).

8.6.17 VOUT_OV_FAULT_LIMIT (40h)

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage that causes an output overvoltage

fault. Attempts to write values outside of the acceptable range is treated as invalid data, causing the device to set

the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert

the SMBALERT signal. Additionally, the value of VOUT_OV_FAULT_LIMIT remains unchanged. Maintaining

values within “acceptable range” also means:

VOUT_OV_WARN_LIMIT < VOUT_OV_FAULT_LIMIT < (922d/VOUT_SCALE_LOOP)

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Note the lower 4 bits can not be backed up in EEPROM.

The VOUT_OV_FAULT_LIMIT takes a two-byte data word formatted as shown below:

COMMAND

Format

VOUT_OV_FAULT_LIMIT

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

r/w^E

5

r/w^E

4

r/w^E

3

2

1

0

r/w^Er/w^Er/w^Er/w^E

r/w^E

Mantissa

1

r/w

Function

Default Value

0

1

0

1

0

8.6.17.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.17.2 Mantissa

default: 0000 0010 1001 0000 (bin) 656 (dec) (equivalent OVF 1.281 V or 134.8% of 0.95 V default reference

(VOUT_COMMAND))

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NOTE

Changing the VOUT_OV_FAULT_LIMIT (or Warn, or UV Fault, or Warn limit) during

regulation causes a brief overshoot/undershoot on the output voltage. This is due to the

Vref DAC being shared with OVUV DAC.

8.6.18 VOUT_OV_FAULT_RESPONSE (41h)

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to a

VOUT_OV_FAULT_LIMIT fault. The device also:

•

Sets the OVF bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the OVF bit in the STATUS_VOUT register, and

Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a output

overvoltage fault.

The default response to a output overvoltage fault is to shut down and restart with 7 × TON_RISE time delay.

COMMAND

Format

VOUT_OV_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w^E

RSP[1]

1

6

r

5

r/w^E

RS[2]

1

4

r/w

3

r/w

2

r

1

r

0

r

Function

0

RS[1]

1

RS[0]

1

X

1

X

1

X

1

Default Value

8.6.18.1 RSP[1]

This bit sets the output voltage over voltage response to either ignore or not. Default is 1.

0:

The PMBus device continues operation without interruption. Note: In this “ignore” fault response

mode, the associated fault status bits is set. Additionally, SMBALERT remains triggered if it is not

masked.

1:

The PMBus device shuts down and restarts according to RS[2:0].

8.6.18.2 RS[2:0]

These bits are output voltage over voltage retry setting. Default is 111b.

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.

8.6.19 VOUT_OV_WARN_LIMIT (42h)

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage that causes an output overvoltage

warning condtion. Attempts to write values outside of the acceptable range is treated as invalid data, causing the

device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as

well as assert the SMBALERT signal. Additionally, the value of VOUT_OV_WARN_LIMIT remains unchanged.

Maintaining values within “acceptable range” also means:

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•

VOUT_COMMAND < VOUT_OV_WARN_LIMIT < VOUT_OV_FAULT_LIMIT

269d < VOUT_OV_WARN_LIMIT × VOUT_SCALE_LOOP

The device also:

•

Sets the oth bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the OVW bit in the STATUS_VOUT register, and

Notifies the host by asserting SMBALERT

The VOUT_OV_WARN_LIMIT takes a two-byte data word formatted as shown below:

COMMAND

Format

VOUT_OV_WARN_LIMIT

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Mantissa

0

r/w

Function

Default Value

0

1

0

1

0

1

8.6.19.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.19.2 Mantissa

default: 0000 0010 0110 0111 (bin) 615(dec) (equivalent OVW 1.201 V or 126.4% of 0.95 V default reference

(VOUT_COMMAND))

Note: The default VOUT_OV_WARN_LIMIT is calculated from the EEPROM backed OVF limit by:

VOUT_OV_WARN_LIMIT = VOUT_OV_FAULT_LIMIT - VOUT_OV_FAULT_LIMIT/16

If the calculated value for VOUT_OV_WARN_LIMIT violates the requirement that VOUT_COMMAND <

VOUT_OV_WARN_LIMIT, then the VOUT_OV_WARN_LIMIT value is set to VOUT_OV_FAULT_LIMIT - 1 LSB.

NOTE

Changing the VOUT_OV_WARN_LIMIT (or Fault, or UV Fault, or Warn limit) during

regulation causes a brief overshoot/undershoot on the output voltage. This is due to the

Vref DAC being shared with OVUV DAC.

8.6.20 VOUT_UV_WARN_LIMIT (43h)

The VOUT_UV_WARN_LIMIT command sets the value of the output voltage that causes an output undervoltage

warning condtion. This warning is masked until the unit reaches the programmed output voltage. This warning is

also masked when the unit is disabled. Attempts to write values outside of the acceptable range is treated as

invalid data, causing the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the

STATUS_CML registers as well as assert the SMBALERT signal. Additionally, the value of

VOUT_UV_WARN_LIMIT remains unchanged. Maintaining values within “acceptable range” also means:

•

VOUT_UV_FAULT_LIMIT < VOUT_UV_WARN_LIMIT < VOUT_COMMAND

178d < VOUT_UV_WARN_LIMIT × VOUT_SCALE_LOOP < 732d

The device also:

•

Sets the oth bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the UVW bit in the STATUS_VOUT register, and

Notifies the host by asserting SMBALERT

The VOUT_UV_WARN_LIMIT takes a two-byte data word formatted as shown below:

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COMMAND

Format

VOUT_UV_WARN_LIMIT

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Mantissa

0

r/w

Function

Default Value

0

1

0

1

8.6.20.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.20.2 Mantissa

default: 0000 0001 0100 0011 (bin) 323(dec) (equivalent UVW 0.631 V or 66.4% of 0.95 V default reference

(VOUT_COMMAND))

Note: The default VOUT_UV_WARN_LIMIT is calculated from the EEPROM backed UVF limit by:

VOUT_UV_WARN_LIMIT = VOUT_UV_FAULT_LIMIT + VOUT_UV_FAULT_LIMIT/16

If the calculated value for VOUT_UV_WARN_LIMIT violates the requirement that VOUT_COMMAND >

VOUT_UV_WARN_LIMIT, then the VOUT_UV_WARN_LIMIT value is set to VOUT_UV_FAULT_LIMIT (rounded)

+ 1 LSB.

For the case when VOUT_UV_FAULT_LIMIT = 0 (which indicates it is disabled), the VOUT_UV_WARN_LIMIT

default shall be the minimum value for the configured VOUT_SCALE_LOOP (179d/VOUT_SCALE_LOOP).

NOTE

Changing the VOUT_UV_WARN_LIMIT (or Fault, or OV Fault, or Warn limit) during

regulation causes a brief overshoot/undershoot on the output voltage. This is due to the

Vref DAC being shared with OVUV DAC.

8.6.21 VOUT_UV_FAULT_LIMIT (44h)

The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage that causes an output undervoltage

fault. This fault is masked until the unit reaches the programmed output voltage. This fault is also masked when

the unit is disabled. Attempts to write values outside of the acceptable range is treated as invalid data, causing

the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers

as well as assert the SMBALERT signal. Additionally, the value of VOUT_UV_FAULT_LIMIT remains

unchanged. Maintaining values within “acceptable range” also means:

•

176d/VOUT_SCALE_LOOP < VOUT_UV_FAULT_LIMIT < VOUT_UV_WARN_LIMIT

A VOUT_UV_FAULT_LIMIT of 0000h shall be a means of disabling VOUT_UV_FAULT response and reporting

completely and is the only exception to the above “acceptable range” requirements. Disabling means that the unit

does not check for Vout_UVF faults; thus there is no setting of UVF status bits, nor associated SMBALERT

triggering. Disabling VOUT_UV_FAULT_LIMIT (by setting it to 0000h) has no bearing on

VOUT_UV_WARN_LIMIT checking – which is considered a completely separate function.

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Note the lower 4 bits can not be backed up in EEPROM.

The VOUT_UV_FAULT_LIMIT takes a two-byte data word formatted as shown below:

COMMAND

Format

VOUT_UV_FAULT_LIMIT

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

r/w^E

5

r/w^E

4

r/w^E

3

2

1

0

r/w^Er/w^Er/w^Er/w^E

r/w^E

Mantissa

0

r/w

Function

Default Value

0

1

0

1

0

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8.6.21.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.21.2 Mantissa

default: 0000 0001 0011 0000 (bin) 304(dec) (equivalent UVW 0.594 V or 62.5% of 0.95 V default reference

(VOUT_COMMAND))

NOTE

•

Changing the VOUT_UV_FAULT_LIMIT (or Warn, or OV Fault, or Warn limit) during

regulation causes a brief overshoot/undershoot on the output voltage. This is due to

the Vref DAC being shared with OVUV DAC.

Since the output undervoltage fault detection is masked until the unit reaches the

programmed output voltage, if the output voltage did not reach the programmed value

during the soft start time UPPER limit required by TON_MAX_FAULT_LIMIT, the

device

asserts

a

TON_MAX

fault

and

reponse

according

to

TON_MAX_FAULT_RESPONSE instead of VOUT_UV_FAULT_RESPONSE

8.6.22 VOUT_UV_FAULT_RESPONSE (45h)

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to a

VOUT_UV_FAULT_LIMIT fault. The device also:

•

Sets the oth bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the UVF bit in the STATUS_VOUT register, and

Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a output

undervoltage fault.

The default response to a output undervoltage fault is to shut down and restart with 7 × TON_RISE time delay.

COMMAND

Format

VOUT_UV_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w^E

RSP[1]

1

6

r

5

r/w^E

RS[2]

1

4

r/w

3

r/w

2

r

1

r

0

r

Function

0

RS[1]

1

RS[0]

1

X

1

X

1

X

1

Default Value

8.6.22.1 RSP[1]

This bit sets the output voltage under voltage response to either ignore or not. Default is 1.

0:

The PMBus device continues operation without interruption. Note: In this “ignore” fault response

mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if

it is not masked.

1:

The PMBus device shuts down and restarts according to RS[2:0].

8.6.22.2 RS[2:0]

These bits are output voltage under voltage retry setting. Default is 111b.

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

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111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.

8.6.23 IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the

overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal

to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than

IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd)

bit in the STATUS_CML registers as well as assert the SMBALERT signal. The contents of this register can be

stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:

COMMAND

Format

IOUT_OC_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Function

Exponent

Mantissa

Default Value

See Below

8.6.23.1 Exponent

default: 11111 (bin) -1 (dec) (0.5 amps)

These default settings are not programmable.

8.6.23.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable.

The actual output current for a given mantissa and exponent is shown in Equation 6.

Mantissa

=

I_OUT(oc)= Mantissa´ 2^Exponent

2

(6)

The default values and allowable ranges for each device are summarized below:

OC_FAULT_LIMIT

DEVICE

UNIT

MIN

DEFAULT

MAX

40

TPS544C25

TPS544B25

5

36

24

A

36

8.6.24 IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an

IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also:

•

Sets the OCF bit in the STATUS_BYTE

Sets the OCFW bit in the STATUS_WORD

Sets the OCF bit in the STATUS_IOUT register, and

Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

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Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over current

fault.

The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.

COMMAND

Format

IOUT_OC_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w^E

RSP[1]

1

6

r

5

r/w^E

RS[2]

1

4

r/w

3

r/w

2

r

1

r

0

r

Function

0

RS[1]

1

RS[0]

1

X

1

X

1

X

1

Default Value

8.6.24.1 RSP[1]

This bit sets the over current fault response to either ignore or not. Default is 1.

0:

The PMBus device continues operation without interruption. Note: In this “ignore” fault response

mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if

it is not masked.

1:

The PMBus device shuts down and restarts according to RS[2:0].

8.6.24.2 RS[2:0]

These bits are over current fault retry setting. Default is 111b.

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (soft-start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.

8.6.25 IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-

current detector to indicate an over-current warning. When this current level is exceeded the device:

•

Sets the oth bit in the STATUS_BYTE

Sets the OCFW bit in the STATUS_WORD

Sets the OCW bit in the STATUS_IOUT register, and

Notifies the host by asserting SMBALERT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the

IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers as well as assert the SMBALERT signal.

The default IOUT_OC_WARN_LIMIT is always set to fixed, relative IOUT_OC_FAULT_LIMIT - 2 A. Since the

IOUT_OC_WARN_LIMIT is not stored in EEPROM, the IOUT_OC_WARN_LIMIT register is set to 2 A less than

the stored IOUT_OC_FAULT_LIMIT upon any RESTORE from EEPROM.

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:

COMMAND

Format

Bit Position

IOUT_OC_WARN_LIMIT

Linear, two's complement binary

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

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ZHCSDR8 –MAY 2015

COMMAND

Access

IOUT_OC_WARN_LIMIT

r/w

r

r/w

Function

Exponent

Mantissa

Default Value

See Below

8.6.25.1 Exponent

default: 11111 (bin) -1 (dec) (0.5 amps)

These default settings are not programmable.

8.6.25.2 Mantissa

The upper four bits are fixed at 0.

Lower seven bits are programmable.

The actual output warning current level for a given mantissa and exponent is:

-°Æ¥©≥≥°

)

= -°Æ¥©≥≥° × 2^{%∏∞ØÆ•Æ¥}

=

/54 (/#7 ꢀ

2

(7)

The default values and allowable ranges for each device are summarized below:

OC_WARN_LIMIT

DEVICE

UNIT

MIN

4

DEFAULT

MAX

TPS544C25

TPS544B25

34

22

39.5

35.5

A

4

8.6.26 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-

temperature fault condition, when the sensed temperature from the external sensor exceeds this limit.

The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT

less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the

invalid data (ivd) bit in the STATUS_CML registers as well as asserts the SMBALERT signal. The contents of

this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.

COMMAND

Format

OT_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r/w^E

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

0

Function

Mantissa

1

Default Value

0

1

0

1

8.6.26.1 Exponent

default: 00000 (bin) 0 (dec) (represents mantissa with steps of 1 degree Celcius)

These default settings are not programmable.

8.6.26.2 Mantissa

default: 000 0111 1101 (bin) 125 (dec) (125 °C)

Minimum : 000 0111 1000 (bin) (equivalent OTF = 120 °C)

Maximum: 000 1010 0101 (bin) (equivalent OTF = 165 °C)

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8.6.27 OT_FAULT_RESPONSE (50h)

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an

OT_FAULT_LIMIT. The device also:

•

Sets the OTFW bit in the STATUS_BYTE

Sets the OTF bit in the STATUS_TEMPERATURE

Notifies the host by asserting SMBALERT

Once the over-temperature fault is tripped, the fault flag is latched until the external sensed temperature falls

20°C from the OT_FAULT_LIMIT.

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over

temperature fault.

The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.

COMMAND

Format

OT_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w^E

RSP[1]

1

6

r

5

r/w^E

RS[2]

1

4

r/w

3

r/w

2

r

1

r

0

r

Function

0

RS[1]

1

RS[0]

1

X

1

X

1

X

1

Default Value

8.6.27.1 RSP[1]

This bit sets the over temperature fault response to either ignore or not. Default is 1.

0:

The PMBus device continues operation without interruption. Note: In this “ignore” fault response

mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if

it is not masked.

1:

The PMBus device shuts down and restarts according to RS[2:0].

8.6.27.2 RS[2:0]

These bits are over temperature fault retry setting. Default is 111b.

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.

NOTE

The programmed response here is also applied to internally detected Over Temperture

faults – with the one exception of the “ignore” response. Internal OT faults are never

ignored. Internal OT faults always respond in a shutdown and attempted re-start once the

part cools.

8.6.28 OT_WARN_LIMIT (51h)

The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-

temperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon

triggering the over-temperature warning, the device takes the following actions:

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•

Sets the TEMPERATURE bit in the STATUS_BYTE

Sets the OT Warning bit in the STATUS_TEMPERATURE

Notifies the host by asserting SMBALERT

Once the over-temperature warning is tripped, the warning flag is latched until the external sensed temperature

falls 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT

greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the

invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal.

The default OT_WARN_LIMIT is mathematically derived from the EEPROM backed OTF limit by subtracting 25

from (4Fh) OT_FAULT_LIMIT to reach the default OT_WARN_LIMIT. If the calculated OTW is less than 100 °C,

then the default value is set to 100 °C. OTW=max(OTF-25, 100)

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

COMMAND

Format

OT_WARN_LIMIT

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

6

5

r/w

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

1

Default Value

0

1

0

1

0

8.6.28.1 Exponent

default: 00000 (bin) 0 (dec) (represents mantissa with steps of 1 degree Celcius)

These default settings are not programmable.

8.6.28.2 Mantissa

default: 000 0110 0100 (bin) 100 (dec) (100 °C) 25°C less than default OTF

Minimum : 000 0110 0100 (bin) (equivalent OTF = 100°C)

Maximum: 000 1000 1100 (bin) (equivalent OTF = 140°C)

8.6.29 TON_DELAY (60h)

The TON_DELAY command sets the time in milliseconds, from when a start condition is received to when the

output voltage starts to rise. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL command.

The TON_DELAY command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TON_DELAY

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

0

Function

Mantissa

0

Default Value

0

8.6.29.1 Exponent

default: 00000 (bin) 0 (dec) (1 millisecond)

These default settings are not programmable.

8.6.29.2 Mantissa

The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000

(bin) (0 ms).

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Only 16 fixed TON_DELAY times are available in the device. As such, the range of programmed TON_DELAY

settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values

are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TON_DELAY Values:

Table 11. Supported TON_DELAY Values

EFFECTIVE

TON_DELAY

(ms)

PROGRAMMED TON_DELAY MANTISSA (dec)

Greater than

Less than or equal to

0 (50 us)

0

1

2

0

1

2

3

2

3

4

3

4

5

4

5

6

5

6

7

6

9

10

14

19

27

37

52

72

100

9

12

17

22

32

44

62

86

12

17

22

32

44

62

86

8.6.30 TON_RISE (61h)

The TON_RISE command sets the time in milliseconds, from when the reference starts to rise until the voltage

has entered the regulation band. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL command.

Programming a value of 0 instructs the unit to bring its output voltage to the programmed regulation value as

quickly as possible. For TPS544x25, this results in an effective TON_RISE time of 1ms (fastest time supported).

If the Soft-Start Detection feature is being used (bit in MFR_??), then the Mantissa value decoded or derived by

from the appropriate SS resistor writes into the TON_RISE register as the initial default. Note: This write

overwrites any value restored from the EEPROM restore operation at initial power-up.

TON_RISE should always be set less than the TON_MAX_FAULT_LIMIT. Attempting to write a value to

TON_RISE greater than TON_MAX_FAULT_LIMIT is not accepted and causes the device to set the ’cml’ bit in

the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.

There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This indicates that the

TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up

the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against

TON_MAX_FAULT_LIMIT is also disabled.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TON_RISE

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

0

Function

Mantissa

0

Default Value

0

1

0

1

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8.6.30.1 Exponent

default: 00000 (bin) 0 (dec) (1 millisecond)

These default settings are not programmable.

8.6.30.2 Mantissa

The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0101

(bin) (5 ms).

The supported TON_RISE times over PMBus are shown in Table 12:

Table 12. Supported TON_RISE Values

Effective

Programmed TON_RISE Mantissa (d)

TON_RISE (ms)

Greater than

Less than or equal to

1

2

1

2

1

2

3

4

3

4

5

4

5

6

5

6

7

6

9

10

14

19

27

37

52

72

100

9

12

17

22

32

44

62

86

12

17

22

32

44

62

86

8.6.31 TON_MAX_FAULT_LIMIT (62h)

The TON_MAX_FAULT_LIMIT command sets an UPPER limt in milliseconds, on how long the unit can attempt

to power up the output without reaching the output undervoltage fault limit. The time begins counting as soon as

the device enters the soft-start state begins to ramp the output. In other words, the TON_MAX_FAULT_LIMIT

timer starts at the beginning of the TON_RISE state.

The TON_MAX_FAULT_LIMIT should always be set greater than the TON_RISE. Attempting to write a value to

TON_MAX_FAULT_LIMIT less than TON_RISE is not accepted and causes the device to set the ’cml’ bit in the

STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.

There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This setting indicates that the

TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up

the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against

TON_MAX_FAULT_LIMIT is also disabled.

The TON_MAX_FAULT_LIMIT command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TON_MAX_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

1

Default Value

0

1

0

1

0

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8.6.31.1 Exponent

default: 00000 (bin) 0 (dec) (1 millisecond)

These default settings are not programmable.

8.6.31.2 Mantissa

The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0110 0100

(bin) (100 ms).

Even though this register is not EEPROM backed, a RESTORE_DEFAULT_ALL command causes the

TON_MAX_FAULT_LIMIT to restore to the default 100 ms value.

The supported TON_MAX_FAULT_LIMIT times over PMBus are shown in Supported TON_MAX_FAULT_LIMIT

Values:

Table 13. Supported TON_MAX_FAULT_LIMIT Values

Effective

TON_MAX_FAUL

T_LIMIT (ms)

Programmed TON_MAX_FAULT_LIMIT Mantissa (d)

Greater than

Less than or equal to

No Limit (timer

disabled)

0

1

2

0

1

2

3

2

3

4

3

4

5

4

5

6

5

6

7

6

9

10

14

19

27

37

52

72

100

9

12

17

22

32

44

62

86

12

17

22

32

44

62

86

8.6.32 TON_MAX_FAULT_RESPONSE (63h)

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an

TON_MAX_FAULT_LIMIT.

The device also:

•

Sets the oth bit in the STATUS_BYTE

Sets the VFW bit in the STATUS_WORD

Sets the TONMAXF bit in the STATUS_VOUT register, and

Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a

TON_MAX_FAULT.

The default response to a TON_MAX_FAULT is to shut down and restart with 7 × TON_RISE time delay.

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COMMAND

Format

TON_MAX_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w^E

RSP[1]

1

6

r

5

r/w^E

RS[2]

1

4

r/w

3

r/w

2

r

1

r

0

r

Function

0

RS[1]

1

RS[0]

1

X

1

X

1

X

1

Default Value

8.6.32.1 RSP[1]

This bit sets the TON_MAX_FAULT response to either ignore or not. Default is 1.

0:

The PMBus device continues operation without interruption. Note: In this “ignore” fault response

mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if

it is not masked.

1:

The PMBus device shuts down and restarts according to RS[2:0].

8.6.32.2 RS[2:0]

These bits are TON_MAX_FAULT retry setting. Default is 111b.

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing

the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in

STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.

8.6.33 TOFF_DELAY (64h)

The TOFF_DELAY command sets the time in milliseconds, from when a stop condition is received and when the

output voltage starts to fall. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL command.

The TOFF_DELAY command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TOFF_DELAY

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

0

Function

Mantissa

0

Default Value

0

8.6.33.1 Exponent

default: 00000 (bin) 0 (dec) (1 millisecond)

These default settings are not programmable.

8.6.33.2 Mantissa

The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000

(bin) (0 ms).

Only 16 fixed TOFF_DELAY times are available in the device. As such, the range of programmed TOFF_DELAY

settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values

are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TOFF_DELAY Values:

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TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

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Table 14. Supported TOFF_DELAY Values

EFFECTIVE

TOFF_DELAY

(ms)

PROGRAMMED TOFF_DELAY MANTISSA (dec)

Greater than

Less than or equal to

0

1

0

1

0

1

2

3

2

3

4

3

4

5

4

5

6

5

6

7

6

9

10

14

19

27

37

52

72

100

9

12

17

22

32

44

62

86

12

17

22

32

44

62

86

8.6.34 TOFF_FALL (65h)

The TOFF_FALL command sets the time in ms, from the end of the TOFF_DELAY time until the voltage reaches

0 V. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL

command.

Programming a value of 0 instructs the unit to bring its output voltage down to 0 as quickly as possible. For

TPS544x25, this results in actively ramping down the output voltage in 1 ms (the fastest supported ramp down).

The TOFF_FALL command is formatted as a linear mode two’s complement binary integer.

COMMAND

Format

TOFF_FALL

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

r

Exponent

0

Function

Mantissa

0

Default Value

0

8.6.34.1 Exponent

default: 00000 (bin) 0 (dec) (1 millisecond)

These default settings are not programmable.

8.6.34.2 Mantissa

The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000

(bin) (0 ms).

The supported TOFF_FALL times over PMBus are shown in Supported TOFF_FALL Values:

Table 15. Supported TOFF_FALL Values

Effective

Programmed TOFF_FALL Mantissa (d)

TOFF_FALL (ms)

Greater than

Less than or equal to

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Table 15. Supported TOFF_FALL Values (continued)

Effective

TOFF_FALL (ms)

Programmed TOFF_FALL Mantissa (d)

1

2

1

2

3

4

3

4

5

4

5

6

5

6

7

6

9

10

14

19

27

37

52

72

100

9

12

17

22

32

44

62

86

12

17

22

32

44

62

86

8.6.35 STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

COMMAND

Format

STATUS_BYTE

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

1

r

0

r

OTFW

0

Function

X

0

OFF

X

OVF

0

OCF

0

X

0

CML

0

oth

1

Default Value

A "1" in any of these bit positions indicates that:

OFF:

The device is not providing power to the output, regardless of the reason. In this family of devices,

this flag means that the converter is not enabled.

OVF:

OCF:

An output overvoltage fault has occurred. This bit directly reflects the state of STATUS_VOUT[7] –

OVF. If the user wants this fault sourc to be masked and not trigger SMBALERT, they must do it by

masking STATUS_VOUT[7]. Per the PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not

clearable via a PMBus write. In contast, the bit is to be cleared by clearing the bit(s) in

STATUS_VOUT that cause this bit to be set.

An output over current fault has occurred. This bit directly reflect the state of STATUS_IOUT[7] –

OCF. If the user wants this fault sourced to be masked and not trigger SMBALERT, they must do it

by masking STATUS_IOUT[7]. Per the PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not

clearable via a PMBus write. In contrast, the bit is to be cleared by clearing the bit(s) in

STATUS_IOUT that cause this bit to be set.

OTFW:

A temperature fault or warning has occurred. Check STATUS_TEMPERATURE. Per the PMBus

v1.2 spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is

to be cleared by clearing the bit(s) in STATUS_TEMPERATURE that cause this bit to be set.

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CML:

A Communications, Memory or Logic fault has occurred. Check STATUS_CML. Per the PMBus v1.2

spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to

be cleared by clearing the bit(s) in STATUS_CML that cause this bit to be set.

oth:

A fault or warning not listed through bits 1-7 has occurred, for example an undervoltage condition or

an over current warning condition. Check other status registers. Per the PMBus v1.2 spec sections

10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by

clearing the bit(s) in STATUS_VOUT and STATUS_IOUT that cause this bit to be set. The default

for this bit is 1 because the default of STATUS_INPUT[3] LOW_Vin defaulting to 1.

8.6.36 STATUS_WORD (79h)

The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning

conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning

conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

COMMAND

Format

STATUS_WORD (low byte) = STATUS_BYTE

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

1

r

0

r

OTFW

0

Function

X

0

OFF

X

OVF

0

OCF

0

x

0

CML

0

oth

1

Default Value

COMMAND

STATUS_WORD (high byte)

Format

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

r

3

2

r

1

r

0

r

INPUT

X

r^E

PGOOD_Z

X

Function

VFW

0

OCFW

0

MFR

X

0

X

0

X

0

Default Value

0

A "1" in any of the high byte bit positions indicates that:

VFW:

An output voltage fault or warning has occurred (OVF or OVW or UVW or UVF or

VOUT_MAX_Warning or TONMAXF). Check STATUS_VOUT. Per the PMBus v1.2 spec sections

10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by

clearing the bit(s) in STATUS_VOUT that cause this bit to be set.

OCFW:

An output current warning or fault has occurred (OCF or OCW). Check STATUS_IOUT. Per the

PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast,

the bit is to be cleared by clearing the bit(s) in STATUS_IOUT that cause this bit to be set.

INPUT:

INPUT fault or warning in STATUS_INPUT is present. Check STATUS_INPUT. Per the PMBus v1.2

spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to

be cleared by clearing the bit(s) in STATUS_INPUT that cause this bit to be set.

MFR:

An manufacturer specific fault/warning condition has occurred (Internal over temperature fault or

VOUT_MIN_Warning). Check STATUS_MFR_SPECIFIC. Per the PMBus v1.2 spec sections 10.2.4

and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by clearing

the bit(s) in STATUS_MFR_SPECIFIC that cause this bit to be set.

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ZHCSDR8 –MAY 2015

PGOOD_Z:

Power is Not Good, and the following condition is present: output over or under voltage warning or

fault, TON_MAX_FAULT, over temperature warning or fault, over current warning or fault,

insufficient input voltage. Please refer to the FAULT RESPONSE table for the possible sources to

trigger PGOOD_Z. The signal is unlatched and always represents the current state of the device.

Unless masked, it triggers SMBALERT; however, the default for this mask bit is 1, indicating that

PGOOD_z cannot trigger SMBALERT by default. The user must clear the associated

SMBALERT_MASK bit if SMBALERT triggering is desired for this condition.

8.6.37 STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related

faults.

COMMAND

Format

STATUS_VOUT

Unsigned binary

Bit Position

Access

7

r/w^E

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r

0

r

VOUT_MA

X_Warning

Function

OVF

0

OVW

0

UVW

0

UVF

0

TONMAXF

0

X

0

X

0

Default Value

0

A "1" in any of these bit positions indicates that:

OVF:

The device has seen the output voltage rise above the output overvoltage fault threshold

VOUT_OV_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

OVW:

The device has seen the output voltage rise above the output overvoltage warn threshold

VOUT_OV_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

UVW:

The device has seen the output voltage fall below the output undervoltage warn threshold

VOUT_UV_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

UVF:

The device has seen the output voltage fall below the output undervoltage fault threshold

VOUT_UV_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

VOUT_MAX_Warning:

An attempt is made to program the VOUT_COMMAND in excess of the value in VOUT_MAX. This

bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.

TONMAXF:

A TON_MAX_FAULT has occurred. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

8.6.38 STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the output current related

faults.

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TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

COMMAND

Format

STATUS_IOUT

Unsigned binary

Bit Position

Access

7

r/w^E

OCF

0

6

r

5

r/w^E

OCW

0

4

r

3

r

2

r

1

r

0

r

Function

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

OCF:

The device has seen the output current rise above the level set by IOUT_OC_FAULT_LIMIT. This

bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.

OCW:

The device has seen the output current rise above the level set by IOUT_OC_WARN_LIMIT. This bit

is writeable to clear and the EEPROM bit is for SMBALERT_MASK.

8.6.39 STATUS_INPUT (7Ch)

The STATUS_INPUT command returns one byte of information relating to the status of the converter's input

related faults.

COMMAND

Format

STATUS_INPUT

Unsigned binary

4

Bit Position

Access

7

r

6

r

5

r

3

2

r

1

r

0

r

r/w^E

LOW_Vin

0

Function

X

0

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

LOW_Vin:

The unit is Off due to insufficient input voltage. The bit sets when the unit powers up and stays set

until the first time VIN exceeds VIN_ON. During the initial power up, LOW_Vin is not latched and

does not trigger SMBALERT. Once VIN does exceed VIN_ON for the first time, any subsequent VIN

< VIN_OFF events are latched, trigger SMBALERT. This bit is writeable to clear and the EEPROM

bit is for SMBALERT_MASK.

8.6.40 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external

temperature related faults.

COMMAND

Format

STATUS_TEMPERATURE

Unsigned binary

Bit Position

Access

7

6

r/w^E

OTW

0

5

r

4

r

3

r

2

r

1

r

0

r

r/w^E

OTF

0

Function

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

OTF:

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TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

The measured external temperature value of READ_TEMPERATURE_2 is equal to or greater than

the level set by OT_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK. However, once cleared, the bit is set again unless the value in

READ_TEMPERATURE_2 has fallen 20°C from the OT_FAULT_LIMIT.

OTW:

The measured external temperature value of READ_TEMPERATURE_2 is equal to or greater than

the level set by OT_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK. However, once cleared, the bit is set again unless the value in

READ_TEMPERATURE_2 has fallen 20°C from the OT_WARN_LIMIT.

8.6.41 STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the converter’s

communication related faults.

COMMAND

Format

STATUS_CML

Unsigned binary

Bit Position

Access

7

r/w^E

ivc

0

6

r/w^E

ivd

0

5

r/w^E

pec

0

4

r/w^E

mem

0

3

r

2

r

1

r/w^E

oth

0

r

Function

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

ivc:

An invalid or unsupported command has been received. This bit is writeable to clear and the

EEPROM bit is for SMBALERT_MASK.

ivd:

An invalid or unsupported data has been received. This bit is writeable to clear and the EEPROM bit

is for SMBALERT_MASK.

pec:

A Packet Error Check failed. This bit is writeable to clear and the EEPROM bit is for

SMBALERT_MASK.

mem:

A fault has been detected with the internal memory. This bit is writeable to clear and the EEPROM

bit is for SMBALERT_MASK.

oth:

Some other communication fault or error has occurred. This bit is writeable to clear and the

EEPROM bit is for SMBALERT_MASK.

8.6.42 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturer-

specific faults or warnings.

COMMAND

Format

STATUS_MFR_SPECIFIC

Unsigned binary

Bit Position

Access

7

r/w^E

6

r

5

r

4

3

2

r

1

r/w^E

0

r

r/w

reset_ VOUT_MIN_Wa

vout rning

Function

otfi

illzero

illmany1s

iv_vset

iv_ss

X

69

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

COMMAND

STATUS_MFR_SPECIFIC

Default Value

0

A "1" in any of these bit positions indicates that:

otfi:

The internal temperature is above the thermal shutdown (TSD) fault threshold. This bit is writeable to

clear and the EEPROM bit is for SMBALERT_MASK.

illzero:

The operation FSM has hit an illegal “ZERO” state. The FSM is a one-hot implementation, so all

zeros in the state is illegal and should never occur. This event is informational only and would not

trigger SMBALERT.

illmany1s:

The operation FSM for has hit an illegal “more than one hot” state. The FSM is a one-hot

implementation, so a state where multiple state bits are HI is illegal and should never occur. This

event is informational only and would not trigger SMBALERT.

iv_vset:

the VSET detection results in an “illegal high”. This condition is intended as “information only” - and

does not trigger SMBALERT. To avoid initial turn-on events from clearing this condition and the user

not being aware why the default vset value was used, this bit is only clearable via the

CLEAR_FAULTS command or writing a logic 1 to this bit. Off and on events do not clear it as with

the other, standard status bits.

iv_ss:

the TON_RISE/SS detection results in an “illegal low” or an “illegal high”. This condition is intended

as “information only” - and does not trigger SMBALERT. To avoid initial turn-on events from clearing

this condition and the user not being aware why the default vset value was used, this bit is only

clearable via the CLEAR_FAULTS command or writing a logic 1 to this bit. Off and on events do not

clear it as with the other, standard status bits.

reset_vout:

The SYNC/RESET_B pin voltage is low and the device is requested to reset the output voltage to

the initial boot-up voltage set by VSET resistor. This event is informational only and would not trigger

SMBALERT.

VOUT_MIN_Warning:

an attempt is made to program the output voltage below the value in (A4h) MFR_VOUT_MIN. This

bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.

8.6.43 READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage

of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the

load is not accounted for. The data format is as shown below:

COMMAND

Format

READ_VOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Mantissa

0

Default Value

0

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8.6.43.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.43.2 Mantissa

The output voltage calculation is shown below.

Exponent

OUT

V

= Mantissa´ 2

(8)

8.6.44 READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current

of the converter. The average output current is sensed according to the method described in Low-Side MOSFET

Current Sensing and Overcurrent Protection. The data format is as shown below:

COMMAND

Format

READ_IOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

1

r

Function

Mantissa

0

Default Value

1

0

The device scales the output current before it reaches the internal analog to digital converter so that resolution of

the output current read is 62.5 mA. The maximum value that can be reported is 40 A. The user must set the

IOUT_CAL_OFFSET parameter correctly in order to obtain accurate results. Calculate the output current using

Equation 9.

Exponent

I

= Mantissa´ 2

OUT

(9)

8.6.44.1 Exponent

default: 11100 (bin) -4 (dec) (62.5 mA lsb)

These default settings are not programmable.

8.6.44.2 Mantissa

The lower 10 bits are the result of the ADC conversion of the average output current, as indicated by the output

of the internal current sense amplifier. The 11th bit is fixed at 0 because only positive numbers are considered

valid. Any computed negative current is reported as 0 A.

8.6.45 READ_TEMPERATURE_2 (8Eh)

The READ_TEMPERATURE_2 command returns the external temperature in degrees Celsius.

COMMAND

Format

READ_TEMPERATURE_2

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

0

r

Function

Mantissa

0

Default Value

0

1

0

1

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8.6.45.1 Exponent

default: 00000 (bin) 0 (dec)

These default settings are not programmable.

8.6.45.2 Mantissa

The lower 11 bits are the result of the ADC conversion of the external temperature.

The default reading is 000 00011001 (bin) 25 (dec), corresponding to a temperature of 25°C.

NOTE

The READ_TEMPERATURE_2 (8Eh) value remains at 25°C when SS_DET_DIS in

OPTIONS (MFR_SPECIFIC_21) (E5h) is set to 0 since the TSNS/SS pin is configured to

set TON_RISE time and not used for external temperature sensing.

8.6.46 PMBUS_REVISION (98h)

The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that these devices are

compatible with the 1.2 revision of the PMBus™ specification.

COMMAND

Format

PMBUS_REVISION

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Default Value

0

1

0

1

0

8.6.47 MFR_VOUT_MIN (A4h)

The MFR_VOUT_MIN command sets the minimum output voltage. The purpose is to protect the device(s) on the

output rail supplied by this device from a lower than acceptable output voltage. MFR_VOUT_MIN imposes a

lower bound to any attempted output voltage setting:

•

programmed VOUT_COMMAND

VSET pin default

If any attempt is made to program the output voltage (using the VOUT_COMMAND ) below the value in

MFR_VOUT_MIN, the device also:

•

Clamps the output voltage at the programmed MFR_VOUT_MIN value

Sets the oth (other) bit in the STATUS_BYTE

Sets the MFR bit in the STATUS_WORD

Sets the VOUT_MIN_Warning bit in the STATUS_MFR_SPECIFIC register, and

Notifies the host via the SMBALERT pin.

The exponent is set by VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed output voltage is

computed as:

Minimum V_OUTallowed = MFR_VOUT_MIN × VOUT_MODE (V) = MFR_VOUT_MIN × 2-9 (V)

(10)

There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:

•

If the commanded MFR_VOUT_MIN is outside the valid data range for the VOUT_SCALE_LOOP configured,

but, is still relationally correct (below VOUT_COMMAND), then that value is not accepted; but,

MFR_VOUT_MIN is set to the lowest allowed value.

•

The second case is the opposite, where the attempted write value is within the absolute range of

MFR_VOUT_MIN; but, is not relationally correct (it is above VOUT_COMMAND). In this case, the

MFR_VOUT_MIN remains unchanged.

Both cases equally cause the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the

STATUS_CML registers, and triggers SMBALERT signal.

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COMMAND

Format

MFR_VOUT_MIN

Linear, unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

Mantissa

8.6.47.1 Exponent

Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in

VOUT_MODE command).

8.6.47.2 Mantissa

The range of valid MFR_VOUT_MIN values is dependent upon the configured (29h) VOUT_SCALE_LOOP as

follows.

If VOUT_SCALE_LOOP = 1:

•

default: 0000 0001 0000 0000 (bin) 256 (dec) (equivalent Vout default = 0.5V)

Minimum : 0000 0001 0000 0000 (bin) 256 (dec) (equivalent VOUT_MAX = 0.5V)

Maximum: 0000 0010 1110 0110 (bin) 742 (dec) (equivalent VOUT_MAX = 1.45V)

If VOUT_SCALE_LOOP = 0.5:

•

default: 0000 0010 0000 0000 (bin) 512 (dec) (equivalent Vout default = 1V)

Minimum : 0000 0010 0000 0000 (bin) 512 (dec) (equivalent VOUT_MIN = 1V)

Maximum: 0000 0101 1100 1100 (bin) 1484 (dec) (equivalent VOUT_MIN = 2.9V)

If VOUT_SCALE_LOOP = 0.25:

•

default: 0000 0100 0000 0000 (bin) 1024 (dec) (equivalent Vout default = 2V)

Minimum : 0000 0100 0000 0000 (bin) 1024 (dec) (equivalent VOUT_MIN = 2V)

Maximum: 0000 1011 1001 1000 (bin) 2968 (dec) (equivalent VOUT_MIN = 2.9V)

8.6.48 IC_DEVICE_ID (ADh)

This Read-only Block Read command returns a single word (16 bits) with the unique Device Code identifier for

each device for which this IC can be configured. The BYTE_COUNT field in the Block Read command is 2

(indicating 2 bytes follow): Low Byte first, then High Byte.

COMMAND

Format

IC_DEVICE_ID

Linear, binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Default Value

See below

Device Identifier Code default:

•

0027h – Code Identifier for TPS544C25 – 30A device

0028h – Code Identifier for TPS544B25 – 20A device

8.6.49 IC_DEVICE_REV (AEh)

This Read-only Block Read command returns a single word (16 bits) with the unique Device revision identifier.

The DEVICE_REV starts at 0 with the first silicon and is incremented with each subsequent silicon revision. The

BYTE_COUNT field in the Block Read command is 2 (indicating 2 bytes follow): Low Byte first, then High

Byte.

COMMAND

Format

IC_DEVICE_REV

Linear, tbinary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

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TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

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COMMAND

IC_DEVICE_REV

Default Value

See below

Device Identifier Code default:

•

0000b

8.6.50 MFR_SPECIFIC_00 (D0h)

The MFR_SPECIFIC_00 register is dedicated as a user scratch pad. Only the lower 8 bits are writeable for

users. This is a read word command, with only the lower 8 bits accessible. Note it's NOT a read byte command.

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

COMMAND

Format

MFR_SPECIFIC_00

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r/w^E

6

r/w^E

5

r/w^E

4

r/w^E

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

Function

User scratch pad

Default Value

0

8.6.51 OPTIONS (MFR_SPECIFIC_21) (E5h)

The OPTIONS register can be used for setting user selectable options, as shown below. The contents of this

register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

COMMAND

Format

OPTIONS

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r/w^E

7

r/w^E

6

r/w^E

5

r/w^E

4

3

2

r/w^E

1

r/w^E

0

r/w^E

r/w

SS_DET_ EN_AUTO

EN_ADC_C PMB_VT PMB_HI_

Function

X

0

X

0

X

0

X

0

X

0

X

0

X

0

AVG_PROG[1:0] DLO VSM

DIS

_ARA

NTL

H

LO

Default

Value

0

1

0

1

8.6.51.1 PMB_HI_LO

This bit forces PMB rail logic levels.

•

0: Force 3V/5V logic thresholds.

1: Force 1.8V logic thresholds.

8.6.51.2 PMB_VTH

This bit configures automatic PMBus logic level detection.

•

0: No automatic bus detection occurs.

1: Allow the automatic bus detection to occur – VTH can result in 3V/5V or 1.8V depending upon comparator

output.

BUS DETECTION

COMPARATOR ( < 2.4 V)

PMB_VTH

PMB_HI_LO

VSET_USED

FINAL VTH

0

1

0

1

X

0

1

X

0

3V/5V

1.8V

X

3V/5V

1.8V

1

X

1.8V

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8.6.51.3 EN_ADC_CNTL

This bit enables ADC operation used for voltage, current and temperature monitoring.

•

0: Disable ADC operation.

1: Enable ADC operation.

NOTE

The EN_ADC_CNTL bit must be set in order to enable output voltage, current and

temperature telemetry. When the EN_ADC_CNTL bit is zero, the READ_VOUT,

READ_IOUT and READ_TEMPERATURE_2 registers do not update continuously, and

retain their previous values from the last time EN_ADC_CNTL was set.

8.6.51.4 VSM

This bit configures the measurement system for fast, vout-only measurement mode. Setting this bit disables

READ_IOUT, and READ_TEMPERATURE_2, and insteasd allows the device to update READ_VOUT more

frequently. This bit does not have EEPROM backup.

•

0: Measure Vout, Temperature, and Iout.

1: Measure only Vout.

8.6.51.5 DLO

This bit allows bypassing the normal valid data checks on register writes. This feature is included for flexibility

during debug to quickly generate fault conditions and/or possibly work around any data limit protection

mechanisms prohibiting output voltage programming. This bit does not have EEPROM backup.

•

0: Normal PMBus data write restrictions.

1: Data write restrictions are overridden for the following registers: SMBALERT_MASK, VOUT_COMMAND,

VOUT_SCALE_LOOP, VOUT_OV_FAULT_LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,

VOUT_UV_FAULT_LIMIT,

IOUT_OC_FAULT_LIMIT,

IOUT_OC_WARN_LIMIT,

OT_FAULT_LIMIT,

OT_WARN_LIMIT, TON_MAX_FAULT_LIMIT, TON_RISE, TOFF_FALL, MFR_VOUT_MIN, VOUT_MAX,

VIN_ON, VIN_OFF, and OPERATION.

NOTE

CAUTION: Users should use this bit with extreme caution. Setting this bit allows invalid

data conditions to be programmed into the device which can lead to damage. Invalid data

written into any register when DLO is enabled does NOT set the IVD bit; nor trigger

SMBALERT. The invalid data is simply allowed to be programmed. Furthermore, invalid

data programmed into a command/status register while DLO is enabled, does not trigger

SMBALERT upon de-assertion of DLO. So, it is possible to exit DLO mode with invalid

data in command/status registers. Use with extreme caution.

8.6.51.6 AVG_PROG[1:0]

These bits configure programmable digital measurement averaging. Bits provide programmable averaging for

current (READ_IOUT), temperature (READ_TEMPERATURE_2), and voltage (READ_VOUT). The default (10b)

yields 8x averaging for all three parameters; however, this default can be changed and stored in EEPROM, if

necessary. Programming options are:

AVG_PROG[1:0]

ACCUMULATING AVERAGING

00b

16x

0x – this ‘bypasses’ the averagers – every sample from measurement system updates

corresponding READ_XXX CSR.

01b

10b

11b

8x

32x

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8.6.51.7 EN_AUTO_ARA

This bit Enables auto Alert Response Address response. When this feature is enabled, and after the device has

successfully responded to an ARA transaction, the hardware automatically masks any fault source currently set

from re-asserting SMBALERT. This prevents PMBus “bus hogging” in the case of a persistent fault in a device

that consistently wins ARA arbitration due to its device address. In contrast, when this bit is cleared, immediate

re-assertion of SMBALERT is allowed in the event of a persistent fault and the responsibility is upon the host to

mask each source individually.

8.6.51.8 SS_DET_DIS

This bit Disables Soft Start Detection when set. The READ_TEMPERATURE_2 value remains at 25°C when

OPTIONS (MFR_SPECIFIC_21) (E5h) is set to 0 since the TSNS/SS pin is configured to set TON_RISE time

and not used for external temperature sensing.

8.6.52 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)

This user-accessible register is used for miscellaneous options, as shown below. The contents of this register

can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

COMMAND

Format

MISC_CONFIG_OPTIONS

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

r

3

r/w^E

2

r/w^E

1

r/w^E

0

r/w^E

Function

X

FORCE_SYNC

HSOC_USER_TRIM[1:0]

OV_RESP_SEL

Default

Value

0

1

0

1

8.6.52.1 OV_RESP_SEL

This bit selects between two options for low-side FET behavior after an output overvoltage fault condition.

Regardless of the setting of this bit, the low-side FET latches on when an output OV fault is detected (if the

OV_FAULT_RESPONSE is not programmed to “ignore”).

•

0: the low-side FET remains on until either the part initiates a new startup of the output voltage or the

CLEAR_FAULTS command is given while the part is in the “DISABLE” operational state

•

1: the low-side FET turns off as soon as the sensed output (at DIFFO pin) drops below the

VOUT_UV_FAULT_LIMIT.

8.6.52.2 HSOC_USER_TRIM[1:0]

This trim is provided so that the customers can adjust the high-side overcurrent (HSOC) threshold in order to

account for their application specific Vin sensing parasitics and component current handling spec requirements.

HSOC_USER_TRIM[1:0]

HSOC Change from Default

00b

01b

10b

11b

0

+12.5%

–25%

–12.5%

8.6.52.3 FORCE_SYNC

This bit configures the SYNC/RESET_B pin functions in conjunction with VSET detection.

•

0: the pin operates as RESET_B if VSET detection is valid, and SYNC otherwise.

1: the SYNC/RESET_B pin operates as a SYNC pin regardless of the outcome of the VSET detection.

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9 Applications and Implementation

9.1 Application Information

The TPS544x25 devices are highly-integrated synchronous step-down DC-DC converters. These devices are

used to convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 20 A

or 30 A. Use the following design procedure to select key component values for this family of devices, and set

the appropriate behavioral options via the PMBus™ interface.

9.2 Typical Applications

9.2.1 TPS544C25 4.5-V to 18-V Input, 0.95-V Output, 30-A Converter

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Typical Applications (continued)

S1

TP12

TP11

U2

R1

3

2

4

5

1

8

7

6

V+

R

V-

NC

BP3

100k

C1

NC

Q1

MMBT3904

33pF

R21

38.3k

LM334SM/NOPB

C2

1000pF

C3

R2

R20

21.5

J2

10.5k

1200pF

Q2

2N7002E-T1-E3

1

3

5

7

9

2

TP7

4

6

R3

8

BP3

10

10.0k

R4

R7

DNP

TP3

TP2

R5

R6

PMBus

40.2k

D1

Pink

10.0k

C4

49.9

R8

R10

10.0k

GND

R9

DNP

U1

TPS544C25RVF

GND

300

1200pF

BP3

R18

10.0k

32

31

30

29

28

27

26

25

24

23

22

21

1

VOUTS-

CNTL

VOUTS-

VOUTS+

CNTL

2

R11

R12

51.1k

JP2

VOUTS+

VSET

VDD

BP6

ADDR1

ADDR0

DATA

CLK

R19

TP8

3

DNP

GND

4

GND

DATA

CLK

5

TP9

C6

1µF

TP4

TP5

6

BP3

SMBALERT

BOOT

SW

BP3

SMBALERT

R13

49.9

VOUTS+

7

PGND

VIN

GND

8

C5

R17

0

R14

0

C8

2.2µF

C7

4.7µF

9

330pF

VIN

SW

R15

49.9

JP1

10

11

12

VIN

SW

VIN = 4.5V - 18V

VOUTS-

TP6

VOUT = 0.95V @ 30A MAX ("C" version)

C9

GND

TP1

L1

VIN

SW

J1

0.1µF

J3

VIN

SW

470nH

744301047

TP13

C10

1000pF

C12

C21

C22

C23

C19

C20

C27

C28

C11

C13

22µF

C14

22µF

C15

22µF

C16

22µF

C17

C18

6800pF 6800pF

TOP BOTTOM

100µF

100µF 100µF 100µF

100µF 100µF 22µF 22µF

100µF

C24

100µF

C25

DNP

C26

DNP

R16

1

J4

TP10

TP14

FSW = 500KHz

GND

Figure 44. Typical Application Schematic

9.2.2 Design Requirements

For this design example, use the following input parameters.

Table 16. Design Example Specifications

PARAMETER

Input voltage

TEST CONDITION

MIN

TYP

MAX UNIT

V_IN

4.5

12.0

18.0

0.4

V

V_IN(ripple)

V_OUT

Input ripple voltage

Output voltage

I_OUT= 30 A

0.95

Line regulation

4.5 V ≤ V_IN≤ 18 V

0 V ≤ I_OUT≤ 30 A

I_OUT= 30 A

0.5%

Load regulation

V_PP

V_OVER

V_UNDER

I_OUT

t_SS

Output ripple voltage

Transient response overshoot

Transient response undershoot

Output current

20

90

mV

A

I_STEP= 10 A

90

4.5 V ≤ V_IN≤ 18 V

V_IN= 12 V

0

20

30

40

Soft-start time

5

ms

A

I_OC

Overcurrent trip point

Peak Efficiency

36

η

I_OUT= 13 A, V_IN= 12 V

88%

500

f_SW

Switching frequency

kHz

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ZHCSDR8 –MAY 2015

9.2.3 Design Procedure

9.2.3.1 Switching Frequency Selection

Select a switching frequency for the regulator. There is a trade off between higher and lower switching

frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and

smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher

switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.

In this design, a moderate switching frequency of 500 kHz achieves both a small solution size and a high-

efficiency operation With the frequency selected, the timing resistor is calculated using Equation 11

ꢀ.01 × 10¹⁰ꢀ.01 × 10¹⁰

2₄=

=

= ꢁ0.ꢀ ´3

¶

500 ´(∫

37

(11)

9.2.3.2 Inductor Selection

To calculate the value of the output inductor, use Equation 12. The coefficient K_INDrepresents the amount of

inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple

current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the

output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. Generally,

K_INDcoefficient should be kept between 0.2 and 0.4 for balanced performance. Using this target ripple current,

the required inductor size can be calculated as shown in Equation 12

6_/54

6

F 6_/54

0ꢀ9ꢁ 6 × (18 6 F 0ꢀ9ꢁ 6ꢂ

).

,1 =

×

=

= 0ꢀtJꢃ

:

;

18 6 × ꢁ00 ´ꢃ∫ × ꢄ0 ! × 0ꢀꢄ

k6

_;× ¶₃₇o k)_{/54 ≠°∏}_;× +_).$o

:

). ≠°∏

(12)

Selecting K_IND= 0.3, the target inductance L₁= 200 nH. Using the next standard value, the 470 nH is chosen in

this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current, and

peak current can be calculated using Equation 13, Equation 14 and Equation 15. These values should be used

to select an inductor with approximately the target inductance value, and current ratings that allow normal

operation with some margin.

6

_{). (≠°∏ ꢀ}F 6_/54

6_/54

× ¶₃₇o

ꢁꢂ9ꢃ 6 × (18 6 F ꢁꢂ9ꢃ 6ꢀ

)

=

×

=

= ꢇꢂ8ꢇ !

2)00,%

:

;

,1

18 6 × ꢃꢁꢁ ´ꢄ∫ × ꢅꢆꢁ Æꢄ

k6

:

;

). ≠°∏

(13)

1

¨

)

=

()_/54ꢀ² + ()_ꢁ)00,%ꢀ² = (3ꢂ !ꢀ² + × (3.83 !ꢀ² = 3ꢂ.ꢂ2 !

,(≤≠≥ ꢀ

12

(14)

(15)

1

2

1

:

)

; : ;

= 3ꢂ ! + 3.83 ! = 31.9ꢃ !

)

= ()_/54ꢀ +

,(∞•°´ ꢀ

ꢁ)00,%

2

The Pulse PG077.401NL is rated for 45 A_RMScurrent, and 48-A saturation. Using this inductor, the ripple current

I_RIPPLE= 3.85 A, the RMS inductor current I_L(rms)= 30.02 A, and peak inductor current I_L(peak)= 31.92 A.

9.2.3.3 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

affects three criteria:

•

how the regulator responds to a change in load current or load transient

the output voltage ripple

the amount of capacitance on the output voltage bus

The last of these three considerations is important when designing regulators that must operate where the

electrical conditions are unpredictable. The output capacitance needs to be selected based on the most stringent

of these three criteria.

9.2.3.3.1 Response to a Load Transient

The desired response to a load transient is the first criterion. The output capacitor needs to supply the load with

the required current when not immediately provided by the regulator. When the output capacitor supplies load

current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient.

79

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

In order to meet the requirements for control loop stability, the TPS544C25 requires the addition of compensation

components in the design of the error amplifier. While these compensation components provide for a stable

control loop, they often also reduce the speed with which the regulator can respond to load transients. The delay

in the regulator response to load changes can be two or more clock cycles before the control loop reacts to the

change. During that time the difference between the old and the new load current must be supplied (or absorbed)

by the output capacitance. The output capacitor impedance must be designed to be able to supply or absorb the

delta current while maintaining the output voltage within acceptable limits. Equation 16 and Equation 17 show the

relationship between the transient response overshoot, V_OVER, the transient response undershoot, V_UNDER, and

the required output capacitance, C_OUT

.

)

^ꢀ× ,1

:

;

42!.

6_/6%2

<

6_/54× #_/54

(16)

^ꢀ× ,1

:

;

)

42!.

6_5.$%2

<

(6 F 6_/54ꢁ × #_/54

).

If

•

V_IN(min)> 2 × V_OUT, use overshoot to calculate minimum output capacitance.

V_IN(min)< 2 × V_OUT, use undershoot to calculate minimum output capacitance.

•

(17)

In this case, the minimum designed input voltage V_IN(min)is greater than 2 × V_OUT, so V_OVERdictates the minimum

output capacitance. Therefore, using Equation 18, the minimum output capacitance required to meet the

transient requirement is 285 µF.

ꢁ

:

;

(ꢀ_42!.)² × ,1

10 ! × ꢂ70 Æꢃ

#

=

= ꢅꢅ0 J&

/54 (≠©Æ )

:

;

:

;

0ꢄ9ꢅ 6 × 90 ≠6

6_/54× 6_/6%2

(18)

9.2.3.3.2 Output Voltage Ripple

The output voltage ripple is the second criterion. Equation 19 calculates the minimum output capacitance

required to meet the output voltage ripple specification. This criterion is the requirement when the impedance of

the output capacitance is dominated by ESR.

ꢀ_2ꢀ00,%

ꢁ.8ꢁ !

#

=

= ꢆ8 J&

/54 (≠©Æ )

:

;

8 × ꢂꢃꢃ ´ꢄ∫ × ꢅꢃ ≠6

o

(19)

In this case, the maximum output voltage ripple is 20 mV. Under this requirement, the minimum output

capacitance for ripple (as calculated in Equation 19) yields 48 μF. Because this capacitance value is smaller than

the output capacitance required to meet the transient response, select the output capacitance value based on the

transient requirement. For this application, seven 100-µF low-ESR ceramic capacitors, and two 22-µF ceramic

capacitors were selected to meet the transient specification with sufficient margin. Therefore C_OUT= 744 µF.

With the target output capacitance value chosen, Equation 20 calculates the maximum ESR the output capacitor

bank can have to meet the output voltage ripple specification. Equation 20 indicates the ESR should be less than

4.9 mΩ. The ceramic capacitors each contribute approximately 3 mΩ, making the effective ESR of the output

capacitor bank approximately 0.3 mΩ, meeting the specification with sufficient margin.

I_RIPPLE

8×f_SW×C_OUT

I_RIPPLE

ꢁ.ꢂꢁ !

ꢂ × 500 ´(∫ × 744 J&

V_OUT(ripple)

-

ꢀ0≠6 F

:

;

:

;

%32_-!8

=

= 4.9 ≠À

ꢁ.ꢂꢁ !

(20)

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases the

minimum required capacitance value. Capacitors generally have limits to the amount of ripple current they can

handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current

must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple

current. Equation 21 can be used to calculate the RMS ripple current the output capacitor needs to support. For

this application, Equation 21 yields 1.11 A.

6_/54× (6

_;F 6_/54ꢀ

0ꢁ9ꢂ 6 × (18 6 F 0ꢁ9ꢂ 6ꢀ

:

). ≠°∏

)

=

= 1ꢁ11 !

#(≤≠≥ ꢀ

12 × 6

_;× ¶₃₇× ,1

12 × 18 6 × ꢂ00 ´ꢃ∫ × ꢄꢅ0 Æꢃ

¾

:

). ≠°∏

(21)

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9.2.3.3.3 Bus Capacitance

The amount of bus capacitance is the third criterion. This requirement is optional. However, extra output bus

capacitance should be considered in systems where the electrical environment is unpredictable, or not fully

defined, or can be subject to severe events such as hot-plug events or even electrostatic discharge (ESD)

events.

During a hot-plug event, when a discharged load capacitor is plugged into the output of the regulator, the

instantaneous current demand required to charge this load capacitance is be far too rapid to be supplied by the

control loop. Often the peak charging current can be multiple times higher than the current limit of the regulator.

Additional output capacitance helps maintain the bus voltage within acceptable limits. For hot-plug events, the

amount of required bus capacitance can be calculated if the load capacitance is known, based on the concept of

conservation of charge.

An ESD event, or even non-direct lightning surges at the primary circuit level can cause glitches at this converter

system level. A glitch of sufficient amplitude to falsely trip OVP or UVLO can cause several clock cycles of

disturbance. In such cases it is beneficial to design in more bus capacitance than is required by the simpler load

transient and ripple requirements. The amount of extra bus capacitance can be calculated based on maintaining

the output voltage within acceptable limits during the disturbance. This capacitance can be as much as required

to fully support the load for the duration of the interrupted converter operation.

9.2.3.4 Input Capacitor Selection

The TPS544x25 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a

value of at least 0.1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input

decoupling capacitance (effective capacitance at the VIN and GND pins) must be sufficient to supply the high

switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage

ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input

capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating

greater than the maximum input current ripple to the device during full load. The input ripple current can be

calculated using Equation 22.

k

6

_;F 6_/54o

0ꢀ9ꢁ 6 (ꢂꢀꢁ 6 F 0ꢀ9ꢁ 6ꢃ

6_/54

:

). ≠©Æ

¨

)

= )

×

;

/54 ≠°∏

×

= 30 A ×

×

:

;

:

#). ≤≠≥

6

ꢂꢀꢁ 6

:

;

:

;

). ≠©Æ

= 12ꢀ2 !≤≠≥

(22)

The minimum input capacitance and ESR values for a given input voltage ripple specification, V_IN(ripple), are

shown in Equation 23 and Equation 24. The input ripple is composed of a capacitive portion, V_RIPPLE(cap), and a

resistive portion, V_RIPPLE(esr)

.

)

× 6_/54

;

ꢁꢂ ! × ꢂꢃ9ꢄ 6

:

/54 ≠°∏

#

=

= ꢁꢆ J&

).(≠©Æ ꢀ

6_2)00,%

× 6

× ¶

;

). ≠°∏

1ꢂꢂ ≠6 × 18 6 × ꢄꢂꢂ +ꢅ∫

:

;

:

£°∞

37

(23)

(24)

6_{2)00,% (%32 ꢀ}

ꢂꢃꢄ 6

%32_{#). (≠°∏ ꢀ}

=

= 9ꢃꢅ ≠À

1

:

;

)

2)00,%

:

;

)

+

ꢄꢂ ! + ꢄꢃ8ꢄ !

/54 (≠°∏ ꢀ

ꢁ

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor

must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at

least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input

ripple for V_RIPPLE(cap), and 0.3-V input ripple for V_RIPPLE(esr). Using Equation 23 and Equation 24, the minimum

input capacitance for this design is 32 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25-V

ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the

power stage. For the VDD pin, one 1-μF, 25-V ceramic capacitor was selected. The input voltage (VDD) and

power input voltage (VIN) pins must be tied together.

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9.2.3.5 Bootstrap Capacitor Selection

A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper

operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor

should have voltage rating of 25 V or higher.

9.2.3.6 BP6 and BP3

According to the recommendations in , BP3 is bypassed to AGND with 2.2 μF of capacitance, and BP6 is

bypassed to PGND with 4.7-µF of capacitance. In order for the regulator to function properly, it is important that

these capacitors be localized to the TPS544x25 , with low-impedance return paths. See for more information.

9.2.3.7 R-C Snubber and VIN Pin High-Frequency Bypass

Though it is possible to operate the TPS544x25 within absolute maximum ratings without ringing reduction

techniques, some designs may require external components to further reduce ringing levels. This example uses

two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between

the SW area and GND.

The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the

outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and

discharge once the high-side MOSFET is turned on. For this example two 6.8-nF, 25-V, 0402 sized high-

frequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Its ideal

placement is shown in .

Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF

capacitor and a 1-Ω resistor are chosen. In this example a 1206 resistor is chosen, which is rated for 0.25 W,

nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.

9.2.3.8 Temperature Sensor

This application design uses a surface-mount MMBT3904 for the temperature sensor, Q1. In this example, the

sensor monitors the PCB temperature where it is generally the highest, next to the power inductor. Placement of

the temperature sensor and routing back to the TSNS pin are critical design features to reduce noise its

temperature measurements. In this example, the temperature sensor is placed on the V_OUTside of the power

inductor to avoid switching noise from the SW plane, and routed back to the TSNS and AGND pin. Additionally, a

1-nF capacitor, C2, is placed from TSNS to AGND near the TSNS pin. The READ_TEMPERATURE_2 (8Eh)

register is continually updated with the digitized temperature measurement, enabling temperature telemetry.

Disable external temperature sensing by terminating TSNS to AGND with a 0 Ω resistor. This termination forces

the temperature readings to –40 °C, and prevents external over-temperature fault trips.

The switch S1 in this example can be used to switch between temperature sensor and SS resistor. Note that the

READ_TEMPERATURE_2 value will be kept at 25°C when SS_DET_DIS in (E5h) MFR_SPECIFIC_21 is set to

0 since the TSNS/SS pin is configured to set TON_RISE time and not used for external temperature sensing.

9.2.3.9 Key PMBus™ Parameter Selection

Several of the key design parameters for the TPS544x25 device can be configured via the PMBus interface, and

stored to its non-volatile memory (NVM) for future use.

9.2.3.9.1 Enable, UVLO and Sequencing

The ON_OFF_CONFIG (02h) command is used to select the turn-on behavior of the converter. For this example,

the CNTL pin was used to enable or disable the converter, regardless of the state of OPERATION (01h), as long

as input voltage is present, and above the UVLO threshold.

The minimum input voltage, V_IN(min), for this example is 4.5 V. The VIN_ON command was set to 4.5 V, and the

VIN_OFF command was set to 4.0 V, giving 500 mV of hysteresis. If VIN falls below VIN_OFF, power conversion

stops, until it is raised above VIN_ON.

The turn-on or turn-off delay time can be set by TON_DELAY and TOFF_DELAY. Accounting for the time during

which the COMP signal rises to the valley of the PWM ramp, the delay between enabling power conversion, and

the rise of the output voltage is approximately 200 µs. See Soft-Start and TON_RISE Command for more

information.

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9.2.3.9.2 Soft-Start Time

The TON_RISE command sets the soft-start time. When selecting the soft-start time, consider the charging

current for the output capacitors. In some applications (e.g., those with large amounts of output capacitance) this

current can lead to problems with nuisance tripping of the overcurrent protection circuitry. To avoid nuisance

tripping, the output capacitor charging current should be included when choosing a soft-start time, and

overcurrent threshold. The capacitor charging current can be calculated using Equation 25

6_/54× # _/54

ꢀ.9ꢁ 6 × 7ꢂꢂ J&

)

#!0

=

= 1ꢂ1.ꢃꢄ ≠!

¥

ꢁ ≠≥

33

(25)

With the charging current calculated, the overcurrent threshold can then be calibrated to the sum of the

maximum load current and the output capacitor charging current plus some margin.

In this example, the soft-start time is arbitrarily selected to be 5 ms. In this case, the charging current, I_CAP

141.36 mA.

=

9.2.3.9.3 Overcurrent Threshold and Response

The IOUT_OC_FAULT_LIMIT command sets the overcurrent threshold. The current limit should be set to the

maximum load current, plus the output capacitor charging current during start-up, plus some margin for load

transients and component variation. The amount of margin required depends on the individual application, but a

suggested starting point is between 25% and 30%. More or less may be required. For this application, the

maximum load current is 30 A, the output capacitor charging current is 141 mA. This design allows some extra

margin, so an overcurrent threshold of 36 A was selected.

The IOUT_OC_FAULT_RESPONSE command sets the desired response to an overcurrent event, which can be

hiccup (continuously restart waiting for a 7 x soft-start time-out between re-trials) in the event of an overcurrent,

latch-off, or continue without interruption (i.e. ignore the fault).

9.2.3.9.4 Power Good, Output Overvoltage and Undervoltage Protection

The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT commands configure the PGOOD window, and

VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT commands configure the output voltage fault limits.

The VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE command sets the desired response

to an output overvoltage and undervoltage event respectively, which can be hiccup (continuously restart waiting

for a 7 x soft-start time-out between re-trials) in the event of a fault, latch-off, or continue without interruption (i.e.

ignore the fault).

Note that the VOUT_UV_FAULT_LIMIT is masked until the unit reaches the programmed output voltage. If the

output voltage did not reach the programmed value during the soft start time UPPER limit required by

TON_MAX_FAULT_LIMIT, the device will assert

TON_MAX_FAULT_RESPONSE.

a

TON_MAX fault and reponse according to

9.2.3.10 Output Voltage Setting and Frequency Compensation Selection

The output voltage can be set by the resistor connected from VSET to AGND with 8 possible options to set initial

boot-up output voltage ranging from 0.80 V to 1.20 V with VOUT_SCALE_LOOP = 1. The output voltage can

also be set by VOUT_COMMAND through the PMBus interface .

It is required that the user program VOUT_SCALE_LOOP prior to any VOUT related commands in order for the

proper range checking to work and to avoid Invalid Data scenarios. VOUT_SCALE_LOOP is equal to the

feedback resistor ratio of (R9/(R5+R9)). It is limited to only 3 possible options/ratios: 1 (default, no bottom

resistor required), 0.5, and 0.25.

In this design, the VSET pin is pulled up to BP3, so the VOUT_COMMAND goes to the default value of 0.95V

stored in the EEPROM. No bottom feedback resistor is needed for the output voltage range of 0.5 V to 1.5V.

The TPS544x25 device uses voltage mode control, with input feedforward. See SLUP206 for an in-depth

discussion of voltage-mode feedback and control. Frequency compensation can be accomplished using standard

techniques. TI also provides a compensation calculator tool to streamline compensation design. Using the

TPS40k Loop Compensation Tool, with 50 kHz of bandwidth, and 60 degrees of phase margin and optimizing

based on measured results yields the following:

83

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

Table 17. Design Example Frequency Compensation Values

RESISTOR

VALUE (kΩ)

10.0

CAPACITOR

VALUE (pF)

1200

R5

R8

C4

C3

C1

0.3

1200

R2

10.5

33

R_Bias

Not Used

The tool provides the recommended compensation components, and approximate bode plots. As a starting point,

the crossover frequency should be set to 1/10 f_SW, and the phase margin at crossover should be greater than

45°. The resulting plots should be reviewed for a few common issues. The error amplifier gain should not hit the

error amplifier gain bandwidth product (GBWP), nor should its mid-band gain, A_MID, be greater than

approximately 20 dB in general. Use the tool to calculate the system bode plot at different loading conditions to

ensure that the phase does not drop below zero prior to crossover, as this condition is known as conditional

stability.

9.2.4 Application Curves

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V_OUT= 0.5 V

V_OUT= 1.0 V

V_OUT= 1.5 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 0.5 V

V_OUT= 1.0 V

V_OUT= 1.5 V

V_OUT= 2.5 V

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Load Current (A)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Load Current (A)

D001

V_IN= 5 V

f_SW= 500 kHz

No snubber

R_BOOT= 0 Ω

R_DCR= 0.3 mΩ

V_IN= 12 V

L = 470 nH

f_SW= 500 kHz

No snubber

R_BOOT= 0 Ω

R_DCR= 0.3 mΩ

L = 470 nH

Figure 45. Efficiency vs. Load Current

Figure 46. Efficiency vs. Load Current

75

400

320

240

160

80

0.96

0.9575

0.955

0.9525

0.95

V_IN= 5 V

V_IN= 12 V

V_IN= 18 V

60

45

30

15

0

0.9475

0.945

0.9425

0.94

0

-15

-30

-45

-80

-160

Gain

Phase

-240

1000000

0.9375

100

1000

V_IN= 12 V

10000

Frequency (Hz)

100000

0

3

6

9

12

15

18

21

24

27

30

Output Current (A)

D00182

D001

V_OUT= 0.95 V

I_OUT= 20 A

V_OUT= 0.95 V

Figure 48. System Bode Plot

Figure 47. Load Regulation

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ZHCSDR8 –MAY 2015

V_IN= 12 V

V_OUT= 0.95 V

I_OUT= 20 A

V_IN= 12 V

V_OUT= 0.95 V

I_OUT= 20 A

Figure 49. Startup from CNTL

Figure 50. Shutdown from CNTL

V_IN= 12 V

V_OUT= 0.95 V

I_OUT= 0 A to 20A , 2.5 A/µs

V_IN= 12 V

V_OUT= 0.95 V

I_OUT= 20 A

Figure 51. Transient Load

Figure 52. DC Ripple

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V_IN= 12 V

I_OUT= 0 A

V_PRE-BIAS= 0.5 V

Natural Convection

I_OUT= 20 A

V_OUT= 0.95 V

f_SW= 500 kHz

V_IN= 12 V

Figure 53. 50% Pre-Biased Start-Up

Figure 54. Thermal Image

10 Power Supply Recommendations

These devices are designed to operate from an input voltage supply between 4.5 V and 18 V. This supply must

be well regulated. These devices are not designed for split-rail operation. The VIN and VDD pins must be the

same potential for accurate high-side short circuit protection. Proper bypassing of input supplies and internal

regulators is also critical for noise performance, as is PCB layout and grounding scheme. See the

recommendations in the Layout section.

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11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. 图 55 shows the recommended PCB layout

configuration. A list of PCB layout considerations using these devices are listed below.

•

As with any switching regulator, there are several signal paths that conduct fast switching voltages or

currents. Minimize the loop area formed by these paths and their bypass connections.

•

Bypass the VIN pins to GND with a low-impedance path. Power-stage input bypass capacitors should be as

close as physically possible to the VIN and GND pins. Additionally, a high-frequency bypass capacitor in 0402

package on the VIN pins can help to reduce switching spikes, which can be tucked right underneath the IC on

the other side of the PCB to keep a minimum loop.

•

BP6 bypass capacitor carries large switching current for gate driver. Bypassing the BP6 pin to GND with a

low-impedance path is very critical to the stable operation of the TPS544x25 devices. Place BP6 high-

frequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to

ground.

The VDD and BP3 also require good local bypassing. Place bypass capacitors as close as possible to the

device pins, with a minimum return loop back to ground and this return loop should be kept away from fast

switching voltage and main current path, as well as BP6 current path. Poor bypassing on VDD and BP3 can

degrade the performance of the regulator.

Keep signal components local to the device, and place them as close as possible to the pins to which they

are connected. These components include the feedback resistors, the RT resistor, the VSET resistor, the SS

resistor, as well as ADDR0 and ADDR1 resistors. These components should also be kept away from fast

switching voltage and current paths. Those components can be terminated to GND with minimum return loop

or bypassed to a separate low impedance analog ground (AGND) copper area, which is isolated from fast

switching voltage and current paths and has single connection to PGND on the thermal tab via AGND pin.

See 图 55 for placement recommendation.

•

The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low-

noise, low-impedance path to ensure accurate current monitoring.

Minimize the SW copper area for best noise performance. Route sensitive traces away from SW and BOOT,

as these nets contain fast switching voltages, and lend easily to capacitive coupling.

Snubber component placement is critical to its effectiveness of ringing reduction. These components should

be on the same layer as the TPS544x25 devices, and be kept as close as possible to the SW and GND

copper areas.

•

The VIN and VDD pins must be the same potential for accurate short circuit protection, but high frequency

switching noise on the VDD pin can degrade performance. VDD should be connected to VIN through a trace

from the input copper area. Optionally form a small low-pass R-C between VIN and VDD, with the VDD

bypass capacitor (1 µF) and a 0-2 Ω resistor between VIN and VDD. See 图 55.

•

Route the VOUTS+ and VOUTS– lines from the output capacitor bank at the load back to the device pins as

a tightly coupled differential pair. It is critical that these traces be kept away from switching or noisy areas

which can add differential-mode noise.

Routing of the temperature sensor traces is critical to the noise performance of temperature monitoring. Keep

these traces away from switching areas or high current paths on the layout. It is also recommended to use a

small 1-nF capacitor from TSNS/SS to AGND to improve the noise performance of temperature readings.

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11.2 Layout Example

(A)

(B)

(C)

(Not to scale)

VIN

(L)

(K)

C

COMP2

GND

R

COMP1

R

BOT

R

TOP

DIFFO

FB

GND

(N)

R

COMP2

GND

C

(D)

COMP2

C

COMP3

COMP

Thermal Pad

PGOOD

TSNS/SS

AGND

R

PG

(J)

(I)

V

OUTSœ

(M)

R

SYNC

SYNC/RESET_B

RT

R

SNSœ

R

RT

(H)

C

AGND

BOOT

R

SNS+

TSNS

AGND

Q

TSNS

R

BOOT

V

OUTS+

Optional

RC

(E)

Address

Resistors

VOUT

Snubber

L1

(G)

(F)

CNTL

PMBus

Signal Communication

(A) Connect to AGND with setting resistor or pull up to BP3 if not used.

(B) Bypass for internal regulators BP3, BP6, VDD. Use multiple vias to reduce parasitic inductance

(C) Place VIN bypass capacitors as close as possible to device, with best high frequency capacitor closest to VIN and

GND pins

(D) Kelvin connect to TPS544C25 VOUTS– and VOUTS+ pins

(E) Sense point should be directly at the load

(F) For best efficiency, use a heavy weight copper and place these planes on multiple PCB layers

(G) Minimize SW area for least noise. Keep sensitive traces away from SW and BOOT on all layers

(H) AGND and PGND are only connected together on Thermal Pad.

(I) Optional SYNC/RESET_B Signal. Pull up to BP3 if not used.

(J) Pull up to BP6 or external voltage to use PGOOD.

(K) Maintain feedback and compensation network components localized to the device.

(L) Internal AGND Plane to reduce the BP3 and VDD bypass parasitics.

(M) Connect AGND to Thermal Pad

(N) Connect PGND to Thermal Pad

图 55. PCB Layout Recommendation

11.2.1 Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the

reflow process can affect electrical performance. 图 56 shows the recommended reflow oven thermal profile.

Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.

88

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

Layout Example (接下页)

t_P

T_P

T_L

T_S(max)

T_S(min)

t_L

r_RAMP(up)

r_RAMP(down)

t_S

t_25P

Time (s)

25

图 56. Recommended Reflow Oven Thermal Profile

表 18. Recommended Thermal Profile Parameters

PARAMETER

MIN

TYP

MAX

UNIT

RAMP UP AND RAMP DOWN

r_RAMP(up)

Average ramp-up rate, T_S(max)to T_P

Average ramp-down rate, T_Pto T_S(max)

3

6

°C/s

r_RAMP(down)

PRE-HEAT

T_S

Pre-heat temperature

150

60

200

180

°C

s

t_S

Pre-heat time, T_S(min)to T_S(max)

REFLOW

T_L

T_P

t_L

Liquidus temperature

217

°C

s

Peak temperature

260

150

40

Time maintained above liquidus temperature, T_L

Time maintained within 5 °C of peak temperature, T_P

Total time from 25 °C to peak temperature, T_P

60

20

t_P

s

t_25P

480

s

89

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 德州仪器 (TI) Fusion Digital Power Designer

德州仪器 (TI) Digital Power Designer 能够为 TPS544x25器件提供全面支持。Fusion digital Power Designer 是一

款图形用户界面 (GUI)，可使用德州仪器 (TI) USB-to-GPIO 适配器通过 PMBus 配置并监控器件。

单击此链接下载德州仪器 (TI) Fusion Digital Power Designer 软件包。

图 57. 使用 Fusion Digital Power Designer 进行器件监控

90

TPS544C25, TPS544B25

www.ti.com.cn

ZHCSDR8 –MAY 2015

器件支持 (接下页)

图 58. 使用 Fusion Digital Power Designer 进行器件配置

12.1.1.2 TPS40k 环路补偿工具

TPS544x25 器件受德州仪器 (TI) TPS40k 环路补偿工具支持。该电子表格工具可用于计算具有电压模式控制功能

的器件的频率补偿组件。

12.2 相关链接

下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的

快速链接。

表 19. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

TPS544C25

TPS544B25

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

SWIFT, NexFET, E2E are trademarks of Texas Instruments.

PMBus is a trademark of SMIF, Inc..

All other trademarks are the property of their respective owners.

91

TPS544C25, TPS544B25

ZHCSDR8 –MAY 2015

www.ti.com.cn

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且

不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

92

PACKAGE OUTLINE

RVF0040A

LQFN-CLIP - 1.52 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

A

B

PIN 1 INDEX AREA

7.1

6.9

C

1.52

1.32

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.3 0.1

EXPOSED

THERMAL PAD

36X 0.5

13

20

12

21

41

SYMM

2X

5.3 0.1

5.5

32

1

0.3

40X

0.2

40

33

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

40X

4222989/B 10/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220.

www.ti.com

EXAMPLE BOARD LAYOUT

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.3)

6X (1.4)

40

33

40X (0.6)

1

32

40X (0.25)

2X

(1.12)

36X (0.5)

6X

(1.28)

(6.8)

(5.3)

41

SYMM

(R0.05) TYP

(

0.2) TYP

VIA

12

21

13

20

SYMM

(4.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222989/B 10/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.815) TYP

40

33

40X (0.6)

1

41

32

40X (0.25)

(1.28)

TYP

36X (0.5)

(0.64)

TYP

SYMM

(6.8)

(R0.05) TYP

8X

(1.08)

12

21

METAL

TYP

20

13

8X (1.43)

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

71% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4222989/B 10/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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型号：	TPS544B25RVFR
厂家：	TEXAS INSTRUMENTS
描述：	具有 PMBus 和频率同步功能的 4.5V 至 18V、20A 同步 SWIFT™ 降压转换器 \| RVF \| 40 \| -40 to 125 转换器
文件：	总99页 (文件大小：2708K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS544B25RVFR [TI]

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