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TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

TPS54541 具有软启动和 Eco-mode™ 的 4.5V 至 42V 输入、

5A、降压 DC-DC 转换器

1 特性

3 说明

1

•

轻负载条件下使用脉冲跳跃实现的高效率 Eco-

mode。™

TPS54541 器件是一款 42V 5A 降压型稳压器，此稳压

器具有一个集成型高侧 MOSFET。按照 ISO 7637 标

准，此器件能够耐受高达 45V 的抛负载脉冲。电流模

式控制提供了简单的外部补偿和灵活的组件选择。一个

低纹波脉冲跳跃模式将无负载输出电源电流减小至

152μA。使能引脚下拉为低电平后，关断电源电流降至

2µA。

87mΩ 高侧金属氧化物半导体场效应晶体管

(MOSFET)

152μA 静态运行电流和

2μA 关断电流

•

100kHz 至 2.5MHz 可调开关频率

同步至外部时钟

欠压闭锁在内部设定为 4.3V，但可用一个使能引脚上

的外部电阻分压器将之提高。输出电压启动斜坡受控于

软启动引脚，该引脚还可被配置用来控制电源排序和跟

踪。一个开漏电源正常信号表示输出处于标称电压值的

93% 至 106% 之内。

轻负载条件下使用集成型引导 (BOOT) 再充电场效

应晶体管 (FET) 实现的低压降

•

可调欠压闭锁 (UVLO) 电压和滞后

欠压 (UV) 和过压 (OV) 电源正常输出

可调软启动和定序

0.8V 1% 内部电压基准

宽可调开关频率范围可针对效率或者外部组件尺寸进行

优化。逐周期电流限制、频率折返和热关断功能可在过

载情况下保护内部和外部组件。

带有散热焊盘的 10 引脚晶圆级小外形无引线

(WSON) 封装

•

T_J运行范围为 -40°C 至 150°C

TPS54541 器件采用 10 引脚 4mm x 4mm WSON 封

装。

使用 TPS54541 并借助 WEBENCH Power

Designer 创建定制设计方案

器件信息⁽¹⁾

2 应用

器件型号

TPS54541

封装

封装尺寸（标称值）

•

工业自动化和电机控制

WSON (10)

4.00mm x 4.00mm

车辆附件：全球卫星定位 (GPS)（请参见

SLVA412），娱乐系统

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

•

USB 专用充电端口和电池充电器（请参见

SLVA464）

12V 和 24V 工业、汽车和通信电源系统

间隔

空白

简化电路原理图

V_IN

PWRGD

VIN

TPS54541

BOOT

EN

RT/CLK

SS/TR

V_OUT

SW

COMP

FB

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSC57

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

效率与负载电流间的关系

100

36 V to 12 V

95

90

85

12 V to 3.3 V

80

12 V to 5 V

75

70

65

60

V_OUT= 12 V, fsw = 620 kHz,

V_OUT= 5 V and 3.3 V, f sw = 400 kHz

0

0.5

1

1.5

2

2.5

3

3.5

C099

I_O- Output Current (A)

2

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

7.4 Device Functional Modes........................................ 28

Application and Implementation ........................ 29

8.1 Application Information............................................ 29

8.2 Typical Applications ............................................... 29

Power Supply Recommendations...................... 42

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 7

6.7 Switching Requirements ........................................... 7

6.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 43

10.1 Layout Guidelines ................................................. 43

10.2 Layout Example .................................................... 43

10.3 Estimated Circuit Area .......................................... 43

11 器件和文档支持 ..................................................... 44

11.1 器件支持................................................................ 44

11.2 文档支持................................................................ 44

11.3 接收文档更新通知 ................................................. 44

11.4 社区资源................................................................ 44

11.5 商标....................................................................... 44

11.6 静电放电警告......................................................... 45

11.7 Glossary................................................................ 45

12 机械、封装和可订购信息....................................... 45

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (February 2016) to Revision C

Page

•

WEBENCH 信息至特性，详细设计流程和器件支持部分........................................................................................................ 1

Changed Equation 10 and Equation 11 .............................................................................................................................. 21

Changed Equation 30 .......................................................................................................................................................... 30

Changed From: "power pad" To: "thermal pad" in the Layout Guidelines section............................................................... 43

Changes from Revision A (August 2015) to Revision B

Page

•

Added: SW, 5-ns Transient to the Absolute Maximum Ratings ............................................................................................ 5

Changed text in the Application Information From: "iterative design procedure" To: "interactive design procedure".......... 29

Changes from Original (October 2013) to Revision A

Page

•

已添加 ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文

档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1

3

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

5 Pin Configuration and Functions

DPR Package

10-Pin WSON With Exposed Thermal Pad

Top View

1

2

3

4

5

10

9

BOOT

VIN

PWRGD

SW

8

EN

GND

COMP

FB

7

SS/TR

RT/CLK

6

Pin Functions

I/O

DESCRIPTION

NAME

NO.

A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the

minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is

refreshed.

BOOT

1

O

Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency

compensation components to this pin.

COMP

EN

7

3

O

I

Enable pin, with an internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the

input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.

FB

6

8

I

Inverting input of the transconductance (gm) error amplifier.

Ground

GND

–

Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal

shutdown, dropout, over-voltage or EN shut down.

PWRGD

RT/CLK

SS/TR

10

O

I

Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an

external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,

a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and

the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-

enabled and the operating mode returns to resistor frequency programming.

5

Soft-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the

voltage on this pin overrides the internal reference, SS/TR can be used for tracking and sequencing.

4

I

SW

VIN

9

2

O

I

The source of the internal high-side power MOSFET and switching node of the converter.

Input supply voltage with 4.5-V to 42-V operating range.

The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper

operation.

Thermal Pad

11

–

4

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

6

Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.6

–7

MAX

45

8.4

8

UNIT

VIN

EN

BOOT–SW

FB

3

COMP

3

Voltage

PWRGD

6

V

SS/TR

3

RT/CLK

3.6

45

65

45

150

SW

SW, 5-ns Transient

SW, 10-ns Transient

–2

Operating junction temperature

Storage temperature

–40

–65

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

0.8

0

NOM

MAX

42

UNIT

V

V_VIN

V_O

I_O

Supply input voltage

Output voltage

41.1

5

V

Output current

A

T_J

Operating junction temperature

–40

150

°C

6.4 Thermal Information

TPS54541

THERMAL METRIC⁽¹⁾⁽²⁾

DPR (WSON)

10 PINS

35.1

UNIT

R_θJA

Junction-to-ambient thermal resistance (standard board)

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

34.1

12.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.3

ψ_JB

12.5

R_θJC(bot)

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Power rating at a specific ambient temperature T_Ashould be determined with a junction temperature of 150°C. This is the point where

distortion starts to substantially increase. See Power Dissipation Estimate for more information.

5

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

6.5 Electrical Characteristics

T_J= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4.5

4.1

42

V

Internal undervoltage lockout

threshold

Rising

4.3

4.48

Internal undervoltage lockout

threshold hysteresis

325

2.25

152

mV

Shutdown supply current

EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V

4.5

μA

Operating: nonswitching supply

current

FB = 0.9 V, T_A= 25°C

200

ENABLE AND UVLO (EN PIN)

Enable threshold voltage

No voltage hysteresis, rising and falling

Enable threshold +50 mV

1.1

1.2

–4.6

–1.2

–3.4

540

1.3

V

Input current

μA

Enable threshold –50 mV

–0.58

–2.2

-1.8

-4.5

Hysteresis current

Enable to COMP active

VOLTAGE REFERENCE

Voltage reference

μA

VIN = 12 V, T_A= 25°C

µs

0.792

0.8

87

0.808

185

V

HIGH-SIDE MOSFET

On-resistance

VIN = 12 V, BOOT-SW = 6 V

mΩ

ERROR AMPLIFIER

Input current

50

nA

Error amplifier transconductance

(gm)

–2 μA < I_COMP< 2 μA, V_COMP= 1 V

350

μS

Error amplifier transconductance

(gm) during soft-start

–2 μA < I_COMP< 2 μA, V_COMP= 1 V, V_FB= 0.4 V

77

μS

Error amplifier dc gain

V_FB= 0.8 V

10,000

2500

±30

V/V

kHz

μA

Min unity gain bandwidth

Error amplifier source/sink

V_(COMP)= 1 V, 100 mV overdrive

COMP to SW current

transconductance

17

A/V

CURRENT LIMIT

All VIN and temperatures, Open Loop⁽¹⁾

All temperatures, VIN = 12 V, Open Loop⁽¹⁾

VIN = 12 V, T_A= 25°C, Open Loop⁽¹⁾

6.3

7.1

7.5

60

8.8

8.3

7.9

Current limit threshold

A

Current limit threshold delay

THERMAL SHUTDOWN

Thermal shutdown

ns

176

12

°C

Thermal shutdown hysteresis

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

RT/CLK high threshold

1.55

1.2

2

V

RT/CLK low threshold

0.5

SOFT START AND TRACKING (SS/TR PIN)

Charge current

V_SS/TR= 0.4 V

98% nominal

1.7

42

µA

mV

V

SS/TR-to-FB matching

SS/TR-to-reference crossover

SS/TR discharge current (overload)

SS/TR discharge voltage

1.16

354

54

FB = 0 V, V_SS/TR= 0.4 V

FB = 0 V

µA

mV

POWER GOOD (PWRGD PIN)

FB threshold for PWRGD low

FB threshold for PWRGD high

FB threshold for PWRGD low

FB falling

FB rising

90%

93%

108%

(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.

6

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

Electrical Characteristics (continued)

T_J= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

PARAMETER

FB threshold for PWRGD high

Hysteresis

TEST CONDITIONS

MIN

TYP

106%

2.5%

10

MAX

UNIT

FB falling

Output high leakage

On resistance

V_PWRGD= 5.5 V, T_A= 25°C

nA

Ω

I_PWRGD= 3 mA, V_FB< 0.79 V

V_PWRGD< 0.5 V, I_PWRGD= 100 µA

45

Minimum VIN for defined output

0.9

2

V

6.6 Timing Requirements

T_J= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Minimum CLK input pulse width

15

55

ns

RT/CLK falling edge to SW rising edge delay – Measured at 500 kHz with RT

resistor in series

6.7 Switching Requirements

T_J= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

ƒ_SW

Switching frequency

R_T= 200 kΩ

450

100

500

550

kHz

Switching frequency

range using RT mode

2500

Switching frequency

range using CLK mode

160

2300

kHz

PLL lock in time

Measured at 500 kHz

78

μs

7

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

6.8 Typical Characteristics

0.25

0.2

0.814

0.809

0.804

0.799

0.794

0.789

0.784

0.15

0.1

0.05

BOOT-SW = 3 V

BOOT-SW = 6 V

V_II_NN==1122VV

0

25

50

75

100

125

150

0

25

50

75

100

125

150

œ50

œ25

œ50

œ25

C001

C002

T_Jœ Junction Temperature (°C)

Figure 1. ON Resistance vs Junction Temperature

Figure 2. Voltage Reference vs Junction Temperature

9

8.5

8

8.5

8

7.5

7

7.5

7

œ40°C

6.5

6

6.5

25°C

VVIN==1122VV

IN

150°C

6

0

25

50

75

100

125

150

0

5

10

15

20

25

30

35

40

45

œ50

œ25

C003

C004

T_Jœ Junction Temperature (°C)

V_I- Input Voltage (V)

Figure 3. Switch Current Limit vs Junction Temperature

Figure 4. Switch Current Limit vs Input Voltage

550

540

530

520

510

500

490

480

470

500

450

400

350

300

250

200

150

100

460

450

RT = 200 k, VIN = 1

V

R_T= 200 kꢀ, V_IN= 12 V

0

25

50

75

100

125

150

œ50

œ25

200

300

400

500

600

700

800

900 1000

C005

T_JJunction - Temperature (°C)

C006

RT/CLK - Resistance (kꢀ)

Figure 5. Switching Frequency vs Junction Temperature

Figure 6. Switching Frequency vs RT/CLK Resistance Low

Frequency Range

8

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

Typical Characteristics (continued)

2500

500

450

400

350

300

250

200

2000

1500

1000

500

0

IN = 12 V

V_IN= 12 V

0

50

100

150

200

0

25

50

75

100

125

150

œ50

œ25

C007

C008

RT/CLK - Resistance (kꢀ)

T_Jœ Junction Temperature (°C)

Figure 7. Switching Frequency vs RT/CLK Resistance High

Frequency Range

Figure 8. EA Transconductance vs Junction Temperature

120

110

100

90

1.3

1.27

1.24

1.21

1.18

80

70

60

50

40

30

IN = 12 V

V_IN= 12 V

IN = 12 V

V_IN= 12 V

20

1.15

0

25

50

75

100

125

150

0

25

50

75

100

125

150

œ50

œ25

œ50

œ25

C009

C010

T_Jœ Junction Temperature (°C)

Figure 9. EA Transconductance During Soft-Start vs

Junction Temperature

Figure 10. EN Pin Voltage vs Junction Temperature

œ3.5

œ0.5

œ3.7

œ3.9

œ4.1

œ4.3

œ4.5

œ4.7

œ4.9

œ5.1

œ5.3

œ5.5

œ0.7

œ0.9

œ1.1

œ1.3

œ1.5

œ1.7

œ1.9

œ2.1

œ2.3

œ2.5

IN = 12 V, IEN = Threshold + 50 mV

V_IN= 12 V, I_EN= Threshold + 50 mV

IN = 12 V, IEN = Threshold + 50 mV

V_IN= 12 V, I_EN= Threshold - 50 mV

0

25

50

75

100

125

150

0

25

50

75

100

125

150

œ50

œ25

œ50

œ25

C011

C012

T_Jœ Junction Temperature (°C)

Figure 11. EN Pin Current vs Junction Temperature

Figure 12. EN Pin Current vs Junction Temperature

9

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

Typical Characteristics (continued)

œ2.5

œ2.7

œ2.9

œ3.1

œ3.3

œ3.5

œ3.7

œ3.9

œ4.1

œ4.3

œ4.5

100.0

75.0

50.0

25.0

0.0

V

Falling

sense Falling

SENSE

VIN = 12 V

V_IN= 12 V

V_Ss_Ee_Nn_Ss_EeRFisailnligng

0.6 0.7

0

25

50

75

100

125

150

0.0

0.1

0.2

0.3

0.4

0.5

0.8

œ50

œ25

C013

C014

T_Jœ Junction Temperature (°C)

V_SENSE(V)

Figure 13. EN Pin Current Hysteresis vs Junction

Temperature

Figure 14. Switching Frequency vs FB

3

2.5

2

3

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

VIN = 12 V

T_J= 25 °C

VIN = 12 V

V_IN= 12 V

0

5

10

15

20

25

30

35

40

45

0

25

50

75

100

125

150

œ50

œ25

C016

V_IN- Input Voltage (V)

C015

T_Jœ Junction Temperature (°C)

Figure 15. Shutdown Supply Current vs Junction

Temperature

Figure 16. Shutdown Supply Current vs Input Voltage (VIN)

210

190

170

150

130

110

90

210

190

170

150

130

110

90

T = 25 °C

VIN = 12 V

V_IN= 12 V

J

70

0

5

10

15

20

25

30

35

40

45

0

25

50

75

100

125

150

œ50

œ25

C018

V_IN- Input Voltage (°C)

C017

T_Jœ Junction Temperature (°C)

Figure 17. VIN Supply Current vs Junction Temperature

Figure 18. VIN Supply Current vs Input Voltage

10

TPS54541

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ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

Typical Characteristics (continued)

4.5

4.4

4.3

4.2

4.1

4

2.6

2.5

2.4

2.3

2.2

2.1

2

3.9

3.8

3.7

UVLO Start Switching

UVLO Stop Switching

BOOT-PH UVLO Falling

BOOT-PH UVLO Rising

1.9

1.8

0

25

50

75

100

125

150

œ50

œ25

0

25

50

75

100

125

150

œ50

œ25

C020

T_Jœ Junction Temperature (°C)

C019

T_Jœ Junction Temperature (°C)

Figure 20. Input Voltage UVLO vs Junction Temperature

Figure 19. BOOT-SW UVLO vs Junction Temperature

80

110

FB

108

70

60

50

40

30

20

10

106

FB Falling

104

102

100

98

96

94

92

90

88

V_IN= 12 V

FB Rising

IN = 12 V

V_IN= 12 V

FB Falling

25

0

25

50

75

100

125

150

0

50

75

100

125

150

œ50

œ25

œ50

œ25

C021

C022

T_Jœ Junction Temperature (°C)

Figure 21. PWRGD ON Resistance vs Junction Temperature

Figure 22. PWRGD Threshold vs Junction Temperature

900

60

VIN = 12 V, 25 °C

V_IN= 12 V, 25 °C

800

700

600

500

400

300

200

100

0

55

50

45

40

35

30

25

IN = 12 V, FB = 0.4 V

V_IN= 12 V, FB = 0.4 V

20

0

100

200

300

400

500

600

700

800

0

25

50

75

100

125

150

œ50

œ25

C024

C025

SS/TR (mV)

T_Jœ Junction Temperature (°C)

Figure 23. SS/TR to FB Offset vs FB

Figure 24. SS/TR to FB Offset vs Temperature

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Typical Characteristics (continued)

5.6

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

Start

Stop

Dropout

Voltage

Dropout

Voltage

4.6

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

C026

Output Current (A)

Figure 25. 5-V Start and Stop Voltage

(see Low Dropout Operation and Bootstrap Voltage (BOOT))

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7 Detailed Description

7.1 Overview

The TPS54541 is a 42-V 5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. The

device implements constant-frequency current-mode control which reduces output capacitance and simplifies

external frequency compensation. The wide switching frequency range of 100 to 2500 kHz allows for either

efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted

using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL)

connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of an external clock

signal.

The TPS54541 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the input-voltage

undervoltage-lockout (UVLO) threshold with two external resistors. An internal-pullup current source enables

operation when the EN pin is floating. The operating current is 152 μA under a no-load condition when not

switching. When the device is disabled, the supply current is 2 μA.

The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering 5

A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied by

a bootstrap capacitor connected from the BOOT to SW pins. The TPS54541 device reduces the external

component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a

UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset

threshold. An automatic BOOT capacitor recharge circuit allows the TPS54541 device to operate at high duty

cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of

the application. The minimum output voltage is the internal 0.8-V feedback reference.

Output overvoltage transients are minimized by an overvoltage protection (OVP) comparator. When the OVP

comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than

106% of the desired output voltage.

The SS/TR (soft-start/tracking) pin minimizes inrush currents or provides power-supply sequencing during power

up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor divider can be

connected to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged before the

output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO fault, or a

disabled condition. When the overload condition is removed, the soft-start circuit controls the recovery from the

fault output level to the nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency

during startup and overcurrent fault conditions to help maintain control of the inductor current.

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7.2 Functional Block Diagram

PWRGD

EN

V_DD

Shutdown

Thermal

Shutdown

UVLO

Enable

Comparator

UV

OV

Logic

Shutdown

Logic

Enable

Threshold

Boot

Charge

Voltage

Reference

Minimum

Clamp

Pulse

Boot

UVLO

Current

Sense

Skip

Error

Amplifier

PWM

Comparator

FB

BOOT

SS/TR

Logic

Shutdown

Slope

Compensation

S

SW

COMP

Frequency

Shift

Overload

Recovery

Maximum

Clamp

Oscillator

With PLL

RT/CLK

GND

Thermal Pad

7.3 Feature Description

7.3.1 Fixed-Frequency PWM Control

The TPS54541 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. The

output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by

an error amplifier. An internal oscillator initiates the turn-on of the high-side power switch. The error amplifier

output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current

reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage

increases and decreases as the output current increases and decreases. The device implements current limiting

by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a

minimum voltage clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54541 device adds a compensating ramp to the MOSFET switch current-sense signal. This slope

compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the

high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.

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Feature Description (continued)

7.3.3 Pulse Skip Eco-mode

The TPS54541 device operates in a pulse-skipping Eco-mode at light-load currents to improve efficiency by

reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at

the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode. The

pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of

600 mV.

When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.

Because the device is not switching, the output voltage begins to decay. The voltage-control loop responds to

the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching

resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to

the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the

device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light

load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54541 device senses and controls peak switch current, not the average

load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor

value. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 152-

μA input quiescent current. The circuit in Figure 46 enters Eco-mode at about 18-mA output current and with no

external load has an average input current of 260 µA.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54541 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT

and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor refreshes when the

high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT

capacitor is 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating

of 10 V or higher for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54541

device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the

voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side

MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at

high output voltages, the low-side MOSFET is disabled at 24-V output and re-enabled when the output reaches

21.5 V.

Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET remains on for

many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of the

switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is

mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode

voltage, and the printed circuit-board resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is

plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within

1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where

switching stops.

During high duty-cycle (low dropout) conditions, the inductor current ripple increases when the BOOT capacitor

recharges resulting in an increase in output voltage ripple. Increased ripple occurs when the off-time required to

recharge the BOOT capacitor is longer than the high-side off-time associated with cycle-by-cycle PWM control.

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Feature Description (continued)

At heavy loads, the minimum input voltage must increase to ensure a monotonic start-up. Use Equation 1 to

calculate the minimum input voltage for this condition.

V_Omax = Dmax × (V_VINmin – I_Omax × R_DS(on)+ V_d) – V_d– I_Omax × R_dc

(1)

where

•

Dmax ≥ 0.9

V_d= forward drop of the catch diode

R_DS(on)= 1 / (–0.3 × VB2SW²+ 3.577 × VB2SW – 4.246)

–

VB2SW = VBOOT + Vd

VBOOT = (1.41 × V_VIN– 0.554 – V_d× ƒ_SW– 1.847 × 10³× IB2SW) / (1.41 + ƒ_SW

)

IB2SW = 100 × 10^-6

A

7.3.5 Error Amplifier

The TPS54541 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier

compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.

The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation,

the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.

The frequency-compensation components (capacitor, series resistor, and capacitor) connect between the error

amplifier output COMP pin and GND pin.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature

and voltage range by scaling the output of a bandgap-reference circuit. A resistor divider from the output node to

the FB pin sets the output voltage. Using 1% tolerance or better divider resistors is recommended. Select the

low-side resistor R_LSfor the desired divider current and use Equation 2 to calculate R_HS. To improve efficiency at

light loads consider using larger value resistors. However, if the values are too high, the regulator is more

susceptible to noise and voltage errors from the FB input current could become noticeable.

æ

ç

è

ö

÷

ø

V_OUT- 0.8 V

R

= R

´

HS

LS

0.8 V

(2)

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54541 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the

enable threshold of 1.2 V. The TPS54541 device disables when the VIN pin voltage falls below 4 V or when the

EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I₁, of 1.2 μA enabling operation

of the TPS54541 device when the EN pin floats.

If an application requires a higher UVLO threshold, use the circuit shown in Figure 26 to adjust the input voltage

UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis

current, I_HYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4-μA I_HYScurrent is

removed. This additional current facilitates adjustable input-voltage UVLO hysteresis. Use Equation 3 to calculate

R_UVLO1for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R_UVLO2for the desired VIN start

voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 to 9 V) and withstand high input

voltages (for example, 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of

8.4 V during the high input-voltage condition. To avoid exceeding this voltage when using the EN resistors, the

EN pin is clamped internally with a 5.8-V Zener diode capable of sinking up to 150 μA.

V

- V

STOP

START

R

=

UVLO1

I

HYS

(3)

V

ENA

R

=

UVLO2

V

- V

ENA

START

+ I

1

R

UVLO1

(4)

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Feature Description (continued)

VIN

TPS54541

VIN

TPS54541

i1 ihys

R_UVLO1

10 kΩ

EN

Node

V

EN

5.8 V

R_UVLO2

Figure 26. Adjustable Undervoltage Lockout

(UVLO)

Figure 27. Internal EN Pin Clamp

7.3.8 Soft-Start/Tracking Pin (SS/TR)

The TPS54541 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin

voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor on the

SS/TR pin to ground implements a soft-start time. The TPS54541 device has an internal pullup current source of

1.7 μA that charges the external soft-start capacitor. The calculations for the soft start time (10% to 90%) are

shown in Equation 5. The voltage reference (V_REF) is 0.8 V and the soft-start current (I_SS) is 1.7μA. The soft-start

capacitor should remain lower than 0.47 μF and greater than 0.47 nF.

T_SS(ms) ´ I_SS(µA)

C_SS(nF) =

V_REF(V) ´ 0.8

(5)

At power up, the TPS54541 device does not begin switching until the soft start pin is discharged to less than 54

mV to ensure a proper power-up, see Figure 28.

Also, during normal operation, the TPS54541 device stops switching, the SS/TR must discharge to 54 mV, and,

when the VIN UVLO is exceeded, the EN pin must pull below 1.2 V, otherwise a thermal shutdown event occurs.

The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.

When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the

effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).

The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.

Figure 28. Operation of SS/TR Pin when Starting

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Feature Description (continued)

7.3.9 Sequencing

Many of the common power supply sequencing methods are implemented using the SS/TR, EN, and PWRGD

pins. The sequential method is implemented using an open-drain output of a power on the reset pin of another

device. The sequential method is illustrated in Figure 29 using two TPS54541 devices. The power good is

connected to the EN pin on the TPS54541 device which enables the second power supply once the primary

supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply

provides a 1-ms startup delay. Figure 30 shows the results of Figure 29.

spacer

TPS54541

PWRGD

TPS54541

EN

SS /TR

PWRGD

Figure 29. Schematic for Sequential Startup Sequence

Figure 30. Sequential Startup using EN and PWRGD

TPS54541

3

4

6

EN

SS/TR

PWRGD

TPS54541

EN

3

4

6

SS/TR

PWRGD

Figure 32. Ratiometric Startup Using Coupled SS/TR pins

Figure 31. Schematic for Ratiometric Startup Sequence

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Feature Description (continued)

Figure 31 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The

regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the pullup

current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.

TPS54541

EN

VOUT

1

SS /TR

PWRGD

TPS54541

VOUT

2

EN

R 1

R 2

SS / TR

PWRGD

R3

R 4

Figure 33. Schematic for Ratiometric and Simultaneous Startup Sequence

Ratiometric and simultaneous power-supply sequencing are implemented by connecting the resistor network of

R1 and R2 shown in Figure 33 to the output of the power supply that must be tracked or another voltage

reference source. Using Equation 6 and Equation 7, calculate the tracking resistors to initiate the V_OUT2slightly

before, after or at the same time as V_OUT1. Equation 8 is the voltage difference between V_OUT1and V_OUT2at the

95% of nominal output regulation.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset

(V_SSoffset) in the soft-start circuit and the offset created by the pullup-current source (I_SS) and tracking resistors,

the V_SSoffsetand I_SSare included as variables in the equations.

To design a ratio-metric start-up in which the V_OUT2voltage is slightly greater than the V_OUT1voltage when V_OUT2

reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a

positive number for applications which the V_OUT2is slightly lower than V_OUT1when V_OUT2regulation is achieved.

Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO, or thermal shutdown

fault, careful selection of the tracking resistors ensures that the device restarts after a fault. The calculated R1

value from Equation 6 must be greater than the value calculated in Equation 9 to ensure the device recovers

from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the V_SSoffsetbecomes larger as

the soft-start circuits gradually hands-off the regulation reference to the internal voltage reference. The SS/TR pin

voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in

Figure 23.

V_OUT2+ DV V_SSoffset

´

R1=

V_REF

V_REF´ R1

V_OUT2+ DV - V_REF

I_SS

(6)

R2 =

(7)

(8)

DV = V_OUT1- V_OUT2

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Feature Description (continued)

R1> 2800 ´ V_OUT1-180 ´ DV

(9)

Figure 34. Ratiometric Startup with Tracking Resistors

Figure 35. Ratiometric Startup with Tracking Resistors

Figure 36. Simultaneous Startup With Tracking Resistor

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Feature Description (continued)

7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)

The switching frequency of the TPS54541 device is adjustable over a wide range from 100 to 2500 kHz by

placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must

have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching

frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size

typically set the switching frequency as high as possible. Consider the tradeoffs of the conversion efficiency,

maximum input voltage, and minimum controllable on time. The minimum controllable on time is typically 135 ns,

which limits the maximum operating frequency in applications with high input to output step-down ratios. The

maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed discussion of the

maximum switching frequency is provided in the next section.

101756

f sw (kHz)^1.008

R_T(kW) =

(10)

92417

RT (kW)^0.991

f sw (kHz) =

(11)

7.3.11 Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement

this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in

Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2.0 V and

have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 to 2300 kHz. The rising edge

of the SW synchronizes to the falling edge of RT/CLK pin signal. Design the external synchronization circuit such

that the default-frequency set resistor connects from the RT/CLK pin to ground when the synchronization signal

is off. When using a low impedance signal source, the frequency set resistor connects in parallel with an AC-

coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 37. The two resistors in the

series provide the default-frequency-setting resistance when the signal source is turned off. The sum of the

resistance sets the switching frequency close to the external CLK frequency. AC-coupling the synchronization

signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.

The first time the RT/CLK is pulled above the PLL threshold, the TPS54541 device switches from the RT-resistor

free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and

the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching

frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from

the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition

from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then

increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the

RT/CLK resistor.

The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device

implements a digital frequency foldback enables synchronization to an external clock during normal startup and

fault conditions. Figure 38, Figure 39 and Figure 40 show the device synchronized to an external system clock in

continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).

SPACER

TPS54541

PLL

TPS54541

PLL

RT/CLK

RT

RT/CLK

RT

Hi-Z

Clock

Source

Clock

Source

Figure 37. Synchronizing to a System Clock

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Feature Description (continued)

Figure 39. Plot of Synchronizing in DCM

Figure 38. Plot of Synchronizing in CCM

Figure 40. Plot of Synchronizing in Eco-mode

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Feature Description (continued)

7.3.12 Maximum Switching Frequency

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54541

device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin

voltage falls from 0.8 V to 0 V. The TPS54541 device uses a digital frequency foldback to enable synchronization

to an external clock during normal startup and fault conditions. During short-circuit events, the inductor current

can exceed the peak current-limit because of the high-input voltage and the minimum controllable on time. When

the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off

time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle

providing more time for the inductor current to ramp down.

With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is

controlled by frequency-foldback protection. Equation 13 calculates the maximum switching frequency at which

the inductor current remains under control when V_OUTis forced to V_OUT(SC). The selected operating frequency

must not exceed the calculated value.

Equation 12 calculates the maximum switching-frequency limitation set by the minimum controllable on time and

the input to output step-down ratio. Setting the switching frequency above this value causes the regulator to skip

switching pulses to achieve the low duty cycle required to regulate the output voltage at maximum input voltage.

æ

ç

ö

÷

I_O´R_dc+ V_OUT+ V_d

1

ƒ_{SW maxskip}

=

´

(

)

ç

÷

t_ON

V_IN-I_O´ R_{DS on}+ V_d

( )

è

ø

(12)

(13)

æ

ç

ö

I_CL´R_dc+ V_{OUT sc}+ V_d

ƒ_DIV

( )

÷

ƒ_SW(shift)

=

´

ç

÷

t_ON

V_IN-I_CL´R_{DS on}+ V_d

( )

è

ø

where (for Equation 12 and Equation 13)

•

I_O= output current

I_CL= current limit

R_dc= inductor resistance

V_IN= maximum input voltage

V_OUT= output voltage

V_OUT(SC)= output voltage during short

V_d= diode voltage drop

R_DS(on)= switch on resistance

t_ON= controllable on time

ƒ_DIV= frequency divide equals (1, 2, 4, or 8)

7.3.13 Accurate Current Limit Operation

The TPS54541 device implements peak current-mode control in which the COMP pin voltage controls the peak

current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage

are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side

switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases

switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level, which

sets the peak switch current limit. The TPS54541 device provides an accurate current limit threshold with a

typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor

current. The relationship between the inductor value and the peak inductor current is shown in Figure 41.

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Feature Description (continued)

Peak Inductor Current

Δ_CLPeak

Open Loop Current Limit

Δ_CLPeak= V /L x t_CLdelay

IN

t_CLdelay

t_ON

Figure 41. Current Limit Delay

7.3.14 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. When the FB pin is between 93% and 106% of the internal voltage

reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is

5.5 V or less is recommended. A higher pullup resistance reduces the amount of current drawn from the pullup

voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise

seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but

with reduced current sinking capability. The PWRGD achieves full current sinking capability as VIN input voltage

approaches 3 V.

The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal

reference voltage. If the UVLO or thermal shutdown are asserted or the EN pin pulled low, the PWRGD is pulled

low.

7.3.15 Overvoltage Protection

The TPS54541 device incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients in designs with low-output capacitance.

For example, when the power supply output is overloaded the error amplifier compares the actual output voltage

to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a

considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak

current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier

output transitions to the normal operating level. In some applications, the power-supply output voltage increases

faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin

voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin

voltage is greater than the rising OVP threshold, the high-side MOSFET immediately disables to minimize output

overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal

voltage reference, the high-side MOSFET resumes normal operation.

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Feature Description (continued)

7.3.16 Thermal Shutdown

The TPS54541 device provides an internal thermal shutdown to protect the device when the junction

temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the

thermal trip threshold. When the die temperature falls below 164°C, the device reinitiates the power-up sequence

controlled by discharging the SS/TR pin.

7.3.17 Small-Signal Model for Loop Response

Figure 42 shows a simplified equivalent model for the TPS54541 control loop which can be simulated to check

the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a

gm_EAof 350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor

R_Oand capacitor C_Omodel the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage

source between the nodes a and b effectively breaks the control loop for the frequency response measurements.

Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small

signal response of the overall loop. The dynamic loop response is evaluated by replacing R_Lwith a current

source with the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is

only valid for CCM operation.

SW

V

O

Power Stage

gm 17 A/V

ps

a

b

R

R1

ESR

R

COMP

L

c

FB

C

OUT

0.8 V

CO

RO

R3

C1

gm

ea

C2

R2

350 mA/V

Figure 42. Small-Signal Model for Loop Response

7.3.18 Simple Small-Signal Model for Peak-Current-Mode Control

Figure 43 describes a simple small-signal model used to design the frequency compensation. The TPS54541

power stage is approximated by a voltage-controlled current source (duty-cycle modulator) supplying current to

the output capacitor and load resistor. Equation 14 shows the control to output transfer function. The control to

output transfer function consists of a DC gain, one dominant pole, and one equivalent-series-resistor (ESR) zero.

The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 42) is the

power stage transconductance, gm_PS. The gm_PSfor the TPS54541 device is 17 A/V. The low-frequency gain of

the power stage is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load may seem problematic, but the dominant pole moves with the load current (see

Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 43. As the load

current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the

same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a

profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors can

reduce the number of frequency compensation components required to stabilize the overall loop because the

phase margin is increased by the ESR zero of the output capacitor (see Equation 17).

25

TPS54541

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Feature Description (continued)

V

O

Adc

VC

R

ESR

fp

R

L

gm

ps

C

OUT

fz

Figure 43. Simple Small-Signal Model and Frequency Response for Peak Current-Mode Control

æ

ç

è

ö

s

1+

÷

2p ´ ƒ_{Z ø}

V_OUT

VC

= Adc ´

æ

ç

ö

÷

s

1+

2p ´ ƒ_{P ø}

è

(14)

(15)

Adc = gm_ps´ R_L

1

ƒ_P

=

C_OUT´ R_L´ 2p

(16)

(17)

1

ƒ_Z

=

C_OUT´ R_ESR´ 2p

7.3.19 Small Signal Model for Frequency Compensation

The TPS54541 device uses a transconductance amplifier for the error amplifier and supports three of the

commonly-used frequency compensation circuits. Figure 44 shows compensation circuits Type 2A, Type 2B, and

Type 1 . Type 2 circuits are typically implemented in high-bandwidth power-supply designs using low-ESR output

capacitors. The Type 1 circuit is implemented with power-supply designs with high-ESR aluminum electrolytic or

tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small

signal model in Figure 44. The open-loop gain and bandwidth are modeled using the R_Oand C_Oshown in

Figure 44. See Figure 44 for a design example using a Type 2A network with a low-ESR output capacitor.

Equation 18 through Equation 27 are provided as references. An alternative is to use WEBENCH^®software tools

to create a design based on the power-supply requirements (go to www.ti.com/WEBENCH for more information).

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Feature Description (continued)

V_O

R1

FB

Type 2A

Type 2B

Type 1

gm_ea

COMP

V_REF

C2

R3

C1

R3

R2

C2

R_O

C_O

C1

Figure 44. Types of Frequency Compensation

Aol

A0

P1

Z1

P2

A1

BW

Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Aol V / V

(

gm_ea

)

R_O

=

(18)

(19)

gm_ea

C_O

=

2p ´ BW (Hz)

æ

ç

è

ö

s

1+

÷

2p ´ ƒ_{Z1 ø}

EA = A0 ´

æ

ç

è

ö

æ

ö

s

1+

´ 1+

÷

ç

÷

2p ´ ƒ_{P1 ø}

2p ´ ƒ_{P2 ø}

è

(20)

(21)

(22)

R2

A0 = gm_ea´ R_O

´

R

1

+

R2

A1= gm_ea´ R_OP R3 ´

R

1

+

R2

1

P1=

2p´Ro´ C1

(23)

27

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

Feature Description (continued)

1

Z1=

2p´R3´ C1

(24)

(25)

(26)

(27)

1

P2 =

Type 2A

2p ´ R3PR_O´ C2 + C

(

)

O

1

P2 =

Type 2B

2p ´ R3PR_O´ C_O

1

Type 1

2p ´ R_O´ C2 + C

(

)

O

7.4 Device Functional Modes

TI designed the TPS54541 to operate with input voltages above 4.5 V. When the VIN voltage is above the 4.3-V

typical rising UVLO threshold and the EN voltage is above the 1.2-V typical threshold, the device is active. If the

VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the EN voltage falls

below the 1.2-V threshold, the device stops switching and enters shutdown mode with a low-supply current of 2

µA typical.

The TPS54541 operates in CCM when the output current is enough to keep the inductor current above 0 A at the

end of each switching period. As a non-synchronous converter, the device enters DCM at low-output currents

when the inductor current falls to 0 A before the end of a switching period. At very-low output current, the COMP

voltage drops to the pulse-skipping threshold and the device operates in a pulse-skipping Eco-mode. In this

mode, the high-side MOSFET does not switch every switching period. This operating mode reduces power loss,

while regulating the output voltage. For more information on Eco-mode, see the Pulse Skip Eco-mode section.

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TPS54541

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54541 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device

typically converts a higher-dc voltage to a lower-dc voltage with a maximum available output current of 5 A.

Example applications are the following: 12-V and 24-V industrial, automotive, and communication power

systems. Use the following design procedure to select component values for the TPS54541 device. The

spreadsheet (SLVC452) on the product page can help with all calculations. Alternatively, use the WEBENCH

software to generate a complete design. The WEBENCH software uses an interactive design procedure and

accesses a comprehensive database of components when generating a design.

8.2 Typical Applications

8.2.1 Buck Converter for 6-V to 42-V Input and 3.3-V at 5-A Output

PWRGD

PWRGD PULL UP

R8

6V to 42V

U1

VIN

TP10

TP9

1.00k

2

1

2

3

5

4

7

10

1

VIN

PWRGD

BOOT

SW

C4

TP1

TP2

C11

GND

L1

EN

+

3.3V @ 5A

R1

365k

C10

4.7µF

C3

4.7µF

C1

4.7µF

C2

4.7µF

0.1µF

DNP

9

1

2

J2

VOUT

GND

RT/CLK

SS/TR

COMP

TP5

TP6

TP4

TP7

TP8

744325550

5.5µH

SS/TR

C13

6

FB

R3

243k

R7

49.9

8

J1

GND

PAD

D1

PDS760-13

+

C12

GND

C9

C7 DNP

47µF

100µF

DNP

C6

100µF

R4

16.9k

TPS54541DPR

GND

0.01µF

C8

47pF

2

1

GND

R5

31.6k

C5

4700pF

J4

R2

88.7k

2

1

EN

GND

FB

GND

J3

R6

10.2k

TP3

GND

2

1

SS/TR

GND

SS/TR

GND

J5

Figure 46. 3.3-V Output TPS54541 Design Example

8.2.1.1 Design Requirements

This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. A few

parameters must be known to start the design process. These requirements are typically determined at the

system level. Calculations can be done with WEBENCH or the excel spreadsheet (SLVC452) located on the

product page. TI designed this example to the known parameters listed in Table 1.

Table 1. Design Parameters

PARAMETER

VALUE

Output Voltage

3.3 V

Transient Response 1.25 A to 3.75 A load step

Maximum Output Current

Input Voltage

ΔV_OUT= 4 %

5 A

12 V nominal 6 V to 42 V

0.5% of V_OUT

5.75 V

Output Voltage Ripple

Start Input Voltage (rising VIN)

Stop Input Voltage (falling VIN)

4.5 V

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TPS54541

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www.ti.com.cn

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54541 device with the WEBENCH^®Power Designer.

1. Start by entering your V_IN, V_OUT, and I_OUTrequirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with

real time pricing and component availability.

4. In most cases, you will also be able to:

–

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand the thermal performance of your board

Export your customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share your design with colleagues

5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Selecting the Switching Frequency

Choose a switching frequency for the regulator. Typically, a designer uses the highest switching frequency

possible because this produces the smallest solution size. High-switching frequency allows for lower-value

inductors and smaller-output capacitors compared to a power supply that switches at a lower frequency. The

switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input

voltage, the output voltage, and the frequency-foldback protection.

Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator.

Choose the lower value result from the two equations. Switching frequencies higher than these values results in

pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, t_onmin, is 135 ns for the TPS54541 device. For this example, the output voltage is

3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of

10.3 mΩ, typical switch resistance of 87 mΩ and 5-A load, from Equation 12 the maximum switch frequency to

avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits, use

Equation 10 to determine the maximum switching frequency for frequency foldback protection. With a current-

limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.

For this design, TI chose a lower-switching frequency of 400 kHz to operate below the calculated maximums. To

determine the timing resistance for a given switching frequency, use Equation 10 or the curve in Figure 6.

Figure 46 shows resistor R₃, which sets the switching frequency . For 400-kHz operation, the closest standard

value resistor is 243 kΩ.

æ

ç

è

ö

÷

ø

1

5 A x 10.3 mW + 3.3 V + 0.52 V

42 V - 5 A x 87 mW + 0.52 V

f

=

´

= 680 kHz

SW(maxskip)

135ns

(28)

æ

ç

è

ö

÷

ø

8

6.3 A x 10.3 mW + 0.1 V + 0.52 V

42 V - 6.3 A x 87 mW + 0.52 V

f

=

´

= 960 kHz

SW(shift)

135 ns

(29)

(30)

101756

400 (kHz)^1.008

R_T(kW) =

= 242 kW

8.2.1.2.3 Output Inductor Selection (L_O)

To calculate the minimum value of the output inductor, use Equation 31.

K_INDis a ratio that represents the amount of inductor ripple current relative to the maximum output current. The

inductor ripple current is filtered by the output capacitor. Choosing high inductor ripple currents impacts the

selection of the output capacitor because the output capacitor must have a ripple current rating equal to or

greater than the inductor ripple current. The inductor ripple value is at the discretion of the designer, but the

following guidelines may be used.

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TPS54541

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ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

For designs using low-ESR output capacitors such as ceramics, use a value as high as K_IND= 0.3. When using

higher-ESR output capacitors, K_IND= 0.2 yields better results. Because the inductor ripple current is part of the

current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable

PWM operation. In a wide input voltage regulator, choose a relatively large inductor ripple current. This provides

sufficient ripple current with the input voltage at the minimum.

For this design example, K_IND= 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS

current and saturation current ratings of the inductor not be exceeded. See Equation 33 and Equation 34 for the

RMS and peak inductor current. For this design, the RMS inductor current is 5 A and the peak inductor current is

5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS

current rating of 10 A. This inductor also has a typical inductance of 5.5 µH at no load and 4.8 µH at 5-A load.

Lastly, the inductor has a DCR of 10.3 mΩ.

As the equation set demonstrates, lower-ripple currents reduce the output voltage ripple of the regulator but

require a larger value of inductance. Selecting higher-ripple currents increases the output voltage ripple of the

regulator but allow for a lower-inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During powerup,

faults, or transient load conditions, the inductor current can increase above the peak inductor current level

calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of

the device. For this reason, the most conservative design approach is to choose an inductor with a saturation

current rating equal to or greater than the switch current limit of the TPS54541 device, which is nominally 7.5 A.

V

- V_OUT

IN max

(

V_OUT

)

42 V – 3.3 V

5 A ´ 0.3

3.3 V

L_{O min}

=

´

=

´

= 5.1 µH

(

)

I

_OUT´ K_IND

V

´ ƒ_SW

42 V ´ 400 kHz

IN max

(

)

(31)

(32)

spacer

I_RIPPLE

V

_OUT´ (V

- V_OUT)

IN max

(

)

3.3 V ´ (42 V – 3.3 V)

=

= 1.58 A

V

´ L_O´ ƒ_SW

42 V ´ 4.8 µH ´ 400 kHz

IN max

(

)

spacer

2

æ

ö

2

V

´ V

- V

OUT

(

OUT

)

æ

ç

è

ö

÷

ø

IN max

(

3.3 V ´ 42 V – 3.3 V

)

(

)

1

ç

÷

1

2

)

2

I

=

I

(

+

´

=

5 A

+

´

= 3.5 A

( )

OUT

÷

L rms

(

)

12

V

´ L ´ ƒ

12

42 V ´ 4.8 µH ´ 400 kHz

O

SW

IN max

(

)

ç

÷

è

ø

(33)

spacer

I_{L peak}= I_OUT

I_RIPPLE

1.58 A

2

+

= 5 A +

= 5.79 A

(

)

2

(34)

8.2.1.2.4 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

determines the following:

•

The modulator pole

The output voltage ripple

How the regulator responds to a large change in load current

Select the output capacitance based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor must to

supply the increased load current until the regulator responds to the load step. A regulator does not respond

immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The

regulator usually requires two or more clock cycles for the control loop to sense the change in output voltage and

adjust the peak switch current in response to the higher load. The output capacitance must be large enough to

supply the difference in current for two clock cycles to maintain the output voltage within the specified range.

Equation 35 shows the minimum output capacitance necessary, where ΔI_OUTis the change in output current, ƒsw

is the switching frequency of the regulators and ΔV_OUTis the allowable change in the output voltage. For this

31

TPS54541

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www.ti.com.cn

example, the transient load response is specified as a 4% change in V_OUTfor a load step from 1.25 A to 3.75 A.

ΔI_OUTis 3.75 A – 1.25 A = 2.5 A and ΔV_OUT= 0.04 × 3.3 V = 0.13 V. These values provide a minimum

capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage

change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and

tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to

low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can

produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical load

step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. The

capacitor must be sized to maintain the output voltage during these transient periods. Equation 36 calculates the

minimum capacitance required to keep the output voltage overshoot to a desired value, where L_Ois the value of

the inductor, I_OHis the output current under heavy load, I_OLis the output under light load, V_fis the peak output

voltage and Vi is the initial voltage. For this example, the worst case load step is from 3.75 A to 1.25 A. The

output voltage increases during this load transition and the stated maximum in our specification is 4% of the

output voltage. This makes V_f= 1.04 × 3.3 V = 3.43 V. V_Iis the initial capacitor voltage which is the nominal

output voltage of 3.3 V. The values in Equation 36 yield a minimum capacitance of 68 μF.

Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,

where ƒsw is the switching frequency, V_ORIPPLEis the maximum allowable output voltage ripple, and I_RIPPLEis the

inductor ripple current. Equation 37 yields 30 μF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification. Equation 38 indicates the equivalent ESR should be less than 10 mΩ.

The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within

regulation tolerance during a load transient.

Capacitance de-ratings for aging, temperature, and DC bias increases this minimum value. For this example, two

100-μF 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR are used. The derated capacitance is 130 µF, well

above the minimum required capacitance of 95 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor

reliability, especially non ceramic capacitors. Some capacitor data sheets specify the Root Mean Square (RMS)

value of the maximum ripple current. Equation 39 can calculate the RMS ripple current that the output capacitor

must support. For this example, Equation 39 yields 460 mA.

2´ DI

2 ´ 2.5 A

OUT

C

>

=

= 95 mF

OUT

f

´ DV

400 kHz x 0.13 V

SW

OUT

(35)

2

(_OH) (_OL)

2

3.75 A²-1.25 A²

I

-

I

(

)

(

)

= 68 mF

)

C_OUT> L_O

x

= 4.8 mH x

2

3.43 V²- 3.3 V²

V

-

V

I

( ) ( )

(

f

(

)

(36)

1

C

>

´

=

x

= 30 mF

OUT

8´ f

8 x 400 kHz

16 mV

1.58 A

æ

ç

è

ö

÷

ø

æ

ö

V

SW

ORIPPLE

ç

è

÷

ø

I

RIPPLE

16 mV

1.58 A

(37)

(38)

V

ORIPPLE

R

<

=

= 10 mW

ESR

I

RIPPLE

V

´ V

(

IN max

(

- V

OUT

)

=

IN max

(

3.3 V ´ 42 V - 3.3 V

)

(

)

12 ´ 42 V ´ 4.8 mH ´ 400 kHz

I

=

= 460 mA

COUT(rms)

12 ´ V

´L ´ f

O

SW

)

(39)

8.2.1.2.5 Catch Diode

The TPS54541 device requires an external catch diode between the SW pin and GND. The selected diode must

have a reverse voltage rating equal to or greater than V_IN(max). The peak current rating of the diode must be

greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due

to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

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Typically, diodes with higher voltage and current ratings have higher forward voltages. TI recommends a diode

with a minimum of 42-V reverse voltage to allow input voltage transients up to the rated voltage of the TPS54541

device.

For the example design, the PDS760 Schottky diode is selected for its lower forward voltage and good thermal

characteristics compared to smaller devices. The typical forward voltage of the PDS760 is 0.52 V at 5 A and

25°C.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during

the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input

voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by

the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher

switching frequencies, consider the AC losses of the diode. The AC losses of the diode are due to the charging

and discharging of the junction capacitance and reverse recovery charge. Equation 40 calculates the total power

dissipation, including conduction losses and AC losses of the diode.

The PDS760 diode has a junction capacitance of 180 pF. Using Equation 40, the total loss in the diode at the

nominal input voltage is 1.89 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a

diode, which has a low leakage current and slightly higher forward voltage drop.

C_j´ ƒ_SW´(V_IN+ Vƒd)²

(V_IN- V_OUT)´I_OUT´ Vƒd

=

P_D=

+

V

2

IN

(12V - 3.3V)´5A´0.52V 180pF´ 400kHz ´(12V + 0.52V)²

+

= 1.89W

12V

2

(40)

8.2.1.2.6 Input Capacitor

The TPS54541 device requires a high-quality ceramic-type X5R or X7R input decoupling capacitor with at least 3

μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective

capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor

must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater

than the maximum input current ripple of the TPS54541 device. Use Equation 41 to calculate the input ripple

current.

The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor.

The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more

stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor

must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC

bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients

up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V,

16 V, 25 V, 50 V, or 100 V. This example uses four 4.7-μF 50-V capacitors in parallel. Table 2 shows several

choices of high-voltage capacitors.

The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage

ripple occurs at 50% duty cycle and can be calculated using Equation 42. Using the design example values, I_OUT

= 5 A, C_IN= 18.8 μF, ƒ_SW= 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of

2.5 A.

V

- V

OUT

)

= 5 A

(

IN min

(

6 V - 3.3 V

)

V

(

)

3.3 V

6 V

OUT

I

= I

x

´

= 2.5 A

OUT

CI rms

(

)

V

6 V

IN min

(

IN min

(

)

(41)

(42)

I

´ 0.25

5 A ´ 0.25

18.8 mF ´ 400 kHz

OUT

DV

=

= 170 mV

IN

C

´ f

IN

SW

33

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

Table 2. Capacitor Types

VENDOR

VALUE (μF)

1 to 2.2

1 to 4.7

1

EIA Size

VOLTAGE (V)

DIALECTRIC

COMMENTS

100

50

1210

GRM32 series

GRM31 series

Murata

100

50

1206

2220

2225

1812

1210

1812

1 to 2.2

1 to 1.8

1 to 1.2

1 to 3.9

1 to 1.8

1 to 2.2

1.5 to 6.8

1 to 2.2

1 to 3.3

1 to 4.7

1

50

100

50

Vishay

TDK

VJ X7R series

100

50

X7R

C series C4532

C series C3225

100

50

100

50

AVX

X7R dielectric series

1 to 4.7

1 to 2.2

100

8.2.1.2.7 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time for the output voltage to reach its nominal

programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This capacitor

is also used if the output capacitance is large and would require large amounts of current to quickly charge the

capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54541 device reach the current limit or excessive current draw from the input power supply may cause the

input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output

voltage without drawing excessive current. Equation 43 can be used to find the minimum slow\-start time, T_ss,

necessary to charge the output capacitor, C_OUT, from 10% to 90% of the output voltage, V_OUT, with an average

slow start current of I_SSavg. In the example, to charge the effective output capacitance of 130 µF up to 3.3 V with

an average current of 1 A requires a 0.3-ms slow-start time.

When the slow-start time is known, the slow-start capacitor value can be calculated using Equation 5. For the

example circuit, the slow-start time is not critical because the output capacitor value is two-times 100 μF which

does not require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary

value of 3.5 ms which requires a 9.3-nF slow-start capacitor calculated with Equation 44. For this design, the

next larger standard value of 10 nF is used.

Cout ´ Vout ´ 0.8

tss >

Issavg

(43)

T_SS(ms) ´ I_SS(µA)

V_REF(V) ´ 0.8

1.7 µA

C_SS(nF) =

= 3.5 ms´

= 9.3 nF

(0.8 V ´ 0.8)

(44)

8.2.1.2.8 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins. TI recommends a ceramic

capacitor with X5R or better grade dielectric. The capacitor must have a 10 V or higher voltage rating.

8.2.1.2.9 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the

TPS54541 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for

power down or brown outs when the input voltage is falling. For the example design, the supply must turn on and

start switching when the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it

must continue until the input voltage falls below 4.5 V (UVLO stop).

34

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

Programmable UVLO threshold voltages are set using the resistor divider of R_UVLO1and R_UVLO2between VIN and

ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values. For the example

application, a 365 kΩ between V_INand EN (R_UVLO1) and a 88.7 kΩ between EN and ground (R_UVLO2) are required

to produce the 5.75-V and 4.5-V start and stop voltages.

V

- V

STOP

5.75 V - 4.5 V

START

R

=

= 368 kW

UVLO1

I

3.4 mA

HYS

(45)

(46)

V

1.2 V

5.75 V - 1.2 V

ENA

R

=

= 88.7 kW

UVLO2

V

- V

ENA

START

+1.2 mA

+ I

1

365 kW

R

UVLO1

8.2.1.2.10 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.

Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input

current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the

accuracy of the output voltage. If the value of R6 is less than 800 kΩ, this requirement is satisfied. Choosing

higher-resistor values decreases quiescent current and improves efficiency at low-output currents but may also

introduce noise immunity problems.

V_OUT- 0.8 V

3.3 V - 0.8 V

æ

ö

R_HS= R_LS

x

= 10.2 kW x

= 31.9 kW

ç

÷

0.8 V

è

ø

(47)

8.2.1.2.11 Compensation

There are several methods to design compensation for DC-DC regulators. The method is simple to calculate and

ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is

ignored, the actual crossover frequency is lower than the crossover frequency in the calculations. This method

assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least

ten-times greater the modulator pole.

To get started, calculate the modulator pole, ƒ_p(mod), and the ESR zero, ƒ_z1using Equation 48 and Equation 49.

For C_OUT, use a derated value of 130 μF. Use equations Equation 50 and Equation 51 to estimate a starting point

for the crossover frequency, ƒ_co. For the example, design, ƒ_p(mod)is 1850 Hz and ƒ_z(mod)is 610 kHz. Equation 49

is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of modulator pole

and half of the switching frequency. Equation 50 yields 34 kHz and Equation 51 gives 19 kHz. Use the geometric

mean value of Equation 50 and Equation 51 for an initial crossover frequency. For this example, after lab

measurement, the crossover frequency target increased to 30 kHz for an improved transient response.

Next, calculate the compensation components. A resistor in series with a capacitor creates a compensating zero.

In parallel to these two components, a capacitor forms the compensating pole.

I_{OUT max}

(

)

5 A

f_{P mod}

=

2´ p´ V_OUT´ C_OUT2 ´ p ´ 3.3 V ´ 130 mF

= 1850 Hz

= 610 kHz

(

)

(48)

1

f

=

Z mod

(

)

2´ p´R

´ C

2 ´ p ´ 1 mW ´ 130 mF

ESR

OUT

(49)

(50)

f

=

f

=

1850 Hz x 610 kHz = 34 kHz

co1

p(mod) x z(mod)

f

400 kHz

SW

f

=

f

=

1850 Hz x

= 19 kHz

co2

p(mod) x

2

(51)

To determine the compensation resistor, R4, use Equation 52. The typical power stage transconductance, gmps,

is 17 A/V. The output voltage, V_O, reference voltage, V_REF, and amplifier transconductance, gmea, are 3.3 V, 0.8

V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use

Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5100 pF for

compensating capacitor C5. 4700 pF is used for this design.

æ

ö

æ

ç

è

ö

÷

ø

2 ´ p ´ ƒ ´ C

V

OUT

æ

ç

è

ö

÷

ø

2 ´ p ´ 30 kHz ´ 130 µF

3.3 V

æ

ö

co

OUT

R4 = ç

÷ ´

=

´

= 17 kW

ç

÷

ç

è

÷

ø

gm

V

x gm

ea

17 A / V

0.8 V ´ 350 µA / V

è

ø

ps

REF

35

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

(52)

1

C5 =

=

= 5100 pF

2´ p´R4 x f

2´ p´16.9 kW x 1850 Hz

p(mod)

(53)

A compensation pole can be implemented by adding capacitor C8 in parallel with the series combination of R4

and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole.

The value of C8 is 47 pF for this design example.

C

x R

ESR

130 mF x 1 mW

OUT

C8 =

=

= 15 pF

R4

16.9 kW

(54)

(55)

1

C8 =

=

= 47 pF

R4 ´ ƒ

´ p

16.9 kW ´ 400 kHz ´ p

sw

8.2.1.2.12 Power Dissipation Estimate

The following formulas estimate the TPS54541 power dissipation under CCM operation. Do not use these

equations if the device is operating in DCM.

The power dissipation of the IC includes conduction loss (P_COND), switching loss (P_SW), gate drive loss (P_GD), and

supply current (P_Q). Example calculations are shown with the 12-V typical input voltage of the design example.

æ

ç

è

ö

÷

ø

V

5 V

2

OUT

P

= I

´R

´

= 5 A ´ 87 mW ´

= 0.958 W

(

)

COND

OUT

DS on

( )

V

12 V

IN

(56)

(57)

(58)

spacer

P

= V ´ f

´I

´ t

= 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W

rise

SW

IN

SW

OUT

spacer

P

= V ´ Q ´ f

= 12 V ´ 3nC´ 400 kHz = 0.014 W

SW

GD

IN

G

spacer

P

= V ´ I = 12 V ´ 146 mA = 0.0018 W

IN Q

Q

where (for Equation 56, Equation 57, Equation 58, and Equation 59)

•

I_OUTis the output current (A)

R_DS(on)is the on-resistance of the high-side MOSFET (Ω)

V_OUTis the output voltage (V)

V_INis the input voltage (V)

ƒ_swis the switching frequency (Hz)

t_riseis the SW pin voltage rise time and can be estimated by trise = V_INx 0.16 ns/V + 3 ns

Q_Gis the total gate charge of the internal MOSFET

I_Qis the operating nonswitching supply current

(59)

(60)

(61)

Therefore,

P

= P

+ P

+ P + P = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W

TOT

COND

SW GD Q

For given T_A,

T = T + R ´P

TOT

J

A

TH

For given T_J(MAX)= 150°C

T_{A max}= T_{J max}- R_TH´P_TOT

(

)

(

)

36

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

where (for Equation 60, Equation 61, and Equation 62)

•

P_TOTis the total device power dissipation (W)

T_Ais the ambient temperature (°C)

T_Jis the junction temperature (°C)

R_THis the thermal resistance from junction to ambient for a given PCB layout (°C/W)

T_J(MAX)is maximum junction temperature (°C)

T_A(MAX)is maximum ambient temperature (°C)

(62)

Additional power loss occurs in the regulator circuit due to the inductor ac and dc losses and the catch diode and

PCB trace resistance impacting the overall efficiency of the regulator.

8.2.1.2.13 Safe Operating Area

Figure 47 shows the safe operating area (SOA) of a typical design, through Figure 50 for 3.3-V, 5-V, and 12-V

outputs and varying amounts of forced air flow. The temperature-derating curves represent the conditions at

which the internal components and external components are at or below the maximum operating temperatures of

the manufacturer. Derating limits apply to devices soldered directly to a double-sided PCB with 2-oz copper,

similar to the EVM. Pay attention to the other components chosen for the design, especially the catch diode. In

most applications, the thermal performance is limited by the catch diode. When operating at high-duty cycles or

in the high end of the switching frequency range, the thermal performance of the TPS54541 can be the limiting

factor.

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

6 V

8 V

12 V

24 V

36 V

12 V

24 V

36 V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

C056

C057

I_OUT(Amps)

Figure 47. 3.3-V Outputs

Figure 48. 5-V Outputs

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

fsw = 800 kIz

400 LFM

200 LFM

100 LFM

Nat Conv

18 V

24 V

36 V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

C058

C048

I_OUT(Amps)

Figure 49. 12-V Outputs

Figure 50. Air Flow Conditions

V_IN= 36 V, V_O= 12 V, fsw = 800 kHz

37

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current

is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input

current draw is 260 μA with no load.

8.2.1.3 Application Curves

Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise

noted.

IOUT

VIN

VOUT œ3.3V offset

Time = 100 ms/div

Time = 4 ms/div

Figure 51. Load Transient

Figure 52. Line Transient (8 V to 40 V)

VIN

EN

VOUT

Time = 20 ms/div

Figure 53. Start-up With VIN

Figure 54. Start-up With EN

38

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

SW

IL

VOUT œ AC Coupled

I

= 100 mA

OUT

Time = 4 ms/div

Figure 55. Output Ripple CCM

Figure 56. Output Ripple DCM

SW

IL

VOUT œ AC Coupled

No Load

VIN œ AC Coupled

Time = 1 ms/div

Time = 4 ms/div

Figure 57. Output Ripple PSM

Figure 58. Input Ripple CCM

SW

IL

SW

IL

VOUT = 5 V

VIN œ AC Coupled

No Load

EN Floating

I

= 100 mA

V

= 5.5 V

OUT

IN

Time = 40 ms/div

Time = 4 ms/div

Figure 60. Low Dropout Operation

Figure 59. Input Ripple DCM

39

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

I

= 100 mA

I

= 1 A

OUT

EN Floating

OUT

EN Floating

V

IN

OUT

Time = 40 ms/div

Figure 61. Low Dropout Operation

Figure 62. Low Dropout Operation

100

95

90

85

80

75

70

65

60

100

90

80

70

60

50

40

30

20

10

0

VIN = 7 V

V_IN= 7 V

VVIN ==1122VV

VIN = 12 V

V_IN= 12 V

IN

_VV_ININ=₌2₂4₄V_V

V

= 24 V

VIN = 24 V

IN

ë_hÜÇ= ñ ëU •_{í= 400 kIz

V_IN= 36 V

VIN = 36 V

0

1

2

3

4

5

0.001

0.01

0.1

1

Output Current (A)

C001

C002

Figure 63. Efficiency vs Load Current

Figure 64. Light Load Efficiency

100

95

90

85

80

75

70

65

60

100

90

80

70

60

50

40

30

20

10

0

VIN = 6 V

V_IN= 6 V

VIN

VIN = 12 V

V_IN= 12 V

V

= 24 V

V

= 24 V

VIN = 24 V

IN

ë_hÜÇ= 3.3 ëU •_{í= 400 kIz

V_IN= 36 V

VIN = 36 V

0

1

2

3

4

5

0.001

0.01

0.1

1

Output Current (A)

C003

C006

Figure 65. Efficiency vs Load Current

Figure 66. Light Load Efficiency

40

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

60

50

180

150

120

90

100

95

90

85

80

75

70

65

40

30

20

60

10

30

0

œ10

œ20

œ30

œ40

œ50

œ60

œ30

œ60

V

= 18 V

18in

ë_Lb= 12 ë

ë_hÜÇ= 3.3 ë

L_hÜÇ= 5 !

IN

œ90

œ120

œ150

œ180

Series1

V_IN= 24 V

Gain

f_{í= 400 kIz

Phase

V_OUT= 12 V, fsw = 800 kHz

Series3

V_IN= 36 V

60

0

10

100

1k

10k

100k

1M

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

C064

Frequency (Hz)

C024

I_O- Output Current (A)

Figure 68. Overall Loop Frequency Response

Figure 67. Efficiency vs Output Current

0.10

0.08

0.10

0.08

ë_Lb= 12 ë

ë_hÜÇ= 3.3 ë

fsw = 400 kIz

0.06

0.04

0.02

0.00

œ0.02

œ0.04

œ0.06

œ0.08

œ0.10

œ0.02

œ0.04

œ0.06

œ0.08

œ0.10

0

5

10

15

20

25

30

35

40

45

0

1

2

3

4

5

Input Voltage (V)

C065

Output Current (A)

C066

Figure 70. Regulation vs Input Voltage

Figure 69. Regulation vs Load Current

41

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output

The TPS54541 can be used to convert a positive input voltage to a negative output voltage. An example

application is an amplifier requiring a negative power supply. For a more detailed example, see SLVA317.

VIN

+

Cin

Cboot

Lo

SW

GND

BOOT

VIN

Cd

R1

R2

+

GND

Co

VOUT

TPS54541

FB

EN

COMP

SS/TR

Rcomp

Cpole

RT/CLK

RT

Czero

C_SS

Figure 71. TPS54541 Inverting Power Supply Based on the Application Note, SLVA317

8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output

The TPS54541 can be used to convert a positive input voltage to a split rail positive and negative output voltage

by using a coupled inductor. An example application is an amplifier requiring a split rail positive and negative

voltage power supply. For a more detailed example, see SLVA369.

VOPOS

+

Copos

VIN

+

Cin

Cboot

SW

GND

BOOT

VIN

Lo

Cd

R1

R2

+

GND

Coneg

TPS54541

VONEG

FB

EN

COMP

SS/TR

Rcomp

Cpole

RT /CLK

RT

Czero

C_SS

Figure 72. TPS54541 Split Rail Power Supply Based on the Application Note, SLVA369

9 Power Supply Recommendations

The design of the device is for operation from an power supply range between 4.5 V and 42 V. The power supply

voltage must remain within this range. If the power supply is more distant than a few inches from the TPS54541

converter, the circuit may require additional bulk capacitance besides the ceramic bypass capacitors. An

electrolytic capacitor with a value of 100 µF is a typical choice.

42

TPS54541

www.ti.com.cn

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast-

changing currents or voltages that interact with stray inductance or parasitic capacitance to generate noise or

degrade performance. To reduce parasitic effects, bypass the VIN pin to ground with a low-ESR ceramic bypass-

capacitor with X5R or X7R dielectric. Minimize the loop area formed by the bypass-capacitor connections, the

VIN pin, and the anode of the catch diode. See Figure 73 for a PCB layout example. Tie the GND pin directly to

the thermal pad under the IC.

Connect the thermal pad to internal PCB ground planes using multiple vias directly under the IC. Route the SW

pin to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching

node, locate the catch diode and output inductor close to the SW pins, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling. For operation at full rated load, ensure the top-side ground

area provides adequate heat dissipating area. The RT/CLK pin is sensitive to noise so locate and rout the RT

resistor as close as possible to the IC with minimal lengths of trace, respectively. The additional external

components are placed approximately as shown. Obtaining acceptable performance with alternate PCB layouts

is possible, however this layout produces good results and TI intends it as a guideline.

10.2 Layout Example

V_OUT

Output

Capacitor

Output

Inductor

Topside

Ground

Route Boot Capacitor

Catch

Area

Trace on another layer to

provide wide path for

topside ground

Diode

Input

Bypass

Capacitor

BOOT

VIN

PWRGD

V_IN

SW

GND

EN

UVLO

SS/TR

COMP

FB

Adjust

Resistors

RT/CLK

Compensation

Network

Resistor

Divider

Thermal VIA

Signal VIA

Soft-Start

Capacitor

Frequency

Set Resistor

Figure 73. PCB Layout Example

10.3 Estimated Circuit Area

Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in²(661

mm²). This area does not include test points or connectors.

43

TPS54541

ZHCSBT5C –OCTOBER 2013–REVISED JANUARY 2017

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 开发支持

有关 TPS54540、TPS54541 和 TPS54541-Q1 系列 Excel 设计工具的信息，请参见 SLVC452。

11.2 文档支持

11.2.1 相关文档ꢀ


型号：	TPS54541DPRT
厂家：	TEXAS INSTRUMENTS
描述：	具有软启动和 Eco-mode™ 的 4.5V 至 42V 输入 5A 降压直流/直流转换器 \| DPR \| 10 \| -40 to 85 开关软启动光电二极管转换器
文件：	总53页 (文件大小：2786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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