TPS54560B-Q1 [TI]
具有 Eco-mode™ 的 4.5V 至 60V 输入、5A 降压直流/直流转换器;
| 型号： | TPS54560B-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-mode™ 的 4.5V 至 60V 输入、5A 降压直流/直流转换器 转换器 |
| 文件： | 总47页 (文件大小：2330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
具有 Eco-Mode™ 的 TPS54560B-Q1 4.5V 至 60V 输入，5A 降压直流/直
流转换器
1 特性
3 说明
1
•
•
•
轻负载条件下使用脉冲跳跃实现的高效率 Eco-
mode。™
TPS54560B-Q1 是一款配有集成型高侧 MOSFET 的
60V、5A 降压稳压器。按照 ISO 7637 标准，此器件
能够耐受的抛负载脉冲高达 65V。电流模式控制提供
了简单的外部补偿和灵活的组件选择。一个低纹波脉冲
跳跃模式将无负载时的电源电流减小至 146μA。当启
用引脚被拉至低电平时，关断电源电流被减少至
2μA。
92mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
146μA 静态运行电流和
2μA 关断电流
•
•
•
100kHz 至 2.5MHz 的固定开关频率
同步至外部时钟
欠压闭锁在内部设定为 4.3V，但可用使能引脚将之提
高。输出电压启动斜升由内部控制以提供一个受控的启
动并且消除过冲。
轻负载条件下使用集成型引导 (BOOT) 再充电场效
应晶体管 (FET) 实现的低压降
•
•
•
•
•
可调欠压闭锁 (UVLO) 电压和滞后
0.8V 1% 内部电压基准
宽开关频率范围可实现对效率或者外部组件尺寸的优
化。输出电流是受限的逐周期电流。频率折返和热关断
在过载条件下保护内部和外部组件。
8 引脚 HSOP，带有 PowerPAD™封装
-40°C 至 150°C TJ运行范围
TPS54560B-Q1 可提供 8 引脚热增强型 HSOP
PowerPAD™ 封装。
TPS54560B-Q1借助 WEBENCH® 电源设计器并
使用 创建定制设计方案
器件信息(1)
2 应用
订货编号
封装
封装尺寸
•
•
•
•
工业自动化和电机控制
TPS54560B-Q1
HSOP (8)
4.89mm x 3.9mm
车辆配件：全球卫星定位系统 (GPS)，娱乐系统
USB 专用充电端口和电池充电器
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
12V，24V 和 48V 工业、汽车和通信电源系统
空白
简化电路原理图
效率与负载电流间的关系
100
36 V to 12 V
V
VIN
95
IN
BOOT
90
85
V
OUT
SW
EN
12 V to 3.3 V
80
12 V to 5 V
75
70
COMP
V
= 12 V, fsw = 800 kHz
65
60
OUT
= 5 V and 3.3 V, fsw = 400 kHz
V
OUT
RT/CLK
FB
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
C024
IO - Output Current (A)
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDP8
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 24
8.3 Inverting Power ....................................................... 37
8.4 Split Rail Power Supply........................................... 37
Power Supply Recommendations...................... 38
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description ................................................ 11
7.4 Device Functional Modes........................................ 23
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Examples................................................... 39
11 器件和文档支持 ..................................................... 40
11.1 器件支持................................................................ 40
11.2 接收文档更新通知 ................................................. 40
11.3 社区资源................................................................ 40
11.4 商标....................................................................... 40
11.5 静电放电警告......................................................... 40
11.6 Glossary................................................................ 40
12 机械、封装和可订购信息....................................... 40
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
初始版本
2017 年2 月
*
最初发布版本
2
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
5 Pin Configuration and Functions
HSOP PACKAGE
(TOP VIEW)
BOOT
VIN
1
8
7
6
5
SW
2
3
4
GND
COMP
FB
PowerPAD
EN
RT/CLK
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
BOOT
1
O
VIN
EN
2
3
I
I
Input supply voltage with 4.5 V to 60 V operating range.
Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper
threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is
disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
RT/CLK
4
I
FB
5
6
I
Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this terminal.
COMP
O
GND
SW
7
8
–
I
Ground
The source of the internal high-side power MOSFET and switching node of the converter.
GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Thermal Pad
–
Copyright © 2017, Texas Instruments Incorporated
3
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
65
8.4
73
3
UNIT
VIN
EN
BOOT
Input voltage
V
FB
–0.3
–0.3
–0.3
COMP
3
RT/CLK
BOOT-SW
3.6
8
Output voltage
SW
–0.6
–2
65
65
150
150
V
SW, 10-ns Transient
Operating junction temperature
Storage temperature range
–40
–65
°C
°C
TSTG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
MIN
MAX
±2000
±500
UNIT
V
(2)
Human Body Model (HBM) ESD Stress Voltage
Charged Device Model (HBM) ESD Stress Voltage
(1)
VESD
(3)
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VO + VDO
0.8
MAX
60
UNIT
V
(1)
VIN
VO
IO
Supply input voltage
Output voltage
58.8
5
V
Output current
0
A
TJ
Junction Temperature
–40
150
°C
(1) See Equation 1
6.4 Thermal Information
TPS54560B-Q1
THERMAL METRIC(1)(2)
UNIT
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
Junction-to-board thermal resistance
42.0
5.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ψJT
ψJB
23.4
45.8
3.6
θJCtop
θJCbot
θJB
23.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
4
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN TERMINAL)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
4.1
60
V
V
Internal undervoltage lockout threshold
Rising
4.3
4.48
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V
2.25
146
4.5
μA
Operating: nonswitching supply current
FB = 0.9 V, TA = 25°C
175
ENABLE AND UVLO (EN TERMINAL)
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold +50 mV
1.1
1.2
–4.6
–1.2
–3.4
1.3
V
Input current
μA
μA
Enable threshold –50 mV
–0.58
–2.2
-1.8
-4.5
Hysteresis current
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
ERROR AMPLIFIER
0.792
0.8
92
0.808
190
V
VIN = 12 V, BOOT-SW = 6 V
mΩ
Input current
50
10,000
2500
±30
nA
V/V
kHz
μA
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
COMP to SW current transconductance
V(COMP) = 1 V, 100 mV overdrive
17
A/V
CURRENT LIMIT
All VIN and temperatures, Open Loop(1)
All temperatures, VIN = 12 V, Open Loop(1)
VIN = 12 V, TA = 25°C, Open Loop(1)
6.3
6.3
7
7.9
7.9
7.9
9.5
9.5
8.8
Current limit test
A
THERMAL SHUTDOWN
Thermal shutdown
176
12
°C
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Switching frequency range using RT mode
100
450
160
2500
550
2300
2
kHz
kHz
kHz
V
fSW
Switching frequency
RT = 200 kΩ
500
Switching frequency range using CLK mode
RT/CLK high threshold
1.55
1.2
RT/CLK low threshold
0.5
V
(1) Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.
Copyright © 2017, Texas Instruments Incorporated
5
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO (EN TERMINAL)
Enable to COMP active
VIN = 12 V, TA = 25°C
340
µs
INTERNAL SOFT-START TIME
Soft-Start Time
fSW = 500 kHz, 10% to 90%
fSW = 2.5 MHz, 10% to 90%
2.1
ms
ms
Soft-Start Time
0.42
ERROR AMPLIFIER
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
350
77
μs
μs
Error amplifier transconductance (gM) during
soft-start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
CURRENT LIMIT
Current limit threshold delay
60
ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Minimum CLK input pulse width
15
55
78
ns
ns
μs
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
6.7 Typical Characteristics
0.25
0.2
0.15
0.1
0.05
0
0.814
0.809
0.804
0.799
0.794
0.789
0.784
BOOT-SW = 3 V
BOOT-SW = 6 V
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C025
C026
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
VIN = 12 V
VIN = 12 V
Figure 1. On Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
9.5
9
9
4.5
12
60
8.5
8
8.5
8
7.5
7
7.5
7
-40 èC
25 èC
150 èC
6.5
6
6.5
6
-40
-10
20
50
80
110
140
170
0
10
20
30
40
50
60
Temperature Junction (Tj)
Input Voltage (V)
D001
D002
VIN = 12 V
Figure 3. Switch Current Limit vs Junction Temperature
Figure 4. Switch Current Limit vs Input Voltage
6
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Typical Characteristics (continued)
550
540
530
520
510
500
490
480
470
460
450
500
450
400
350
300
250
200
150
100
50
0
œ50
œ25
0
25
50
75
100
125
150
200
300
400
500
600
700
800
900 1000
C029
C030
TJ - Junction Temperature (°C)
RT = 200 kΩ
RT/CLK - Resistance (kꢀ)
VIN = 12 V
ƒsw (kHz) = 92471 x RT (kΩ)-0.991
RT (kΩ) = 101756 x ƒsw (kHz)-1.008
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
2500
2300
2100
1900
1700
1500
1300
1100
900
500
450
400
350
300
250
200
700
500
0
50
100
150
200
œ50
œ25
0
25
50
75
100
125
150
C031
C032
RT/CLK - Resistance (kꢀ)
TJ - Junction Temperature (°C)
VIN = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
120
110
100
90
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
80
70
60
50
40
30
20
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C033
C034
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
VIN = 12 V
VIN = 12 V
Figure 10. EN Terminal Voltage vs Junction Temperature
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
Copyright © 2017, Texas Instruments Incorporated
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TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
Typical Characteristics (continued)
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
œ4.7
œ4.9
œ5.1
œ5.3
œ5.5
œ0.5
œ0.7
œ0.9
œ1.1
œ1.3
œ1.5
œ1.7
œ1.9
œ2.1
œ2.3
œ2.5
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C035
C036
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
VIN = 12 V
IEN = Threshold +50 mV
VIN = 12 V
IEN = Threshold –50 mV
Figure 11. EN Terminal Current vs Junction Temperature
Figure 12. EN Terminal Current vs Junction Temperature
œ2.5
œ2.7
œ2.9
œ3.1
œ3.3
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
100
VSENSEFalling
V
Rising
SENSE
75
50
25
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
œ50
œ25
0
25
50
75
100
125
150
C038
C037
TJ - Junction Temperature (°C)
VSENSE (V)
VIN = 12 V
Figure 13. EN Terminal Current Hysteresis vs Junction
Temperature
Figure 14. Switching Frequency vs VSENSE
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
œ50
œ25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
C039
C040
TJ - Junction Temperature (°C)
VIN - Input Voltage (V)
VIN = 12 V
TA = 25°C
Figure 16. Shutdown Supply Current vs Input Voltage (VIN
Figure 15. Shutdown Supply Current vs Junction
Temperature
)
8
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Typical Characteristics (continued)
210
210
190
170
150
130
110
90
190
170
150
130
110
90
70
70
œ50
œ25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
C041
C042
TJ - Junction Temperature (°C)
VIN - Input Voltage (V)
VIN = 12 V
TJ = 25°C
Figure 17. VIN Supply Current vs Junction Temperature
Figure 18. VIN Supply Current vs Input Voltage
2.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
BOOT-PH UVLO Falling
UVLO Start Switching
UVLO Stop Switching
BOOT-PH UVLO Rising
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C043
C044
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
Figure 19. BOOT-SW UVLO vs Junction Temperature
Figure 20. Input Voltage UVLO vs Junction Temperature
10
9
8
7
6
5
4
3
2
1
0
C045
Switching Frequency (kHz)
VIN = 12 V
TJ = 25°C
Figure 21. Soft-Start Time vs Switching Frequency
Copyright © 2017, Texas Instruments Incorporated
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TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
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7 Detailed Description
7.1 Overview
The TPS54560B-Q1 is a 60 V, 5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of
an external clock signal.
The TPS54560B-Q1 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to
adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up
current source enables operation when the EN terminal is floating. The operating current is 146 μA under no load
condition (not switching). When the device is disabled, the supply current is 2 μA.
The integrated 92mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54560B-Q1 reduces the
external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is
monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54560B-Q1to operate at high
duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage
of the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54560B-Q1 includes an internal soft-start circuit that slows the output rise time during start-up to reduce
in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
10
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ZHCSG05 –FEBRUARY 2017
7.2 Functional Block Diagram
EN
VIN
Thermal
Shutdown
UVLO
Enable
OV
Comparator
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Current
Sense
Skip
Error
Amplifier
PWM
FB
Comparator
BOOT
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft-Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012A 0192789
RT/CLK
GND
POWERPAD
/opyright © 2016, Çexas Lnstruments Lncorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54560B-Q1 uses fixed frequency, peak current mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB terminal to an internal voltage
reference by an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error
amplifier output at the COMP terminal controls the high side power switch current. When the high side MOSFET
switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP
terminal voltage will increase and decrease as the output current increases and decreases. The device
implements current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-
mode is implemented with a minimum voltage clamp on the COMP terminal.
7.3.2 Slope Compensation Output Current
The TPS54560B-Q1 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
Copyright © 2017, Texas Instruments Incorporated
11
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
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Feature Description (continued)
7.3.3 Pulse Skip Eco-mode
The TPS54560B-Q1 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by
reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at
the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The
pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited.
Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54560B-Q1 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 33 enters Eco-mode at about 25.3 mA output current. As the load current approaches
zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54560B-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT
and SW terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed
when the high side MOSFET is off and the external low side diode conducts. The recommended value of the
BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V
or higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54560B-Q1
will operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at
high output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal
operation of the device. This calculation must include tolerance of the component specifications and the variation
of these specifications at their maximum operating temperature in the application
VOUT + VF + Rdc ìIOUT
V
min =
+RDS on ìIOUT - VF
(
)
IN
(
)
0.99
where
•
•
•
VF = Schottky diode forward voltage
Rdc = DC resistance of inductor and PCB
RDS(on) = High-side MOSFET RDS(on)
(1)
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
Equation 2 calculates the minimum input voltage required to regulate the output voltage and ensure proper
operation of the device. This calculation must include tolerance of the component specifications and the variation
of these specifications at their maximum operating temperature in the application
12
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
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ZHCSG05 –FEBRUARY 2017
Feature Description (continued)
VOUT + VF + R dc ìIOUT
VIN (min) =
+ RDS(on) ìIOUT - VF
D
where
•
•
•
•
VF = Schottky diode forward voltage
RDC = Total DC resistance of inductor and PCB
RDS(on) = High-side MOSFET resistance
D = 0.99 effective duty cycle
(2)
Copyright © 2017, Texas Instruments Incorporated
13
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 3 can be
used to calculate the minimum input voltage for this condition.
V
= D
x (V
- I
x R
+ VF) - VF + I
x R
OUT(max)
(max)
IN(min)
OUT(max)
DS(on)
OUT(max) dc
where
•
•
•
•
•
•
D(max) ≥ 0.9
IB2SW = 100 µA
TSW = 1 / Fsw
VB2SW = VBOOT + VF
VBOOT = (1.41 x VIN - 0.554 - VF / TSW - 1.847 x 103 x IB2SW) / (1.41 + 1 / Tsw)
RDS(on) = 1 / (-0.3 x VB2SW2 + 3.577 x VB2SW - 4.246)
(3)
7.3.5 Error Amplifier
The TPS54560B-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error
amplifier compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V
voltage reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During
soft-start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the
internal soft-start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP terminal and GND terminal.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider
resistors. Select the low side resistor RLS for the desired divider current and use Equation 4 to calculate RHS. To
improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the
regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
Vout - 0.8V
æ
ö
RHS = RLS
´
ç
÷
0.8 V
è
ø
(4)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54560B-Q1 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage
exceeds the enable threshold of 1.2 V. The TPS54560B-Q1 is disabled when the VIN terminal voltage falls below
4 V or when the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of
1.2 μA that enables operation of the TPS54560B-Q1 when the EN terminal floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to
adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an
additional 3.4 μA of hysteresis current, IHYS, is sourced out of the EN terminal. When the EN terminal is pulled
below 1.2 V, the 3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO
hysteresis. Use Equation 5 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 6 to
calculate RUVLO2 for the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN terminal may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN terminal is clamped internally with a 5.8 V zener diode that will sink up to 150 μA.
14
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
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ZHCSG05 –FEBRUARY 2017
Feature Description (continued)
VIN
TPS54560B-Q1
VIN
i1 ihys
R
R
UVLO1
UVLO1
10 kW
EN
EN
Node
5.8 V
VEN
R
R
UVLO2
UVLO2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Adjustable Undervoltage Lockout
(UVLO)
Figure 23. Low Input Voltages Applications
V
- V
STOP
START
R
=
UVLO1
I
HYS
(5)
(6)
V
ENA
R
=
UVLO2
V
- V
ENA
START
+ I
1
R
UVLO1
7.3.8 Internal Soft-Start
The TPS54560B-Q1 has an internal digital soft-start that ramps the reference voltage from zero volts to its final
value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 7.
1024
t
(ms) =
SS
f
(kHz)
SW
(7)
If the EN terminal is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets.
The soft-start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
The switching frequency of the TPS54560B-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by
placing a resistor between the RT/CLK terminal and GND terminal. The RT/CLK terminal voltage is typically 0.5
V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a
given switching frequency, use Equation 8 or Equation 9 or the curves in Figure 5 and Figure 6. To reduce the
solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion
efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum
controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high
input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback
circuit. A more detailed discussion of the maximum switching frequency is provided in the next section.
101756
f sw (kHz)1.008
RT (kW) =
(8)
92417
RT (kW)0.991
f sw (kHz) =
(9)
Copyright © 2017, Texas Instruments Incorporated
15
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
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Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
The TPS54560B-Q1 implements peak current mode control in which the COMP terminal voltage controls the
peak current of the high side MOSFET. A signal proportional to the high side switch current and the COMP
terminal voltage are compared each cycle. When the peak switch current intersects the COMP control voltage,
the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error
amplifier increases switch current by driving the COMP terminal high. The error amplifier output is clamped
internally at a level which sets the peak switch current limit. The TPS54560B-Q1 provides an accurate current
limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a
higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown
in Figure 24.
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = V /L x tCLdelay
IN
tCLdelay
tON
Figure 24. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54560B-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB
terminal voltage falls from 0.8 V to 0 V. The TPS54560B-Q1 uses a digital frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the
inductor current can exceed the peak current limit because of the high input voltage and the minimum
controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases
slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the
period of the switching cycle providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 11 calculates the maximum switching frequency at
which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating
frequency should not exceed the calculated value.
Equation 10 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
16
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Feature Description (continued)
æ
ö
÷
IO ´Rdc + VOUT + Vd
1
ç
fSW maxskip
=
´
(
)
ç
÷
tON
VIN -IO ´RDS on + Vd
( )
è
ø
(10)
æ
ö
÷
ICL ´Rdc + VOUT sc + Vd
fDIV
( )
ç
fSW(shift)
=
´
ç
÷
tON
VIN -ICL ´RDS on + Vd
( )
è
ø
where
•
•
•
•
•
•
•
•
•
•
IO — Output current
ICL — Current limit
Rdc — inductor resistance
VIN — maximum input voltage
VOUT — output voltage
VOUTSC — output voltage during short
Vd — diode voltage drop
RDS(on) — switch on resistance
tON — controllable on time
ƒDIV — frequency divide equals (1, 2, 4, or 8)
(11)
7.3.11 Synchronization to RT/CLK Terminal
The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To
implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit
network shown in Figure 25. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and
higher than 1.7 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to
2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The
external synchronization circuit should be designed such that the default frequency set resistor is connected from
the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal
source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor
(e.g., 50 Ω) as shown in Figure 25. The two resistors in series provide the default frequency setting resistance
when the signal source is turned off. The sum of the resistance should set the switching frequency close to the
external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic
capacitor to RT/CLK terminal.
The first time the RT/CLK is pulled above the PLL threshold the TPS54560B-Q1 switches from the RT resistor
free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and
the RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The
device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-
up and fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system
clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
Copyright © 2017, Texas Instruments Incorporated
17
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
TPS54560B-Q1
PLL
TPS54560B-Q1
PLL
RT/CLK
RT/CLK
RT
RT
Hi-Z
Clock
Source
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Synchronizing to a System Clock
SW
SW
EXT
EXT
IL
IL
Figure 26. Plot of Synchronizing in CCM
Figure 27. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 28. Plot of Synchronizing in Eco-mode
18
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Feature Description (continued)
7.3.12 Overvoltage Protection
The TPS54560B-Q1 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low output capacitance.
For example, when the power supply output is overloaded the error amplifier compares the actual output voltage
to the internal reference voltage. If the FB terminal voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak
current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power supply output voltage can
increase faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB
terminal voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB
terminal voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to
minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106%
of the internal voltage reference, the high side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54560B-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by the internal soft-start circuitry.
7.3.14 Small Signal Model for Loop Response
Figure 29 shows an equivalent model for the TPS54560B-Q1 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro
and capacitor Co model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
V
O
Power Stage
gm 17 A/V
ps
a
b
R
R1
ESR
R
COMP
L
c
FB
C
OUT
0.8 V
CO
RO
R3
C1
gm
ea
C2
R2
350 mA/V
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Small Signal Model for Loop Response
Copyright © 2017, Texas Instruments Incorporated
19
TPS54560B-Q1
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Feature Description (continued)
7.3.15 Simple Small Signal Model for Peak Current Mode Control
Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54560B-Q1 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 12 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP terminal voltage (node c in Figure 29) is the power stage
transconductance, gmPS. The gmPS for the TPS54560B-Q1 is 17 A/V. The low-frequency gain of the power stage
is the product of the transconductance and the load resistance as shown in Equation 13.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 14). The combined effect is highlighted by the dashed line in the right half of
Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 15).
V
O
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
20
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Feature Description (continued)
æ
ç
è
ö
÷
ø
s
1+
1+
2p´ fZ
VOUT
= Adc ´
VC
æ
ç
è
ö
÷
ø
s
2p´ fP
(12)
(13)
Adc = gmps ´ RL
1
f
=
P
C
´R ´ 2p
L
OUT
(14)
(15)
1
f
=
Z
C
´R
´ 2p
OUT
ESR
7.3.16 Small Signal Model for Frequency Compensation
The TPS54560B-Q1 uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors. Equation 16 and Equation 17 relate the frequency response of the amplifier to
the small signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown
in Figure 31. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 16 through Equation 25 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
V
O
R1
FB
Type 2A
Type 2B
Type 1
gm
ea
R
COMP
Vref
C2
R3
C1
R3
R2
C2
C
O
O
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Types of Frequency Compensation
Copyright © 2017, Texas Instruments Incorporated
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TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
Aol
P1
A0
Z1
P2
A1
BW
Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
Ro =
gmea
gmea
(16)
(17)
CO
=
2p ´ BW (Hz)
æ
ç
è
ö
÷
ø
s
1+
2p´ fZ1
EA = A0´
æ
ç
è
ö æ
ö
÷
ø
s
s
1+
´ 1+
÷ ç
2p´ fP1
2p´ fP2
ø è
(18)
(19)
(20)
R2
A0 = gmea ´ Ro ´
R1 + R2
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
1
P1=
2p´Ro´ C1
(21)
1
Z1=
2p´R3´ C1
(22)
(23)
1
P2 =
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
(24)
(25)
1
P2 =
type 1
2p ´ RO ´ (C2 + CO
)
22
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
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ZHCSG05 –FEBRUARY 2017
7.4 Device Functional Modes
7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. If EN is externally pulled up to VIN or left floating, when VIN passes the
UVLO threshold the device will become active. Switching is enabled the soft start sequence is initiated. The
TPS54560B-Q1 will start at the soft start time determined by the internal soft start time.
7.4.2 Operation with EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft start sequence is initiated. The TPS54560B-Q1 will start at the soft
start time determined by the internal soft start time.
Copyright © 2017, Texas Instruments Incorporated
23
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54560B-Q1 is a 60 V, 5 A, step down regulator with an integrated high side MOSFET. Idea applications
are: 12 V, 24 V and 48 V Industrial, automotive and communications power systems
8.2 Typical Application
L1
7.2uH
VOUT
0.1uF
C4
5V, 5A
C6
C7
C9
U1
TPS54560B-Q1
D1
47uF
47uF
47uF
B560C
8
7
6
5
1
2
3
4
R5
53.6k
BOOT
SW
GND
COMP
FB
VIN
7V to 60V
C1
VIN
EN
C10
C3
C2
2.2uF
R1
442k
FB
FB
RT/CLK
2.2uF
2.2uF
2.2uF
R4
16.9k
9
C8
47pF
R6
10.2k
R2
90.9k
R3
243k
C5
4700pF
Copyright © 2016, Texas Instruments Incorporated
Figure 33. 5 V Output TPS54560B-Q1 Design Example
8.2.1 Design Requirements
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet (SLVC452)
located on the product page. For this example, start with the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETERS
Output Voltage
EXAMPLE VALUES
5 V
ΔVOUT = 4 %
5 A
Transient Response 1.25 A to 3.75 A load step
Maximum Output Current
Input Voltage
12 V nom. 7 V to 60 V
0.5% of VOUT
6.5 V
Output Voltage Ripple
Start Input Voltage (rising VIN)
Stop Input Voltage (falling VIN)
5 V
24
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54560B-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
–
–
–
–
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand the thermal performance of your board
Export your customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 10 and Equation 11 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54560B-Q1. For this example, the output voltage is 5 V
and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 708 kHz to avoid
pulse skipping from Equation 10. To ensure overcurrent runaway is not a concern during short circuits use
Equation 11 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch resistance of 92
mΩ, a current limit value of 6 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 855
kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 8 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 33. For 400 kHz operation, the closest
standard value resistor is 243 kΩ.
1
5 A x 11 mW + 5 V + 0.7 V
60 V - 5 A x 92 mW + 0.7 V
æ
ö
fSW(maxskip)
=
´
= 708 kHz
ç
÷
135ns
è
ø
(26)
(27)
(28)
8
6 A x 11 mW + 0.1 V + 0.7 V
60 V - 6 A x 92 mW + 0.7 V
æ
ö
fSW(shift)
=
´
= 855 kHz
ç
÷
135 ns
è
ø
101756
400 (kHz)1.008
RT (kW) =
= 242 kW
8.2.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 29.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
Copyright © 2017, Texas Instruments Incorporated
25
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 7.6 μH. The nearest standard value
is 7.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The
RMS and peak inductor current can be found from Equation 31 and Equation 32. For this design, the RMS
inductor current is 5 A and the peak inductor current is 5.8 A. The chosen inductor is a WE 7447798720, which
has a saturation current rating of 7.9 A and an RMS current rating of 6 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54560B-Q1 which is nominally 7.5 A.
V
- VOUT
IN max
(
VOUT
)
60 V - 5 V
5 A x 0.3
5 V
LO min
=
´
=
´
= 7.6 mH
(
)
IOUT ´KIND
V
´ fSW
60 V ´ 400 kHz
IN max
(
)
(29)
(30)
spacer
IRIPPLE
V
OUT ´(V
- VOUT )
IN max
(
)
5 V x (60 V - 5 V)
=
=
= 1.591 A
V
´LO ´ fSW
60 V x 7.2 mH x 400 kHz
IN max
(
)
spacer
2
æ
ö
2
V
´ V
- V
OUT
(
OUT
)
æ
ç
ç
è
ö
÷
÷
ø
IN max
(
5 V ´ 60 V - 5 V
)
(
)
1
ç
ç
÷
1
2
2
I
=
I
(
+
´
=
5 A
+
´
= 5 A
)
( )
OUT
÷
L rms
(
)
12
V
´L ´ f
12
60 V ´ 7.2 mH ´ 400 kHz
O
SW
IN max
(
)
ç
÷
è
ø
(31)
spacer
IL peak = IOUT
IRIPPLE
1.591 A
2
+
= 5 A +
= 5.797 A
(
)
2
(32)
8.2.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 33 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,
ΔIOUT is 3.75 A - 1.25 A = 2.5 A and ΔVOUT = 0.04 × 5 = 0.2 V. Using these numbers gives a minimum
capacitance of 62.5 μF. This value does not take the ESR of the output capacitor into account in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic
and tantalum capacitors have higher ESR that must be included in load step calculations.
26
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 34. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 34 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step
will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in
our specification is 4 % of the output voltage. This makes Vf = 1.04 × 5 = 5.2. Vi is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 34 yields a minimum capacitance of
44.1 μF.
Equation 35 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 35 yields 19.9 μF.
Equation 36 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 36 indicates the ESR should be less than 15.7 mΩ.
The most stringent criteria for the output capacitor is 62.5 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 3 x
47 μF, 10 V ceramic capacitors with 5 mΩ of ESR will be used. The derated capacitance is 87.4 µF, well above
the minimum required capacitance of 62.5 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 37 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 37 yields 459 mA.
2´ DI
2 ´ 2.5 A
OUT
C
>
=
= 62.5 mF
OUT
f
´ DV
400 kHz x 0.2 V
SW
OUT
(33)
2
(OH ) (OL )
2
3.75 A2 -1.25 A2
I
-
I
(
)
(
)
= 44.1 mF
COUT > LO
x
= 7.2 mH x
2
2
5.2 V2 - 5 V2
V
-
V
I
( ) ( )
(
)
f
(
)
(34)
1
1
1
1
C
>
´
=
x
= 19.9 mF
OUT
8´ f
8 x 400 kHz
25 mV
1.591 A
æ
ç
è
ö
÷
ø
æ
ö
V
SW
ORIPPLE
ç
è
÷
ø
I
RIPPLE
25 mV
1.591 A
(35)
(36)
V
ORIPPLE
R
<
=
= 15.7 mW
ESR
I
RIPPLE
V
´ V
(
IN max
(
- V
OUT
OUT
)
=
IN max
(
5 V ´ 60 V - 5 V
)
(
)
12 ´ 60 V ´ 7.2 mH ´ 400 kHz
I
=
= 459 mA
COUT(rms)
12 ´ V
´L ´ f
O
SW
)
(37)
8.2.2.5 Catch Diode
The TPS54560B-Q1 requires an external catch diode between the SW terminal and GND. The selected diode
must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54560B-Q1.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 volts
at 5 A.
Copyright © 2017, Texas Instruments Incorporated
27
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 38 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 38, the total loss in the diode at the
maximum input voltage is 3.43 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
)
V
(
- V
´ I
´ Vf d
OUT
)
IN max
OUT
C ´ f
´ V + Vf d
(
IN max
(
)
j
SW
IN
P =
+
=
D
V
2
(
)
2
60 V - 5 V ´ 5 A x 0.7 V
(
)
60 V
300 pF x 400 kHz x (60 V + 0.7 V)
+
= 3.43 W
2
(38)
8.2.2.6 Input Capacitor
The TPS54560B-Q1 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3
μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum input current ripple of the TPS54560B-Q1. The input ripple current can be calculated using
Equation 39.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, four 2.2 μF, 100 V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 40. Using the design example values, IOUT = 5 A, CIN = 8.8 μF, ƒsw = 400 kHz, yields
an input voltage ripple of 355 mV and a rms input ripple current of 2.26 A.
V
- V
OUT
)
= 5 A
(
IN min
(
7 V - 5 V
)
V
(
)
5 V
7 V
OUT
I
= I
x
x
´
= 2.26 A
OUT
CI rms
(
)
V
V
7 V
IN min
(
IN min
(
)
)
(39)
(40)
I
´ 0.25
5 A ´ 0.25
8.8 mF ´ 400 kHz
OUT
DV
=
=
= 355 mV
IN
C
´ f
IN
SW
28
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
Table 2. Capacitor Types
VALUE (μF)
EIA Size
VOLTAGE
100 V
50 V
DIALECTRIC
COMMENTS
1 to 2.2
1 to 4.7
1
1210
GRM32 series
100 V
50 V
1206
2220
2225
1812
1210
1210
1812
GRM31 series
VJ X7R series
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
50 V
100 V
50 V
100 V
100 V
50 V
X7R
C series C4532
C series C3225
100 V
50 V
50 V
100 V
50 V
X7R dielectric series
1 to 4.7
1 to 2.2
100 V
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW terminals for proper operation. A
ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or
higher voltage rating.
8.2.2.8 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the
TPS54560B-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts
switching, it should continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and
ground connected to the EN terminal. Equation 5 and Equation 6 calculate the resistance values necessary. For
the example application, a 442 kΩ between VIN and EN (RUVLO1) and a 90.9 kΩ between EN and ground (RUVLO2
)
are required to produce the 6.5 V and 5 V start and stop voltages.
(41)
(42)
V
1.2 V
6.5 V - 1.2 V
442 kW
ENA
R
=
=
= 90.9 kW
UVLO2
V
- V
ENA
START
+1.2 mA
+ I
1
R
UVLO1
8.2.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 4, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB terminal, the current flowing through the feedback network should be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
VOUT - 0.8 V
5 V - 0.8 V
æ
ö
RHS = RLS
x
= 10.2 kW x
= 53.5 kW
ç
÷
0.8 V
0.8 V
è
ø
(43)
29
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
8.2.2.10 Minimum Input Voltage, VIN
To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the
device must be above the value calculated with Equation 44. Using the typical values for the RDS(on), Rdc and VF
in this application example, the minimum input voltage is 5.71 V. The BOOT-SW = 3 V curve in Figure 1 was
used for RHS = 0.12 Ω because the device will be operating with low drop out. When operating with low dropout,
the BOOT-SW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed every
switching cycle. In the final application, the values of RDS(on), Rdc and VF used in this equation must include
tolerance of the component specifications and the variation of these specifications at their maximum operating
temperature in the application.
VOUT + VF + Rdc ìIOUT
V
=
=
+ RDS on ìIOUT - VF
IN min
(
)
)
(
)
0.99
5 V + 0.5 V + 0.0113 Wì5 A
0.99
V
+ 0.12 Wì5 A - 0.5 V = 5.71 V
IN min
(
(44)
8.2.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 45 and
Equation 46. For COUT, use a derated value of 87.4 μF. Use equations Equation 47 and Equation 48 to estimate
a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1821 Hz and ƒz(mod) is 1100
kHz. Equation 46 is the geometric mean of the modulator pole and the ESR zero and Equation 48 is the mean of
modulator pole and half of the switching frequency. Equation 47 yields 44.6 kHz and Equation 48 gives 19.1 kHz.
Use the geometric mean value of Equation 47 and Equation 48 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT max
(
)
5 A
fP mod
=
=
2´ p´ VOUT ´ COUT 2 ´ p ´ 5 V ´ 87.4 mF
= 1821 Hz
(
)
(45)
1
1
f
=
=
= 1100 kHz
Z mod
(
)
2´ p´R
´ C
2 ´ p ´ 1.67 mW ´ 87.4 mF
ESR
OUT
(46)
(47)
f
=
f
f
=
1821 Hz x 1100 kHz = 44.6 kHz
co1
p(mod) x z(mod)
f
400 kHz
SW
f
=
f
=
1821 Hz x
= 19.1 kHz
co2
p(mod) x
2
2
(48)
To determine the compensation resistor, R4, use Equation 49. Assume the power stage transconductance,
gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 16.8 kΩ and a standard value of 16.9 kΩ is selected.
Use Equation 50 to set the compensation zero to the modulator pole frequency. Equation 50 yields 5172 pF for
compensating capacitor C5. 4700 pF is used for this design.
æ
ç
è
ö
÷
ø
æ 2´ p´ f ´ C
ö
÷
ø
V
OUT
æ
ç
è
ö
÷
ø
2´ p´ 29.2 kHz ´ 87.4 mF
17 A / V
5V
æ
ö
co
OUT
R4 =
x
=
x
= 16.8 kW
ç
ç
÷
gmps
V
x gmea
0.8 V x 350 mA / V
è
ø
è
REF
(49)
1
1
C5 =
=
= 5172 pF
2´ p´R4 x f
2´ p´16.9 kW x 1821 Hz
p(mod)
(50)
30
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 51 and Equation 52 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x R
ESR
87.4 mF x 1.67 mW
OUT
C8 =
=
= 8.64 pF
R4
16.9 k
(51)
(52)
1
1
C8 =
=
= 47.1 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 408 mA. The power supply enters Eco-mode when the output current is lower than 25.3 mA. The
input current draw is 257 μA with no load.
8.2.2.13 Power Dissipation Estimate
The following formulas show how to estimate the TPS54560B-Q1 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æ
ç
è
ö
÷
ø
V
5 V
2
2
OUT
P
= I
´R
´
= 5 A ´ 92 mW ´
= 0.958 W
(
)
COND
OUT
DS on
( )
V
12 V
IN
(53)
(54)
(55)
spacer
P
= V ´ f
´I
´ t
= 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
rise
SW
IN
SW
OUT
spacer
P
= V ´ Q ´ f
= 12 V ´ 3nC´ 400 kHz = 0.014 W
SW
GD
IN
G
spacer
P
= V ´ I = 12 V ´ 146 mA = 0.0018 W
IN Q
Q
where
•
•
•
•
•
•
•
•
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz)
trise is the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
(56)
Copyright © 2017, Texas Instruments Incorporated
31
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
Therefore,
P
= P
+ P
+ P + P = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W
TOT
COND
SW GD Q
(57)
(58)
For given TA,
T = T + R ´P
TOT
J
A
TH
For given TJMAX = 150°C
TA max = TJ max - RTH ´PTOT
(
)
(
)
where
•
•
•
•
•
•
Ptot is the total device power dissipation (W)
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W)
TJMAX is maximum junction temperature (°C)
TAMAX is maximum ambient temperature (°C).
(59)
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
32
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
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ZHCSG05 –FEBRUARY 2017
8.2.3 Application Curves
VIN
IOUT
VOUT œ5V offset
VOUT œ5V offset
Time = 4 ms/div
Time = 100 ms/div
Figure 35. Line Transient (8 V to 40 V)
Figure 34. Load Transient
VIN
VIN
EN
EN
VOUT
VOUT
Time = 2 ms/div
Time = 2 ms/div
Figure 37. Start-up With EN
Figure 36. Start-up With VIN
SW
SW
IL
IL
VOUT œ AC Coupled
VOUT œ AC Coupled
Time = 4 ms/div
Time = 4 ms/div
IOUT = 100 mA
Figure 39. Output Ripple DCM
Figure 38. Output Ripple CCM
Copyright © 2017, Texas Instruments Incorporated
33
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
SW
SW
IL
IL
VOUT œ AC Coupled
VIN œ AC Coupled
Time = 1 ms/div
Time = 4 ms/div
No Load
Figure 40. Output Ripple PSM
Figure 41. Input Ripple CCM
SW
IL
SW
IL
VOUT
VIN œ AC Coupled
Time = 4 ms/div
Time = 40 ms/div
IOUT = 100 mA
No Load
EN Floating
Figure 42. Input Ripple DCM
Figure 43. Low Dropout Operation
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
VIN = 24 V
VIN = 12 V
VIN = 24V
VIN = 60V
VIN = 7 V
VIN = 12 V
VIN = 7 V
VIN = 36 V
VIN = 48 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
0.001
0.01
0.10
1.00
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
C024
IO - Output Current (A)
C024
IO - Output Current (A)
VOUT = 5 V
ƒsw = 400 kHz
VOUT = 5 V
ƒsw = 400 kHz
Figure 45. Light Load Efficiency
Figure 44. Efficiency vs Load Current
34
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
10
0
VIN = 6 V
VIN = 12 V
VIN =24V
VIN =36V
VIN = 48 V
VIN = 12 V
VIN = 24 V
VIN =6V
VIN = 36 V
VIN = 48 V
VIN =60V
4.5
VIN = 60 V
60
0
0.001
0.5
1
1.5
2
2.5
3
3.5
4
5
0.01
0.10
1.00
C024
C024
IO - Output Current (A)
IO - Output Current (A)
VOUT = 3.3 V
ƒsw = 400 kHz
VOUT = 3.3 V
ƒsw = 400 kHz
Figure 46. Efficiency vs Load Current
Figure 47. Light Load Efficiency
60
50
180
150
120
90
100
95
90
85
80
75
70
65
60
Gain
Phase
40
30
20
60
10
30
0
0
œ10
œ20
œ30
œ40
œ50
œ60
œ30
œ60
œ90
VIN = 18 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VOUT = 5 V
IOUT = 5 A
œ120
œ150
œ180
V
= 48 V
IN
V
= 60 V
IN
10
100
1k
10k
100k
1M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
C001
Frequency (Hz)
C024
IO - Output Current (A)
VIN = 12 V
VOUT = 5 V
IOUT = 5 A
V = 12 V
Figure 48. Efficiency vs Output Current
Figure 49. Overall Loop Frequency Response
0.6
0.5
0.3
0.2
0.1
0.0
0.4
0.3
0.2
0.1
œ0.0
œ0.1
œ0.2
œ0.3
œ0.4
œ0.5
œ0.6
œ0.1
œ0.2
œ0.3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5
10 15 20 25 30 35 40 45 50 55 60
C024
IO - Output Current (A)
C024
VI - Input Voltage (V)
VIN = 12 V
VOUT = 5 V
ƒsw = 400 kHz
VOUT = 5 V
IOUT = 5 A
ƒsw = 400 kHz
Figure 50. Regulation vs Load Current
Figure 51. Regulation vs Input Voltage
Copyright © 2017, Texas Instruments Incorporated
35
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
8.2.3.1 Safe Operating Area
The safe operating area (SOA) of the device is shown in Figure 52, through Figure 55 for 3.3 V, 5 V and 12 V
outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at
which the internal and external components are at or below the manufacturer’s maximum operating
temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar
to the EVM. Careful attention must be paid to the other components chosen for the design, especially the catch
diode. In most of these test conditions, the thermal performance is limited by the catch diode. When operating at
high duty cycles or at higher switching frequency the TPS54560B-Q1 thermal performance can become the
limiting factor.
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
6 V
8 V
12 V
24 V
36 V
48 V
60 V
12 V
24 V
36 V
48 V
60 V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C047
C048
IOUT (Amps)
IOUT (Amps)
Figure 52. 3.3 V Outputs
Figure 53. 5 V Outputs
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
400 LFM
200 LFM
100 LFM
Nat Conv
18 V
24 V
36 V
48 V
60 V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C048
C048
IOUT (Amps)
IOUT (Amps)
ƒsw = 800 kHz
ƒsw = 800 kHz
Figure 54. 12 V Outputs
Figure 55. Air Flow Conditions
VIN = 36 V, VO = 12 V
36
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
8.3 Inverting Power
The TPS54560B-Q1can be used to convert a positive input voltage to a negative output voltage. Idea
applications are amplifiers requiring a negative power supply. For a more detailed example see SLVA317.
VIN
+
Cin
Cboot
Lo
SW
GND
BOOT
VIN
Cd
R1
R2
+
GND
Co
TPS54560B-Q1
FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero Cpole
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 56. TPS54560B-Q1 Inverting Power Supply from SLVA317 Application Note
8.4 Split Rail Power Supply
The TPS54560B-Q1 can be used to convert a positive input voltage to a split rail positive and negative output
voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and negative
voltage power supply. For a more detailed example see SLVA369.
VOPOS
+
Copos
VIN
+
Cin
Cboot
SW
GND
BOOT
VIN
GND
Lo
Cd
R1
R2
+
Coneg
TPS54560B-Q1
VONEG
FB
EN
COMP
Rcomp
RT/CLK
Czero Cpole
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 57. TPS54560B-Q1 Split Rail Power Supply
Copyright © 2017, Texas Instruments Incorporated
37
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 60 V. If the input
supply is located more than a few inches from the TPS54560B-Q1 converter additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical
choice.
38
Copyright © 2017, Texas Instruments Incorporated
TPS54560B-Q1
www.ti.com.cn
ZHCSG05 –FEBRUARY 2017
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance.
•
To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
•
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN
terminal, and the anode of the catch diode.
•
•
The GND terminal should be tied directly to the power pad under the IC and the PowerPAD™.
The PowerPAD™ should be connected to internal PCB ground planes using multiple vias directly under the
IC.
•
•
The SW terminal should be routed to the cathode of the catch diode and to the output inductor.
Since the SW connection is the switching node, the catch diode and output inductor should be located close
to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
•
•
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
•
•
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
10.2 Layout Examples
Vout
Output
Capacitor
Output
Inductor
Topside
Ground
Area
Route Boot Capacitor
Catch
Diode
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
VIN
SW
GND
COMP
FB
Vin
EN
UVLO
RT/CLK
Compensation
Network
Adjust
Resistor
Divider
Resistors
Frequency
Thermal VIA
Signal VIA
Set Resistor
Figure 58. PCB Layout Example
10.2.1 Estimated Circuit Area
Boxing in the components in the design of Figure 33 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
版权 © 2017, Texas Instruments Incorporated
39
TPS54560B-Q1
ZHCSG05 –FEBRUARY 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 使用 WEBENCH® 工具定制设计方案
请单击此处，使用 TPS54560B-Q1 并借助 WEBENCH®电源设计器定制设计方案。
1. 首先输入您的 VIN、VOUT 和 IOUT 要求。
2. 使用优化器拨盘可优化效率、封装和成本等关键设计参数并将您的设计与德州仪器 (TI) 的其他可行解决方案进
行比较。
3. WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
4. 在多数情况下，您还可以：
–
–
–
–
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
5. 有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
Eco-mode。, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
40
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54560BQDDAQ1
TPS54560BQDDARQ1
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
5456BQ
5456BQ
2500 RoHS & Green
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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