TPS54561-Q1 [TI]
具有软启动和 Eco-Mode™ 的汽车类 4.5V 至 60V 输入 5A 降压直流/直流转换器;
| 型号： | TPS54561-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有软启动和 Eco-Mode™ 的汽车类 4.5V 至 60V 输入 5A 降压直流/直流转换器 软启动 转换器 |
| 文件： | 总53页 (文件大小：1763K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
TPS54561-Q1 支持 Eco-mode™ 的 4.5V 至 60V 输入，5A，降压 DC-DC
转换器
1 特性
2 应用范围
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 的下列结果：
•
•
•
车辆附件：全球卫星定位 (GPS)（请参见
SLVA412），娱乐系统
USB 专用充电端口和电池充电器（请参见
SLVA464）
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
12V 和 24V 车载电源系统
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
H1C
3 说明
器件组件充电模式 (CDM) ESD 分类 C5
TPS54561-Q1 器件是一款 60V，5A 降压稳压器，具
有一个集成的高侧 MOSFET。根据 ISO 7637 标准，
该器件可承受高达 65V 的负载突降脉冲。电流模式控
制提供了简单的外部补偿和灵活的组件选择。其低纹波
脉冲跳跃模式和 152µA 电源电流可在轻负载条件下实
现高效率。将使能引脚下拉为低电平可将关断电源电流
降至 2µA。
•
•
•
在具有脉冲跳跃的轻负载下实现高效率 Eco-mode
™控制
87mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
152µA 静态工作电流和
2µA 关断电流
•
•
•
100kHz 至 2.5MHz 开关频率
同步至外部时钟
欠压锁定的内部设定为 4.3V。使能 (EN) 引脚使用外
部电阻分压器时可增大该设置。软启动引脚控制输出电
压启动斜升，还可配置排序或跟踪。一个开漏电源正常
信号表示输出处于其标称电压值的 93% 至 106% 之
内。
轻负载条件下使用集成型引导 (BOOT) 再充电场效
应晶体管 (FET) 可实现低压降操作
•
•
•
•
•
可调 UVLO 电压和滞后
针对欠压及过压的电源正常状态输出监控
可调软启动和定序
0.8V 1% 内部电压基准
宽范围可调开关频率允许针对效率或者外部组件尺寸进
行优化。逐周期电流限制、频率折返和热关断功能可在
过载情况下保护器件。
带散热焊盘的 10 引脚晶圆级小外形无引线
(WSON) 封装
•
•
TJ 运行范围为 -40°C 至 150°C
TPS54561-Q1 采用 10 引脚 4mm x 4mm WSON 封
装。
使用 TPS54561-Q1 并借助 WEBENCH Power
Designer 创建定制设计方案
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TPS54561-Q1
WSON (10)
4.00mm x 4.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
空白
简化电路原理图
效率与负载电流间的关系
100
VI
36 V to 12 V
VDD
PWRGD
95
TPS54561-Q1
90
85
BOOT
SW
EN
VO
RT/CLK
SS/TR
12 V to 3.3 V
80
12 V to 5 V
75
70
COMP
FB
VO = 12 V, f(SW) = 620 kHz
VO = 5 V and 3.3 V, f(SW) = 400 kHz
65
60
GND
0
1
2
3
4
5
C024
IO - Output Current (A)
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSC60
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 27
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 28
Power Supply Recommendations...................... 42
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics.......................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 43
11 器件和文档支持 ..................................................... 44
11.1 器件支持................................................................ 44
11.2 文档支持 ............................................................... 44
11.3 接收文档更新通知 ................................................. 44
11.4 社区资源................................................................ 44
11.5 商标....................................................................... 44
11.6 静电放电警告......................................................... 45
11.7 Glossary................................................................ 45
12 机械、封装和可订购信息....................................... 45
7
4 修订历史记录
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
已将封装由“SON”更改至“WSON”（位于 特性 和通篇数据表中） .......................................................................................... 1
WEBENCH 信息至特性，详细设计流程和器件支持部分........................................................................................................ 1
Added SW, 5-ns transient to the Absolute Maximum Ratings ............................................................................................... 4
Moved Storage temperature range to the Absolute Maximum Ratings ................................................................................. 4
Changed the Handling Ratings table to the ESD Ratings ..................................................................................................... 4
Changed Equation 10 and Equation 11 .............................................................................................................................. 19
Changed Equation 30 .......................................................................................................................................................... 30
Changed Equation 33 .......................................................................................................................................................... 30
Moved Power Dissipation Estimate to the Detailed Design Procedure section ................................................................... 35
Moved the location of the Safe Operating Area ................................................................................................................... 37
Moved Inverting Power Supply and Split-Rail Power Supply to the Application Information section................................... 41
2
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
5 Pin Configuration and Functions
DPR Package
10-Pin WSON
(Top View)
1
10
9
BOOT
VDD
PWRGD
SW
2
3
4
5
Thermal
Pad
8
EN
GND
COMP
FB
7
SS/TR
RT/CLK
6
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
The device requires a bootstrap capacitor between BOOT and SW. If the voltage on this capacitor is below
the minimum required voltage to operate the high-side MOSFET, the gate driver switches off until the
bootstrap capacitor recharges.
BOOT
1
O
Error amplifier output, and input to the output switch-current comparator (PWM comparator). Connect
frequency compensation components to this pin.
COMP
EN
7
3
O
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjust Undervoltage Lockout section.
FB
6
8
I
Inverting input of the transconductance (gm) error amplifier.
Ground
GND
—
Power-good is an open-drain output that asserts if the output voltage is low because of thermal shutdown,
dropout, overvoltage, or EN shutdown.
PWRGD
RT/CLK
SS/TR
10
O
I
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. When pulled above the PLL upper threshold, a
mode change occurs, and the pin becomes a synchronization input. This change disables the internal
amplifier, and the pin is a high-impedance clock input to the internal PLL. Stopping the clocking edges re-
enables the internal amplifier, and the operating mode returns to resistor programmed mode.
5
Soft-start and tracking input pin. An external capacitor connected to this pin sets the output rise time. A
voltage on this pin overrides the internal reference, which allows use of the pin for tracking and sequencing.
4
I
SW
VDD
9
2
I
I
The source of the internal high-side power MOSFET, and switching node of the converter.
Input supply pin with 4.5-V to 60-V operating range.
To ensure proper operation, electrically connect the GND pin to the copper pad under the IC on the printed
circuit board.
Thermal pad
—
—
Copyright © 2014–2017, Texas Instruments Incorporated
3
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–7
MAX
65
8.4
3
VDD
EN
FB
Input voltage
COMP
3
V
PWRGD
6
SS/TR
3
RT/CLK
3.6
8
BOOT-SW
SW
65
65
65
150
150
Output voltage
V
SW, 5-ns transient
SW, 10-ns transient
–2
Operating junction temperature
Storage temperature range, Tstg
-40
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under
Rec–65ommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC-Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
60
UNIT
VDD
VO
IO
Supply input voltage
Output voltage
4.5
0.8
0
V
V
58.8
5
Output current
A
TJ
Junction temperature
–40
150
°C
4
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
6.4 Thermal Information
TPS54561-Q1
THERMAL METRIC(1)(2)
DPR
10 PINS
35.1
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
34.1
12.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
12.5
RθJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Determination of the power rating at a specific ambient temperature must be at the maximum junction temperature of 150°C. This is the
point where distortion starts to increase substantially. See the power dissipation estimate in the Power Dissipation Estimate section of
this data sheet for more information.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VDD = 4.5 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VDD PIN)
Operating input voltage
4.5
4.1
60
V
V
Internal undervoltage lockout threshold
VDD rising
4.3
4.48
Internal undervoltage lockout threshold
hysteresis
325
mV
µA
Shutdown supply current
V(EN) = 0 V, TA = 25°C, 4.5 V ≤ VDD ≤ 60 V
2.25
152
4.5
Operating: nonswitching supply current
V(FB) = 0.9 V, TA = 25°C
200
ENABLE AND UVLO (EN PIN)
V(EN)th
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold + 50 mV
1.1
1.2
–4.6
–1.2
–3.4
1.3
V
Input current
µA
µA
Enable threshold – 50 mV
–0.58
–2.2
-1.8
-4.5
I(HYS)
Hysteresis current
VOLTAGE REFERENCE
Vref
Voltage reference
0.792
0.8
87
0.808
185
V
HIGH-SIDE MOSFET
On-resistance
ERROR AMPLIFIER
Input current
VDD = 12 V, V(BOOT-SW) = 6 V
mΩ
50
nA
µS
gm(ea)
Error-amplifier transconductance
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V
350
Error-amplifier transconductance (gm) during
soft-start
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, V(FB)
0.4 V
=
78
µS
A(OL)
Error-amplifier open-loop dc gain
Minnimum unity-gain bandwidth
Error-amplifier source and sink
COMP to SW current transconductance
V(FB) = 0.8 V
10 000
2500
±30
V/V
kHz
µA
S
V(COMP) = 1 V, 100 mV overdrive
gm(ps)
17
CURRENT LIMIT
All VDD and temperatures, open loop(1)
All temperatures, VDD = 12 V, open loop(1)
VDD = 12 V, TA = 25°C, open loop(1)
6.3
6.3
7.1
7.5
7.5
7.5
8.8
8.3
7.9
Current limit threshold
A
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
12
°C
°C
(1) Measure open-loop current limit directly at the SW pin. The current is independent of the inductor value and slope compensation.
Copyright © 2014–2017, Texas Instruments Incorporated
5
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –40°C to 150°C, VDD = 4.5 to 60 V (unless otherwise noted)
PARAMETER
EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.55
1.2
2
V
V
RT/CLK low threshold
0.5
SOFT-START AND TRACKING (SS/TR PIN)
I(SS)
Charge current
V(SS/TR) = 0.4 V
1.7
42
µA
mV
V
SS/TR-to-FB matching
V(SS/TR) = 0.4 V
SS/TR-to-reference crossover
SS/TR discharge current (overload)
SS/TR discharge voltage
98% of nominal FB voltage
V(FB) = 0 V, V(SS/TR) = 0.4 V
V(FB) = 0 V
1.16
354
54
µA
mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low
FB falling
91%
93%
108%
106%
2%
FB threshold for PWRGD high
FB threshold for PWRGD low
FB threshold for PWRGD high
Hysteresis
FB rising
FB rising
FB falling
FB falling
Output-high leakage
V(PWRGD) = 5.5 V, TA = 25°C
I(PWRGD) = 3 mA, V(FB) < 0.79 V
10
nA
On-resistance
45
Ω
Minimum input voltage for defined output
voltage
V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA
0.9
2
V
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
RT/CLK
Minimum CLK input pulse duration
15
ns
6.7 Switching Characteristics
TJ = –40°C to 150°C, VDD = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
ENABLE AND UVLO (EN PIN)
Enable to COMP active
TEST CONDITIONS
MIN
TYP
540
60
MAX
UNIT
µs
VDD = 12 V, TA = 25°C
CURRENT-LIMIT
td(CL)
Current limit threshold delay
ns
SW
VDD = 23.7 V, VO = 5 V, IO = 3.5 A, R(RT)
= 39.6 kΩ, TA = 25°C
t(ON)
Minimum controllable on-time
100
ns
RT/CLK
Switching frequency range using RT
mode
100
450
160
2500
550
kHz
kHz
kHz
f(SW)
Switching frequency
R(RT) = 200 kΩ
500
Switching frequency range using CLK
mode
2300
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with an RT resistor
(R(RT)) in series
55
78
ns
µs
PLL lock-in time
Measured at 500 kHz
6
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
6.8 Typical Characteristics
0.25
0.814
0.809
0.804
0.799
0.794
0.789
0.784
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
BOOT-SW = 6 V
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D004
D028
VDD = 12 V
Figure 1. On-Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
9
8.5
8
-40è
25è
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
150è
7.5
7
6.5
6
0
10
20
30
40
50
60
-50
-25
0
25
50
75
100
125
150
Input Voltage (V)
Junction Temperature (èC)
D026
D027
VDD = 12 V
Figure 4. Switch-Current Limit vs Input Voltage
Figure 3. Switch-Current Limit vs Junction Temperature
550
500
450
400
350
300
250
200
150
100
540
530
520
510
500
490
480
470
460
450
-50
-25
0
25
50
75
100
125
150
200
300
400
500
600
700
800
900
1000
Junction Temperature (èC)
Resistance at RT/CLK (kW)
D025
D024
R(RT) = 200 kΩ
VDD = 12 V
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance,
Low-Frequency Range
Copyright © 2014–2017, Texas Instruments Incorporated
7
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Typical Characteristics (continued)
2500
500
450
400
350
300
250
200
2000
1500
1000
500
0
0
50
100
150
200
-50
-25
0
25
50
75
100
125
150
Resistance at RT/CLK (kW)
Junction Temperature (ºC)
D023
D022
VDD = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance,
High-Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
1.33
120
110
100
90
80
70
60
50
40
30
20
1.3
1.27
1.24
1.21
1.18
1.15
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D020
D021
VDD = 12 V
VDD = 12 V
Figure 10. EN Pin Threshold Voltage vs Junction
Temperature
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
-3.5
-3.7
-3.9
-4.1
-4.3
-4.5
-4.7
-4.9
-5.1
-5.3
-5.5
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
-1.7
-1.9
-2.1
-2.3
-2.5
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D019
D018
VDD = 12 V
V(EN) = Threshold + 50 mV
VDD = 12 V
V(EN) = Threshold – 50 mV
Figure 11. EN Pin Current vs Junction Temperature
Figure 12. EN Pin Current vs Junction Temperature
8
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Characteristics (continued)
-2.5
-2.7
-2.9
-3.1
-3.3
-3.5
-3.7
-3.9
-4.1
-4.3
-4.5
100
75
50
25
0
V (FB) Falling
V (FB) Rising
-50
-25
0
25
50
75
100
125
150
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Junction Temperature (èC)
Voltage at FB (V)
D017
D016
VDD = 12 V
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
Figure 14. Switching Frequency vs FB
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
Junction Temperature (èC)
Input Voltage (V)
D015
D014
VDD = 12 V
TJ = 25ºC
Figure 15. Shutdown Supply Current vs Junction
Temperature
Figure 16. Shutdown Supply Current vs Input Voltage
210
190
170
150
130
110
90
210
190
170
150
130
110
90
70
70
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
Junction Temperature (èC)
Input Voltage (V)
D013
D012
VDD = 12 V
TJ = 25ºC
Figure 17. I(VDD) Supply Current vs Junction Temperature
Figure 18. I(VDD) Supply Current vs Input Voltage
Copyright © 2014–2017, Texas Instruments Incorporated
9
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Typical Characteristics (continued)
2.6
4.5
4.4
4.3
4.2
4.1
4
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
2.5
2.4
2.3
2.2
2.1
2
3.9
3.8
3.7
1.9
1.8
UVLO Start Switching
UVLO Stop Switching
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D011
D010
Figure 19. BOOT-SW UVLO vs Junction Temperature
Figure 20. Input Voltage UVLO vs Junction Temperature
80
70
60
50
40
30
20
10
0
110
108
106
104
102
100
98
FB Rising
FB Falling
FB Rising
FB Falling
96
94
92
90
88
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D009
D008
VDD = 12 V
VDD = 12 V
Figure 21. PWRGD On-Resistance vs Junction Temperature
Figure 22. PWRGD Threshold vs Junction Temperature
900
800
700
600
500
400
300
200
100
0
60
55
50
45
40
35
30
25
20
0
100
200
300
400
500
600
700
800
-50
-25
0
25
50
75
100
125
150
FB Pin Voltage (mV)
Junction Temperature (èC)
D007
D006
VDD = 12 V
TJ = 25ºC
VDD = 12 V
V(FB) = 0.4 V
Figure 23. SS/TR to FB Offset vs FB
Figure 24. SS/TR to FB Offset vs Temperature
10
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Characteristics (continued)
5.6
5.5
5.4
5.3
5.2
5.1
5
Start
Stop
Dropout
Voltage
4.9
4.8
4.7
4.6
Dropout
Voltage
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Output Current (A)
D005
Figure 25. 5-V Start and Stop Voltage (see Low-Dropout Operation and Bootstrap Voltage (BOOT))
7 Detailed Description
7.1 Overview
The TPS54561-Q1 device is a 60-V, 5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. The device implements constant-frequency current-mode control, which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows either efficiency or size optimization when selecting the output filter components. The use of a resistor
connected to ground from the RT/CLK pin adjusts the switching frequency. The device has an internal phase-
locked loop (PLL) connected to the RT/CLK pin that synchronizes the power-switch turnon to the falling edge of
an external clock signal.
The TPS54561-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin adjusts the
input-voltage undervoltage-lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 152 µA under no-load conditions when
not switching. With the device disabled, the supply current is 2 µA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power supply designs capable of delivering
5 A of continuous current to a load. A bootstrap capacitor connected from the BOOT pin to the SW pin supplies
the gate-drive bias voltage for the integrated high-side MOSFET. The TPS54561-Q1 device reduces the external
component count by integrating the bootstrap recharge diode. A BOOT UVLO circuit monitors the BOOT pin
capacitor voltage, and turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54561-Q1 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is 0.8 V, which equals the internal feedback reference.
An overvoltage protection (OVP) comparator minimizes output overvoltage transients. On activation of the OVP
comparator, the high-side MOSFET turns off and remains off until the output voltage is less than 106% of the
desired output voltage.
Using the SS/TR (soft-start and tracking) pin minimizes inrush currents or provides power supply sequencing
during power-up. Couple a small-value capacitor from the SS/TR pin to the GND pin to adjust the soft-start time.
Couple a resistor divider from SS/TR pin to GND pin for critical power-supply sequencing requirements. The
device discharges the SS/TR pin before the output powers up. This discharging ensures a repeatable restart
after an overtemperature fault, UVLO fault, or a disabled condition. When the overload condition goes away, the
soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency
foldback circuit reduces the switching frequency during start-up or overcurrent fault conditions to help maintain
control of the inductor current.
Copyright © 2014–2017, Texas Instruments Incorporated
11
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
7.2 Functional Block Diagram
PWRGD
EN
VDD
Shutdown
Thermal
Shutdown
UVLO
Enable
Comparator
UV
OV
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Boot
UVLO
Current
Sense
Skip
Error
Amplifier
PWM
Comparator
FB
BOOT
SS/TR
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
With PLL
RT/CLK
GND
Thermal Pad
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54561-Q1 device uses fixed-frequency, peak-current-mode control with adjustable switching frequency.
An error amplifier compares the output voltage to an internal voltage reference through an external resistor
divider connected to the FB pin. An internal oscillator initiates the turnon of the high-side MOSFET. The error
amplifier output at the COMP pin controls the high-side MOSFET current. When the high-side MOSFET switch
current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. Implementation of the pulse-skipping Eco-mode control
scheme is through a minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54561-Q1 adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The slope compensation does
not affect the peak current limit of the high-side switch, which remains constant over the full duty cycle range.
12
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
7.3.3 Pulse-Skipping Eco-mode Control Scheme
The TPS54561-Q1 device operates in a pulse-skipping Eco-mode control scheme at light load currents to
improve efficiency by reducing switching and gate-drive losses. If the output voltage is within regulation and the
peak switch current of any switching cycle is below the pulse-skipping current threshold, the device enters pulse-
skipping mode. The pulse-skipping current threshold is the peak switch-current level corresponding to a nominal
COMP voltage of 600 mV.
When in pulse-skipping mode, the TPS54561-Q1 device clamps the COMP pin voltage to 600 mV and inhibits
the high-side MOSFET. Because the device is not switching, the output voltage begins to decay. The voltage
control loop responds to the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET
enables and switching resumes when the error amplifier lifts COMP above the pulse-skipping threshold. The
output voltage recovers to the regulated value, and COMP eventually falls below the pulse-skipping threshold, at
which time the device again enters pulse-skipping mode. The internal PLL remains operational when in pulse-
skipping mode. When operating at light load currents in pulse-skipping mode, the switching transitions occur
synchronously with the external clock signal.
During pulse-skipping operation, the TPS54561-Q1 device senses and controls the peak switch current, not the
average load current. Therefore, the load current at which the device enters pulse-skipping mode depends on the
output inductor value. The circuit in Figure 46 enters pulse-skipping mode at about 25.3 mA output current. As
the load current approaches zero, the device enters the pulse-skipping mode. During the time period when there
is no switching the input current falls to the 152-µA quiescent current.
7.3.4 Low-Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54561-Q1 device provides an integrated bootstrap voltage regulator. A small capacitor between the
BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor recharges
when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the
BOOT capacitor is 0.1 µF. For stable performance over temperature and voltage, TI recommends a ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54561-Q1
operates at 100% duty cycle as long as the BOOT-to-SW pin voltage is greater than 2.1 V. When the voltage
from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high output
voltages, the device disables this small low-side MOSFET at 24-V output and re-enables it when the output
reaches 21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The main influences on the effective duty cycle of the
converter during dropout are the voltage drops across the power MOSFET, the inductor resistance, the low-side
diode voltage, and the printed-circuit-board (PCB) resistance.
Figure 25 shows the start and stop voltages for a typical 5-V output application, and plots the input voltage
versus load current. The definition of start voltage is the input voltage required to regulate the output within 1% of
nominal voltage. The definition of stop voltage is the input voltage at which the output drops by 5% or where
switching stops.
During high-duty-cycle (low dropout) conditions, inductor current ripple increases while the BOOT capacitor
recharges, resulting in an increase in output-voltage ripple. Increased ripple occurs when the off-time required to
recharge the BOOT capacitor is longer than the high-side off-time associated with cycle-by-cycle PWM control.
At heavy loads, increase the minimum input voltage to ensure a monotonic start-up. For this condition, use
Equation 1 to calculate the maximum output voltage for a given minimum input voltage.
VO max = Dmax ´(VI min - IOmax ´rDS(on) + V(d) ) - V(d) + IOmax ´R(DC)
where
•
•
•
Dmax = 0.9
V(d) = Forward drop of the catch diode
R(DC) = DC resistance of output inductor
Copyright © 2014–2017, Texas Instruments Incorporated
13
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
•
•
•
•
•
rDS(on) = 1 / (–0.3 × V(BOOT_SW)2 + 3.577 × V(BOOT_SW) – 4.246)
V(BOOT_SW) = V(BOOT) + V(d)
V(BOOT) = (1.41 × VImin – 0.554 – V(d) x f(SW) – 1.847 × 103 × I(BOOT_SW)) / (1.41 + f(SW)
)
I(BOOT_SW) = 100 × 10-6
A
f(SW) = Operating frequency in MHz
(1)
7.3.5 Error Amplifier
A transconductance error amplifier controls the TPS54561-Q1 voltage regulation loop. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm(ea)) of the error amplifier is 350 µS during normal operation. During soft-start
operation, the device reduces the transconductance to 78 µS and references the error amplifier to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) connect the error-amplifier
output COMP pin to the GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. A resistor divider from the output node to
the FB pin sets the output voltage. Divider resistors with a 1% tolerance or better are recommended. Select the
low-side resistor, R(LS), for the desired divider current, and use Equation 2 to calculate R(HS). To improve
efficiency at light loads, consider using larger-value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors because of the FB input current may become noticeable.
æ VO - 0.8 V ö
R(HS) = R(LS)
´
ç
÷
0.8 V
è
ø
(2)
7.3.7 Enable and Adjust Undervoltage Lockout
The VDD pin voltage rising above 4.3 V when the EN pin voltage exceeds the enable threshold of 1.2 V enables
the TPS54561-Q1 device. The VDD pin voltage falling below 4 V or the EN pin voltage dropping below 1.2 V
disables the TPS54561-Q1 device. The EN pin has an internal pullup current source, I(1), of 1.2 µA that enables
operation of the TPS54561-Q1 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, the EN pin
sources an additional 3.4 µA of hysteresis current, I(HYS). This additional current facilitates adjustable input
voltage UVLO hysteresis. Pulling the EN pin below 1.2 V removes the 3.4-µA I(HYS) current. Use Equation 3 to
calculate R(UVLO1) for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R(UVLO2) for the desired
VDD start voltage.
In applications designed to start at relatively low input voltages (for example, from 4.5 V to 9 V) and withstand
high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the
absolute maximum voltage of 8.4 V during the high-input-voltage condition. To avoid exceeding this voltage
when using the EN resistors, a 5.8-V Zener diode that is capable of sinking up to 150 µA internally clamps the
EN pin.
æ
ö
÷
÷
ø
V(START) - V(STOP)
R(UVLO1) = ç
ç
è
I(HYS)
(3)
(4)
V
(EN)th
R(UVLO2)
=
V
- V
(EN)th
(START)
+ I(1)
R(UVLO1)
14
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
VI
VDD
VI
TPS54561-Q1
I(1) I(HYS)
R(UVLO1)
R(UVLO1)
EN
10 kW
EN
Node
5.8 V
V(EN)th
R(UVLO2)
R(UVLO2)
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Adjustable Undervoltage Lockout
(UVLO)
Figure 27. Internal Clamp On EN Pin
7.3.8 Soft-Start and Tracking Pin (SS/TR)
The TPS54561-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR
pin to ground implements a soft-start time. The TPS54561-Q1 device has an internal pullup current source of 1.7
µA that charges the external soft-start capacitor. Equation 5 shows the calculation for the soft-start time (10% to
90%). The voltage reference (Vref) is 0.8 V and the soft-start current (I(SS)) is 1.7 µA. The soft-start capacitor
should remain lower than 0.47 µF and greater than 0.47 nF.
t(SS) (ms)´ I(SS) (μA)
C(SS) (nF) =
V
ref ´ 0.8
(5)
At power up, the TPS54561-Q1 device does not start switching until the voltage in the soft-start pin is less than
54 mV to ensure a proper power up (see Figure 28).
Also, during normal operation, the TPS54561-Q1 stops switching and the SS/TR pin must discharge to 54 mV
when one of the following occurs: the VDD pin voltage exceeds the UVLO threshold, the EN pin drops below
1.2 V, or a thermal shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typical, as shown in Figure 28.
Copyright © 2014–2017, Texas Instruments Incorporated
15
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
V
(EN)
V
(SS/TR)
V
(FB)
V
O
Figure 28. Operation of SS/TR Pin When Starting
7.3.9 Sequencing
A designer can implement many of the common power-supply sequencing methods using the SS/TR, EN, and
PWRGD pins. Implementation of the sequential method can be by using an open-drain output of the power-on-
reset pin of another device. Figure 29 illustrates the sequential method using two TPS54561-Q1 devices.
Connecting the power-good signal of the first TPS54561-Q1 device to the EN pin on the second TPS54561-Q1
device enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic
capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results
of Figure 29.
TPS54561-Q1
TPS54561-Q1
PWRGD
EN
V(EN)(1)
EN
V(PWRGD)(1)
SS/TR
SS/TR
PWRGD
Copyright © 2016, Texas Instruments Incorporated
VO(1)
VO(2)
Figure 29. Schematic for Sequential Start-Up
Sequence
Figure 30. Sequential Start-Up Using EN and
PWRGD
White space
16
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
TPS54561-Q1
3
4
6
EN
V
, V
(EN)(1) (EN)(2)
SS/TR
PWRGD
V
O(1)
TPS54561-Q1
V
O(2)
3
4
6
EN
SS/TR
PWRGD
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Schematic for Ratiometric Start-Up
Sequence
Figure 32. Ratiometric Start-Up Using Coupled
SS/TR Pins
Figure 31 shows a method for a ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start capacitor by
using Equation 5, double the pullup current source (I(SS)). Figure 32 shows the results of Figure 31.
TPS54561-Q1
BOOT
EN
SW
VO(1)
SS/TR
PWRGD
TPS54561-Q1
BOOT
R1
R2
EN
VO(2)
SW
SS/TR
FB
R3
PWRGD
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence
One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of
R1 and R2 shown in Figure 33 to the output of a power supply that must be tracked, or to another voltage
reference source. Using Equation 7 and Equation 8, one can calculate values for the tracking resistors to initiate
VO(2) slightly before, after, or at the same time as VO(1). Equation 6 is the voltage difference between VO(1) and
VO(2) at 95% of nominal output regulation.
Copyright © 2014–2017, Texas Instruments Incorporated
17
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR-to-FB
offset (V(SSoffset)) in the soft-start circuit and the offset created by the pullup current source (I(SS)) and tracking
resistors, the equations include V(SSoffset) and I(SS) as variables.
To design a ratiometric start-up in which the VO(2) voltage is slightly greater than the VO(1) voltage when VO(2)
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 6 results in a
positive number for applications in which VO(2) is slightly lower than VO(1) when VO(2) reaches its regulation.
Because of the requirement for pulling the SS/TR pin below 54 mV before starting after an EN, UVLO, or thermal
shutdown fault, careful selection of the tracking resistors ensures that the device restarts after a fault. Make sure
the calculated R1 value from Equation 7 is greater than the value calculated in Equation 9 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(SSoffset) becomes larger as the
soft-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
DV = VO(1) - VO(2)
(6)
at 95% of nominal output regulation.
V
O(2) + DV V(SSoffset)
´
R1= VO(1)
-
Vref
ref ´R1
I(SS)
(7)
V
R2 =
V
O(2) + DV - Vref
(8)
(9)
R1 > 2800´ VO(1) - 180´ DV
V
(EN)
V
(EN)
V
V
O(1)
O(1)
V
V
O(2)
O(2)
Figure 34. Ratiometric Start-Up With Tracking Resistors –
VO(2) Before VO(1)
Figure 35. Ratiometric Start-Up With Tracking Resistors –
VO(2) After VO(1)
18
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
V
(EN)
V
O(1)
V
O(2)
Figure 36. Simultaneous Start-Up With Tracking Resistors
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54561-Q1 device is adjustable over a wide range, from 100 kHz to 2500 kHz,
by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 6 and Figure 7. To reduce the solution size,
one would typically set the switching frequency as high as possible, but consider tradeoffs of the conversion
efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is
typically 100 ns, which limits the maximum operating frequency in applications with high input-to-output step-
down ratios. The frequency foldback circuit also limits the maximum switching frequency. The next section talks
about the maximum switching frequency in detail.
101756
f sw (kHz)1.008
RT (kW) =
(10)
92417
RT (kW)0.991
f sw (kHz) =
(11)
7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
The TPS54561-Q1 device implements peak-current-mode control, in which the COMP pin voltage controls the
peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-
side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The device clamps the error-amplifier output internally at a level
which sets the switch-current limit. The TPS54561-Q1 device provides an accurate current-limit threshold with a
typical current-limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor
current. Figure 37 shows the relationship between the inductor value and the peak inductor current.
Copyright © 2014–2017, Texas Instruments Incorporated
19
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
Peak Inductor Current
ΔCLpk
Open-Loop Current Limit
td(CL)
ΔCLpk= (V / L(O)) ´ td(CL)
I
t(ON)
Figure 37. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54561-Q1 device implements frequency foldback. The divisor of the oscillator frequency changes from 1 to
2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54561-Q1 device uses digital frequency
foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-
circuit events, the inductor current may exceed the peak current limit because of the high input voltage and the
minimum controllable on-time. When the shorted load forces the output voltage low, the inductor current
decreases slowly during the switch off-time. The frequency foldback effectively increases the off-time by
increasing the period of the switching cycle, providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which frequency foldback
protection can still control the inductor current. Equation 12 calculates the maximum switching frequency at
which the inductor current remains under control with VO forced to VO(SC). The selected operating frequency
should not exceed the calculated value.
Equation 13 calculates the maximum switching frequency limitation set by the minimum controllable on-time and
the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
æ
ö
÷
÷
ø
f(DIV)
I(CL) ´R(dc) + VO(SC) + V(d)
VI -I(CL) ´rDS(on) + V(d)
f(SW_ shift)
=
´ ç
ç
t(ON)
è
(12)
(13)
æ
ö
÷
÷
ø
IO´ R(dc) + VO + V
1
(d)
f(SW_skip) max =
´ ç
ç
t(ON)
VI - IO ´ rDS(on) + V
(d)
è
where
•
•
•
•
•
•
•
•
f(DIV) is the frequency divisor, which equals (1, 2, 4, or 8)
t(ON) is the minimum controllable on-time
I(CL) is the switch current limit
R(dc) is the inductor resistance
VO(SC) is the output voltage during output short
V(d) is the forward voltage drop of the catch diode
VI is the maximum input voltage
rDS(on) is the high-side MOSFET on-resistance
20
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
•
•
IO is the output current
VO is the output voltage
7.3.12 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V, and higher than 2 V, and
have a pulse duration greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The
rising edge of SW synchronizes to the falling edge of the RT/CLK pin signal. The design of the external
synchronization circuit should be such that the default frequency-set resistor connects from the RT/CLK pin to
GND pin when the synchronization signal is off. When using a low-impedance signal source, the connection of
the frequency-set resistor is in parallel with an ac-coupling capacitor to a termination resistor (for example, 300
Ω) as shown in Figure 38. The two resistors in series provide the default frequency-setting resistance when the
signal source turns off. The sum of the resistance should set the switching frequency close to the external CLK
frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor to the
RT/CLK pin.
The first time the input pulls the RT/CLK pin above the PLL high threshold, which has a 2-V maximum value, the
TPS54561-Q1 switches from the RT resistor free-running frequency mode to the PLL synchronized mode.
Removal of the internal 0.5-V voltage source results, and the RT/CLK pin becomes high-impedance as the PLL
starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with
the RT/CLK resistor. The device transitions from the resistor-programmed mode to the PLL mode and locks onto
the external clock frequency within 78 µs. During the transition from the PLL mode to the resistor-programmed
mode, the switching frequency falls to 150 kHz and then increases or decreases to the resistor-programmed
frequency on re-application of the 0.5-V bias voltage to the RT/CLK resistor.
The switching frequency divisor goes from 8 to 4, 2, and 1 as the FB pin voltage ramps from 0 V to 0.8 V. The
device implements a digital-frequency foldback to enable synchronization to an external clock during normal
start-up and fault conditions. Figure 39, Figure 40, and Figure 41 show the device synchronized to an external
system clock in continuous-conduction mode (CCM), discontinuous-conduction (DCM) and pulse-skipping mode.
SPACER
TPS54561-Q1
PLL
TPS54561-Q1
PLL
RT/CLK
RT
RT
RT/CLK
Hi-Z
Clock
Source
Clock
Source
Copyright © 2017, Texas Instruments Incorporated
Figure 38. Synchronizing to a System Clock
Copyright © 2014–2017, Texas Instruments Incorporated
21
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
V(SW)
V(SW)
External
Clock
External
Clock
I(L)
I(L)
Figure 39. Plot of Synchronizing in CCM
Figure 40. Plot of Synchronizing in DCM
V(SW)
External
Clock
I(L)
Figure 41. Plot of Synchronizing in Pulse-Skipping Mode
7.3.13 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output. When the FB pin is between 93% and 106% of the internal voltage
reference, TPS54561-Q1 device de-asserts the PWRGD pin and this pin floats. TI recommends a pullup resistor
of 1 kΩ to a voltage source that is 5.5 V or less. A higher pullup resistance reduces the amount of current drawn
from the pullup voltage source when the PWRGD pin is low. A lower pullup resistance reduces the switching
noise seen on the PWRGD signal. PWRGD is in a defined state once the VDD pin voltage is greater than 2 V, but
with reduced current sinking capability. PWRGD achieves full current-sinking capability as the VDD pin voltage
approaches 3 V.
TPS54561-Q1 device pulls the PWRGD pin low when the FB pin voltage is lower than 90% or greater than 108%
of the nominal internal reference voltage. Also, the TPS54561-Q1 device pulls the PWRGD pin low after an EN,
UVLO, or thermal shutdown fault.
22
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
7.3.14 Overvoltage Protection
The TPS54561-Q1 incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low output capacitance.
For example, on an overload event of the power-supply output, the error amplifier compares the actual output
voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak
current-limit threshold. On removal of the overload condition, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power-supply output voltage can
increase faster than the response of the error amplifier output, resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin
voltage to the rising OVP threshold, which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, immediately disabling the high-side MOSFET minimizes output
overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the internal
voltage reference, the high-side MOSFET resumes normal operation.
7.3.15 Thermal Shutdown
The TPS54561-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the silicon temperature falls below 164°C, the device reinitiates the power-up sequence
controlled by the SS/TR pin.
7.3.16 Small-Signal Model for Loop Response
Figure 42 shows a simplified model for the TPS54561-Q1 control loop, with which the designer can simulate to
check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier
with a gm(ea) of 350 µS. A user can model the error amplifier using an ideal voltage controlled current source. The
resistor, R(OEA), and capacitor, C(OEA), model the open-loop gain and frequency response of the amplifier. The
1-mV ac voltage source between nodes a and b effectively breaks the control loop for the frequency-response
measurements. Plotting c/b provides the small-signal response of the frequency compensation. Plotting a/b
provides the small-signal response of the overall loop. To evaluate the dynamic loop response, replace the load
resistor, R(L), with a current source that has the appropriate load-step amplitude and step rate in a time-domain
analysis. This equivalent model is only valid for continuous-conduction-mode (CCM) operation.
SW
V
O
Power Stage
gm(ps) 17 S
a
b
R(ESR)
R(HS)
R(L)
COMP
c
FB
0.8 V
C(O)
gm(ea)
R(COMP)
350 µS
C(OEA)
R(OEA)
R(LS)
C(POLE)
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Small-Signal Model for Loop Response
Copyright © 2014–2017, Texas Instruments Incorporated
23
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
7.3.17 Simplified Small-Signal Model for Peak-Current-Mode Control
Figure 43 describes a simple small-signal model for use in design of the frequency compensation. A voltage-
controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor can
approximate the TPS54561-Q1 power stage. Equation 14 shows the control-to-output transfer function, which
consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and
the change in COMP pin voltage (node c in Figure 42) is the power stage transconductance, gm(ps). The gm(ps) for
the TPS54561-Q1 device is 17 S. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 15.
As the load current increases or decreases, the low-frequency gain decreases or increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The dashed line in the right half of Figure 43 highlights the combined effect. As
the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same with varying load conditions. The type of output capacitor chosen determines whether the
ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum electrolytic
capacitors may reduce the number of frequency compensation components needed to stabilize the overall loop,
because the phase margin increases by the ESR zero of the output capacitor (see Equation 17).
VO
A(dc)
V(c)
R(ESR)
f(P)
R(L)
gm(ea)
C(O)
f(Z)
Copyright © 2017, Texas Instruments Incorporated
Figure 43. Simplified Small-Signal Model and Frequency Response for Peak-Current-Mode Control
24
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
æ
ç
ç
è
ö
÷
÷
ø
s
1+
1+
2p´ f(Z)
VO
= A(dc)
´
V(C)
æ
ç
ç
è
ö
÷
÷
ø
s
2p´ f(P)
(14)
(15)
A(dc) = gm(ps) ´R(L)
1
f(P)
=
C
(O) ´ R(L) ´ 2p
(16)
(17)
1
f(Z)
=
C
(O) ´ R(ESR) ´ 2p
7.3.18 Small-Signal Model for Frequency Compensation
The TPS54561-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonly-
used frequency-compensation circuits. Figure 44 shows compensation circuits of Type 2A, Type 2B, and Type 1.
Implementation of Type 2 circuits is typically in high-bandwidth power-supply designs using low-ESR output
capacitors. The Type 1 circuit is good for the power-supply designs using high-ESR aluminum electrolytic or
tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small-
signal model in Figure 44. Modeling of the open-loop gain and bandwidth uses R(OEA) and C(OEA), as shown in
Figure 44. See the application section for a design example using a Type 2A network with a low-ESR output
capacitor.
This data sheet includes Equation 18 through Equation 27 as a reference. An alternative is to use WEBENCH
software tools to create a design based on the power-supply requirements.
V
O
a
b
R(HS)
FB
Type 1
Type 2B
Type 2A
gm(ea)
COMP
c
Vref
R(COMP)
R(COMP)
R(LS)
C(POLE)
R(OEA)
C(POLE)
C(OEA)
C(ZERO)
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Types of Frequency Compensation
Copyright © 2014–2017, Texas Instruments Incorporated
25
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
A(OL)
P1
A0
Z1
P2
A1
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
A(OL)
R(OEA)
=
gm(ea)
gm(ea)
(18)
(19)
C(OEA)
=
2p´ BW (Hz)
æ
ç
ç
è
ö
÷
÷
ø
s
1+
2p´ f(Z1)
V
(c)
= A0´
V
æ
ç
ç
è
ö æ
ö
÷
÷
ø
(b)
s
s
1+
´ 1+
÷ ç
÷ ç
2p´ f(P1)
2p´ f(P2)
ø è
R(LS)
R(HS) + R(LS)
(20)
(21)
A0= gm(ea) ´ R(OEA)
´
R(LS)
R(HS) + R(LS)
A1= gm(ea) ´ R(OEA) P R(COMP)
´
(22)
(23)
(24)
1
P1=
2p´ R(OEA) ´ C(ZERO)
1
Z1=
2p´ R(COMP) ´ C(ZERO)
1
P2 =
Type 2A
2p´R(OEA) P R(COMP) ´ C(POLE) + C(OEA)
(
)
(25)
(26)
1
P2 =
P2 =
Type 2B
2p´R(OEA) P R(COMP) ´ C(OEA)
1
Type 1
2p´ R(OEA) ´ C(POLE) + C(OEA)
(
)
(27)
26
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
7.4 Device Functional Modes
7.4.1 Operation With VI = < 4.5 V (Minimum VDD
)
TI recommends operating the TPS54561-Q1 device with input voltages above 4.5 V. The typical VDD UVLO
threshold is 4.3 V, and the device may operate at input voltages down to the UVLO voltage. At input voltages
below the actual UVLO voltage, the device does not switch. If an external resistor divider pulls the EN pin up to
VDD or EN pin is floating, when VDD passes the UVLO threshold the device becomes active. Switching begins,
and the soft-start sequence initiates. The TPS54561-Q1 device starts at the soft-start time determined by the
external capacitance on the SS/TR pin.
7.4.2 Operation With EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage, the device shuts down and
switching stops even if VDD is above its UVLO threshold. The IC quiescent current decreases in this state. After
increasing the EN pin voltage above the threshold while VDD is above its UVLO threshold, the device becomes
active. Switching resumes and the soft-start sequence begins. The TPS54561-Q1 device starts at the soft-start
time determined by the external capacitance at the SS/TR pin.
Copyright © 2014–2017, Texas Instruments Incorporated
27
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54561-Q1 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 5 A.
Example applications are: 12-V, 24-V and 48-V industrial, automotive and communication power systems. Use
the following design procedure to select component values for the TPS54561-Q1 device. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors. The Excel™
spreadsheet (SLVC452) located on the product page can help on all calculations. Alternatively, use the
WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
8.2 Typical Application
7 V to 60 V
2
VI
TP1
C11
1
GND
+
C10
2.2µF
C3
2.2µF
C1
2.2µF
C2
2.2µF
DNP
J2
PWRGD
TP10
PWRGD PULLUP
TP9
R8
U1
PWRGD
1.00k
TP2
2
3
5
4
7
10
VDD
C4
GND
1
9
6
8
EN
BOOT
SW
R1
442k
0.1µF
RT/CLK
SS/TR
COMP
2
1
SS/TR
GND
FB
FB
R3
243k
GND
PAD
J4
R4
16.9k
C13
0.01µF
TPS54561-Q1
GND
C8
47pF
GND
C5
4700pF
L1
R2
90.9k
2
1
5 V @ 5 A
EN
GND
1
2
VO
7447798720
7.2µH
TP6
TP4
TP7
TP8
TP5
J3
GND
R7
49.9
J1
TP3
D1
PDS760-13
+
C12
C9 DNP
47µF
C6
47µF
C7
47µF
GND
SS/TR
GND
2
1
GND
SS/TR
GND
R5
53.6k
J5
FB
GND
R6
10.2k
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 46. 5-V Output TPS54561-Q1 Design Example
8.2.1 Design Requirements
This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. The
designer must know a few parameters in order to start the design process. Determination of these requirements
is typically at the system level. This example design uses the following known parameters:
28
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Application (continued)
DESIGN PARAMETER
Output voltage (VO)
EXAMPLE VALUE
5 V
Transient response, 1.25-A to 3.75-A load step
Maximum output current (IO)
Input voltage (VI)
ΔVO = ±4 %
5 A
12 V nominal, 7 V to 60 V
Output voltage ripple (VO(RIPPLE)
Start input voltage (rising VI)
Stop input voltage (falling VI)
)
0.5% of VO
6.5 V
5 V
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
–
–
–
–
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand the thermal performance of your board
Export your customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because this produces the smallest solution size. High switching frequency allows
for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. Several factors including the minimum controllable on-time of the internal power switch, the input
voltage, the output voltage, and the frequency-foldback protection limit the switching frequency that the designer
can select.
Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator.
Choose the lower-value result from the two equations. Switching frequencies higher than these values result in
pulse-skipping or the lack of overcurrent protection during a short circuit.
The typical minimum controllable on-time, t(ON), is 100 ns for the TPS54561-Q1 device. For this example, the
output voltage is 5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to
955 kHz to avoid pulse skipping from Equation 28. To ensure overcurrent runaway is not a concern during short
circuits, use Equation 29 to determine the maximum switching frequency for frequency foldback protection. With
a maximum input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch
resistance of 87 mΩ, a current limit value of 6 A, and short-circuit output voltage of 0.1 V, the maximum switching
frequency is 1151 kHz.
For this design, choose a lower switching frequency of 400 kHz to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10, or the curve in
Figure 6, or the curve in Figure 7. Resistor R3 sets the switching frequency shown in Figure 46. For 400-kHz
operation, the closest standard value resistor is 243 kΩ.
æ
ç
è
ö
÷
ø
1
5 A´ 11 mW + 5 V + 0.7 V
60 V - 5 A´ 87 mW + 0.7 V
f(SW_skip)max =
´
= 955 kHz
100 ns
(28)
29
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
æ
ç
è
ö
÷
ø
8
6 A´ 11 mW + 0.1 V + 0.7 V
60 V - 6 A´87 mW + 0.7 V
f(SW_shift)
=
´
= 1151 kHz
100 ns
(29)
(30)
101756
400 (kHz)1.008
RT (kW) =
= 242 kW
8.2.2.3 Output Inductor Selection (L(O)
)
To calculate the minimum value of the output inductor, use Equation 31.
k(IND) is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts the
selection of the output capacitor, because the output capacitor must have a ripple current rating equal to or
greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer.
However, the designer may use the following guidelines.
For designs using low-ESR output capacitors such as ceramics, a value as high as k(IND) = 0.3 may be desirable.
When using higher-ESR output capacitors, k(IND) = 0.2 yields better results. Because the inductor ripple current is
part of the current-mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide-input voltage regulator, choosing a relatively large inductor ripple current is
best to provide sufficient ripple current with the input voltage at the minimum.
For this design example, k(IND) = 0.3 and the calculated inductor value is 7.6 µH. The nearest standard value is
7.2 µH. It is important not to exceed both the rms current and saturation-current ratings of the inductor.
Equation 33 and Equation 34 calculate the rms and peak inductor current. For this design, the rms inductor
current is 5.021 A and the peak inductor current is 5.817 A. The chosen inductor has an rms current rating of 6 A
and a saturation current rating of 7.9 A.
As the equation set demonstrates, lowering ripple currents reduces the output voltage ripple of the regulator but
requires a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit of
the device. For this reason, the most-conservative design approach is to choose an inductor with a saturation
current rating equal to or greater than the switch-current limit of the TPS54561-Q1 device, which is nominally 7.5
A.
æ
ö
æ
ö
VI max - VO
IO´ K(IND)
VO
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
60 V - 5 V
5 A ´ 0.3
5 V
L(O)min = ç
÷´ ç
÷ =
´
= 7.6 mH
ç
è
÷ ç
VI max ´ f(SW)
÷
60 V´ 400 kHz
ø
è
ø
(31)
(32)
spacer
I(RIPPLE)
spacer
V ´ V max - V
O
(
)
VI max ´ L(O) ´ f(SW) 60 V´ 7.2 mH ´400 kHz
5 V´ 60 V - 5 V
(
)
O
I
=
=
= 1.591 A
ö2
÷
÷
ø
æ
ç
ç
è
ö2
÷
V ´ V max - V
O
æ
ç
ç
è
(
)
5 V ´ 60 V - 5 V
2
(
)
O
I
1
1
2
I(L)RMS =
I
+
´
=
5 A
+
´
= 5.021 A
( )
(O )
÷
12
VI max ´ L(O) ´ f(SW)
12
60 V´ 7.2 mH´ 400 kHz
ø
(33)
(34)
spacer
I(L)peak = IO +
I(RIPPLE)
1.591 A
= 5.021 A +
= 5.817 A
30
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
8.2.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and the regulator response to a large change in load
current. It is necessary to select the output capacitance based on the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIO is the change in output current, f(sw) is
the regulator switching frequency, and ΔVO is the allowable change in the output voltage. For this example, the
transient load response specification is 4% change in VO for a load step from 1.25 A to 3.75 A. Therefore, ΔIO is
3.75 A – 1.25 A = 2.5 A, and ΔVO = 4% × 5 V = 0.2 V. Using these numbers gives a minimum capacitance of
62.5 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For
ceramic capacitors, the ESR is usually small enough to ignore. Aluminum electrolytic and tantalum capacitors
have higher ESR, and load-step calculations must include the ESR term.
Sizing of the output capacitor must be such as to absorb energy stored in the inductor when transitioning from a
high to low load current. The catch diode of the regulator cannot sink current, so energy stored in the inductor
can produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical
load-step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
Sizing of the capacitor must be such as to maintain the desired output voltage during these transient periods.
Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where L(O) is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, VP is the peak output voltage, and V(int) is the initial voltage. For this example, the worst-case load step
is from 3.75 A to 1.25 A. The output voltage increases during this load transition, and the stated maximum in our
specification is 4% of the output voltage. This makes V(P) = 1.04 × 5 V = 5.2 V. V(int) is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of
44.1 µF.
Equation 37 calculates the minimum output capacitance needed to meet the output-voltage ripple specification,
where f(SW) is the switching frequency, VO(RIPPLE) is the maximum allowable output voltage ripple, and IO(RIPPLE) is
the inductor ripple current. Equation 37 yields 19.9 µF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR should be less than 15.7 mΩ.
The most stringent criterion for the output capacitor is 62.5 µF, required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature, and dc bias increase this minimum value. For this example, the
selection is three 47-µF, 10-V ceramic capacitors with 5 mΩ of ESR. The derated capacitance is 87.4 µF, well
above the minimum required capacitance of 62.5 µF.
Capacitors generally have a maximum ripple-current rating. Filtering a ripple current equal to or below that
maximum ripple current does not degrade capacitor reliability. Some capacitor data sheets specify the root-
mean-square (rms) value of the maximum ripple current. Use Equation 39 to calculate the rms ripple current that
the output capacitor must support. For this example, Equation 39 yields 459 mA.
2´ DIO
(SW) ´ DVO 400 kHz ´ 0.2 V
2 ö
2´ 2.5 A
C(O)
>
=
= 62.5 μF
f
(35)
æ
3.75 A2 - 1.25 A2
I
2 - I
èç(OH ) (OL ) ø÷
(
)
= 44.1mF
C(O) > L(O)
´
= 7.2 mH´
2 - V
2 ö
5.2 V2 - 5 V2
æ
(
)
V
èç( (P) ) ( (int) ) ÷ø
(36)
Copyright © 2014–2017, Texas Instruments Incorporated
31
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
1
1
1
1
C(O)
>
´
=
´
= 19.9 mF
8´ f(SW)
8´ 400 kHz
æ
ç
ç
è
ö
÷
÷
ø
æ
ç
è
ö
÷
ø
25 mV
1.591 A
VO(RIPPLE)
IO(RIPPLE)
(37)
(38)
VO(RIPPLE)
25 mV
R(ESR)
<
=
= 15.7 mW
IO(RIPPLE)
1.591 A
V ´ V min - V
O
(
12 ´ VI min ´ L(O)´ f(SW)
)
5 V´ 60 V - 5 V
(
)
12 ´ 60 V´ 7.2 mH´ 400 kHz
O
I
I(CO)RMS =
=
= 459 mA
(39)
8.2.2.5 Catch Diode
The TPS54561-Q1 device requires an external catch diode between the SW pin and GND. The selected diode
must have a reverse voltage rating equal to or greater than maximum input voltage. The peak current rating of
the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the
catch diode because of the low forward voltage of these diodes. The lower the forward voltage of the diode, the
higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60-V reverse voltage is preferable, to allow input voltage transients up to the rated voltage of the TPS54561-Q1
device.
For the example design, select the Schottky diode for its lower forward voltage and good thermal characteristics
compared to smaller devices. The typical forward voltage of the diode is 0.52 V at 5 A.
One must select the diode with an appropriate power rating. The diode conducts the output current during the
off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. Multiplying the output current during the off-time with
the forward voltage of the diode can calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, take the ac losses of the diode into account. The ac losses of the diode are because of
the charging and discharging of the junction capacitance, and also of reverse-recovery charge. Use Equation 40
to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The selected diode has a junction capacitance of 180 pF. Using Equation 40 with the nominal input voltage of
12 V, the total loss in the diode is 1.65 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
V - V ´ I ´ V
)
C(j) ´ f(SW) ´ V + V
I (d)
(
(
)
I
O
O
(d)
P(D)
=
+
=
VI
2
2
)
12 V - 5 V ´ 5 A ´ 0.52 V 180 pF´ 400 kHz ´ 12 V + 0.52 V
(
(
)
12 V
+
= 1.65 W
2
(40)
8.2.2.6 Input Capacitor
The TPS54561-Q1 device requires a high-quality ceramic type X5R or X7R input decoupling capacitor with at
least 3 µF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance because of dc bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater
than the maximum input current ripple of the TPS54561-Q1 device. Use Equation 41 to calculate the input ripple
current.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
Selecting a dielectric material that is more stable over temperature can minimize the capacitance variations
because of temperature. The usual selection for capacitors in a switching regulator is X5R or X7R ceramic
dielectric, because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The
input capacitor selection must also consider the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
32
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
This example design requires a ceramic capacitor with at least a 60-V voltage rating to support the maximum
input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or
100 V. For this example, use four 2.2-µF, 100-V capacitors in parallel.
The input capacitance value determines the input ripple voltage of the regulator. Use Equation 42 to calculate the
input voltage ripple. Using the design example values, IO = 5 A, C(I) = 8.8 µF, f(sw) = 400 kHz, yields an input
voltage ripple of 355 mV and an rms input ripple current of 2.26 A.
æ
ö
VI min - VO
VO
æ
ç
è
ö
÷
ø
5 V
7 V
7 V - 5 V
I(CI)RMS = IO ´
´ ç
÷ = 5 A ´
´
= 2.26 A
ç
÷
ø
VI min
VI min
7 V
è
(41)
(42)
IO´ 0.25
DVI =
5 A´ 0.25
=
C(I)´ f(SW) 8.8 mF´ 400 kHz
= 355 mV
8.2.2.7 Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time for the output voltage to reach its nominal
programmed value during power up. This is useful if a load requires a controlled voltage slew rate. Adjustable
soft-start is also useful if the output capacitance is large and would require large amounts of current to charge
the capacitor quickly to the output-voltage level. The large currents necessary to charge the output capacitor may
make the TPS54561-Q1 device reach the current limit, or the excessive current draw from the input power supply
may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Use Equation 43 to find the minimum soft-start time, t(SS), necessary
to charge the output capacitor, C(O), from 10% to 90% of the output voltage, VO, with an typical soft-start current
of I(SS). In the example, to charge the effective output capacitance of 87.4 µF up to 5 V with an average current of
1 A requires a 0.3-ms soft-start time.
After selecting the soft-start time, calculate the soft-start capacitor value by using Equation 5. For the example
circuit, the soft-start time is not too critical, because the output capacitor value is 3 × 47 µF, which does not
require much current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of
3.5 ms, which requires a 9.3-nF soft-start capacitor, as calculated by Equation 44. For this design, use the next-
larger standard value of 10 nF.
C
(O) ´ VO ´ 0.8
t(SS)
>
I(SS)
(43)
(44)
t(SS) (ms) ´ I(SS) (mA)
3.5 ms´ 1.7 mA
0.8 V´ 0.8
C13 =
=
= 9.3 nF
V
(V)´ 0.8
ref
8.2.2.8 Bootstrap Capacitor Selection
The TPS54561-Q1 device requires a 0.1-µF ceramic capacitor connected between the BOOT and SW pins for
proper operation. The recommendation is a ceramic capacitor with X5R or better grade dielectric. The capacitor
should have a 10-V or higher voltage rating.
Copyright © 2014–2017, Texas Instruments Incorporated
33
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
8.2.2.9 Undervoltage Lockout Set Point
Using an external voltage divider on the EN pin of the TPS54561-Q1 device can adjust the undervoltage lockout
(UVLO). The UVLO has two thresholds, one for power up when the input voltage is rising and the other for power
down when the input voltage is falling. For the example design, the TPS54561-Q1 device should turn on and
start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5 V (UVLO stop).
A resistor divider consisting of R(UVLO1) and R(UVLO2) between VI and ground, and connected to the EN pin, can
set programmable UVLO threshold voltage. Equation 3 and Equation 4 calculate the resistance values
necessary. For the example application, a 442-kΩ resistor between VI and EN (R1) and a 90.9-kΩ resistor
between EN and ground (R2) are required to produce the 6.5-V start and 5-V stop voltages.
V
(START) - V
6.5 V - 5 V
3.4 mA
(STOP)
R1=
=
= 441.18 kW
I(HYS)
(45)
(46)
V
1.2 V
(EN)th
R2 =
=
= 90.97 kW
V
(START) - V
6.5 V - 1.2 V
(EN)th
+1.2 mA
+ I(1)
442 kW
R(UVLO1)
8.2.2.10 Output Voltage and Feedback Resistor Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, select 10.2 kΩ for R6. Use
Equation 2 to calculate R5 as 53.55 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 µA to maintain
the output voltage accuracy. A value for R6 of less than 800 kΩ satisfies this requirement. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
æ VO - 0.8 V ö
æ
ç
è
ö
÷
ø
5 V - 0.8 V
R5 = R6´
= 10.2 kW´
÷
= 53.55 kW
ç
0.8 V
0.8 V
è
ø
(47)
8.2.2.11 Compensation
There are several methods to design compensation for dc-dc regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Ignoring the slope
compensation causes the actual crossover frequency to be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, calculate the modulator pole, f(P,mod), and the ESR zero, f(Z,mod) using Equation 48 and
Equation 49. For output capacitance C(O), use a derated value of 87.4 µF. Use equations Equation 50 and
Equation 51 to estimate a starting point for the crossover frequency, f(CO). For the example design, f(P,mod) is 1821
Hz and f(Z,mod) is 1090 kHz. Equation 50 is the geometric mean of the modulator pole and the ESR zero, and
Equation 51 is the geometric mean of modulator pole and half of the switching frequency. Equation 50 yields
44.6 kHz and Equation 51 gives 19.1 kHz. Use the geometric mean value of Equation 50 and Equation 51 for an
initial crossover frequency which is 29.2 kHz. For this example, the target crossover frequency is 30 kHz for an
improved transient response.
Next, calculate the compensation components. Use of a resistor in series with a capacitor creates a
compensating zero. A capacitor in parallel with these two components forms the compensating pole.
IO max
5 A
f(P,mod)
=
=
= 1821Hz
2p´ VO ´ C(O) 2p´ 5 V´ 87.4 mF
(48)
1
1
f(Z,mod)
=
=
2p´R(ESR) ´ C(O) 2p´1.67 mW ´ 87.4 mF
= 1090 kHz
(49)
(50)
f(CO1)
=
f
(P,mod) ´ f(Z,mod)
=
1821Hz ´1090 kHz = 44.6 kHz
f(SW)
400 kHz
f(CO2)
=
f(P,mod)
´
=
1821Hz ´
= 19.1kHz
2
2
(51)
34
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance,
gm(ps), is 17 S. The output voltage VO, reference voltage Vref, and amplifier transconductance gm(ea), are 5 V,
0.8 V and 350 µS, respectively. Calculated the value for R4 as 16.84 kΩ, and then select a standard value of
16.9 kΩ. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields
5172 pF for compensating capacitor C5. The selection for this design is 4700 pF.
æ
ö
æ
ö
2p´ f(CO) ´ C(O)
VO
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
2p´ 29.2 kHz ´ 87.4 mF
17 S
5 V
R4 = ç
÷´ ç
÷ =
´
= 16.84 kW
ç
è
÷
ø
ç
Vref ´ gm(ea)
÷
gm(ps)
0.8 V´ 350 mS
è
ø
(52)
(53)
1
1
C5 =
=
2p ´ R4´ f(P,mod) 2p ´ 16.9 kW ´1821Hz
= 5172 pF
If desired, implement a compensation pole by adding capacitor C8 in parallel with the series combination of R4
and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole.
The selected value of C8 is 47 pF for this example design.
C
(O) ´ R(ESR)
87.4 mF ´ 1.67 mW
C8 =
=
= 8.64 pF
R4
16.9 kW
(54)
(55)
1
1
C8 =
=
p´ R4´ f(SW) p´ 16.9 kW ´ 400kHz
= 47.1pF
8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the example design enters discontinuous-conduction mode when the output
current is less than 408 mA. The power supply enters Eco-mode when the output current is lower than 25.3 mA.
The input current draw is 257 µA with no load.
Copyright © 2014–2017, Texas Instruments Incorporated
35
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
8.2.2.13 Power Dissipation Estimate
The following formulas show how to estimate the TPS54561-Q1 device power dissipation under continuous
conduction mode (CCM) operation. These equations are not suitable if the device operates in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (P(COND)), switching loss (P(SW)), gate drive loss (P(G)
)
and supply current loss (P(Q)). Example calculations are shown with the 12-V nominal input voltage of the
example design.
1. Conduction loss
æ
ö
P(COND) = I 2 ´ rDS(on) ´ ç
÷ = 5 A2 ´ 87 mW ´
= 0.906 W
VO
VI
æ
ç
è
ö
÷
ø
5 V
(O )
ç
è
÷
ø
12 V
where
•
•
•
•
IO is the output current (A)
rDS(on) is the on-resistance of the high-side MOSFET (Ω)
VO is the output voltage (V)
VI is the input voltage (V)
(56)
2. Switching loss
P(SW) = VI ´ f(SW) ´ IO ´ tr = 12 V´ 400 kHz ´ 5 A´ 4.9 ns = 0.118 W
where
•
•
f(SW) is the switching frequency (Hz)
tr is the SW pin voltage rise time, estimated by tr = VDD (V) × 0.16 (ns/V) + 3 (ns)
(57)
(58)
3. Gate drive loss
P
(G) = VI ´ Qg ´ f(SW) = 12 V´ 3 nC ´ 400 kHz = 0.014 W
where
•
Qg is the total gate charge of the internal MOSFET
4. Quiescent current loss
(Q) = VI ´ IQ = 12 V´152 mA = 0.0018 W
P
where
•
IQ is the operating nonswitching supply current
(59)
(60)
Therefore,
P(tot) = P(COND) + P(SW) + P(G) + P(Q) = 0.906 W + 0.118 W + 0.014 W + 0.0018 W = 1.040 W
For given TA,
TJ = TA + RqJA ´ P(tot)
where
•
•
•
•
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
RθJA is the thermal resistance of the package (°C/W)
P(tot) is the total device power dissipation (W)
(61)
(62)
For given TJmax = 150°C
TA max = TJ max - RqJA ´ P(tot)
where
•
•
TAmax is maximum ambient temperature (°C)
TJmax is maximum junction temperature (°C)
Additional power losses occur in the regulator circuit because of the inductor ac and dc losses, the catch diode
and PCB trace resistance. All of these losses impact the overall efficiency of the regulator.
36
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
8.2.3 Safe Operating Area
Figure 47 through Figure 50 show the safe operating area (SOA) of the device for 3.3-V, 5-V, and 12-V outputs
and varying amounts of forced air flow applications. The temperature derating curves represent the conditions at
which the TPS54561-Q1 device, PCB and the output Inductor are at or below the manufacturer’s maximum
operating temperatures. Figure 47, through Figure 50 doesn't consider the impact from the catch diode thermal
performance. For higher reliability, TI uses 125 °C as the temperature limit for TPS54561-Q1 device on
Figure 47, through Figure 50. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz.
copper, similar to the board on TPS54561EVM-555 evaluation module.
Pay careful attention to the other components chosen for the design, especially the catch diode. In most
applications, the catch diode limits the thermal performance. When operating at high duty cycles or at a higher
switching frequency, the thermal performance of the TPS54561-Q1 device can become the limiting factor.
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
8 V
8 V
12 V
24 V
36 V
48 V
60 V
12 V
24 V
36 V
48 V
60 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
D047
D048
VO = 3.3 V
Natural Convection
f(SW) = 400 kHz
VO = 5 V
Natural Convection
f(SW) = 400 kHz
Figure 47. 3.3-V Outputs
Figure 48. 5-V Outputs
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
18 V
24 V
36 V
48 V
60 V
400 LFM
200 LFM
100 LFM
Nat. Conv.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
D049
D050
VO = 12 V
Natural Convection
f(SW) = 600 kHz
VI = 48 V
VO = 12 V
Air flow direction: L1 to output terminal
f(SW) = 600 kHz
Figure 49. 12-V Outputs
Figure 50. Air Flow Conditions
Copyright © 2014–2017, Texas Instruments Incorporated
37
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
8.2.4 Application Curves
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
IO
VI
Vo, DC-Coupled With –5-V Offset
Vo, DC-Coupled With –5-V Offset
Time = 100 µs/div
Time = 4 ms/div
Figure 51. Load Transient Response (1.25-A to 3.75-A
Load Step)
Figure 52. Line Transient (8 V to 40 V)
VI
VI
V(EN)
V(EN)
VO
VO
Time = 2 ms/div
IO = 5 A
IO = 5 A
Figure 53. Start-Up With Input Voltage
Figure 54. Start-Up With EN
V(SW)
V(SW)
I(L)
I(L)
VO, AC-Coupled
VO, AC-Coupled
Time = 4 µs/div
Time = 4 µs/div
IO = 100 mA
IO = 5 A
Figure 56. Output Ripple, DCM
Figure 55. Output Ripple, CCM
38
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
V(SW)
V(SW)
I(L)
I(L)
VO, AC-Coupled
VI, AC-Coupled
Time = 4 µs/div
Time = 1 ms/div
No load
IO = 5 A
Figure 57. Output Ripple, Eco-mode
Figure 58. Input Ripple, CCM
V(SW)
I(L)
V(SW)
I(L)
VO
VI, AC-Coupled
Time = 40 µs/div
No load
Time = 4 µs/div
VI = 5.5 V
VO = 5.0 V
IO = 100 mA
100 mA
EN floating
Figure 60. Low-Dropout Operation, Steady State
Figure 59. Input Ripple, DCM
VI
VI
VO
VO
Time = 40 ms/div
Time = 40 ms/div
IO = 100 mA
EN floating
IO = 1 A
EN floating
Figure 61. Low-Dropout Operation
Figure 62. Low-Dropout Operation
Copyright © 2014–2017, Texas Instruments Incorporated
39
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VDD
7 V
VDD
7 V
12 V
24 V
36 V
48 V
60 V
12 V
24 V
36 V
48 V
60 V
0
1
2
3
4
5
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D029
D030
f(SW) = 400 kHz
VO = 5 V
f(SW) = 400 kHz
VO = 5 V
Figure 63. Efficiency vs Load Current
Figure 64. Light-Load Efficiency
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VDD
6 V
12 V
24 V
36 V
48 V
60 V
VDD
6 V
12 V
24 V
36 V
48 V
60 V
0
1
2
3
4
5
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D031
D032
f(SW) = 400 kHz
VO = 3.3 V
f(SW) = 400 kHz
VO = 3.3 V
Figure 65. Efficiency vs Load Current
Figure 66. Light-Load Efficiency
60
40
180
0.1
0.08
0.06
0.04
0.02
0
120
60
20
0
0
-0.02
-0.04
-0.06
-0.08
-0.1
-20
-40
-60
-60
-120
-180
Gain
Phase
10
100
1000
10000
100000
0
1
2
3
4
5
Frequency (Hz)
Output Current (A)
D033
D034
f(SW) = 400 kHz
IO = 5 A
VI = 12 V
VO = 5 V
f(SW) = 400 kHz
VI = 12 V
VO = 5 V
Figure 68. Regulation vs Load Current
Figure 67. Overall Loop Frequency Response
40
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
D035
f(SW) = 400 kHz
IO = 2.5 A
VO = 5 V
Figure 69. Regulation vs Input Voltage
8.2.5 Inverting Power Supply
One use of the TPS54561-Q1 is to convert a positive input voltage to a negative output voltage. Ideal
applications are amplifiers requiring a negative power supply. For a more-detailed example, see Create an
Inverting Power Supply From a Step-Down Regulator, application report SLVA317.
VI
+
C(I)
C(BOOT)
L(O)
VDD BOOT SW
GND
C(O)
C(VDD)
R(HS)
R(LS)
+
GND
TPS54561-Q1
VO
EN
FB
PWRGD
SS/TR
COMP
C(SS)
R(COMP)
RT/CLK
R(RT)
C(ZERO)
C(POLE)
Copyright © 2017, Texas Instruments Incorporated
Figure 70. TPS54561-Q1 Inverting Power Supply Based on Application Report SLVA317
Copyright © 2014–2017, Texas Instruments Incorporated
41
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
8.2.6 Split-Rail Power Supply
Another use of the TPS54561-Q1 device is to convert a positive input voltage to a split-rail positive- and
negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail
positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power
Supply With a Wide Input Voltage Buck Regulator, application report SLVA369.
VO+
+
VI
C(O)+
+
T(O)
C(I)
C(BOOT)
VDD BOOT SW
GND
R(HS)
R(LS)
C(VDD)
+
GND
C(O)–
VO–
TPS54561-Q1
EN
FB
PWRGD
COMP
SS/TR
C(SS)
R(COMP)
C(POLE)
RT/CLK
C(ZERO)
R(RT)
Copyright © 2016, Texas Instruments Incorporated
Figure 71. TPS54561-Q1 Split-Rail Power Supply Based on Application Report SLVA369
9 Power Supply Recommendations
The design of the device is for operation from an input voltage supply range between 4.5 V and 60 V. Good
regulation of this input supply is essential. If the input supply is more distant than a few inches from the
TPS54561-Q1 converter, the circuit may require additional bulk capacitance besides the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
42
Copyright © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. There are several signal paths that conduct fast-
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 72 for a PCB layout example.
•
To reduce parasitic effects, bypass the VDD pin to ground with a low-ESR ceramic bypass capacitor with X5R
or X7R dielectric.
•
Take care to minimize the loop area formed by the bypass capacitor connections, the VDD pin, and the anode
of the catch diode. Route the SW pin to the cathode of the catch diode and to the output inductor. Because
the SW connection is the switching node, locate the catch diode and output inductor close to the SW pins,
and minimize the area of the PCB conductor to prevent excessive capacitive coupling.
•
Tie the GND pin directly to the copper pad under the IC for the exposed thermal pad. Connect this copper
pad to internal PCB ground planes using multiple vias directly under the IC.
•
•
For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area.
The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC and route
conductors with minimal lengths of trace.
•
•
Figure 72 shows the approximate placement for the additional external components.
It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout, meant
as a guideline, demonstrably produces good results.
Boxing in the components in the design of Figure 46, the estimated printed-circuit board area is 1.025 in2
(661 mm2). This area does not include test points or connectors. To further reduce the area, use a two-sided
assembly and replace the 0603-sized passives with a smaller-sized equivalent.
10.2 Layout Example
VO
Output
Capacitor
Output
Inductor
Top-Side
Ground
Route boot-capacitor
Catch
Area
trace on another layer to
provide a wide path for
the top-side ground.
Diode
Input
Bypass
Capacitor
PWRGD
BOOT
VDD
SW
VI
GND
EN
UVLO
Adjust
COMP
FB
SS/TR
Resistors
RT/CLK
Compensation Resistor
Network
Divider
Thermal Via
Signal Via
Soft-Start
Capacitor
Frequency
Set Resistor
Figure 72. PCB Layout Example
版权 © 2014–2017, Texas Instruments Incorporated
43
TPS54561-Q1
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
有关 TPS54560、TPS54561 和 TPS54561-Q1 系列 Excel 设计工具的信息，请参见 SLVC452。
11.2 文档支持
11.2.1 相关文档
相关文档如下：
•
•
•
•
《使用降压稳压器创建反向电源》，SLVA317
《使用宽范围输入电压降压稳压器创建分离轨电源》，SLVA369
《针对 TPS54561 降压转换器的评估模块》，SLVU993
《利用 TPS54240 和 TPS2511 制作供 USB 设备使用的通用车载充电器》，SLVA464
11.2.2 使用 WEBENCH® 工具定制设计方案
请单击此处，借助 WEBENCH®Power Designer 并使用 TPS54561-Q1 器件定制设计方案
1. 首先输入您的 VIN、VOUT 和 IOUT 要求。
2. 使用优化器拨盘可优化效率、封装和成本等关键设计参数并将您的设计与德州仪器 (TI) 的其他可行解决方案进
行比较。
3. WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
4. 在多数情况下，您还可以：
–
–
–
–
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
5. 有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
44
版权 © 2014–2017, Texas Instruments Incorporated
TPS54561-Q1
www.ti.com.cn
ZHCSCT5A –SEPTEMBER 2014–REVISED JANUARY 2017
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。本数据随时可能发生变更并
且不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧导航栏。
版权 © 2014–2017, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54561QDPRRQ1
TPS54561QDPRTQ1
ACTIVE
WSON
WSON
DPR
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS
54561Q
ACTIVE
DPR
NIPDAU
TPS
54561Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54561QDPRRQ1
TPS54561QDPRTQ1
WSON
WSON
DPR
DPR
10
10
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54561QDPRRQ1
TPS54561QDPRTQ1
WSON
WSON
DPR
DPR
10
10
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS54610-EP
3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢)
TI
TPS54610-Q1
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢)
TI
TPS54610MPWPREP
3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢)
TI
TPS54610MPWPREPG4
3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢)
TI
TPS54610PWPG4
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK SWITCHER WITH INTEGRATED FETs (SWIFT)
TI
©2020 ICPDF网 联系我们和版权申明