TPS54615PWPRG4 [TI]
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT); 3 V至6 V的输入, 6 -A输出同步降压PWM具有集成FET SWITCHER ( SWIFT )型号: | TPS54615PWPRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) |
文件: | 总24页 (文件大小:1012K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
Typical Size
6,6 mm X 9,8 mm
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
DESCRIPTION
D
D
D
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
and Sink
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed
Output Voltage Devices With 1.0% Initial
Accuracy
Internally Compensated for Easy Use and
Minimal Component Count
The SWIFT™ family of dc/dc regulators, the TPS54611,
TPS54612, TPS54613, TPS54614, TPS54615 and
TPS54616 low-input voltage high-output current
synchronous-buck PWM converters integrate all required
active components. Included on the substrate are true,
high-performance, voltage error amplifiers that provide
high performance under transient conditions; an
under-voltage-lockout circuit to prevent start-up until the
input voltage reaches 3 V; an internally and externally set
slow-start circuit to limit in-rush currents; and a power good
output useful for processor/logic reset, fault signaling, and
supply sequencing.
D
Fast Transient Response
D
Wide PWM Frequency − Fixed 350 kHz,
550 kHz or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
D
D
The TPS54611−6 devices are available in a thermally
enhanced 28-pin TSSOP (PWP) PowerPAD™ package,
which eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to aid in
quickly achieving high-performance power supply designs
to meet aggressive equipment development cycles.
APPLICATIONS
D
D
Low-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
D
D
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
EFFICIENCY AT 350 kHz
100
SIMPLIFIED SCHEMATIC
95
90
Output
Input
VIN
PH
85
80
75
70
65
60
55
50
TPS54614
BOOT
PGND
VSENSE
VBIAS
AGND
0
1
2
3
4
5
6
Load Current − A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2001−2005, Texas Instruments Incorporated
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PWP PACKAGE
(TOP VIEW)
1
2
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
NC
PWRGD
BOOT
PH
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
4
5
6
7
8
9
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
VIN
VIN
10
11
12
13
14
PGND
PGND
PGND
PGND
PGND
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC HTSSOP
PACKAGED DEVICES
PLASTIC HTSSOP
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
T
A
T
A
)(1)(2)
)(1)(2)
(PWP
(PWP
0.9 V
1.2 V
1.5 V
TPS54611PWP
TPS54612PWP
TPS54613PWP
1.8 V
2.5 V
3.3 V
TPS54614PWP
TPS54615PWP
TPS54616PWP
−40°C to 85°C
−40°C to 85°C
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54616PWPR). See the application section
of this data sheet for PowerPAD drawing and layout information.
Terminal Functions
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-set FET driver.
NC
3
No connection
PGND
15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High-Z when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when
ref
SS/ENA is low or internal shutdown signal active.
RT
28
26
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL
27
25
Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect directly to output voltage sense point.
2
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
VIN, SS/ENA, FSEL
−0.3 V to 7 V
−0.3 V to 6 V
−0.3 V to 4 V
−0.3 V to 17 V
−0.3 V to 7 V
−0.6 V to 10 V
Internally Limited
6 mA
RT
Input voltage range, V
I
VSENSE
BOOT
VBIAS, PWRGD
PH
Output voltage range, V
O
PH
Source current, I
O
VBIAS
PH
12 A
Sink current, I
S
SS/ENA, PWRGD
AGND to PGND
10 mA
Voltage differential
0.3 V
Continuous power dissipation
See Power Dissipation Rating Table
−40°C to 125°C
−65°C to 150°C
300°C
Operating virtual junction temperature range, T
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)(2)
DISSIPATION RATINGS
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T = 25°C
T = 70°C
T = 85°C
A
A
A
POWER RATING POWER RATING POWER RATING
(3)
28 Pin PWP with solder
18.2 °C/W
40.5 °C/W
5.49 W
2.48 W
3.02 W
1.36 W
2.20 W
0.99 W
28 Pin PWP without solder
(1)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
(2)
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
(3)
ADDITIONAL 6A SWIFT™ DEVICES
DEVICE
TPS54610
TPS54672
TPS54680
TPS54673
OUTPUT VOLTAGE
0.9 V to 3.3 V
DDR memory adjustable
Sequencing adjustable
Prebias adjustable
RELATED DC/DC PRODUCTS
D
D
D
TPS40000—Low-input, voltage-mode synchronous buck controller
TPS759xx—7.5-A low dropout regulator
PT6440 series—6 A plugin modules
3
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
ELECTRICAL CHARACTERISTICS
T = –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
3.0
6.0
V
f = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open
6.2
9.6
12.8
1.4
s
f = 550 kHz, FSEL ≤ 2.5 V, RT open, phase pin open
s
8.4
1
I
Quiescent current
mA
(Q)
Shutdown, SS/ENA = 0 V
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.95
2.80
0.16
3.0
V
V
V
2.70
0.14
Rising and falling edge deglitch,
UVLO
2.5
µs
(1)
BIAS VOLTAGE
Output voltage, VBIAS
I
= 0
2.70
2.80
2.90
100
V
(VBIAS)
(2)
Output current, VBIAS
µA
OUTPUT VOLTAGE
T = 25°C, VIN = 5 V
0.9
1.2
1.5
1.8
2.5
3.3
V
V
V
V
V
V
J
TPS54611
3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
−2.0%
−2.0%
−2.0%
−3.0%
−3.0%
−3.0%
2.0%
2.0%
2.0%
3.0%
3.0%
3.0%
L
J
T = 25°C, VIN = 5 V
J
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
L
J
T = 25°C, VIN = 5 V
J
3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
L
J
V
O
Output voltage
T = 25°C, VIN = 5 V
J
3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
L
J
T = 25°C, VIN = 5 V
J
3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
L
J
T = 25°C, VIN = 5 V
J
4 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C
L
J
REGULATION
Line regulation
(1) (3)
(1) (3)
I = 3 A, 350 ≤ f ≤ 550 kHz, T = 85°C
0.088
%/V
%/A
L
s
J
Load regulation
OSCILLATOR
I = 0 A to 6 A, 350 ≤ f ≤ 550 kHz, T = 85°C
0.0917
L
s
J
FSEL ≤ 0.8 V, RT open
280
440
252
460
663
2.5
350
550
280
500
700
420
660
308
540
762
Internally set—free running frequency
kHz
kHz
FSEL ≥ 2.5 V, RT open
(1)
RT = 180 kΩ (1% resistor to AGND)
Externally set—free running
frequency range
RT = 100 kΩ (1% resistor to AGND)
(1)
RT = 68 kΩ (1% resistor to AGND)
High level threshold, FSEL
Low level threshold, FSEL
V
V
0.8
(1)
Ramp valley
0.75
1
V
(1)
Ramp amplitude (peak-to-peak)
V
(1)
Minimum controllable on time
200
ns
(1)
Maximum duty cycle
90%
(1)
(2)
(3)
Specified by design
Static resistive loads only
Tested using circuit in Figure 10.
4
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
T = –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
(1)
Error amplifier open loop voltage gain
26
dB
MHz
V
(1)
Error amplifier unity gain bandwidth
Error amplifier common mode input voltage range
PWM COMPARATOR
3
0
5
(1)
Powered by internal LDO
VBIAS
85
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding deadtime)
(1)
10-mV overdrive
70
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
0.82
1.20
0.03
2.5
3.3
4.5
5.6
3.3
4.7
6.1
5
1.40
V
V
(1)
(1)
Falling edge deglitch, SS/ENA
µs
TPS54611
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
2.6
3.5
4.4
2.6
3.6
4.7
3
4.1
5.4
6.7
4.1
5.6
7.6
8
(1)
Internal slow-start time
ms
Charge current, SS/ENA
SS/ENA = 0V
µA
Discharge current, SS/ENA
SS/ENA = 0.2 V, V = 2.7 V
1.5
2.3
4.0
mA
I
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
Power good falling edge deglitch
Output saturation voltage, PWRGD
Leakage current, PWRGD
VSENSE falling
See Note 1
90
3
%V
%V
O
O
See Note 1
35
µs
V
I
= 2.5 mA
0.18
0.3
1
(sink)
V = 5.5 V
I
µA
CURRENT LIMIT
(1)
V = 3 V
7.2
10
10
12
I
Current limit
A
(1)
V = 6 V
I
Current limit leading edge blanking time (see Note 1)
Current limit total response time (see Note 1)
100
200
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
C
Thermal shutdown hysteresis
OUTPUT POWER MOSFETS
(2)
(2)
I
I
= 3 A, V = 6 V
26
36
47
65
O
I
r
Power MOSFET switches
mΩ
DS(on)
= 3 A, V = 3 V
O
I
(1)
(2)
Specified by design
Matched MOSFETs, low side r
production tested, high side r
specified by design.
DS(on)
DS(on)
5
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
VIN
Enable
Comparator
5 µA
SS/ENA
REG
Falling
Edge
Deglitch
SHUTDOWN
VIN
ILIM
Comparator
1.8 V
VIN
Thermal
Shutdown
145°C
Hysteresis: 0.03
V
Leading
Edge
Blanking
2.5 µs
VIN UVLO
Comparator
Falling
and
Rising
Edge
100 ns
VIN
BOOT
2.94 V
Sensefet
Deglitch
Hysteresis: 0.16
V
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-Start
(Internal Slow-Start Time
=
+
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
−
2 kΩ
3.3 ms to 6.6 ms)
PWM
Comparator
40 kΩ
Error
Amplifier
VIN
25 ns Adaptive
Deadtime
V
I
30 mΩ
Feed-Forward
Compensation
V
I
OSC
PGND
Power good
Comparator
Reference/
DAC
Falling
Edge
PWRGD
VSENSE
0.90 V
ref
Deglitch
TPS5461x
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
FSEL
VSENSE
RT
6
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE
DRAIN-SOURCE ON-STATE
INTERNALLY SET OSCILLATOR
RESISTANCE
vs
JUNCTION TEMPERATURE
RESISTANCE
vs
JUNCTION TEMPERATURE
FREQUENCY
vs
JUNCTION TEMPERATURE
100
120
100
80
750
V = 5 V
I
V = 3.3 V
I
I
= 3 A
O
I
= 3 A
O
80
60
40
20
0
650
FSEL ≥ 2.5 V
550
60
450
FSEL ≤ 0.8 V
40
350
250
20
0
−40
0
25
85
125
−40
0
25
85
125
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1
Figure 2
Figure 3
EXTERNALLY SET OSCILLATOR
FREQUENCY
OUTPUT VOLTAGE REGULATION
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
0.8950
0.8930
0.8910
0.8890
0.895
800
T
A
= 85°C
RT = 68 k
700
600
500
400
0.893
0.891
RT = 100 k
f = 350 kHz
0.889
RT = 180 k
0.8870
0.8850
0.887
0.885
300
200
−40
0
25
85
125
3
4
5
6
−40
0
25
85
125
V
− Input Voltage − V
I
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 4
Figure 5
Figure 6
DEVICE POWER LOSSES
vs
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
ERROR AMPLIFIER
OPEN LOOP RESPONSE
LOAD CURRENT
0
−20
5
140
3.80
3.65
3.50
3.35
3.20
3.05
R = 10 kΩ,
L
T
F
= 125°C
= 700 kHz
J
4.5
C
L
= 160 pF,
120
100
80
S
T
A
= 25°C
−40
−60
−80
4
V = 3.3 V
I
3.5
3
Phase
−100
−120
60
2.5
2
1.5
1
40
20
Gain
−140
−160
V = 5.0 V
I
0
2.90
2.75
−180
−200
0.5
0
−20
0
1
2
3
4
5
6
7
8
0
10
100 1 k 10 k 100 k 1 M 10 M
−40
0
25
85
125
I
− Load Current − A
f − Frequency − Hz
L
T
J
− Junction Temperature − °C
Figure 7
Figure 8
Figure 9
7
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54614 application. The TPS54614 (U1) can provide
greater than 6 A of output current at a nominal output
voltage of 1.8 V. For proper operation, the exposed thermal
PowerPAD underneath the integrated circuit package
needs to be soldered to the printed-circuit board.
V
20
21
5
I
VIN
VIN
VIN
VIN
VIN
BOOT
3 V − 6 V
220 µF
6
10 µF
0.047 µF
PH
22
23
24
7
8
PH
7.2 µH
680 µF
PH
PH
PH
PH
PH
PH
V
1.8 V
O
9
10
11
10 kΩ
27
28
26
FSEL
RT
PwrGood
Enable
12
13
SS/ENA
VBIAS
PWRGD
NC
25
4
14
15
PH
PGND
PGND
16
17
18
3
2
0.1 µF
VSENSE
PGND
PGND
PGND
C
SS
1
19
AGND
PwrPad
Figure 10. Application Circuit
COMPONENT SELECTION
OPERATING FREQUENCY
In the application circuit, 350 kHz operation is selected by
leaving FSEL open. Different operating frequencies can
be selected by connecting a resistor between RT pin and
AGND. Choose the value of R using Equation 1 for the
desired operating frequency:
The values for the components used in this design
example were selected using the SWIFT designer
software tool. SWIFT designer provides a complete design
environment for developing dc-dc converters using the
TPS54614, or other devices in the SWIFT product family.
Additional design information is available at www.ti.com.
500 kHz
SwitchingFrequency
R +
100 kW
(1)
INPUT FILTER
Alternately, a preset operating frequency of 550 kHz can
be selected by leaving RT open and connecting the FSEL
The input to the circuit is a nominal 3.3 VDC or 5 VDC. The
input filter is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. A 10-µF ceramic
capacitor for the TPS54614 is required, and must be
located as close as possible to the device.
pin to V .
I
OUTPUT FILTER
The output filter is composed of a 5.2-µH inductor and a
470-µF capacitor. The inductor is low dc resistance
(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor
used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal
compensation network to provide a stable closed loop
response for the converter.
FEEDBACK CIRCUIT
The output voltage of the converter is fed directly into the
VSENSE pin of the TPS54614. The TPS54614 is
internally compensated to provide stability of the output
under varying line and load conditions.
8
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
decoupling capacitor, and the PGND pins of the
TPS54311−16. Use a separate wide trace for the analog
ground signal path. This analog ground should be used for
the timing resistor RT, slow start capacitor and bias
capacitor grounds. Connect this trace directly to AGND
(pin 1).
PCB LAYOUT
Figure 11 shows a generalized PCB layout guide for the
TPS54311−16
The VIN pins should be connected together on the printed
circuit board (PCB) and bypassed with a low ESR ceramic
bypass capacitor. Care should be taken to minimize the
loop area formed by the bypass capacitor connections, the
VIN pins, and the TPS54311−16 ground pins. The
minimum recommended bypass capacitance is 10-µF
ceramic with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the PGND pins.
The PH pins should be tied together and routed to the
output inductor. Since the PH connection is the switching
node, inductor should be located very close to the PH pins
and the area of the PCB conductor minimized to prevent
excessive capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown. Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
The TPS54311−16 has two internal grounds (analog and
power). Inside the TPS54311−16, the analog ground ties
to all of the noise sensitive signals, while the power ground
ties to the noisier power signals. Noise injected between
the two grounds can degrade the performance of the
TPS54311−16, particularly at higher output currents.
Ground noise on an analog ground plane can also cause
problems with some of the control and bias signals. For
these reasons, separate analog and power ground traces
are recommended. There should be an area of ground one
the top layer directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect this
ground area to any internal ground planes. Use additional
vias at the ground side of the input and output filter
capacitors as well. The AGND and PGND pins should be
tied to the PCB ground by connecting them to the ground
area under the device as shown. The only components
that should tie directly to the power ground plane are the
input capacitors, the output capacitors, the input voltage
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, Lout, Cout and PGND as small as
practical.
Connect the output of the circuit directly to the VSENSE
pin. Do not place this trace too close to the PH trace. Do
to the size of the IC package and the device pinout, they
will have to be routed somewhat close, but maintain as
much separation as possible while still keeping the layout
compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace as well.
9
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
ANALOG GROUND TRACE
AGND
FREQUENCY SET RESISTOR
RT
SLOW START
CAPACITOR
FSEL
SS/ENA
VBIAS
VSENSE
NC
BIAS CAPACITOR
PWRGD
BOOT
BOOT
CAPACITOR
VIN
VIN
EXPOSED
POWERPAD
AREA
PH
PH
PH
PH
VOUT
VIN
VIN
VIN
PH
VIN
PGND
PGND
PGND
PGND
PGND
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 11. TPS54611 − 16 PCB Layout
10
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
any area available should be used when 3 A or greater
operation is desired. Connection from the exposes area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
0.0400
Minimum Recommended Top
Side Analog Ground Area
Figure 12. Recommended Land Pattern for 28-Pin PWP PowerPAD
11
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT VOLTAGE
vs
LOAD CURRENT
LOAD CURRENT
LOOP RESPONSE
100
1.03
180
60
50
1.02
1.01
90
135
90
40
30
Phase
V = 5 V
I
V = 5 V
I
80
70
V = 3.3V
I
1
20
10
V = 3.3V
I
Gain
0.99
45
0
60
50
0.98
0.97
−10
−20
0
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
I
− Load Current − A
I − Load Current − A
L
f − Frequency − Hz
L
Figure 13
Figure 14
START-UP WAVEFORMS
Figure 15
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
16
80
70
60
400
8
7
6
14
12
10
350
300
50
40
30
20
250
200
150
100
5
4
3
2
8
6
4
10
0
2
0
50
0
1
0
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
t − Time − µs
Figure 16
Figure 17
Figure 18
AMBIENT TEMPERATURE
vs
LOAD CURRENT
125
T
F
= 125°C
= 700 kHz
J
115
105
S
V = 5 V
I
95
85
75
65
55
45
V = 3.3 V
I
Safe Operating Area
35
25
0
1
2
3
4
5
6
7
8
I
− Load Current − A
L
Figure 19
12
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
www.ti.com
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
DETAILED DESCRIPTION
0.7 V
5 mA
(3)
t
+ C
(SS)
(SS)
Under Voltage Lock Out (UVLO)
The actual slow-start time is likely to be less than the above
approximation due to the brief ramp up at the internal rate.
The TPS5461x incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit, reduces the
likelihood of shutting the device down due to noise on VIN.
VBIAS Regulator
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
Slow-Start/Enable (SS/ENA)
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.7 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise. Refer to the following
table for start up times for each device
Voltage Reference
The voltage reference system produces a precise,
temperature-stable voltage from a bandgap circuit. A
scaling amplifier and DAC are then used to produce the
reference voltages for each of the fixed output devices.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the FSEL pin as a static
digital input. If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor from the RT pin to AGND and floating the FSEL
pin. The switching frequency is approximated by the
following equation, where R is the resistance from RT to
AGND:
DEVICE
OUTPUT VOLTAGE
SLOW-START
3.3 ms
TPS54611
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
4.5 ms
5.6 ms
3.3 ms
4.7 ms
6.1 ms
100 kW
Switching Frequency +
500 [kHz]
The second function of the SS/ENA pin provides an
external means for extending the slow-start time with a
ceramic capacitor connected between SS/ENA and
AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release
of the SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
(4)
R
The following table summarizes the frequency selection
configurations:
SWITCHING FREQUENCY
350 kHz, internally set
550 kHz, internally set
SYNC PIN
RT PIN
Float or AGND Float
≥2.5 V
Float
R = 180 k to 68 k
Externally set 280 kHz to
700 kHz
Float
1.2 V
5 mA
(2)
Error Amplifier
t + C
d
(SS)
The high performance, wide bandwidth, voltage error
amplifier is gain-limited to provide internal compensation
of the control loop. The user is given limited flexibility in
choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from
several vendors. The resulting designs exhibit good noise
Second, as the output becomes active, a brief ramp up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
13
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
and ripple characteristics, but with exceptional transient
response. Transient recovery times are typically in the
range of 10 µs to 20 µs.
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. The high-side and low-side drivers are
designed with 300 mA source and sink capability to quickly
drive the power MOSFETs gates. The low-side driver is
supplied from VIN, while the high-side drive is supplied
from the BOOT pin. A bootstrap circuit uses an external
BOOT capacitor and internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately set and reset the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the
current flow through the high-side MOSFET and a
differential amplifier with preset overcurrent threshold. The
high-side MOSFET is turned off within 200 ns of reaching
the current limit threshold. A 100 ns leading edge blanking
circuit prevents false tripping of current limit. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point, and starts up
under control of the slow-start circuit.Thermal shutdown
provides protection when an overload condition is
sustained for several milliseconds. With a persistent fault
condition, the device cycles continuously: starting up by
control of the slow-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown trip point.
approximately the same voltage as V . If the error
ref
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54611 − TPS54616 devices are capable of
sinking current continuously until the output reaches the
regulation set-point.
Power Good (PWRGD)
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and the
low-side FET turns on to decrease the energy in the output
inductor and consequently decrease the output current.
This process is repeated each cycle in which the current
limit comparator is tripped.
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE falls
10% below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or
thermal shutdown is asserted. When VIN = UVLO
threshold, SS/ENA = enable threshold, and VSENSE >
Dead-Time Control and MOSFET Drivers
90% of V , the open drain output of the PWRGD pin is
ref
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
high. A hysteresis voltage equal to 3% of V and a 35-µs
falling edge deglitch circuit prevent tripping of the power
good comparator due to high-frequency noise.
ref
14
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS54611PWP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS54611
TPS54611PWPG4
TPS54611PWPR
TPS54611PWPRG4
TPS54612PWP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
50
2000
2000
50
Green (RoHS
& no Sb/Br)
TPS54611
TPS54611
TPS54611
TPS54612
TPS54612
TPS54612
TPS54612
TPS54613
TPS54613
TPS54613
TPS54613
TPS54614
TPS54614
TPS54614
TPS54614
TPS54615
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS54612PWPG4
TPS54612PWPR
TPS54612PWPRG4
TPS54613PWP
50
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS54613PWPG4
TPS54613PWPR
TPS54613PWPRG4
TPS54614PWP
50
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS54614PWPG4
TPS54614PWPR
TPS54614PWPRG4
TPS54615PWP
50
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS54615PWPG4
TPS54615PWPR
TPS54615PWPRG4
TPS54616PWP
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
28
28
28
28
28
28
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS54615
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
PWP
PWP
PWP
2000
2000
50
Green (RoHS
& no Sb/Br)
TPS54615
TPS54615
TPS54616
TPS54616
TPS54616
TPS54616
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS54616PWPG4
TPS54616PWPR
TPS54616PWPRG4
50
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54611, TPS54612, TPS54613, TPS54614, TPS54615, TPS54616 :
Automotive: TPS54612-Q1, TPS54613-Q1, TPS54614-Q1, TPS54615-Q1, TPS54616-Q1
•
Enhanced Product: TPS54611-EP, TPS54612-EP, TPS54613-EP, TPS54614-EP, TPS54615-EP, TPS54616-EP
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54611PWPR
TPS54612PWPR
TPS54613PWPR
TPS54614PWPR
TPS54615PWPR
TPS54616PWPR
HTSSOP PWP
HTSSOP PWP
HTSSOP PWP
HTSSOP PWP
HTSSOP PWP
HTSSOP PWP
28
28
28
28
28
28
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.9
6.9
6.9
6.9
6.9
6.9
10.2
10.2
10.2
10.2
10.2
10.2
1.8
1.8
1.8
1.8
1.8
1.8
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54611PWPR
TPS54612PWPR
TPS54613PWPR
TPS54614PWPR
TPS54615PWPR
TPS54616PWPR
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
PWP
PWP
28
28
28
28
28
28
2000
2000
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
38.0
Pack Materials-Page 2
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