TPS54617RUVR [TI]
3-V TO 6-V INPUT, 6-A, SMALL SYNCHRONOUS-BUCK SWITCHER WITH INTEGRATED FETs (SWIFT™); 3 V至6 V的输入, 6 -A ,具有集成FET小同步降压开关( SWIFT ™ )型号: | TPS54617RUVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 3-V TO 6-V INPUT, 6-A, SMALL SYNCHRONOUS-BUCK SWITCHER WITH INTEGRATED FETs (SWIFT™) |
文件: | 总18页 (文件大小:585K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Typical Size
3,5 mm x 7 mm
TPS54617
www.ti.com ........................................................................................................................................................................................... SLVS880–NOVEMBER 2008
3-V TO 6-V INPUT, 6-A, SMALL SYNCHRONOUS-BUCK
SWITCHER WITH INTEGRATED FETs (SWIFT™)
1
FEATURES
DESCRIPTION
23
•
30-mΩ MOSFET Switches for High Efficiency
at 6-A Continuous Output
As a member of the SWIFT™ family of dc/dc
regulators, the TPS54617 low-input voltage
high-output current synchronous buck PWM
converter offers the same features as the TPS54610
in a small package and higher switching frequency.
Included on the substrate with the listed features are
a true, high performance, voltage error amplifier that
enables maximum performance under transient
conditions and flexibility in choosing the output filter L
and C components; an undervoltage-lockout circuit to
prevent start-up until the input voltage reaches 3 V;
an internally and externally set slow-start circuit to
limit in-rush currents; and a power good output useful
for processor/logic reset, fault signaling, and supply
sequencing.
•
Adjustable Output Voltage Down to 0.9 V With
1% Accuracy
•
•
Externally Compensated for Design Flexibility
Wide PWM Frequency: Fixed 350 kHz, 550 kHz,
or Adjustable 280 kHz to 1.6 MHz
•
•
Synchronizable to 1.6MHz
Load Protected by Peak Current Limit and
Thermal Shutdown
•
•
Small 3.5mm x 7mm Package and Similar
Layout to TPS54610 Reduces Board Area and
Total Cost
SWIFT Documentation Application Notes, and
SwitcherPro™ Software: www.ti.com/swift
The TPS54617 is available in a thermally enhanced
34 pin QFN (RUV) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SwitcherPro™ design software tool
to aid in achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
APPLICATIONS
•
•
•
Low-Voltage, High-Density Systems With
Power Distributed at 3.3 V or 5 V
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs, and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
EFFICIENCY vs OUTPUT CURRENT
95
TPS54617
89
83
77
71
65
59
53
47
41
VIN
PH
Input
Output
SS/ENA
PWRGD
RT
BOOT
PGND
VI = 3 V
VI = 3.3 V
VI = 5 V
VI = 6 V
COMP
SYNC
VBIAS
VSENSE
AGND
f
= 1600 kHz
s
VO = 1.8 V
Compensation
Network
35
0
0.5 1 1.5
2
2.5 3 3.5 4 4.5 5 5.5
6
6.5
I
− Output Current − A
O
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SwitcherPro, SWIFT, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS54617
SLVS880–NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TJ
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
–40°C to 125°C
Adjustable down to 0.9 V
QFN (RUV)(2)
TPS54617RUV
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The RUV package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54617RUVR). See the application
section of this data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
SS/ENA, SYNC
–0.3 V to 7 V
–0.3 V to 6 V
–0.3 V to 4 V
–0.3 V to 7 V
–0.3 V to 17 V
–0.6 V to 7 V
–0.6 V to 10 V
-2.0 V
RT
VI
Input voltage range
VSENSE
VIN
BOOT
VBIAS, PWRGD, COMP
VO
Output voltage range
Source current
PH
PH (transient < 10 nsec)
PH
Internally Limited
6 mA
IO
COMP, VBIAS
PH
12 A
IS
Sink current
COMP
6 mA
SS/ENA, PWRGD
AGND to PGND
10 mA
Voltage differential
±0.3 V
TJ
Operating virtual junction temperature range
Storage temperature
–40°C to 125°C
–65°C to 150°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX
6
UNIT
V
VI
Input voltage range
TJ
Operating junction temperature
–40
125
°C
2
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(1)
PACKAGE DISSIPATION RATINGS
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
JUNCTION-TO-CASE
PACKAGE
34-Pin RUV with solder
14.5°C/W
0.5 °C/W(2)
(1) Test board conditions:
a. 3 inch × 3 inch, 4 layers, Thickness: 0.062 inch
b. 2.0 oz copper traces located on the top of the PCB
c. 2.0 oz copper ground plane on the bottom of the PCB
d. 2.0 oz copper ground planes on the 2 internal layers
e. 12 thermal vias
(2) Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN input voltage range
3
6
15.8
23.5
1.4
V
fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open
fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open
Shutdown, SS/ENA = 0 V
9.2
13.9
1
Quiescent current
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.95
2.80
0.16
2.5
3.0
V
2.70
2.70
V
Rising and falling edge deglitch,
UVLO(1)
µs
BIAS VOLTAGE
Output voltage, VBIAS
VO
I(VBIAS) = 0
2.80
2.90
100
V
Output current, VBIAS(2)
µA
CUMULATIVE REFERENCE
Vref
Accuracy
0.882 0.891 0.900
V
REGULATION
IL = 3 A, fs = 350 kHz, TJ = 85°C
0.04
0.04
0.03
0.03
Line regulation(1)
Load regulation(1)
OSCILLATOR
%/V
%/A
IL = 3 A, fs = 550 kHz, TJ = 85°C
IL = 0 A to 6 A, fs = 350 kHz, TJ = 85°C
IL = 0 A to 6 A, fs = 550 kHz, TJ = 85°C
SYNC ≤ 0.8 V, RT open
280
440
460
1480
2.5
350
550
420
660
Internally set free-running frequency
range
kHz
kHz
SYNC ≥ 2.5 V, RT open
RT = 100 kΩ (1% resistor to AGND)
RT = 27 kΩ (1% resistor to AGND)
500
540
Externally set free-running frequency
range
1600
1720
High-level threshold voltage, SYNC
Low-level threshold voltage, SYNC
Pulse duration, SYNC(1)
V
V
0.8
50
Frequency range, SYNC
Ramp valley(1)
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time
Maximum duty cycle
330
1600
kHz
V
0.75
1
V
160
ns
90%
(1) Specified by design
(2) Static resistive loads only
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
ERROR AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND(3)
90
3
110
5
dB
Parallel 10 kΩ, 160 pF COMP to AGND(3)
Powered by internal LDO(3)
VSENSE = Vref
MHz
Error amplifier common-mode input
voltage range
0
VBIAS
250
V
IIB
Input bias current, VSENSE
60
nA
Output voltage slew rate (symmetric),
COMP(3)
1
1.4
V/µs
VO
PWM COMPARATOR
PWM comparator propagation delay
time, PWM comparator input to PH pin
(excluding dead time)
10 mV overdrive(3)
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA(1)
Falling edge deglitch, SS/ENA(1)
Internal slow-start time
0.82
1.20
0.03
2.5
3.35
5
1.40
V
V
µs
ms
µA
mA
2.6
3
4.1
8
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
1.5
2.3
4
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage(1)
Power good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
VSENSE falling
90
3
%Vref
%Vref
µs
35
I(sink) = 2.5 mA
VI = 5.5 V
0.18
0.3
1
V
µA
CURRENT LIMIT
VI = 3 V(1), Output shorted
VI = 6 V(1), Output shorted
7.2
10
10
12
Current limit trip point
A
Current limit leading edge blanking
time(3)
100
ns
Current limit total response time(3)
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown hysteresis(1)
135
150
10
165
°C
°C
OUTPUT POWER MOSFETS
VI = 3 V
26
36
47
65
rDS(on) Power MOSFET switches
(3) Specified by design
mΩ
VI = 3.6 V
4
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TPS54617
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PIN ASSIGNMENTS
RUV PACKAGE
(Top VIEW)
34 33 32 31 30
29
1
2
3
4
5
6
RT
AGND
VSENSE
COMP
PWRGD
BOOT
28
SYNC
27
26
25
24
SS/ENA
VBIAS
VIN
THERMAL
PAD
VIN
PH
23
22
21
20
19
18
7
VIN
PH
PH
PH
PH
PH
PH
8
VIN
9
VIN
10
11
PGND
PGND
PGND
12
13 14 15 16 17
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Connect PowerPAD to AGND.
AGND
1
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
BOOT
COMP
5
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single
point connection to AGND is recommended.
13–20
30–34
PGND
PH
6–12
4
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
PWRGD
RT
29
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SS/ENA
27
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
SYNC
VBIAS
28
26
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high-quality, low-ESR 10-µF ceramic capacitor.
VIN
21–25
2
VSENSE
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
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INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
REG
VBIAS
Falling
Edge
SHUTDOWN
VIN
ILIM
Comparator
1.2 V
Hysteresis: 0.03 V
3 − 4 V
Deglitch
Thermal
Shutdown
150oC
Leading
Edge
2.5 ms
Blanking
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.95 V
Deglitch
Hysteresis: 0.16 V
15 mW
2.5 ms
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-start
+
−
C
Adaptive Dead-Time
R
S
Q
O
(Internal Slow-start Time = 3.35 ms
and
Error
Control Logic
PWM
Amplifier
Reference
Comparator
VIN
V
= 0.891 V
ref
15 mW
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
0.90 V
Falling
Edge
ref
Deglitch
TPS54917
Hysteresis: 0.03 V
ref
SHUTDOWN
35 ms
SYNC
VSENSE
COMP
RT
RELATED DC/DC PRODUCTS
•
•
•
•
TPS40000 – dc/dc controller
TPS56300 – dc/dc controller
TPS54610 - SWIFT 6A converter
TPS54917 and TPS54910 - SWIFT 9A converters
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TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
45
750
650
550
40
VI = 3 V
IO = 500 mA
V
= 3.6 V
I
40
35
30
35
30
25
I
= 500 mA
O
SYNC ≥ 2.5 V
SYNC ≤ 0.8 V
HRds
450
350
250
LRds
25
20
20
15
−40
0
25
85
125
−40
0
25
85
125
−40
0
25
85
125
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
JUNCTION TEMPERATURE
LOAD CURRENT
5
4.5
4
1800
1600
1400
1200
1000
800
0.895
V
= 3.3 V
= 125oC
I
T
RT = 27 kΩ
0.893
0.891
0.889
j
3.5
3
2.5
2
1.5
1
0.887
0.885
RT = 100 kΩ
600
0.5
0
400
7
1
2
5
4
6
0
3
−40
0
25
85
125
−40
0
25
85
125
I
- Load Current - A
L
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 4.
Figure 5.
Figure 6.
ERROR AMPLIFIER
vs
OPEN LOOP RESPONSE
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE REGULATION
INPUT VOLTAGE
0.895
0.893
0.891
0.889
0
140
3.80
3.65
3.50
3.35
3.20
3.05
2.90
2.75
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
−20
−40
−60
−80
120
100
80
L
A
Phase
Gain
−100
−120
−140
−160
−180
−200
60
40
20
0.887
0.885
0
−20
1
10 100 1 k 10 k 100 k 1 M 10 M
3
3.1
3.2
3.3
3.4
3.5
3.6
−40
0
25
85
125
f − Frequency − Hz
V − Input Voltage − V
I
TJ − Junction Temperature − °C
Figure 7.
Figure 8.
Figure 9.
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APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54617 application. The TPS54617 (U1) can provide up
to 6A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed
thermal PowerPAD underneath the integrated circuit, TPS54617, package must be soldered to the printed-circuit
board.
U1
TPS5461RUV
L1
0.82 mH
TP4
VOUT = 1.8 V, 6 A MAX
VIN = 3 - 6 V
C3
100 mF
C11
0.01 mF
C4
100 mF
C6
0.047 mF
C12
0.01 mF
C1
22 mF
C2
22 mF
R4
10.0 kW
C5 1200 pF
R6
4.99 kW
R7 590 W
C10
150 pF
C9
0.01 mF
C8
0.047 mF
C7
2700 pF
R5
27.4 kW
R1 10.0 kW
R8
10.0 kW
R2
10.0 kW
Analog and power grounds are ties at the pad under the package of the IC
Figure 10. Application Circuit
COMPONENT SELECTION
INPUT FILTER
The values for the components used in this design
example were selected for best load transient
response and small PCB area. Additional design
information is available at www.ti.com.
The input voltage is a nominal 3.3 or 5 VDC. The
input filter capacitors (C1 and C2) are 10-µF ceramic
capacitors (MuRata). C12 is a 0.01-µF ceramic
capacitor that provides high-frequency decoupling of
the TPS54617 from the input supply. C1, C2 and C12
must be located as close as possible to the device.
Input ripple current is shared among C1, C2 and C12.
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FEEDBACK CIRCUIT
cause problems with some of the control and bias
signals. For these reasons, separate analog and
power ground traces are recommended. There
should be an area of ground on the top layer directly
under the IC, with an exposed area for connection to
the PowerPAD. Use vias to connect this ground area
to any internal ground planes. Use additional vias at
the ground side of the input and output filter
capacitors as well. The AGND and PGND pins should
be tied to the PCB ground by connecting them to the
ground area under the device as shown. Use a
separate wide traces for the analog ground signal
path. This analog ground should be used for the
voltage set point divider, timing resistor RT, slow start
capacitor, and bias capacitor grounds. Connect this
trace the topside groud area near AGND (Pin 1).
The values for these components are selected to
provide fast transient response times.
The resistor divider network of R1 and R2 sets the
output voltage for the circuit at 1.8 V. R1 along with
R6, R7, C5, C7, and C10 forms the loop
compensation network for the circuit. For this design,
a Type-3 topology is used. The feedback loop is
compensated so that the closed loop crossover
frequency is approximately 45 kHz at 5 V input.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a
27.4-kΩ resistor to select the operating frequency of
1.6 MHz. To set a different frequency, place a 27-kΩ
to 180-kΩ resistor between RT (pin 29) and analog
ground or leave RT floating to select the default of
350 kHz. The switching frequency in MHz can be
approximated using the following equation:
The PH pins should be tied together and routed to
the output inductor. Since the PH connection is the
switching node, the inductor should be located very
close to the PH pins and the area of the PCB
conductor minimized to prevent excessive capacitive
coupling.
51000
FSW
=
R + 4400
T
(
)
(1)
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace
lengths.
OUTPUT FILTER
The output filter is composed of a 0.82-µH inductor
and 2 × 100-µF capacitors. The inductor is a Vishay
IHLM-2525CZ-01 type. The capacitors used are
100-µF, 6.3-V ceramic types with X5R dielectric.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important to
keep the loop formed by the PH pins, Lout, Cout and
PGND as small as practical.
PCB LAYOUT
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pinout, the
components will have to be routed somewhat close,
but maintain as much separation as possible while
still keeping the layout compact.
Figure 11 shows a generalized PCB layout guide for
the TPS54617. The VIN pins should be connected
together on the printed circuit board (PCB) and
bypassed with a low ESR ceramic bypass capacitor.
Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN
pins, and the TPS54617 ground pins. The minimum
recommended bypass capacitance is 10 µF ceramic
with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the PGND
pins.
Connect the bias capacitor from the VBIAS pin to
analog ground using the isolated analog ground
trace. If a slow-start capacitor or RT resistor is used,
or if the SYNC pin is used to select 350 kHz
operating frequency, connect them to this trace as
well.
The TPS54617 has two internal grounds (analog and
power). The analog ground ties to all of the
noise-sensitive signals, while the power ground ties to
the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54617, particularly at higher output currents.
Ground noise on an analog ground plane can also
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VOUT
TOPSIDE
GROUND
OUTPUT
AREA
FILTER
CAPACITOR
OUTPUT
INDUCTOR
PGND
PGND
PGND
VIN
PH
PH
EXPOSED
POWERPAD
AREA
PH
PH
PH
BOOT
CAPACITOR
PH
VIN
Vin
PH
VIN
VIN
INPUT
BULK
FILTER
PH
INPUT
BYPASS
CAPACITOR
VIN
BOOT
PWRGD
COMP
VSENSE
VBIAS
SS/ENA
SYNC
RT
COMPENSATION
NETWORK
BIAS CAPACITOR
AGND
SLOW START
CAPACITOR
FREQUENCY SET RESISTOR
ANALOG GROUND TRACE
ANALOG GROUND TRACE
VIA to Ground Plane
Figure 11. TPS54617 PCB Layout
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 11 is 0.55 in2. This area
does not include test points or connectors.
heat, and any area available must be used when 6 A
or greater operation is desired. Connection from the
exposed area of the PowerPAD to the analog ground
plane layer must be made using 0.013-inch diameter
vias to avoid solder wicking through the vias.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
The RUV package has been chosen to enable a
thermal management scheme, allowing a ground
plane to extend beyond both ends of the package.
12 vias must be in the PowerPAD area located under
the device package. Additional vias beyond the
twelve recommended may be added in the ground
area outside the package footprint to enhance
thermal performance. The size of the vias outside of
the package, not in the exposed thermal pad area,
can be increased to 0.018.
For operation at full rated load current, the analog
ground plane must provide an adequate heat
dissipating area. A 3-inch by 3-inch plane of 1 ounce
copper is recommended, though not mandatory,
depending on ambient temperature and airflow. Most
applications have larger areas of internal ground
plane available, and the PowerPAD must be
connected to the largest area available. Additional
areas on the top or bottom layers also help dissipate
10
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PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
LINE REGULATION
vs
INPUT VOLTAGE
0.4
0.35
0.3
95
89
0.3
0.25
0.2
f
= 1600 kHz
= 25oC
s
T
0.25
0.2
A
83
77
71
65
59
53
47
41
V
I
= 3.3 V
V
= 1.8 V
O
0.15
0.1
V
= 3 V
0.15
0.1
I
VI = 3 V
I
= 0 A
0.05
0.05
0
O
VI = 3.3 V
VI = 5 V
0
-0.05
-0.1
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
VI = 6 V
-0.15
-0.2
V
= 5 V
I
V
= 6 V
I
I
= 3 A
O
f
s
= 1600 kHz
= 25oC
f
= 1600 kHz
s
-0.25
-0.3
T
V
VO = 1.8 V
A
= 1.8 V
I
= 6 A
-0.35
-0.4
O
O
35
0
1
2
3
4
5
6
0
0.5 1 1.5
2
2.5 3 3.5 4 4.5 5 5.5
6
6.5
3
3.5
4
4.5
5
5.5
6
I
− Output Current − A
I
− Output Current − A
O
O
V − Input Voltage − V
I
Figure 12.
Figure 13.
Figure 14.
AMBIENT TEMPERATURE
vs
LOAD CURRENT(1)
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
125
100
VI = 5 V
VO = 1.8 V
VI = 5 V
f
= 1600 kHz
= 6 A
s
VO = 1.8 V
V
O
75
50
25
T
V
V
= 125°C
j
= 3.3 V
= 1.8 V
I
O
f
= 1600 kHz
s
0
1
2
3
4
5
6
7
8
t − Time − 1 ms/div
t − Time − 5 ms/div
I
− Output Current − A
O
Figure 15.
Figure 16.
Figure 17.
SLOW-START TIMING
INPUT RIPPLE VOLTAGE
CLOSED LOOP RESPONSE
180 deg
60 dB
150 deg
120 deg
90 deg
60 deg
30 deg
VI = 5 V
VO = 1.8 V
50 dB
40 dB
30 dB
20 dB
10 dB
1-Phase
1-Gain
f
= 1600 kHz
= 6 A
VI = 5 V
0.047 mF
Slow-Start Capacitor
s
V
VO = 1.8 V
O
0
deg
0
dB
-30 deg
-60 deg
-90 deg
-120 deg
-150 deg
-180 deg
-10 dB
-20 dB
-30 dB
-40 dB
-50 dB
-60 dB
100 Hz
1 kHz
10 kHz
100 kHz
1M
t − Time − 1 ms/div
t − Time − 5 ms/div
Frequency
Figure 18.
Figure 19.
Figure 20.
(1)Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this
data sheet.
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VBIAS Regulator (VBIAS)
DETAILED DESCRIPTION
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
high quality, low-ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R or X5R grade
dielectrics are recommended because their values
are more stable over temperature. The bypass
capacitor must be placed close to the VBIAS pin and
returned to AGND.
Under Voltage Lock Out (UVLO)
The TPS54617 incorporates an under voltage lockout
circuit to keep the device disabled when the input
voltage (VIN) is insufficient. During power up, internal
circuits are held inactive until VIN exceeds the
nominal UVLO threshold voltage of 2.95 V. Once the
UVLO start threshold is reached, device start-up
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
the UVLO comparator, and a 2.5-µs rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
VBIAS of 2.70 V, and external loads on VBIAS with
ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
exceeds the start threshold voltage of approximately
1.2 V. When SS/ENA exceeds the enable threshold,
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5-µs falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
Voltage Reference
The voltage reference system produces a precise
Vref signal by scaling the output of a temperature
stable bandgap circuit. During manufacture, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure adds to the high precision regulation of the
TPS54617, since it cancels offset errors in the scale
and error amplifier circuits.
Oscillator and PWM Ramp
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
and AGND.
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as
a static digital input. If a different frequency of
operation is required for the application, the oscillator
frequency can be externally adjusted from 280 to
1600 kHz by connecting a resistor between the RT
pin to ground and floating the SYNC pin. The
switching frequency in MHz is approximated by the
following equation, where R is the resistance in Ohms
from RT to AGND:
Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of
the SS/ENA pin and start-up of the output. The delay
is proportional to the slow-start capacitor value and
lasts until the SS/ENA pin reaches the enable
threshold. The start-up delay is approximately:
1.2 V
t + C
51000
d
(SS)
5 mA
FSW
=
(2)
R + 4400
T
(
)
(4)
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be
observed before the externally set slow-start rate
External synchronization of the PWM ramp is
possible over the frequency range of 330 kHz to 1600
kHz by driving a synchronization signal into SYNC
and connecting a resistor from RT to AGND. Choose
a RT resistor that sets the free running frequency to
takes control and the output rises at
a rate
proportional to the slow-start capacitor. The slow-start
time set by the capacitor is approximately:
80% of the synchronization signal. Table
summarizes the frequency selection configurations:
1
0.7 V
t
+ C
(SS)
(SS)
5 mA
(3)
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
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Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
350 kHz, internally set
SYNC PIN
Float or AGND
RT PIN
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 1.6MHz
Externally synchronized frequency
Float
R = 27 k to 180 k
Synchronization signal
R = RT value for 80% of external synchronization frequency
low-side FET remains on until the VSENSE voltage
Error Amplifier
decreases to
a
range that allows the PWM
comparator to change states. The TPS54617 is
capable of sinking current continuously until the
output reaches the regulation set-point.
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54617 apart from most dc/dc
converters. The user is given the flexibility to use a
wide range of output L and C filter components to suit
the particular application needs. Type-2 or Type-3
compensation can be employed using external
compensation components.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
turns off and low-side FET turns on to decrease the
energy in the output inductor and consequently the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time
and control-logic block. During steady-state operation
below the current limit threshold, the PWM
comparator output and oscillator pulse train
alternately reset and set the PWM latch. Once the
PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width.
During this period, the PWM ramp discharges rapidly
to its valley voltage. When the ramp begins to charge
back up, the low-side FET turns off and high-side
FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator
resets the latch, thus turning off the high-side FET
and turning on the low-side FET. The low-side FET
remains on until the next oscillator pulse discharges
the PWM ramp.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs during the switching transitions by actively
controlling the turnon times of the MOSFET drivers.
The high-side driver does not turn on until the voltage
at the gate of the low-side FET is below 2 V. While
the low-side driver does not turn on until the voltage
at the gate of the high-side MOSFET is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to drive the power
MOSFETs gates. The low-side driver is supplied from
VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency
and reduces external component count.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset, and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
low-side FET on. The device operates at its
maximum duty cycle until the output voltage rises to
the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually
reset and the high-side FET does not turn on. The
Overcurrent Protection
The cycle-by-cycle current limiting is achieved by
sensing the current flowing through the high-side
MOSFET and comparing this signal to a preset
overcurrent threshold. The high side MOSFET is
turned off within 200 ns of reaching the current limit
threshold. A 100-ns leading edge blanking circuit
prevents current limit false tripping. Current limit
detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
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Thermal Shutdown
Power Good (PWRGD)
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown automatically when the
junction temperature decreases to 10°C below the
thermal shutdown trip point, and starts up under
control of the slow-start circuit.
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold or SS/ENA
is low. When VIN ≥ UVLO threshold, SS/ENA ≥
enable threshold, and VSENSE > 90% of Vref, the
open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35 µs
falling edge deglitch circuit prevent tripping of the
power good comparator due to high frequency noise.
Thermal shutdown provides protection when an
overload condition is sustained for several
milliseconds. With a persistent fault condition, the
device cycles continuously; starting up by control of
the soft-start circuit, heating up due to the fault
condition, and then shutting down upon reaching the
thermal shutdown trip point. This sequence repeats
until the fault condition is removed.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2008
PACKAGING INFORMATION
Orderable Device
TPS54617RUVR
TPS54617RUVT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RUV
34
3000 Green (RoHS &
no Sb/Br)
Cu NiPdAu
Level-3-260C-168 HR
VQFN
RUV
34
250 Green (RoHS &
no Sb/Br)
Cu NiPdAu
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS54617RUVR
TPS54617RUVT
VQFN
VQFN
RUV
RUV
34
34
3000
250
330.0
180.0
16.4
16.4
3.85
3.85
7.35
7.35
1.2
1.2
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Nov-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54617RUVR
TPS54617RUVT
VQFN
VQFN
RUV
RUV
34
34
3000
250
346.0
190.5
346.0
212.7
33.0
31.8
Pack Materials-Page 2
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