TPS54618C-Q1 [TI]
汽车 2.95V 至 6V、6A、2MHz 同步降压转换器;
| 型号： | TPS54618C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车 2.95V 至 6V、6A、2MHz 同步降压转换器 转换器 |
| 文件： | 总41页 (文件大小：2505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54618C-Q1
ZHCSLU7A –SEPTEMBER 2020 –REVISED AUGUST 2021
TPS54618C-Q1 汽车类2.95V 至6V、6A 同步降压转换器
TPS54618C-Q1 借助以下功能实现了小尺寸设计：集
成 MOSFET；实现可减少外部组件数量的电流模式控
制；通过启用高达 2MHz 的开关频率来减小电感器尺
寸；借助小型 3mm × 3mm 热增强型 WQFN 封装尽量
减小IC 封装尺寸。
1 特性
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：-40°C 至+125°C，TA
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 两个可在6A 负载下获得高效率的12mΩ（典型
值）MOSFET
TPS54618C-Q1 可在工作温度范围内为各种负载提供
具有±1% 精确电压基准(VREF) 的准确调节。
通过集成12mΩ MOSFET 和典型值
• 300kHz 至2MHz 开关频率
为515μA 的电源电流，有效提升效率。通过使用使能
引脚进入关断模式，关断电流被减少至5.5µA。
• 在工作温度范围（-40°C 至+150°C）内
具有0.8V ±1% 电压基准
• 与外部时钟同步
欠压闭锁被内部设定在 2.6V 上，但是可通过一个使能
引脚上的电阻器网络来编辑阈值，以增加此电压值。输
出电压启动斜坡由慢启动引脚控制。一个开漏电源正常
信号表示输出处于其标称电压值的 93% 至 107% 之
内。
• 可调缓启动和排序
• 欠压(UV) 和过压(OV) 电源正常输出
• 推出的新产品：TPS62816-Q1 采用具有可湿性侧
面的2mm x 3mm QFN 封装的6V 降压转换器
• 热增强型3mm × 3mm、16 引脚WQFN 封装
频率折返和热关断功能可在过流情况下保护器件。
2 应用
器件信息
• 汽车音响主机
• 汽车仪表组
• 汽车ADAS 摄像头
器件型号(1)
封装尺寸（标称值）
封装
WQFN (16)
TPS54618C-Q1
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
TPS54618C-Q1 器件是一款具有两个集成 MOSFET
的全功能6V、6A、同步降压电流模式转换器。
VIN
100
C
BOOT
3 Vin
VIN
95
BOOT
C
5 Vin
I
R
R
4
5
90
TPS54618C-Q1
EN
L
O
VOUT
PH
85
C
O
80
75
R
1
2
PWRGD
VSENSE
70
65
60
R
SS/TR
RT /CLK
COMP
GND
f
= 500kHz
AGND
s
55
50
C
POWERPAD
ss
Vout = 1.8V
R
R
T
3
0
1
2
3
4
5
6
I
- Output Current - A
O
C
1
效率与输出电流间的关系
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEW2
TPS54618C-Q1
ZHCSLU7A –SEPTEMBER 2020 –REVISED AUGUST 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................24
8.1 Application Information............................................. 24
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................32
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Example...................................................... 34
10.3 Power Dissipation Estimate.................................... 34
11 Device and Documentation Support..........................36
11.1 Device Support........................................................36
11.2 接收文档更新通知................................................... 36
11.3 支持资源..................................................................36
11.4 Trademarks............................................................. 36
11.5 静电放电警告...........................................................36
11.6 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
Information.................................................................... 36
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2020) to Revision A (August 2021)
Page
• 添加了TPS62816-Q1 促销要点..........................................................................................................................1
• Changed "Start with 100 kΩfor the R1 resistor and use equation 1..." to "Pick a suitable value for R1 and
use equation 1..."..............................................................................................................................................14
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5 Pin Configuration and Functions
16
15
14
13
VIN
VIN
1
PH
PH
12
11
10
9
2
3
4
Thermal
Pad
GND
GND
PH
SS/TR
5
6
7
8
图5-1. 16-Pin WQFN With Exposed Thermal Pad RTE Package (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AGND
5
G
I
Analog ground must be electrically connected to GND close to the device.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
BOOT
COMP
EN
13
7
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
O
I
Enable pin and internal pullup current source. Pull below 1.2 V to disable. Float to enable. Can be used
to set the on/off threshold (adjust UVLO) with two additional resistors.
15
3
GND
PH
G
O
Power ground. This pin must be electrically connected directly to the power pad under the device.
4
10
11
12
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
An open-drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
overvoltage and undervoltage, or EN shutdown.
PWRGD
RT/CLK
SS/TR
14
8
O
I/O
I/O
Resistor timing or external clock input pin
Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time.
This pin can also be used for tracking.
9
1
2
VIN
I
Input supply voltage: 2.95 V to 6 V
16
6
VSENSE
I
Inverting node of the transconductance (gm) error amplifier
Thermal
Pad
GND pin must be connected to the exposed power pad for proper operation. This power pad must be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
G
—
(1) I = Input, O = Output, G = Ground
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AGND
5
G
Analog ground must be electrically connected to GND close to the device.
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PIN
TYPE(1)
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
BOOT
13
I
O
I
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
COMP
EN
7
Enable pin and internal pullup current source. Pull below 1.2 V to disable. Float to enable. Can be used
to set the on/off threshold (adjust UVLO) with two additional resistors.
15
3
GND
PH
G
O
Power ground. This pin must be electrically connected directly to the power pad under the device.
4
10
11
12
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
An open-drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
overvoltage and undervoltage, or EN shutdown.
PWRGD
RT/CLK
SS/TR
14
8
O
I/O
I/O
Resistor timing or external clock input pin
Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time.
This pin can also be used for tracking.
9
1
2
VIN
I
Input supply voltage: 2.95 V to 6 V
16
6
VSENSE
I
Inverting node of the transconductance (gm) error amplifier
Thermal
Pad
GND pin must be connected to the exposed power pad for proper operation. This power pad must be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
G
—
(1) I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
7
UNIT
PWRGD, VIN
EN, RT/CLK
Input voltage
4
V
COMP, SS, VSENSE
3
BOOT
VPH+ 7
7
BOOT-PH
PH
7
Output voltage
–0.6
–2
V
PH (10-ns transient)
EN, RT/CLK
COMP, SS
PWRGD
10
Source current
Sink current
100
100
10
µA
µA
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
–40
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level XX
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level XX
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
V
VVIN
TA
Input voltage
6
Operating ambient temperature
125
°C
–40
6.4 Thermal Information
TPS54618C-Q1
RTE (WQFN)
16 PINS
44.38
THERMAL METRIC(2) (1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.09
Junction-to-board thermal resistance
15.96
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.69
ψJT
15.91
ψJB
RθJC(bot)
4.55
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
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6.5 Electrical Characteristics
at TJ = –40°C to +125°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.95
6
2.5
2.6
15
V
V
VIN UVLO STOP
VIN UVLO START
2.28
2.45
5.5
Internal undervoltage lockout
threshold
Shutdown supply current
Quiescent current, IQ
EN = 0 V, 25°C, 2.95 V ≤VIN ≤6 V
μA
μA
515
650
VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ
ENABLE AND UVLO (EN PIN)
Rising
1.25
1.18
Enable threshold
Input current
V
Falling
Enable threshold + 50 mV
–3.5
–1.9
μA
Enable threshold –50 mV
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
0.791
0.799
0.807
V
2.95 V ≤VIN ≤6 V, –40°C <TJ < 150°C
MOSFET
BOOT-PH = 5 V
BOOT-PH = 2.95 V
VIN = 5 V
12
16
13
17
25
33
25
33
High-side switch resistance
Low-side switch resistance
mΩ
mΩ
VIN = 2.95 V
ERROR AMPLIFIER
Input current
2
nA
Error amplifier transconductance
(gm)
245
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
μmhos
Error amplifier transconductance
(gm)
during slow start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
VSENSE = 0.4 V
79
μmhos
Error amplifier source/sink
COMP to Iswitch gm
V(COMP) = 1 V, 100-mV overdrive
±20
25
μA
A/V
CURRENT LIMIT
VIN = 6 V, 25°C < TJ < 150°C
7.46
7.68
10.6
10.2
15.3
13.5
Current limit threshold
A
VIN = 2.95 V, 25°C < TJ < 150°C
THERMAL SHUTDOWN
Thermal shutdown
Hysteresis
168
20
°C
°C
BOOT (BOOT PIN)
BOOT charge resistance
BOOT-PH UVLO
VIN = 5 V
16
Ω
VIN= 2.95 V
2.1
V
SLOW-START AND TRACKING (SS/TR PIN)
Charge current
V(SS/TR) = 0.4 V
2
54
μA
mV
V
SS/TR to VSENSE matching
SS/TR to reference crossover
V(SS/TR) = 0.4 V
98% normal
1.1
61
SS/TR discharge voltage (overload) VSENSE = 0 V
mV
µA
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V
350
SS discharge current (UVLO, EN,
VIN = 5 V, V(SS) = 0.5 V
Thermal fault)
1.9
mA
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at TJ = –40°C to +125°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault)
91%
93%
109%
107%
2%
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling (Good)
VSENSE falling
VSENSE threshold
Vre
Hysteresis
Vref
nA
Output high leakage
ON-resistance
VSENSE = VREF, V(PWRGD) = 5.5 V
7
56
100
0.3
1.5
Ω
Output low
I(PWRGD) = 3 mA
0.2
V
Minimum VIN for valid output
0.65
V
V(PWRGD) < 0.5 V at 100 μA
6.6 Timing Requirements
MIN NOM MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
200
400
300
75
2000
600
kHz
kHz
kHz
ns
Switching frequency
500
Rt = 400 kΩ
Switching frequency range using CLK mode
Minimum CLK pulse width
RT/CLK voltage
2000
0.5
1.6
0.6
90
V
R(RT/CLK) = 400 kΩ
RT/CLK high threshold
RT/CLK low threshold
2.2
V
0.4
V
RT/CLK falling edge to PH rising edge delay
PLL lock in time
Measure at 500 kHz with RT resistor in series
Measure at 500 kHz
ns
42
μs
PH (PH PIN)
Measured at 50% points on PH, IOUT = 3 A
75
Minimum ON-time
ns
Measured at 50% points on PH, VIN = 6 V,
IOUT = 0 A
120
Prior to skipping off pulses, BOOT-PH = 2.95 V,
IOUT = 3 A
Minimum OFF-time
60
ns
Rise time
Fall time
VIN = 6 V, 6 A
VIN = 6 V, 6 A
2.25
2
V/ns
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6.7 Typical Characteristics
0.025
0.023
525
520
RT = 400 kW,
Vin = 5 V
High Side Rdson Vin = 3.3 V
515
510
505
500
495
490
485
0.021
0.019
0.017
0.015
0.013
0.011
0.009
0.007
0.005
Low Side Rdson Vin = 3.3 V
High Side Rdson Vin = 5 V
Low Side Rdson Vin = 5 V
480
475
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
图6-2. Switching Frequency vs Junction
图6-1. High-Side and Low-Side ON-Resistance
Temperature
vs Junction Temperature
12
0.807
Vin = 3.3 V
Vin = 6 V
11.5
0.805
0.803
0.801
0.799
0.797
0.795
0.793
0.791
11
10.5
Vin = 2.95 V
10
9.5
9
8.5
8
25
75
- Junction Temperature - °C
50
100
125
150
-50
-25
0
25
50
75
100
125
150
T
T
- Junction Temperature - °C
J
J
图6-3. High-Side Current Limit vs Junction
图6-4. Voltage Reference vs Junction Temperature
Temperature
100
2000
1800
1600
1400
1200
1000
800
Vsense Falling
75
Vsense Rising
50
600
25
0
400
200
100 200 300 400 500 600 700 800
Resistance (kΩ)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
G000
Vsense - V
图6-5. Switching Frequency vs RT Resistance
图6-6. Switching Frequency vs Vsense
Low Frequency Range
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105
100
95
310
Vin = 3.3 V
Vin = 3.3 V
290
270
250
230
210
90
85
80
75
70
65
190
170
60
55
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
T - Junction Temperature - °C
J
50
75
100
125
150
T
- Junction Temperature - °C
J
图6-7. Transconductance vs Junction Temperature
图6-8. Transconductance (Soft-Start)
vs Junction Temperature
-3
1.3
1.29
1.28
Vin = 5 V,
Ven = Threshold +50 mV
-3.1
Vin = 3.3 V, rising
1.27
-3.2
-3.3
-3.4
-3.5
-3.6
-3.7
-3.8
1.26
1.25
1.24
1.23
1.22
1.21
1.2
Vin = 3.3 V, falling
1.19
1.18
1.17
-3.9
-4
1.16
1.15
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
图6-10. EN Pin Current vs Junction Temperature
图6-9. Enable Pin Voltage vs Junction
Temperature
-1
-1.4
Vin = 5 V
Vin = 5 V,
Ven = Threshold -50 mV
-1.2
-1.4
-1.6
-1.8
-2
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.2
-2.4
-2.6
-2.8
-3
-2.8
-3
-50
-30
-10
10
30
50
70
90
110
130
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
图6-12. Charge Current vs Junction Temperature
图6-11. EN Pin Current vs Junction Temperature
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2.8
2.7
2.6
8
7
6
5
4
3
2
Vin = 3.3 V
UVLO Stop Switching
2.5
2.4
2.3
2.2
UVLO Start Switching
1
0
2.1
2
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
图6-14. Shutdown Supply Current
图6-13. Input Voltage vs Junction Temperature
vs Junction Temperature
800
700
600
500
400
8
T
= 25°C
Vin = 3.3 V
J
7
6
5
4
3
2
300
200
1
0
-50
-25
0
25
50
75
100
125
150
3
3.5
4
4.5
V - Input Voltage - V
I
5
5.5
6
T
- Junction Temperature - °C
J
图6-15. Shutdown Supply Current vs Input Voltage
图6-16. Supply Current vs Junction Temperature
800
110
108
106
T
= 25°C
J
700
600
500
400
Vsense Rising, Vin = 5 V
Vsense Falling
104
102
100
98
96
94
92
Vsense Rising
Vsense Falling
300
200
90
88
-50
-25
0
25
50
75
100
125
150
3
3.5
4
4.5
V - Input Voltage - V
I
5
5.5
6
T
- Junction Temperature - °C
J
图6-17. Supply Current vs Input Voltage
图6-18. PWRGD Threshold vs Junction
Temperature
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100
100
90
80
70
60
50
40
30
20
Vin = 5 V,
SS = 0.4 V
Vin = 3.3 V
90
80
70
60
50
40
30
20
10
0
10
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
T - Junction Temperature - °C
J
50
75
100
125
150
T
- Junction Temperature - °C
J
图6-19. PWRGD ON-Resistance
图6-20. SS/TR to VSENSE Offset
vs Junction Temperature
vs Junction Temperature
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
55
Vout = 3.3 V
Vout = 1.8 V
Vout = 1.8 V
Vout = 1.05 V
Vout = 1.05 V
Vin = 5 V,
f
Vin = 3.5 V,
= 1 MHz,
f
= 1 MHz,
T = 25°C
J
s
s
55
50
T
= 25°C
J
50
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current - A
Output Current - A
图6-21. Efficiency vs Load Current
图6-22. Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
Vout = 3.3 V
Vout = 1.8 V
Vout = 1.8 V
Vout = 1.05 V
Vout = 1.05 V
Vin = 5 V,
= 500 kHz,
Vin = 3.5 V,
f
f
= 500 kHz,
T = 25°C
J
s
s
55
50
55
50
T
= 25°C
J
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current - A
Output Current - A
图6-23. Efficiency vs Load Current
图6-24. Efficiency vs Load Current
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7 Detailed Description
7.1 Overview
The TPS54618C-Q1 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients, the device implements a constant frequency,
peak current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization
when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on
the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize
the power switch turnon to a falling edge of an external system clock.
The TPS54618C-Q1 has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup current
source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In
addition, the pullup current provides a default condition when the EN pin is floating for the device to operate. The
total operating current for the TPS54618C-Q1 is typically 515 μA when not switching and under no load. When
the device is disabled, the supply current is less than 5.5 μA.
The integrated 12-mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 6 A.
The TPS54618C-Q1 reduces the external component count by integrating the boot recharge diode. The bias
voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The
boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage
falls below a preset threshold. This BOOT circuit allows the TPS54618C-Q1 to operate approaching 100%. The
output voltage can be stepped down to as low as the 0.799-V reference.
The TPS54618C-Q1 has a power-good comparator (PWRGD) with 2% hysteresis.
The TPS54618C-Q1 minimizes excessive output overvoltage transients by taking advantage of the overvoltage
power-good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the
overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until
the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor must be coupled to the pin for slow start. The SS/TR pin is discharged
before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault, or disabled
condition.
The use of a frequency foldback circuit reduces the switching frequency during start-up and over current fault
conditions to help limit the inductor current.
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7.2 Functional Block Diagram
PWRGD EN
VIN
Thermal
UVLO
i1
iHYS
Shutdown
93%
Logic
Enable
Comparator
107%
Shutdown
Logic
Boot
Charge
Voltage
Reference
Enable
Threshold
Boot
UVLO
VSENSE
SS
+
+
BOOT
Minimum
COMP Clamp
Shutdown
Logic
PWM
Comparator
Logic and
PWM Latch
COMP
PH
Slope
Compensation
ꢀ
Frequency
Shift
GND
Overload
Recovery
Maximum
Clamp
OSC with
PLL
AGND
PowerPad
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54618C-Q1 uses an adjustable, fixed frequency, peak current mode control. The output voltage is
compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error
amplifier output is compared to the high-side power switch current. When the power switch current reaches the
COMP voltage level, the high-side power switch is turned off and the low-side power switch is turned on. The
COMP pin voltage increases and decreases as the output current increases and decreases. The device
implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a
minimum clamp for improved transient response performance.
7.3.2 Slope Compensation and Output Current
The TPS54618C-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents
subharmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the
full duty cycle range.
7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
The TPS54618C-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT
and PH pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor must
be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
To improve dropout, the TPS54618C-Q1 is designed to operate at 100% duty cycle as long as the BOOT-to-PH
pin voltage is greater than 2.2 V. The high-side MOSFET is turned off using a UVLO circuit, allowing for the low-
side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current
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sourced from the BOOT pin is very low, the high-side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.
7.3.4 Error Amplifier
The TPS54618C-Q1 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the
lower of the SS/TR pin voltage or the internal 0.799-V voltage reference. The transconductance of the error
amplifier is 245 μA/V during normal operation. When the voltage of VSENSE pin is below 0.799 V and the
device is regulating using the SS/TR voltage, the gm is typically greater than 79 μA/V, but less than 245 μA/V.
The frequency compensation components are placed between the COMP pin and ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.799 V at the noninverting
input of the error amplifier.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using
divider resistors with 1% tolerance or better. Pick a suitable value for the R1 resistor and use 方程式 1 to
calculate R2. To improve efficiency at very light loads, consider using larger value resistors. If the values are too
high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are
noticeable.
æ
ç
è
ö
÷
ø
0.799 V
R2 = R1 ´
VO - 0.799 V
(1)
TPS54618C-Q1
VOUT
R1
VSENSE
+
0.799 V
R2
图7-1. Voltage Divider Circuit
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54618C-Q1 is disabled when the VIN pin voltage falls below 2.28 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in 图 7-2 to adjust the input voltage UVLO by using two
external resistors. TI recommends using the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6 V.
The rising threshold (VSTART) must be set to provide enough hysteresis to allow for any input supply variations.
The EN pin has an internal pullup current source that provides the default condition of the TPS54618C-Q1
operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 μA of hysteresis is
added. When the EN pin is pulled below 1.18 V, the 1.6 μA is removed. This additional current facilitates input
voltage hysteresis.
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TPS54618C-Q1
Ih 1.6 µA
Ip 1.9
µA
VIN
EN
R1
R2
+
图7-2. Adjustable Undervoltage Lockout
- VSTOP
æ
ç
è
ö
÷
ø
VENFALLING
VENRISING
VSTART
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+I
p ç
h
VENRISING
è
(2)
(3)
vertical spacer
R1´ VENFALLING
VSTOP - VENFALLING + R1(Ip + Ih )
R2 =
where
• R1 and R2 are in Ω
• Ih = 1.6 µA
• Ip = 1.9 µA
• VENRISING = 1.25 V
• VENFALLING = 1.18 V
7.3.8 Soft-Start Pin
The TPS54618C-Q1 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on
the SS/TR pin to ground implements a slow-start time. The TPS54618C-Q1 has an internal pullup current source
of 2 μA, which charges the external slow-start capacitor. 方程式 4 calculates the required slow-start capacitor
value.
Tss(mS) ´ Iss(mA)
Css(nF) =
Vref(V)
(4)
where
• Tss is the desired slow-start time in ms
• Iss is the internal slow-start charging current of 2 μA
• Vref is the internal voltage reference of 0.799 V
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If, during normal operation, the VIN goes below UVLO, the EN pin pulls below 1.2 V, or a thermal shutdown
event occurs, the TPS54618C-Q1 stops switching. When the VIN goes above UVLO, EN is released or pulled
high, or a thermal shutdown is exited, then SS/TR is discharged to below 40 mV before reinitiating a powering-
up sequence. The VSENSE voltage follows the SS/TR pin voltage with a 54-mV offset up to 85% of the internal
voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage, the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open-drain or collector output of a power-on
reset pin of another device. 图 7-3 shows the sequential method. The power good is coupled to the EN pin on
the TPS54618C-Q1 which enables the second power supply once the primary supply reaches regulation.
Ratio-metric start-up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp
up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must
be doubled in 方程式4. The ratio-metric method is shown in 图7-5.
TPS54618C-Q1
PWRGD
TPS54618C-Q1
EN1
EN
SS
EN
SS/TR
PWRGD
EN2
CSS
CSS
VO1
VO2
图7-3. Sequential Start-Up Sequence
图7-4. Sequential Start-Up
Using EN and PWRGD
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TPS54618C-Q1
EN
EN
SS
SS
CSS
PWRGD
VO1
VO2
TPS54618C-Q1
EN
SS
PWRGD
图7-6. Ratio-Metric Start-Up
图7-5. Schematic for Ratio-Metric Start-Up
Sequence
space
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in 图 7-7 to the output of the power supply that needs to be tracked or another voltage
reference source. Using 方程式 5 and 方程式 6, the tracking resistors can be calculated to initiate the Vout2
slightly before, after, or at the same time as Vout1. 方程式 7 is the voltage difference between Vout1 and Vout2.
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start-
up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a
negative number in 方程式 5 through 方程式 7 for ΔV. 方程式 7 results in a positive number for applications
which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Because the SS/TR pin must be
pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, careful selection of the
tracking resistors is needed to ensure the device restarts after a fault. Make sure the calculated R1 value from 方
程式 5 is greater than the value calculated in 方程式 8 to ensure the device can recover from a fault. As the
SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the
slow-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage needs to be greater than 1.1 V for a complete hand off to the internal voltage reference as shown in 图
7-6.
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space
Vout2 + DV
Vssoffset
Iss
R1 =
´
Vref
(5)
space
R2 =
Vref ´ R1
Vout2 + DV - Vref
(6)
(7)
(8)
space
DV = Vout1 - Vout2
space
R1> 2930´ Vout1-145´DV
space
TPS54618C-Q1
EN
VOUT(1)
EN1
SS/TR
PWRGD
CSS
SS2
Vout1
Vout2
TPS54618C-Q1
VOUT(2)
EN
R1
SS/TR
R2
PWRGD
图7-8. Ratio-Metric Start-Up Using Coupled SS/TR
图7-7. Ratio-Metric and Simultaneous Start-Up
Pins
Sequence
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54618C-Q1 is adjustable over a wide range from 300 kHz to 2000 kHz by
placing a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier
holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The
RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in 方
程式9 or 方程式10.
235892
RT kW =
( )
1.027
fSW kHz
(
)
(9)
space
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171032
f
kHz =
( )
SW
0.974
RT kW
( )
(10)
To reduce the solution size, you would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage, and minimum controllable ON-time must be considered.
The minimum controllable ON-time is typically 75 ns at full current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
7.3.11 Overcurrent Protection
The TPS54618C-Q1 implements a cycle-by-cycle current limit. During each switching cycle, the high-side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
7.3.12 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54618C-
Q1 implements a frequency shift. If frequency shift was not implemented during an overcurrent condition, the
low-side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift during an overcurrent condition, the switching frequency is reduced from 100%,
then 50%, then 25%, as the voltage decreases from 0.799 to 0 V on VSENSE pin to allow the low-side MOSFET
to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases
as the voltage on VSENSE increases from 0 to 0.799 V.
7.3.13 Reverse Overcurrent Protection
The TPS54618C-Q1 implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into prebiased
outputs.
7.3.14 Synchronize Using the RT/CLK Pin
The RT/CLK pin is used to synchronize the converter to an external system clock. See 图 7-9. To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an ON-time of at least
75 ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency
set by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is
synchronized to the falling edge of RT/CLK pin.
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TPS54618C-Q1
PLL
SYNC Clock
RT/CLK
RRT
PH
图7-9. Synchronizing to a System Clock
图7-10. Plot of Synchronizing to System Clock
7.3.15 Power Good (PWRGD Pin)
The PWRGD pin output is an open-drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 107% of the internal voltage reference, the PWRGD output MOSFET is turned off. TI recommends
using a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. The
PWRGD is in a valid state once the VIN input voltage is greater than 1.5 V.
7.3.16 Overvoltage Transient Protection
The TPS54618C-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which
is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the
high-side MOSFET is disabled, preventing current from flowing to the output and minimizing output overshoot.
When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on
the next clock cycle.
7.3.17 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 150°C, the device reinitiates the power-up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 20°C.
7.4 Device Functional Modes
7.4.1 Simple Small Signal Model for Peak Current Mode Control
图 7-11 shows an equivalent model for the TPS54618C-Q1 control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor R0 and capacitor Co model the open loop gain and frequency response
of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for
the frequency response measurements. Plotting a/c shows the small signal response of the frequency
compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can
be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a
time domain analysis.
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TPS54618C-Q1
PH
VOUT
Power Stage
25 A/V
a
RESR
b
R1
RLOAD
VSENSE
COUT
COMP
c
+
gM 245 µA/V
0.799V
R2
COUT(ea)
R3
C1
C2
ROUT(ea)
图7-11. Small Signal Model for Loop Response
图 7-11 is a simple, small-signal model that can be used to understand how to design the frequency
compensation. The TPS54618C-Q1 power stage can be approximated to a voltage-controlled current source
(duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in 方程式11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in 图 7-11) is the power stage
transconductance. The gm for the TPS54618C-Q1 is 25 A/V. The low frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in 方程式 12. As
the load current increases and decreases, the low frequency gain decreases and increases, respectively. This
variation with load can seem problematic at first glance, but the dominant pole moves with load current. The
combined effect is highlighted by the dashed line in the right half of 图 7-13. As the load current decreases, the
gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying
load conditions which makes it easier to design the frequency compensation.
space
VC
RESR
Adc
RLOAD
COUT
gm(ps)
f
P
f
Z
Frequency
Copyright © 2016, Texas Instruments Incorporated
图7-13. Frequency Response Model for Peak
图7-12. Small Signal Model for Peak Current Mode
Current Mode Control
Control
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æ
ç
è
æ
ç
è
s
ö
÷
ø
ö
÷
ø
1+
1+
2p × ¦z
vo
vc
= Adc ´
s
2p × ¦p
(11)
(12)
Adc = gmps ´ RL
1
¦p =
COUT ´ RL ´ 2p
(13)
space
¦z =
1
COUT ´ RESR ´ 2p
(14)
7.4.2 Small Signal Model for Frequency Compensation
The TPS54618C-Q1 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in 图 7-14. The Type-2
circuits are most likely implemented in high-bandwidth power supply designs using low-ESR output capacitors.
In Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.
VOUT
TPS54618C-Q1
R1
VSENSE
gM(ea)
COMP
VREF
+
R2
R3
C1
R3
C2
ROUT(ea)
COUT(ea)
5 pF
C1
Type IIA
Type IIB
图7-14. Types of Frequency Compensation
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The design guidelines for TPS54618C-Q1 loop compensation are as follows:
1. The modulator pole, fpmod, and the esr zero, fz1, must be calculated using 方程式15 and 方程式16.
Derating the output capacitor (COUT) can be needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use 方程式17
and 方程式18 to estimate a starting point for the crossover frequency, fc. 方程式17 is the geometric mean
of the modulator pole and the esr zero and 方程式18 is the mean of modulator pole and the switching
frequency. Use the lower value of 方程式17 or 方程式18 as the maximum crossover frequency.
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(15)
space
1
¦z mod =
2p ´ Resr ´ Cout
(16)
space
¦
=
¦p mod´ ¦z mod
C
(17)
(18)
space
¦sw
¦p mod´
2
¦
=
C
space
2. R3 can be determined by 方程式19:
2p × ¦c ´ Vo ´ COUT
R3 =
gmea ´ Vref ´ gmps
(19)
where
• the gmea amplifier gain (245 μA/V)
• gmps is the power stage gain (25 A/V)
vertical spacer
3. Place a compensation zero at the dominant pole:
1
¦p =
COUT ´ RL ´ 2p
C1 can be determined by 方程式20:
RL ´ COUT
C1 =
R3
(20)
space
4. C2 is optional. It can be used to cancel the zero from the ESR of COUT
.
Resr ´ COUT
C2 =
R3
(21)
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8 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
This design example describes a high-frequency switching regulator design using ceramic output capacitors.
This design is available as the HPA606 evaluation module (EVM).
8.2 Typical Application
This section details a high-frequency, 1.8-V output power supply design application with adjusted UVLO.
图8-1. Typical Application Schematic TPS54618C-Q1
8.2.1 Design Requirements
The design parameters for the TPS54618C-Q1 are listed in 表8-1.
表8-1. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
3.3
MAX UNIT
VIN
Input voltage
Operating
3
6
V
V
VOUT
Output voltage
1.8
Transient response
Maximum output current
1.5-A to 4.5-A load step
4%
ΔVOUT
IOUT(max)
6
A
VOUT(ripple) Output voltage ripple
fSW Switching frequency
30 mVP-P
kHz
1000
8.2.2 Detailed Design Procedure
8.2.2.1 Step One: Select the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible because this produces the smallest solution size. The high-switching frequency
allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a
lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the
performance of the converter. The converter is capable of running from 300 kHz to 2 MHz. Unless a small
solution size is an ultimate goal, a moderate switching frequency of 1 MHz is selected to achieve both a small
solution size and a high-efficiency operation. Using 方程式 9, R4 is calculated to be 180 kΩ. A standard 1% 182-
kΩ value was chosen in the design.
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8.2.2.2 Step Two: Select the Output Inductor
The inductor selected works for the entire TPS54618C-Q1 input voltage range. To calculate the value of the
output inductor, use 方程式 22. KIND is a coefficient that represents the amount of inductor ripple current relative
to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing
high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must
have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple
value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of
applications.
For this design example, use KIND = 0.3 and the inductor value is calculated to be 0.7 μH. For this design, a
nearest standard value was chosen: 0.75 μH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from 方程式
24 and 方程式25.
For this design, the RMS inductor current is 6.01 A and the peak inductor current is 6.84 A. The chosen inductor
is a Toko FDV0630-R75M. It has a saturation current rating of 10 A and a RMS current rating of 8.9 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Io ´ Kind
Vout
L1 =
´
Vinmax ´ ¦sw
(22)
(23)
space
Iripple =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦sw
space
æ
ö2
÷
1
Vo ´ (Vinmax - Vo)
Vinmax ´ L1 ´ ¦sw
ILrms = Io2
+
´
ç
12
è
ø
(24)
(25)
space
ILpeak = Iout +
Iripple
2
8.2.2.3 Step Three: Choose the Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired holdup
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
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output capacitance must be large enough to supply the difference in current for two clock cycles while only
allowing a tolerable amount of droop in the output voltage. 方程式 26 shows the minimum output capacitance
necessary to accomplish this.
For this example, the transient load response is specified as a 3% change in Vout for a load step from 1.5 A
(25% load) to 4.5 A (75% load). For this example, ΔIout = 4.5 – 1.5 = 3.0 A and ΔVout = 0.04 × 1.8 = 0.072 V.
Using these numbers gives a minimum capacitance of 83 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
方程式 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, 方程式
27 yields 7 μF.
space
2 ´ DIout
Co >
¦sw ´ DVout
(26)
space
1
1
Co >
´
Voripple
8 ´ ¦sw
Iripple
(27)
where
• ΔIout is the change in output current
• fsw is the regulators switching frequency
• and ΔVout is the allowable change in the output voltage
space
方程式 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. 方程式 28 indicates the ESR should be less than 18 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 18 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias must be factored in which increases this
minimum value. For this example, five 22-μF, 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. The
estimated capacitance after derating by a factor 0.75 is 82.5 µF.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. 方程式 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, 方程式 29 yields
520 mA.
Voripple
Resr <
Iripple
(28)
space
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(29)
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8.2.2.4 Step Four: Select the Input Capacitor
The TPS54618C-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10
μF of effective capacitance and in some applications, a bulk capacitance. The effective capacitance includes
any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
TPS54618C-Q1. The input ripple current can be calculated using 方程式30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10-V voltage rating is required to support the
maximum input voltage. For this example, two 10-μF and one 0.1-μF 10-V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using 方程式 31. Using the design example values (Ioutmax = 6 A, Cin = 20 μF, Fsw =
1 MHz) yields an input voltage ripple of 149 mV and an RMS input ripple current of 2.94 A.
Vinmin - Vout
(
)
Vout
Icirms = Iout ´
´
Vinmin
Vinmin
(30)
space
DVin =
Ioutmax ´ 0.25
Cin ´ ¦sw
(31)
8.2.2.5 Step Five: Choose the Soft-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54618C-Q1 reach the current limit or excessive current draw from the input power supply can cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start capacitor value can be calculated using 方程式 32. For the example circuit, the slow-start time is
not too critical because the output capacitor value is 110 μF which does not require much current to charge to
1.8 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms which requires a 10-nF
capacitor. In TPS54618C-Q1, Iss is 2.2 μA and Vref is 0.799 V.
Tss(ms) ´ Iss(mA)
Css(nF) =
Vref(V)
(32)
8.2.2.6 Step Six: Select the Bootstrap Capacitor
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. TI
recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor must have 10-V or
higher voltage rating.
8.2.2.7 Step Eight: Select Output Voltage and Feedback Resistors
For the example design, 100 kΩ was selected for R6. Using 方程式 33, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.6 kΩ.
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Vref
R7 =
R6
Vo - Vref
(33)
8.2.2.7.1 Output Voltage Limitations
Due to the internal design of the TPS54618C-Q1, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.799 V. Above 0.799 V,
the output voltage can be limited by the minimum controllable ON-time. The minimum output voltage in this case
is given by 方程式34.
Voutmin = Ontimemin´Fsmax ´ Vinmax - loutmin´RDSmin -Ioutmin´ RL + RDSmin
(
(
)
)
(34)
where
• Voutmin = minimum achievable output voltage
• Ontimemin = minimum controllable ON-time (75 ns typical. 120 ns no load)
• Fsmax = maximum switching frequency including tolerance
• Vinmax = maximum input voltage
• Ioutmin = minimum load current
• RDSmin = minimum high-side MOSFET ON-resistance (see 节6.5)
• RL = series resistance of output inductor
There is also a maximum achievable output voltage which is limited by the minimum OFF-time. The maximum
output voltage is given by 方程式35.
Offtimemax
ts
tdead
ts
æ
ö
æ
ö
Voutmax = Vin´ 1-
-Ioutmax ´ RDSmax + RI - 0.7 -Ioutmax ´RDSmax ´
(
) (
)
ç
÷
ç
÷
è
ø
è
ø
(35)
where
• Voutmax = maximum achievable output voltage
• Vin = minimum input voltage
• Offtimemax = maximum OFF-time (90 ns typical for adequate margin)
• ts = 1/Fs
• Ioutmax = maximum current
• RDSmax = maximum high-side MOSFET ON-resistance (see 节6.5)
• RI = DCR of the inductor
• tdead = dead time (60 ns)
8.2.2.8 Step Nine: Select Loop Compensation Components
There are several industry techniques used to compensate DC–DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54618C-Q1. Because the slope compensation is ignored, the actual cross over frequency is usually
lower than the cross over frequency used in the calculations. Use SwitcherPro™ software for a more accurate
design.
To get started, the modulator pole, fpmod, and the esr zero, fz1, must be calculated using 方程式 36 and 方程式
37. For COUT, the derated capacitance value is 82.5 µF. Use 方程式38 and 方程式39 to estimate a starting point
for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz. 方程式 38 is
the geometric mean of the modulator pole and the esr zero and 方程式39 is the mean of modulator pole and the
switching frequency. 方程式 38 yields 64.3 kHz and 方程式 39 gives 56.7 kHz. The lower value of 方程式 38 or
方程式 39 is the maximum recommended crossover frequency. For this example, a lower fc value of 40 kHz is
specified. Next, the compensation components are calculated. A resistor in series with a capacitor is used to
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create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if
needed).
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(36)
space
1
¦z mod =
2p ´ Resr ´ Cout
(37)
space
¦
=
¦p mod´ ¦z mod
C
(38)
(39)
space
¦sw
¦p mod´
2
¦
=
C
space
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use 方程式40 to calculate the resistor value of the
compensation network. In this example, the anticipated crossover frequency (fc) is 40 kHz. The power stage
gain (gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
2p × ¦c ´ Vo ´ Co
R3 =
Gm ´ Vref ´ VIgm
(40)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The capacitor of
the compensation network can be calculated from 方程式41.
Ro ´ Co
C4 =
R3
(41)
3. An additional pole can be added to attenuate high-frequency noise. In this application, it is not necessary to
add it.
From the previously listed procedures, the compensation network includes a 7.50-kΩ resistor and a
3300-pF capacitor.
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8.2.3 Application Curves
100
90
100
90
Vin = 3.3 V
Vin = 5 V
80
80
70
60
50
40
30
20
10
0
Vin = 3 V
70
60
50
40
30
20
Vin = 5 V
10
0
0
1
2
3
4
5
6
0.01
0.1
1
10
Output Current - A
Output Current - A
图8-2. Efficiency vs Load Current
图8-3. Efficiency vs Load Current
Vout = 50 mV / div (ac coupled)
Vin = 2 V / div
Iout = 2 A / div (1.5 A to 4.5 A load step)
Vout = 1 V / div
PWRGD = 2 V / div
Time = 200 usec / div
Time = 2 msec / div
1-A Load Step
图8-4. Transient Response
图8-5. Power Up, VOUT, VIN
Vout = 10 mV / div (ac coupled)
EN = 2 V / div
Vout = 1 V / div
PH = 2 V / div
PWRGD = 2 V / div
Time = 2 msec / div
Time = 500 nsec / div
IOUT = 0 A
图8-7. Output Ripple
图8-6. Power Up, VOUT, EN
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60
50
40
180
150
120
Vin = 100 mV / div (ac coupled)
30
20
90
60
10
30
0
0
–10
–30
PH = 2 V / div
–20
–30
–40
–50
–60
–60
–90
–120
–150
Gain
Phase
–180
100
1000
10k
Frequency - Hz
100k
1M
Time = 500 nsec / div
VIN = 3.3. V
IOUT = 2 A
IOUT = 2A
图8-9. Closed-Loop Response
图8-8. Input Ripple
0.4
0.4
0.3
0.3
0.2
0.1
Iout = 3 A
Vin = 5 V
0.2
0.1
Vin = 3.3 V
0
-0.1
-0.2
-0.3
-0.4
0
-0.1
-0.2
-0.3
-0.4
0
1
2
3
4
5
6
3
3.5
4
4.5
5
5.5
6
Output Current - A
Input Voltage-V
图8-10. Load Regulation vs Load Current
图8-11. Regulation vs Input Voltage
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 2.95 V and 6 V. This supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme. See the recommendations in 节10.1.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance.
• Minimize the loop area formed by the bypass capacitor connections and the VIN pins. See 图10-1 for a PCB
layout example.
• The GND pins and AGND pin should be tied directly to the power pad under the TPS54618C-Q1 device. The
power pad must be connected to any internal PCB ground planes using multiple vias directly under the
device. Additional vias can be used to connect the top-side ground area to the internal planes near the input
and output capacitors. For operation at full rated load, the top-side ground area along with any additional
internal ground planes must provide adequate heat dissipating area.
• Place the input bypass capacitor as close to the device as possible.
• Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output
inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive
coupling.
• The boot capacitor must also be located close to the device.
• The sensitive analog ground connections for the feedback voltage divider, compensation components, soft-
start capacitor, and frequency set resistor must be connected to a separate analog ground trace as shown in
图10-1.
• The RT/CLK pin is particularly sensitive to noise so the RT resistor must be located as close as possible to
the device and routed with minimal trace lengths.
• The additional external components can be placed approximately as shown. It is possible to obtain
acceptable performance with alternate PCB layouts, however, this layout has been shown to produce good
results and can be used as a guide.
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTRORS
VIN
BOOT
CAPACITOR
VIN
INPUT
OUTPUT
INDUCTOR
VIN
PH
PH
PH
SS
VOUT
BYPASS
CAPACITOR
VIN
OUTPUT
FILTER
EXPOSED
POWERPAD
AREA
CAPACITOR
GND
GND
PH
SLOW START
CAPACITOR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
图10-1. PCB Layout Example
10.3 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode
(CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd),
switching loss (Psw), gate drive loss (Pgd), and supply current loss (Pq).
Pcon = Io2 × RDS_on_Temp
(42)
(43)
(44)
where
• IO is the output current (A)
• RDS_on_Temp is the ON-resistance of the high-side MOSFET with given temperature (Ω)
Pd = ƒsw × Io × 0.7 × 40 × 10–9
where
• IO is the output current (A)
• ƒsw is the switching frequency (Hz)
Psw = 1/2 × Vin × Io × ƒsw× 13 × 10–9
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where
• IO is the output current (A)
• Vin is the input voltage (V)
• ƒsw is the switching frequency (Hz)
Pgd = 2 × Vin × ƒsw× 10 × 10–9
(45)
where
• Vin is the input voltage (V)
• ƒsw is the switching frequency (Hz)
Pq = Vin × 515 × 10–6
(46)
(47)
where
• Vin is the input voltage (V)
Ptot = Pcon + Pd + Psw + Pgd + Pq
where
• Ptot is the total device power dissipation (W)
For given TA:
TJ = TA + Rth × Ptot
where
(48)
• TA is the ambient temperature (°C)
• TJ is the junction temperature (°C)
• Rth is the thermal resistance of the package (°C/W)
For given TJmax = 150°C:
TAmax = TJmax –Rth × Ptot
where
(49)
• Ptot is the total device power dissipation (W)
• Rth is the thermal resistance of the package (°C/W)
• TJmax is maximum junction temperature (°C)
• TAmax is maximum ambient temperature (°C)
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Developmental Support
For developmental support, see the following:
• Evaluation Module for TPS54618C-Q1 Synchronous Step-Down SWIFT™ DC/DC Converter, HPA606
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
11.4 Trademarks
SwitcherPro™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
36
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Product Folder Links: TPS54618C-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54618CQRTERQ1
ACTIVE
WQFN
RTE
16
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
618CQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54618CQRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS54618CQRTERQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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