首页 |元器件品牌

TPS54620RGYT [TI]

17V Input, 6A Output, Synchronous Step Down Switcher With Integrated FET in 3.5mm x 3.5mm Package(SWIFT™); 17V输入， 6A输出，同步降压切换器，带集成FET了3.5mm X 3.5毫米包（ SWIFT ™ ）
TPS54620RGYT
型号： TPS54620RGYT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

17V Input, 6A Output, Synchronous Step Down Switcher With Integrated FET in 3.5mm x 3.5mm Package(SWIFT™)
17V输入， 6A输出，同步降压切换器，带集成FET了3.5mm X 3.5毫米包（ SWIFT ™ ）

稳压器 开关式稳压器或控制器 电源电路 开关式控制器 PC
文件： 总39页 (文件大小：1716K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
17V Input, 6A Output, Synchronous Step Down Switcher  
With Integrated FET in 3.5mm x 3.5mm Package(SWIFT™)  
1
FEATURES  
•
Power Good Output Monitor for Undervoltage  
& Overvoltage  
2
•
Integrated 26mΩ / 19mΩ MOSFETs  
•
•
•
Adjustable Input Undervoltage Lockout  
Supported by SwitcherPro™ Software Tool  
•
•
•
•
•
•
•
Split Power Rail: 1.6V to 17V on PVIN  
200kHz to 1.6MHz Switching Frequency  
Synchronizes to External Clock  
For SWIFT™ Documentation and  
SwitcherPro™, visit http://www.ti.com/swift  
0.8V ±1% Voltage Reference Over Temperature  
Low 2uA Shutdown Quiscent Current  
Monotonic Start-Up into Prebiased Outputs  
APPLICATIONS  
•
•
•
High Density Distributed Power Systems  
High Peformance Point of Load Regulation  
Broadband, Networking and Optical  
Communications Infrastructure  
–40°C to 150°C Operating Junction  
Temperature Range  
•
Adjustable Slow Start/Power Sequencing  
DESCRIPTION  
The TPS54620 in thermally enhanced 3.5mm x 3.5mm QFN package is a full featured 17V, 6A synchronous step  
down converter which is optimized for small designs through high efficiency and integrating the high-side and  
low-side MOSFETs. Further space savings are achieved through current mode control, which reduces  
component count, and by selecting a high switching frequency, reducing the inductor's footprint.  
The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone  
power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and  
the open drain power good pins.  
Cycle by cycle current limiting on the high-side fet protects the device in overload situations and is enhanced by  
a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit  
which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part  
when die temperature rises too high.  
WHITE SPACE  
SIMPLIFIED SCHEMATIC  
100  
8 V  
PVIN  
VIN  
95  
VIN  
Cboot  
TPS54620  
BOOT  
90  
85  
Cin  
17 V  
12 V  
VOUT  
Lo  
80  
75  
70  
EN  
PH  
Co  
PWRGD  
R1  
VSENSE  
SS/TR  
RT/CLK  
COMP  
65  
60  
R2  
VOUT = 3.3 V  
Fsw = 480 kHz  
GND  
PowerPAD  
R3  
C1  
55  
50  
Css  
Rrt C2  
0
1
2
3
4
5
6
Load Current - A  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
SWIFT, PowerPAD are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
TJ  
PACKAGE  
PART NUMBER(2)  
–40°C to 150°C  
14 Pin QFN  
TPS54620RGY  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) The RGY package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54620RGYR). See applications  
section of data sheet for layout information  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating temperature range (unless otherwise noted)  
VALUE  
–0.3 to 20  
–0.3 to 20  
–0.3 to 3  
–0.3 to 27  
–0.3 to 3  
–0.3 to 3  
–0.3 to 6  
–0.3 to 3  
–0.3 to 6  
0 to 7  
UNIT  
V
VIN  
PVIN  
V
EN  
V
BOOT  
V
Input Voltage  
VSENSE  
COMP  
V
V
PWRGD  
SS/TR  
V
V
RT/CLK  
BOOT-PH  
PH  
V
V
Output Voltage  
–1 to 20  
–3 to 20  
–0.2 to 0.2  
±100  
V
PH 10ns Transient  
V
Vdiff(GND to PowerPAD)  
Source Current  
V
RT/CLK  
PH  
µA  
A
Current Limit  
Current Limit  
Current Limit  
±200  
PH  
A
PVIN  
A
Sink Current  
COMP  
PWRGD  
µA  
mA  
kV  
V
–0.1 to 5  
2
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)  
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)  
Operating Junction Temperature  
500  
–40 to 150  
–65 to 150  
°C  
°C  
Storage Temperature  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
PACKAGE DISSIPATION RATINGS(1) (2) (3)  
THERMAL IMPEDANCE  
JUNCTION TO AMBIENT  
ψJT THERMAL CHARACTERISTIC  
PACKAGE  
JUNCTION TO TOP  
RGY  
32°C/W  
5°C/W  
(1) Maximum power dissipation may be limited by overcurrent protection  
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where  
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below  
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more  
information.  
(3) Test board conditions:  
a. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch  
b. 2 oz. copper traces located on the top of the PCB  
c. 2 oz. copper ground planes on the 2 internal layers and bottom layer  
d. 4 thermal vias located under the device package  
ELECTRICAL CHARACTERISTICS  
TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)  
DESCRIPTION  
SUPPLY VOLTAGE (VIN AND PVIN PINS)  
PVIN operating input voltage  
VIN operating input voltage  
VIN internal UVLO threshold  
VIN internal UVLO hysterisis  
VIN shutdown supply Current  
VIN operating – non switching supply current  
ENABLE AND UVLO (EN PIN)  
Enable threshold  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.6  
4.5  
17  
17  
V
V
VIN rising  
EN = 0 V  
4.0  
150  
2
4.5  
V
mV  
µA  
µA  
5
VSENSE = 810 mV  
600  
800  
Rising  
1.21  
1.17  
1.15  
3.4  
1.26  
V
Enable threshold  
Falling  
1.10  
Input current  
EN = 1.1 V  
EN = 1.3 V  
µA  
µA  
Hysteresis current  
VOLTAGE REFERENCE  
Voltage reference  
0 A ≤ Iout ≤ 6 A  
0.792  
0.800  
0.808  
V
MOSFET  
High-side switch resistance  
High-side switch resistance(1)  
Low-side Switch Resistance(1)  
ERROR AMPLIFIER  
BOOT-PH = 3 V  
BOOT-PH = 6 V  
VIN = 12 V  
32  
26  
19  
60  
40  
30  
mΩ  
mΩ  
mΩ  
Error amplifier Transconductance (gm)  
Error amplifier dc gain  
–2 µA < ICOMP < 2 µA, V(COMP) = 1 V  
VSENSE = 0.8 V  
1300  
3100  
±110  
0.25  
16  
µMhos  
V/V  
µA  
1000  
Error amplifier source/sink  
Start switching threshold  
COMP to Iswitch gm  
V(COMP) = 1 V, 100 mV input overdrive  
V
A/V  
CURRENT LIMIT  
High-side switch current limit threshold  
Low-side switch sourcing current limit  
Low-side switch sinking current limit  
8
7
11  
10  
A
A
A
2.3  
(1) Measured at pins  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)  
DESCRIPTION  
THERMAL SHUTDOWN  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Thermal shutdown  
160  
175  
10  
°C  
°C  
Thermal shutdown hysterisis  
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)  
Minimum switching frequency  
Switching frequency  
Rrt = 240 kΩ (1%)  
180  
400  
200  
480  
1600  
20  
220  
560  
kHz  
kHz  
kHz  
ns  
Rrt = 100 kΩ (1%)  
Rrt = 29 kΩ (1%)  
Maximum switching frequency  
Minimum pulsewidth  
1440  
1760  
RT/CLK high threshold  
2
V
RT/CLK low threshold  
0.8  
V
RT/CLK falling edge to PH rising edge delay  
Measure at 500 kHz with RT resistor in series  
66  
ns  
Switching frequency range (RT mode set point  
and PLL mode)  
200  
1600  
135  
kHz  
PH (PH PIN)  
Minimum on time  
Measured at 90% to 90% of VIN, 25°C, IPH = 2A  
94  
0
ns  
ns  
Minimum off time  
BOOT-PH ≥ 3 V  
BOOT (BOOT PIN)  
BOOT-PH UVLO  
2.1  
3
V
SLOW START AND TRACKING (SS/TR PIN)  
SS charge current  
2.3  
29  
µA  
SS/TR to VSENSE matching  
POWER GOOD (PWRGD PIN)  
VSENSE threshold  
V(SS/TR) = 0.4 V  
60  
mV  
VSENSE falling (Fault)  
91  
94  
% Vref  
% Vref  
% Vref  
% Vref  
nA  
VSENSE rising (Good)  
VSENSE rising (Fault)  
109  
106  
30  
VSENSE falling (Good)  
VSENSE = Vref, V(PWRGD) = 5.5 V  
I(PWRGD) = 2 mA  
Output high leakage  
100  
0.3  
1
Output low  
V
Minimum VIN for valid output  
Minimum SS/TR voltage for PWRGD  
V(PWRGD) < 0.5V at 100 µA  
0.6  
V
1.4  
V
4
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
DEVICE INFORMATION  
PIN ASSIGNMENTS  
RGY (Top View )  
RT/CLK  
1
PWRGD  
14  
GND  
GND  
2
3
13 BOOT  
12  
PH  
PowerPAD  
(15)  
11  
PH  
PVIN  
PVIN  
4
5
10 EN  
VIN  
6
9 SS/TR  
7
8
VSENSE  
COMP  
PIN FUNCTIONS  
PIN  
DESCRIPTION  
NAME  
No.  
RT/CLK  
1
Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching  
frequency of the device; In CLK mode, the device synchronizes to an external clock.  
GND  
2, 3  
4, 5  
6
Return for control circuitry and low-side power MOSFET.  
Power input. Supplies the power switches of the power converter.  
Supplies the control circuitry of the power converter.  
Inverting input of the gm error amplifier.  
PVIN  
VIN  
VSENSE  
COMP  
7
8
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this  
pin.  
SS/TR  
9
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time.  
The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.  
EN  
10  
Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.  
PH  
11, 12 The switch node.  
BOOT  
13  
14  
15  
A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the  
high-side MOSFET.  
PWRGD  
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN  
shutdown or during slow start.  
PowerPAD  
Thermal pad of the package and signal ground. It must be soldered down for proper operation.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
FUNCTIONAL BLOCK DIAGRAM  
VIN  
PVIN PVIN  
PWRGD  
EN  
Thermal  
Shutdown  
UVLO  
Shutdown  
Enable  
Comparator  
Ip  
Ih  
Shutdown  
Shutdown  
Logic  
UV  
OV  
Logic  
Enable  
Threshold  
Boot  
Charge  
Current  
Sense  
Minimum Clamp  
Pulse Skip  
ERROR  
AMPLIFIER  
VSENSE  
SS/TR  
BOOT  
Boot  
UVLO  
HS MOSFET  
Current  
Comparator  
Voltage  
Reference  
Power Stage  
& Deadtime  
Control  
PH  
PH  
Logic  
Slope  
Compensation  
VIN  
Regulator  
Overload Recovery  
and  
Oscillator  
with PLL  
LS MOSFET  
Current Limit  
Clamp  
Current  
Sense  
GND  
GND  
COMP  
RT/CLK  
POWERPAD  
6
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
TYPICAL CHARACTERISTICS  
CHARACTERISTIC CURVES  
HIGH-SIDE Rdson vs TEMPERATURE  
VIN = 12 V  
LOW-SIDE Rdson vs TEMPERATURE  
VIN = 12 V  
40  
35  
30  
25  
20  
30  
27  
24  
21  
18  
15  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
− Junction Temperature − °C  
− Junction Temperature − °C  
J
J
Figure 1.  
Figure 2.  
VOLTAGE REFERENCE vs TEMPERATURE  
OSCILLATOR FREQUENCY vs TEMPERATURE  
0.805  
0.803  
0.801  
0.799  
0.797  
0.795  
490  
485  
480  
475  
470  
RT = 100 kΩ  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
− Junction Temperature − °C  
− Junction Temperature − °C  
J
J
Figure 3.  
Figure 4.  
SHUTDOWN QUIESCENT CURRENT vs INPUT VOLTAGE  
PIN HYSTERISIS CURRENT vs TEMPERATURE  
4
3.50  
3.45  
3.40  
3.35  
3.30  
EN = 0 V  
VIN = 12 V  
EN = 1.3 V  
T
= 150°C  
J
3
2
1
0
T
= 25°C  
J
T
= −40°C  
J
3
6
9
12  
15  
18  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
V − Input Voltage − V  
I
− Junction Temperature − °C  
J
Figure 5.  
Figure 6.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
PIN PULLUP CURRENT vs TEMPERATURE  
PIN UVLO THRESHOLD vs TEMPERATURE  
1.20  
1.15  
1.10  
1.220  
1.215  
1.210  
1.205  
1.200  
VIN = 12 V  
EN = 1.1 V  
VIN = 12 V  
−50  
−25  
0
25  
50  
75  
100  
125  
150  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
T
− Junction Temperature − Deg  
− Junction Temperature − °C  
J
J
Figure 7.  
Figure 8.  
NON-SWITCHING OPERATING QUIESCENT CURRENT  
(VIN) vs INPUT VOLTAGE  
SLOW START CHARGE CURRENT vs TEMPERATURE  
2.5  
800  
T
= −40°C  
J
2.4  
2.3  
2.2  
2.1  
700  
600  
500  
400  
T
= −25°C  
J
T
= 150°C  
J
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
3
6
9
12  
15  
− Junction Temperature − °C  
J
V − Input Voltage − V  
I
Figure 9.  
Figure 10.  
(SS/TR - VSENSE) OFFSET vs TEMPERATURE  
PWRGD THRESHOLD vs TEMPERATURE  
0.05  
0.04  
0.03  
0.02  
0.01  
120  
VIN = 12 V  
VSENSE Rising  
110  
100  
90  
VSENSE Falling  
VSENSE Rising  
VSENSE Falling  
80  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
− Junction Temperature − °C  
− Junction Temperature − °C  
J
J
Figure 11.  
Figure 12.  
8
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
TYPICAL CHARACTERISTICS (continued)  
HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT  
VOLTAGE  
MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE  
120  
13  
12  
11  
10  
9
VIN = 12 V  
IOUT = 2A  
110  
100  
90  
T
= −40°C  
J
T
= 25°C  
J
T
= 150°C  
J
8
7
80  
6
70  
5
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
1
5
9
13  
17  
− Junction Temperature − °C  
V − Input Voltage − V  
I
J
Figure 13.  
Figure 14.  
MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION  
TEMPERATURE  
BOOT-PH UVLO THRESHOLD vs TEMPERATURE  
2.2  
2.1  
2.0  
6.0  
5.0  
4.0  
RT = 100 kΩ  
VIN =12 V  
IOUT = 2 A  
3.0  
−50  
−25  
0
T
25  
50  
75  
100  
125  
150  
−50  
−25  
0
25  
50  
75  
100 125 150  
− Junction Temperature − °C  
J
T
− Junction Temperature − Deg  
J
Figure 15.  
Figure 16.  
OVERVIEW  
The device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To  
improve performance during line and load transients the device implements a constant frequency, peak current  
mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to  
1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching  
frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock  
loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge  
of an external system clock.  
The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN  
is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage  
under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to  
operate with the internal pull up current. The total operating current for the device is approximately 600µA when  
not switching and under no load. When the device is disabled, the supply current is typically less than 2µA.  
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6  
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for  
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor  
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to  
recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is  
higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped  
down to as low as the 0.8V voltage reference (Vref).  
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through  
the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage  
is less than 91% or greater than 109% of the reference voltage Vref and asserts high when the VSENSE pin  
voltage is 94% to 106% of the Vref.  
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing  
during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical  
power supply sequencing requirements.  
The device is protected from output overvoltage, overload and thermal fault consitions. The device minimizes  
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.  
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning  
on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET  
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor  
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal  
shutdown trip point. The device is restarted under control of the slow start circuit automatically when the junction  
temperature drops 10°C typically below the thermal shutdown trip point.  
DETAILED DESCRIPTION  
Fixed Frequency PWM Control  
The device uses a adjustable fixed frequency, peak current mode control. The output voltage is compared  
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives  
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output  
is converted into a current reference which compares to the high-side power switch current. When the power  
switch current reaches current reference generated by the COMP voltage level the high-side power switch is  
turned off and the low-side power switch is turned on.  
Continuous Current Mode Operation (CCM)  
As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all  
load conditions.  
VIN and Power VIN Pins (VIN and PVIN)  
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN  
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to  
the power converter system.  
If tied together, the input voltage for VIN and PVIN can range from 4.5V to 17V. If using the VIN separately from  
PVIN, the VIN pin must be between 4.5V and 17V, and the PVIN pin can range from as low as 1.6V to 17V. A  
voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the  
input voltage UVLO on the PVIN pin helps to provide consistant power up behavior.  
Voltage Reference  
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output  
of a temperature stable bandgap circuit.  
10  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
Adjusting the Output Voltage  
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to  
use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10  
kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value  
resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the  
VSENSE input current are noticeable.  
Vo - Vref  
R5 =  
R6  
Vref  
(1)  
Where Vref = 0.8V  
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the  
high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in  
Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation.  
Safe Start-up into Pre-Biased Outputs  
The device has been designed to prevent the low-side MOSFET from diacharging a prebiased output. During  
monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is  
higher than 1.4V.  
Error Amplifier  
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the  
lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier  
is 1300 µA/V during normal operation. The frequency compensation network is connected between the COMP  
pin and ground.  
Slope Compensation  
The device adds a compensating ramp to the switch current signal. This slope compensation prevents  
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.  
Enable and Adjusting Under-Voltage Lockout  
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold  
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator  
stops switching and enters low Iq state.  
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If  
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the  
pin.  
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage  
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV.  
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in  
split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 and Figure 19. When  
using the external UVLO function it is recommended to set the hysteresis to be greater than 500mV.  
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external  
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO  
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be  
calculated using Equation 2 and Equation 3.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s) :TPS54620  
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
TPS54620  
VIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 17. Adjustable VIN Under Voltage Lock Out  
TPS54620  
PVIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V  
TPS54620  
PVIN  
VIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 19. Adjustable VIN and PVIN Under Voltage Lock Out  
æ
ç
è
ö
÷
ø
VENFALLING  
VENRISING  
VSTART  
- VSTOP  
R1 =  
æ
ö
÷
ø
VENFALLING  
I
1-  
+I  
p ç  
h
VENRISING  
è
(2)  
(3)  
R1´ VENFALLING  
VSTOP - VENFALLING + R1(Ip + Ih )  
R2 =  
Where Ih = 3.4 µA, Ip = 1.15 µA, VENRISING = 1.21 V, VENFALLING = 1.17 V  
Adjustable Switching Frequency and Synchronization (RT/CLK)  
The RT/CLK pin can be used to set the switching frequency of the device in two mode.  
12  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of  
the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kOhm and minimum of 29 kΩ  
respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized  
to the external clock frequency with PLL.  
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch  
from the RT mode to CLK mode.  
Adjustable Switching Frequency (RT Mode)  
To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20. To  
reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply  
efficiency and minimum controllable on time should be considered.  
-0.997  
)
Rrt(kW) = 48000 ×Fsw kHz  
(
- 2  
(4)  
250  
200  
150  
100  
50  
0
200  
400  
600  
800  
1000  
1200  
1400  
1600  
Fsw − Oscillator Frequency − kHz  
Figure 20. RT Set Resistor vs Switching Frequency  
Synchronization (CLK mode)  
An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and  
1600kHz, and to easily switch from RT mode to CLK mode.  
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty  
cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8V and higher than 2.0V.  
The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.  
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in  
Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set  
by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the  
SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK  
mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external  
clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching  
frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.  
RT/CLK  
mode select  
TPS54620  
RT/CLK  
Rrt  
Figure 21. Works with Both RT mode and CLK mode  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s) :TPS54620  
 
 
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
Slow Start (SS/TR)  
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference  
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start  
time. The device has an internal pull-up current source of 2.3µA that charges the external slow start capacitor.  
The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in  
Equation 5. The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3µA.  
Css(nF) ´ Vref(V)  
Tss(ms) =  
Iss(mA)  
(5)  
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the  
device stops switching and enters low current operation. At the subsequent power up, when the shutdown  
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring  
propper soft start behavior.  
Power Good (PWRGD)  
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal  
voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a  
pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is  
in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The  
PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V.  
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal  
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN  
pin is pulled low or the SS/TR pin is below 1.4V.  
Bootstrap Voltage (BOOT) and Low Dropout Operation  
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH  
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT  
pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor  
should be 0.1µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher  
is recommended because of the stable characteristics over temperature and voltage.  
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin  
voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1V. When the voltage between BOOT  
and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side  
MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails  
100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4V.  
Sequencing (SS/TR)  
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD  
pins.  
The sequential method is illustrated in Figure 22 using two TPS54620 devices. The power good of the first  
device is coupled to the EN pin of the second device which enables the second power supply once the primary  
supply reaches regulation. Figure 23 shows the results of Figure 22.  
14  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
PWRGD = 2 V / div  
TPS54620  
TPS54620  
PWRGD  
EN  
EN  
EN = 2 V / div  
Vout1 = 1 V / div  
SS/TR  
SS/TR  
Vout2 = 1 v / div  
PWRGD  
Time = 20 msec / div  
Figure 22. Sequencial Start Up Sequence  
Figure 23. Sequential Start Up using EN and PWRGD  
Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices  
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start  
time the pull up current source must be doubled in Equation 5. Figure 25 shows the results of Figure 24.  
EN = 2 V / div  
TPS54620  
EN  
Vout1 = 1 V / div  
SS/TR  
Vout2 = 1 v / div  
PWRGD  
Time = 20 msec / div  
TPS54620  
EN  
SS/TR  
PWRGD  
Figure 24. Ratiometric Start Up Sequence  
Figure 25. Ratio-metric Startup using Coupled SS/TR  
Pins  
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network  
of R1 and R2 shown in Figure 26 to the output of the power supply that needs to be tracked or another voltage  
reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2  
slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and  
Vout2.  
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2  
reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a  
positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.  
Figure 27 and Figure 28 show the results for positive deltaV and negtive deltaV respectively.  
The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to  
VSENSE offset (Vssoffset, 29mV) in the slow start circuit and the offset created by the pullup current source (Iss,  
2.3µA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. Figure 29 shows  
the result when deltaV = 0V.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Link(s) :TPS54620  
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the  
value calculated in Equation 9.  
Vout2 + DV  
Vssoffset  
R1 =  
´
Vref  
Iss  
(6)  
Vref ´ R1  
Vout2 + DV - Vref  
R2 =  
(7)  
(8)  
(9)  
DV = Vout1 - Vout2  
R1> 2800´ Vout1-180´DV  
TPS54620  
EN  
VOUT1  
SS/TR  
PWRGD  
TPS54620  
VOUT2  
EN  
R1  
R2  
SS/TR  
PWRGD  
R3  
R4  
Figure 26. Ratiometric and Simultaneous Startup Sequence  
EN = 2 V / div  
Vout1 = 1 V / div  
Vout2 = 1 V / div  
Time = 20 msec / div  
Figure 27. Ratio-metric Startup with Vout1 Leading Vout2  
16  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
EN = 2 V / div  
Vout1 = 1 V / div  
Vout2 = 1 V / div  
Time = 20 msec / div  
Figure 28. Ratio-metric Startup with Vout2 Leading Vout1  
EN = 2 V / div  
Vout1 = 1 V / div  
Vout2 = 1 V / div  
Time = 20 msec / div  
Figure 29. Simultaneous Startup  
Output Overvoltage Protection (OVP)  
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For  
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to  
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a  
considerable time, the output of the error amplifier demands maximum output current. Once the condition is  
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some  
applications with small output capacitance, the power supply output voltage can respond faster than the error  
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by  
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP  
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output  
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to  
turn on at the next clock cycle.  
Overcurrent Protection  
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side  
MOSFET and the low-side MOSFET.  
High-side MOSFET overcurrent protection  
The device implements current mode control which uses the COMP pin voltage to control the turn off of the  
high-side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch  
current and the current reference generated by the COMP pin voltage are compared, when the peak switch  
current intersects the current reference the high-side switch is turned off.  
Low-side MOSFET overcurrent protection  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During  
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side  
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side  
sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the  
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing  
current limit at the start of a cycle.  
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the  
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are  
off until the start of the next cycle.  
Thermal Shutdown  
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds  
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C  
typically.  
Small Signal Model for Loop Response  
Figure 30 shows an equivalent model for the device control loop which can be modeled in a circuit simulation  
program to check frequency response and transient responses. The error amplifier is a transconductance  
amplifier with a gm of 1300µA/V. The error amplifier can be modeled using an ideal voltage controlled current  
source. The resistor Roea (2.38 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency  
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the  
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of  
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the  
overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the  
appropriate load step amplitude and step rate in a time domain analysis.  
PH  
VOUT  
Power Stage  
16 A/V  
a
b
RESR  
R1  
RL  
COMP  
c
C
O
VSENSE  
R2  
0.8 V  
Coea  
Roea  
R3  
C1  
gm  
1300 mA/V  
C2  
Figure 30. Small Signal Model for Loop Response  
Simple Small Signal Model for Peak Current Mode Control  
Figure 31 is a simple small signal model that can be used to understand how to design the frequency  
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle  
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is  
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the  
change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage  
transconductance (gmps) which is 16 A/V for the device. The DC gain of the power stage is the product of gmps  
and the load resistance (RL) as shown in Equation 11 with resistive loads. As the load current increases, the DC  
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole  
moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 32.  
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover  
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.  
18  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
VOUT  
VC  
RESR  
RL  
gm  
ps  
CO  
Figure 31. Simplified Small Signal Model for Peak Current Mode Control  
VOUT  
Adc  
VC  
RESR  
fp  
RL  
gm  
ps  
CO  
fz  
Figure 32. Simplified Frequency Response for Peak Current Mode Control  
æ
ç
è
s
ö
÷
ø
1+  
2p ´ ¦z  
VOUT  
VC  
= Adc ´  
æ
ö
÷
ø
s
1+  
ç
2p ´ ¦p  
è
(10)  
(11)  
Adc = gmps ´ RL  
1
¦p =  
C
´ R ´ 2p  
O
L
(12)  
(13)  
1
¦z =  
C
´ R  
´ 2p  
ESR  
O
Where  
gmea is the GM amplifier gain ( 1300µA/V)  
gmps is the power stage gain (16A/V).  
RL is the load resistance  
CO is the output capacitance.  
RESR is the equivalent series resistance of the output capacitor.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
Small Signal Model for Frequency Compensation  
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly  
used frequency compensation circuits shown in Figure 33. In Type 2A, one additional high frequency pole is  
added to attenuate high frequency noise.  
The design guideline below are provided for advanced users who prefer to compensate using the general  
method. The step-by-step design procedure described in the application section may also be used.  
VOUT  
R1  
VSENSE  
Type 2A  
Type 2B  
COMP  
Coea  
Vref  
R3  
C1  
gm  
C2  
R3  
C1  
ea  
Roea  
R2  
Figure 33. Types of Frequency Compensation  
The general design guidelines for device loop compensation are as follows  
1. Determine the crossover frequency fc  
2. R3 can be determined by  
2p ´ ¦c ´ VOUT ´ Co  
R3 =  
gm  
´ Vref ´ gm  
ps  
ea  
(14)  
Where  
gmea is the GM amplifier gain ( 1300µA/V)  
gmps is the power stage gain (16A/V).  
Vref is the reference voltage (0.8V)  
æ
ç
è
ö
÷
ø
1
¦p =  
CO ´ RL ´ 2p  
3. Place a compensation zero at the dominant pole  
C1 can be determined by  
RL ´ Co  
.
C1 =  
R3  
(15)  
4. C2 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output  
capacitor Co.  
RESR ´ Co  
C2 =  
R3  
(16)  
20  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
APPLICATION INFORMATION  
Design Guide – Step-By-Step Design Procedure  
This example details the design of a high frequency switching regulator design using ceramic output capacitors.  
A few parameters must be known in order to start the design process. These parameters are typically determined  
at the system level. For this example, we start with the following known parameters:  
Parameter  
Output Voltage  
Value  
3.3 V  
Output Current  
6 A  
Transient Response 1A load step  
Input Voltage  
ΔVout = 5 %  
12 V nominal, 8 V to 17 V  
33 mV p-p  
6.528 V  
Output Voltage Ripple  
Start Input Voltage (Rising Vin)  
Stop Input Voltage (Falling Vin)  
Switching Frequency  
6.190 V  
480 kHz  
Typical Application Schematic  
The application schematic of Figure 34 was developed to meet the requirements above. This circuit is available  
as the TPS54620EVM-374 evaluation module. The design procedure is given in this section.  
Figure 34. Typical Application Circuit  
Operating Frequency  
The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and  
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower  
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.  
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and  
thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a  
small solution size and a high efficiency operation.  
Output Inductor Selection  
To calculate the value of the output inductor, use Equation 17. KIND is a coefficient that represents the amount  
of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the  
output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor  
since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In  
general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3  
for the majority of applications.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Link(s) :TPS54620  
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
Vinmax - Vout  
Io ×Kind  
Vout  
L1 =  
×
Vinmax × f sw  
(17)  
For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 uH. For this design, a  
nearest standard value was chosen: 3.3 uH. For the output filter inductor, it is important that the RMS current and  
saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 19  
and Equation 20.  
Vinmax - Vout  
Vout  
Iripple =  
×
L1  
Vinmax × f sw  
(18)  
æ
ö2  
V × Vinmax - Vo  
(
)
1
o
ILrms = Io2 +  
ILpeak = Iout +  
×
ç
ç
÷
÷
12  
Vinmax×L1× f sw  
è
ø
(19)  
(20)  
Iripple  
2
For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor  
is a Coilcraft MSS1048 series 3.3 uH. It has a saturation current rating of 7.38 A and a RMS current rating of  
7.22 A.  
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,  
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current  
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of  
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current  
rating equal to or greater than the switch current limit rather than the peak inductor current.  
Output Capacitor Selection  
There are three primary considerations for selecting the value of the output capacitor. The output capacitor  
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in  
load current. The output capacitance needs to be selected based on the more stringent of these three criteria  
The desired response to a large change in the load current is the first criteria. The output capacitor needs to  
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up  
times for the regulator where the output capacitor must hold the output voltage above a certain level for a  
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply  
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning  
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the  
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor  
must be sized to supply the extra current to the load until the control loop responds to the load change. The  
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing  
a tolerable amount of droop in the output voltage. Equation 21 shows the minimum output capacitance necessary  
to accomplish this.  
2×DIout  
Co >  
f sw ×DVout  
(21)  
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the  
allowable change in the output voltage. For this example, the transient load response is specified as a 5%  
change in Vout for a load step of 1A. For this example, ΔIout = 1.0 A and ΔVout= 0.05 x 3.3 = 0.165 V. Using  
these numbers gives a minimum capacitance of 25 µF. This value does not take the ESR of the output capacitor  
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in  
this calculation.  
Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification.  
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the  
inductor ripple current. In this case, the maximum output voltage ripple is 33mV. Under this requirement,  
Equation 22 yields 13.2uF.  
22  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
 
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
1
1
Co >  
×
Voripple  
Iripple  
8× f sw  
(22)  
Equation 23 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple  
specification. Equation 23 indicates the ESR should be less than 19.7 mOhm. In this case, the ceramic caps’  
ESR is much smaller than 19.7 mOhm.  
Voripple  
Resr <  
Iripple  
(23)  
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this  
minimum value. For this example, a 47 µF 6.3V X5R ceramic capacitor with 3 milliohms of ESR is be used.  
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing  
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor  
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 24 can be used  
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 24 yields  
485mA.  
Vout × Vinmax - Vout  
(
12 ×Vinmax×L1× f sw  
)
Icorms =  
(24)  
Input Capacitor Selection  
The TPS54620 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 uF of  
effective capacitance on the PVIN input voltage pins and 4.7 uF on the Vin input voltage pin. In some  
applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance  
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input  
voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the  
TPS54620. The input ripple current can be calculated using Equation 25.  
Vinmin - Vout  
(
)
Vout  
Icirms = Iout ×  
×
Vinmin  
Vinmin  
(25)  
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the  
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that  
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors  
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output  
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor  
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at  
least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 µF and  
one 4.7 uF 25 V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the  
TPS54620 may operate from a single supply. The input capacitance value determines the input ripple voltage of  
the regulator. The input voltage ripple can be calculated using Equation 26. Using the design example values,  
Ioutmax=6 A, Cin=14.7 µF, Fsw=480 kHz, yields an input voltage ripple of 213 mV and a rms input ripple current  
of 2.95 A.  
Ioutmax ×0.25  
DVin =  
Cin× f sw  
(26)  
Slow Start Capacitor Selection  
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its  
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This  
is also used if the output capacitance is very large and would require large amounts of current to quickly charge  
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the  
TPS54620 reach the current limit or excessive current draw from the input power supply may cause the input  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Link(s) :TPS54620  
 
 
 
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor  
value can be calculated using Equation 27. For the example circuit, the soft start time is not too critical since the  
output capacitor value is 47 µF which does not require much current to charge to 3.3 V. The example circuit has  
the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF capacitor. In TPS54620, Iss is 2.3  
uA and Vref is 0.8V.  
Tss(ms)×Iss(mA)  
C7 =  
Vref(V)  
(27)  
Bootstrap Capacitor Selection  
A 0.1 uF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is  
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or  
higher voltage rating.  
Under Voltage Lockout Set Point  
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.  
R3 is connected between VIN and the EN pin of the TPS54620 and R4 is connected between EN and GND .  
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or  
brown outs when the input voltage is falling. For the example design, the supply should turn on and start  
switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts  
switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or dissable).  
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the  
stop voltages specified the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ.  
Output Voltage Feedback Resistor Selection  
The resistor divder nework R5 and R6 is used to set the output voltage.For the example design, 10 kOhm was  
selected for R6. Using Equation 28, R5 is calculated as 31.25 kOhm. The nearest standard 1% resistor is 31.6  
kOhm.  
Vo - Vref  
R5 =  
R6  
Vref  
(28)  
Minimum Output Voltage  
Due to the internal design of the TPS54620, there is a minimum output voltage limit for any given input voltage.  
The output voltage can never be lower than the internal vlotage reference of 0.8 V. Above 0.8 V, the ouyput  
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by  
Equation 29  
Voutmin = ontimemin ×Fsmax × Ioutmin × RDS2min  
(
- Ioutmin × RL + RDS2min  
)
)
)
(
)
(
(
(29)  
Where:  
Voutmin = minimum achieveable output voltage  
Ontimemin = minimum controllable on-time (135 nsec maximum)  
Fsmax = maximum switching frequency including tolerance  
Vinmax = maximum input voltage  
Ioutmax = minimum load current  
RDS1min = minimum high side MOSFET on resistance (36-32 mΩ typical)  
RDS2min = minimum low side MOSFET on resistance (19 mΩ typical)  
RL = series resistance of output inductor  
Compensation Component Selection  
There are several industry techniques used to compensate DC/DC regulators. The method presented here is  
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between  
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to  
the TPS54620. Since the slope compensation is ignored, the actual cross over frequency is usually lower than  
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.  
24  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
 
 
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 30 and Equation 31.  
For Cout, use a derated value of 22.4 µf. use Equation 32 and Equation 33 to estimate a starting point for the  
closed loop crossover frequency fco. Then the required compensation components may be derived. For this  
design example, fpmod is 12.9 kHz and fzmod is 2730 kHz. Equation 32 is the geometric mean of the modulator  
pole and the esr zero and Equation 33 is the geometric mean of the modulator pole and one half the switching  
frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this  
case Equation 32 yields 175 kHz and Equation 33 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher  
frequency of 60.5 kHz is chosen as the intended crossover frequency.  
Iout  
f pmod =  
2×p ×Vout ×Cout  
1
(30)  
f zmod =  
2 ×p ×RESR ×Cout  
(31)  
(32)  
f co = f pmod× f zmod  
f sw  
f co = f pmod×  
2
(33)  
Now the compensation components can be calculated.First claculate the value for R2 which sets the gain of the  
compensated network at the crossover frequency. Use Equation 34 to determine the value of R2.  
2p × f c × Vout×Cout  
R2 =  
Gm×Vref ×VIgm  
(34)  
Next calcutlate the value of C3. Together with R2, C3 places a compensation sero at the modulator pole  
frequency. Equation 35 to determine the value of C3.  
Vout ×Cout  
C3 =  
Iout ×R2  
(35)  
Using Equation 34 and Equation 35 the standard values for R2 and C3 are 1.69 kΩ and 8200 pF.  
An additional high frequency pole can be used if necessary by adding a capcitor in parallel with the series  
combination of R2 and C3. The pole frequency is given by Equation 36. This pole is not used in this design.  
1
f p =  
2×p ×R2×Cp  
(36)  
Application Curves  
LOAD TRANSIENT  
STARTUP with VIN  
Vin = 10 V / div  
Vout = 50 mV / div (ac coupled)  
EN = 2 V / div  
Iout = 2A / div (1.5 A to 4.5 load step)  
SS/TR = 1 V / div  
Vout = 2 V / div  
Time = 500 μsec / div  
Time = 2 msec / div  
Figure 35.  
Figure 36.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Link(s) :TPS54620  
 
 
 
 
 
 
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
STARTUP with EN  
STARTUP with PRE-BIAS  
Vin = 5 V / div  
Vin = 10 V / div  
EN = 2 V / div  
Vout = 2 V / div  
SS/TR = 1 V / div  
Vout starting from pre-bias voltage  
Vout = 2 V / div  
Time = 2 msec / div  
Time = 20 msec / div  
Figure 37.  
Figure 38.  
SHUTDOWN with VIN  
Vin = 10 V / div  
SHUTDOWN with EN  
Vin = 10 V / div  
EN = 2 V / div  
EN = 2 V / div  
SS/TR = 1 V / div  
SS/TR = 1 V / div  
Vout = 2 V / div  
Vout = 2 V / div  
Time = 2 msec / div  
Time = 2 msec / div  
Figure 39.  
Figure 40.  
OUTPUT VOLTAGE RIPPLE with NO LOAD  
Vout = 10 mV / div (ac coupled)  
OUTPUT VOLTAGE RIPPLE with FULL LOAD  
Vout = 10 mV / div (ac coupled)  
PH = 5 V / div  
PH = 5 V / div  
Time = 1 μsec / div  
Time = 1 μsec / div  
Figure 41.  
Figure 42.  
26  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
INPUT VOLTAGE RIPPLE with NO LOAD  
INPUT VOLTAGE RIPPLE with FULL LOAD  
Vin = 200 mV / div (ac coupled)  
Vin = 200 mV / div (ac coupled)  
PH = 5 V / div  
PH = 5 V / div  
Time = 1 μsec / div  
Time = 1 μsec / div  
Figure 43.  
Figure 44.  
CLOSED LOOP RESPONSE  
LINE REGULATION  
0.05  
0.04  
0.03  
0.02  
0.01  
0
180  
150  
60  
50  
120  
40  
Phase  
90  
30  
60  
20  
Gain  
30  
10  
0
0
Io = 3A  
Io = 0A  
-30  
-60  
-90  
-120  
-150  
-180  
-10  
-20  
-30  
-40  
-50  
-60  
-0.01  
-0.02  
-0.03  
-0.04  
-0.05  
Io = 6A  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
Frequency - Hz  
Input Voltage - V  
Figure 45.  
Figure 46.  
LOAD REGULATION  
TRACKING PERFORMANCE  
0.05  
0.04  
0.03  
0.02  
0.01  
0
10  
10  
Vin = 12 V  
Vout  
1
1
0.1  
0.1  
Ideal Vsense  
Vsense  
0.01  
0.001  
0.01  
0.001  
0.0001  
0.00001  
-0.01  
-0.02  
-0.03  
-0.04  
-0.05  
0.0001  
0.00001  
0.001  
0.01  
0.1  
1
10  
0
1
2
3
4
5
6
7
8
Track In Voltage - V  
Output Current - A  
Figure 47.  
Figure 48.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
27  
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
MAXIMUM AMBIENT TEMPERATURE  
MAXIMUM AMBIENT TEMPERATURE  
vs  
vs  
LOAD CURRENT  
IC POWER DISSIPATION  
150  
150  
Tjmax = 150 °C,  
no air flow  
125  
100  
125  
100  
75  
75  
50  
25  
V
V
= 12 V,  
IN  
= 3.3 V,  
50  
25  
OUT  
Fsw = 480 kHz,  
room temp, no air flow  
0
0.5  
1
1.5  
2
2.5  
3
- IC Power Dissipation - W  
3.5  
4
0
1
2
3
4
Load Current - A  
5
6
P
D
Figure 49.  
Figure 50.  
JUNCTION TEMPERATURE  
vs  
IC POWER DISSIPATION  
EFFICIENCY  
vs  
LOAD CURRENT  
150  
125  
100  
100  
95  
T
= room temperature,  
A
no air flow  
90  
85  
80  
75  
70  
65  
VOUT = 5 V  
VOUT = 3.3 V  
VOUT = 1.8 V  
VOUT = 1.2 V  
VOUT = 0.8 V  
75  
50  
25  
60  
55  
50  
VIN = 12 V  
Fsw = 500 kHz  
0
0.5  
1
1.5  
2
2.5  
3
Pic - IC Power Dissipation - W  
3.5  
4
0
1
2
3
4
5
6
Load Current - A  
Figure 51.  
Figure 52.  
Thermal Performance  
Figure 53. Thermal Signature of TPS54620EVM-374 Operating at  
VIN=12V,VOUT=3.3V/6A, TA = Room Temperature  
28  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
Fast Transient Considerations  
In applications where fast transinet responses are very important, the application circuit in Figure 34 can be  
modified as shown in Figure 54 which is a customized reference design (PMP4854-2, REV.B).  
The frequency responses of Figure 54 is shown in Figure 55. The crossover frequency is pushed much higher to  
118kHz and the phase margin is about 57Deg.  
Figure 54. 3.3V Output Power Supply Design (PMP4854-2) with Fast Transients  
Figure 55. Closed Loop Response for PMP4854-2  
PCB Layout Guidelines  
Layout is a critical portion of good power supply design. See Figure 56 for a PCB layout example. The top layer  
contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the  
remaining pins of the TPS54620 and a large top side area filled with ground. The top layer ground area sould be  
connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter cpacitor and  
directly under the TPS54620 device to provide a thermal path from the PowerPAD™ land to ground. The GND  
pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the  
top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There  
are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance  
or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these  
problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or  
X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the  
PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
29  
Product Folder Link(s) :TPS54620  
 
 
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quite analog ground trace rather  
than the power ground trace of the PVIn bypass capacitor. Since the PH connection is the switching node, the  
output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent  
excessive capacitive coupling.The output filter capacitor ground should use the same power ground trace as the  
PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small  
signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to  
noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of  
trace. The additional external components can be placed approximately as shown. It may be possible to obtain  
acceptable performance with alternate PCB layouts, however this layout has been shown to produce good  
results and is meant as a guideline.  
30  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
TPS54620  
www.ti.com ........................................................................................................................................................................................................ SLVS949–MAY 2009  
TOPSIDE  
GROUND  
AREA  
FREQUENCY SET RESISTOR  
OUTPUT  
FILTER  
CAPACITOR  
PVIN  
INPUT  
BYPASS  
CAPACITOR  
RT/CLK  
PWRGD  
BOOT  
CAPACITOR  
GND  
GND  
PVIN  
PVIN  
VIN  
BOOT  
PH  
OUTPUT  
INDUCTOR  
EXPOSED  
POWERPAD  
AREA  
PH  
VOUT  
PH  
EN  
SS/TR  
V_SNS  
COMP  
PVIN  
VIN  
SLOW START  
CAPACITOR  
UVLO SET  
RESISTORS  
VIN  
INPUT  
BYPASS  
CAPACITOR  
COMPENSATION  
NETWORK  
FEEDBACK  
RESISTORS  
ANALOG GROUND TRACE  
VIA to Ground Plane  
Etch Under Component  
Figure 56. PCB Layout  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
31  
Product Folder Link(s) :TPS54620  
TPS54620  
SLVS949–MAY 2009........................................................................................................................................................................................................ www.ti.com  
Figure 57. Ultra-Small PCB layout Using TPS54620 (PMP4854-2)  
Estimated Circuit Area  
The estimated printed circuit board area for the components used in the design of Figure 34 is 0.58. in2 (374  
mm2). This area does not include test points or connectors.  
The board area can be further reduced if size is a big concern in an application. Figure 57 shows the printed  
circuit board layout for PMP4854-2 as shown in Figure 54 whose board area is as small as 17.27 mm x 11.30  
mm.  
32  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s) :TPS54620  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
2-Jun-2009  
PACKAGING INFORMATION  
Orderable Device  
TPS54620RGYR  
TPS54620RGYT  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
QFN  
RGY  
14  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
QFN  
RGY  
14  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
10-Jul-2009  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
TPS54620RGYR  
TPS54620RGYT  
QFN  
QFN  
RGY  
RGY  
14  
14  
1000  
250  
180.0  
180.0  
12.4  
12.4  
3.85  
3.85  
3.85  
3.85  
1.35  
1.35  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
10-Jul-2009  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS54620RGYR  
TPS54620RGYT  
QFN  
QFN  
RGY  
RGY  
14  
14  
1000  
250  
190.5  
190.5  
212.7  
212.7  
31.8  
31.8  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Amplifiers  
Applications  
Audio  
Automotive  
Broadband  
Digital Control  
Medical  
Military  
Optical Networking  
Security  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
www.ti.com/audio  
Data Converters  
DLP® Products  
DSP  
Clocks and Timers  
Interface  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/medical  
www.ti.com/military  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
dsp.ti.com  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
power.ti.com  
microcontroller.ti.com  
www.ti-rfid.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
Telephony  
Video & Imaging  
Wireless  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2009, Texas Instruments Incorporated  

相关型号：

TPS54620RHL

 IC SWITCHING REGULATOR, 1760 kHz SWITCHING FREQ-MAX, PQCC14, 3.50 X 3.50 MM, PLASTIC, QFN-14, Switching Regulator or Controller
TI

TPS54620RHLR

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter
TI

TPS54620RHLT

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter
TI

TPS54620_1002

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT™ Converter
TI

TPS54620_11

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter
TI

TPS54620_16

 4.5-V to 17-V Input, 6-A Synchronous Step Down SWIFT Converter
TI

TPS54622

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter With Hiccup
TI

TPS54622-EP

 增强型产品 17V、6A 同步降压转换器
TI

TPS54622RHLR

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter With Hiccup
TI

TPS54622RHLREP

 增强型产品 17V、6A 同步降压转换器 | RHL | 14 | -55 to 125
TI

TPS54622RHLT

 4.5V to 17V Input, 6A Synchronous Step Down SWIFT? Converter With Hiccup
TI

TPS54622_17

 4.5-V to 17-V Input, 6-A Synchronous Step-Down SWIFT Converter With Hiccup Protection
TI
©2020 ICPDF网 联系我们和版权申明