TPS54626 [TI]
采用 HTSSOP 封装、具有 Eco-Mode 的 4.5V 至 18V、6.5A 同步降压转换器;型号: | TPS54626 |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 HTSSOP 封装、具有 Eco-Mode 的 4.5V 至 18V、6.5A 同步降压转换器 转换器 |
文件: | 总23页 (文件大小:1326K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
具有 ECO-Mode™ 的 4.5V 至 18V 输入,6.5A 同步降压 SWIFT™ 转换器
查询样品: TPS54626
1
特性
说明
23
•
D-CAP2™ 模式支持快速瞬态响应
低输出纹波,支持陶瓷输出电容器
宽 VIN 输入电压范围:4.5V 至 18V
输出电压范围:0.76V 至 5.5V
TPS54626 是一款自适应接通时间 D-CAP2™ 模式同
步降压转换器。 TPS54626 可帮助系统设计人员用成
本有效、低组件数量、低待机电流解决方案来完成不同
终端设备的电源总线调节器集。 TPS54626 的主控制
环路采用 D-CAP2™ 模式控制,此模式无需外部补偿
组件便可实现极快的瞬态响应。 自适应接通时间支持
高负载条件下脉宽调制 (PWM) 模式与轻负载下减频运
行之间的无缝操作,以实现高效率。 TPS54626 的专
有电路还可使该器件能够适应诸如高分子聚合物电容器
(SP-CAP) 等低等效串联电阻 (ESR) 输出电容器以及
超低 ESR 陶瓷电容器。 该器件在 4.5V 至 18V 的 VIN
输入电源电压范围内运行。 输出电压可在 0.76V 与
5.5V 之间设定。该器件还特有一个可调软启动时间和
一个电源正常功能。 TPS54626 采用 14 引脚散热薄
型小外形尺寸 (HTSSOP) 封装,设计工作温度介于 -
40°至 85° 之间。
•
•
•
•
高效率集成型场效应晶体管 (FET) 针对更低占空比
应用进行了优化 - 36mΩ(高侧)与ꢀ28
mΩ(低侧)
•
•
•
•
•
•
•
•
关断时的高效率,流耗不足 10μA
高初始带隙基准精度
可调软启动
预偏置软启动
650kHz 开关频率 (fSW
)
逐周期限流
电源正常输出
自动跳跃 Eco-mode™ 为了在轻负载下实现高效率
应用范围
Io = 50 mA – 6.5 A
S/R = 0.35 A/μs
•
低电压系统的广泛应用
–
–
–
–
数字电视电源
Vo (50 mV/div)
Io (2 A/div)
高清 Blu-ray Disc™ 播放器
网络家庭终端设备
数字机顶盒 (STB)
U1
TPS54626PWP
Time (100 μs/div)
L004_SLVSC34
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2, Eco-mode are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC34
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TA
PACKAGE(2) (3)
ORDERABLE PART NUMBER
PIN
TRANSPORT MEDIA
Tube
TPS54626PWP
–45°C to 85°C
PWP
14
TPS54626PWPR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
VIN1, VIN2, EN
VBST
V
V
26
VBST (10 ns transient)
VBST (vs Sw1, SW2)
VFB, VO, SS, PG
SW1, SW2
28
V
VI
Input voltage range
Output voltage range
6.5
6.5
20
V
V
V
SW1, SW2 (10 ns transient)
VREG5
–3
22
V
–0.3
–0.3
–0.2
6.5
0.3
0.2
2
V
VO
PGND1, PGND2
V
Vdiff
Voltage from GND to POWERPAD
Human Body Model (HBM)
Charged Device Model (CDM)
V
kV
V
ESD rating
Electrostatic discharge
500
150
150
TJ
Operating junction temperature
Storage temperature
–40
–55
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54626
THERMAL METRIC(1)
UNITS
PWP (14 PINS)
θJA
Junction-to-ambient thermal resistance
40.5
28.7
24.2
0.8
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
23.9
2.4
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
18
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3
24
VBST (10 ns transient)
VBST (vs SW)
SS, PG
27
6.0
5.7
18
VI
Input voltage range
EN
V
VO, VFB
5.5
18
SW1, SW2
SW1, SW2 (10 ns transient)
PGND1, PGND2
VREG5
21
–0.1
–0.1
0
0.1
5.7
5
VO
IO
Output voltage range
V
Output Current range
IVREG5
mA
kΩ
°C
°C
RPG
TA
TJ
Power Good resistor
25
150
85
Operating free-air temperature
Operating junction temperature
–40
–40
150
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, EN = 5 V,
VVFB = 0.8 V
IVIN
Operating - non-switching supply current
Shutdown supply current
950
3.6
1400
10
μA
μA
IVINSDN
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
En
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.6
VEN = 12 V
200
400
800
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB voltage light load mode, TA = 25°C,
VO = 1.05 V, IO = 10mA
772
765
TA = 25°C, VO = 1.05 V, continuous mode
757
753
773
777
VFBTH
VFB threshold voltage
mV
TA = 0°C to 85°C, VO = 1.05 V, continuous
mode(1)
TA = –40°C to 85°C, VO = 1.05 V, continuous
mode(1)
751
779
IVFB
VFB input current
VVFB = 0.8 V, TA = 25°C
0
±0.15
150
μA
RDischg
VO discharge resistance
VEN = 0 V, VO = 0.5 V, TA = 25°C
100
Ω
VREG5 OUTPUT
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 output voltage
5.2
20
5.5
5.7
V
IVREG5
MOSFET
Rdsonh
Output current
VIN = 6 V, VVREG5 = 4 V, TA = 25°C
mA
High side switch resistance
Low side switch resistance
TA = 25°C, VBST-SW1,2 = 5.5V
TA = 25°C
36
28
mΩ
mΩ
Rdsonl
(1) Not production tested.
Copyright © 2013, Texas Instruments Incorporated
3
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
Iocl Current limit
THERMAL SHUTDOWN
L = 1.5 μH(2)
,
7.2
8.2
9.5
A
(2)
Shutdown temperature
165
35
TSDN
Thermal shutdown threshold
°C
(2)
Hysteresis
ON-TIME TIMER CONTROL
TON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.7 V
150
260
ns
ns
TOFF(MIN)
Minimum off time
310
7.8
SOFT START
ISSC SS charge current
ISSD SS discharge current
POWER GOOD
VSS = 1.0 V
VSS = 0.5 V
4.2
1.5
6.0
3.3
μA
mA
VVFB rising (good)
VVFB falling (fault)
VPG = 0.5 V
85%
2.5
90%
85%
5
95%
VTHPG
IPG
PG threshold
PG sink current
mA
μs
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
Output OVP prop delay
OVP detect
120% 125% 130%
10
TOVPDEL
UVP detect
Hysteresis
60%
65%
10%
0.25
70%
VUVP
Output UVP trip threshold
TUVPDEL
TUVPEN
UVLO
Output UVP delay
ms
Output UVP enable delay
Relative to soft-start time
X 1.7
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.45
0.13
3.75
0.32
4.05
0.48
VUVLO
UVLO threshold
V
(2) Not production tested.
4
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
14
13
1
2
VIN2
VIN1
VO
VFB
3
4
5
VREG5
12
11
VBST
SW2
POWER PAD
SS
SW1
10
GND
6
7
9
PGND2
PGND1
PG
EN
8
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NUMBER
VO
1
2
Connect to output of converter. This pin is used for output discharge function.
Converter feedback input. Connect with feedback resistor divider.
VFB
5.5V power supply output. A Capacitor (typical 1µF) should be connected to GND. VREG5 is not active
when EN is low.
VREG5
3
SS
4
5
6
7
Soft start control. An external capacitor should be connected to GND.
Signal ground pin.
GND
PG
Open drain power good output
EN
Enable control input. EN is active high and must be pulled up to enable the device.
PGND1,
PGND2
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
GND strongly together near the IC.
8, 9
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
comparator.
SW1, SW2
10,11
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective
SW1,SW2 terminals. An internal PN diode is connected between VREG5 and VBST pin.
VBST
12
VIN1,VIN2
13,14
Power Input and connected to high side NFET drain.
Supply Input for 5V internal linear regulator for the control circuitry
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to
PGND
PowerPAD™
Back side
Copyright © 2013, Texas Instruments Incorporated
5
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
FUNCTIONAL BLOCK DIAGRAM (HTSSOP)
-35%
UV
OV
VIN
VIN2
VIN1
14
13
1
VO
+25%
VREG5
VBST
12
Control logic
1 shot
Ref
SS
SW2
SW1
VO
11
10
2
VFB
XCON
VREG5
SGND
VREG5
Ceramic
Capacitor
3
4
PGND2
PGND1
SS
9
8
1mF
SW
Softstart
ZC
SS
PGND
PGND
5
GND
SW
OCP
PGND
SGND
PG
Ref
-10%
VI
N
6
UV
VREG5
OV
UVLO
TSD
Protection
Logic
UVLO
Ref
EN
EN
7
Logic
REF
OVERVIEW
The TPS54626 is a 6.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54626 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
6
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54626 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54626 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage. Therefore, when duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode™ Control
The TPS54626 is designed with Auto-Skip mode to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
V -V
IN OUT
×V
)
OUT
(
1
IOUT(LL)
=
×
2×L×fSW
V
IN
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 μA.
C
(nF) x V
´1.1
C
(nF) x 0.765´1.1
SS
REF
SS
t
(ms) =
=
SS
I
(mA)
6
SS
(2)
TPS54626 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
Power Good
The TPS54626 has power good open drain output. The power-good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage
becomes within –10% of the target value, internal comparators detect power good state and the power good
signal becomes high. Rpg resistor value, which is connected between PG and VREG5, is required from 25kΩ to
150kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low.
Output Discharge Control
TPS54626 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The device discharges the output using an internal 100-Ω MOSFET which is
connected from VO to PGND.ꢀThe internal low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output.
Copyright © 2013, Texas Instruments Incorporated
7
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the measured voltage is
above the voltage proportional to the current limit, then the device constantly monitors the low side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and new switching cycle begins. IN subsequent
switching cycles, the on-time is set to fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold. Also, when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output under-voltage protection circuit to be activated. This protection itself is non-
latching.
Over/Under Voltage Protection
TPS54626 detects over and under voltage conditions by monitoring the feedback voltage (VFB). This function is
enabled after approximately 1.7 x times the softstart time.
When the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes
high and the circuit latches and both the high-side MOSFET driver and the low-side MOSFET driver turn off.
When the feedback voltage becomes lower than 65% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins. After 250us, the device latches off both internal top and bottom
MOSFET.
UVLO Protection
Under voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54626 is shut off. This is protection is non-latching.
Thermal Shutdown
Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 165°C),
the TPS54626 is shut off. This protection is non-latching.
8
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25 °C (unless otherwise noted)
Vin CURRENT
Vin SHUTDOWN CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1200
1000
800
14
12
10
8
EN = 0 V
600
6
400
4
200
2
Vin = 12 V
150
Vin = 12 V
100 150
EN = 5 V
0
0
0
50
100
0
50
±50
±50
Junction Temperature (C)
Junction Temperature (C)
C001
C002
Figure 1.
Figure 2.
EN CURRENT
vs
EN VOLTAGE
1.05V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
50
45
40
35
30
25
20
15
10
5
1.100
1.075
1.050
1.025
1.000
Vo = 1.05 V
Vin = 12 V
Vin = 5 V
Vin = 12 V
Vin = 18 V
0
0
5
10
15
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Output Current (A)
EN Input Voltage (V)
C003
C004
Figure 3.
Figure 4.
Copyright © 2013, Texas Instruments Incorporated
9
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25 °C (unless otherwise noted)
1.05V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.05 V 0.05A to 6.5A LOAD TRANSIENT RESPONSE
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
Io = 50 mA – 6.5 A
S/R = 0.35 A/μs
Vo (50 mV/div)
Io (2 A/div)
Io = 10 mA
Io = 1 A
Time (100 μs/div)
0
5
10
15
20
L004_SLVSC34
Input Voltage (V)
C005
Figure 5.
Figure 6.
EFFICIENCY vs OUTPUT CURRENT
STARTUP WAVEFORM
100
90
80
70
60
50
40
EN (10 V/div)
Vi = 12 V
VREG (5 V/div)
Vo (0.5 V/div)
Vo = 1.8 V
Vo = 3.3 V
Vo = 5 V
Io = 0 A
Css = 8200 pF
Time (1 ms/div)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
L003_SLVSC34
Output Current (A)
C006
Figure 7.
Figure 8.
10
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25 °C (unless otherwise noted)
LIGHT LOAD EFFICIENCY
SWITCHING FREQUENCY
vs
vs
OUTPUT CURRENT
INPUT VOLTAGE (IO=1A)
100
90
80
70
60
50
40
30
20
10
0
850
800
750
700
650
600
550
500
450
400
Vi = 12 V
Vo = 1.05 V
Vo = 1.2 V
Vo = 1.5 V
Vo = 1.8 V
Vo = 2.5 V
Vo = 3.3 V
Vo = 5 V
Vo = 1.8 V
Vo = 3.3 V
Vo = 5 V
0.001
0.01
0.1
0
5
10
15
20
Output Current (A)
Input Voltage (V)
C007
C008
Figure 9.
Figure 10.
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
VFB VOLTAGE vs JUNCTION TEMPERATURE
900
0.780
0.775
0.770
0.765
0.760
0.755
0.750
Vin = 12 V
Io = 1 A
800
700
600
500
400
300
200
100
0
Vo=1.05V
Vo=1.8V
Vo=3.3V
VFB
0.01
0.1
Output Current (A)
1
10
0
50
100
150
±50
Junction Temperature (C)
C009
C010
Figure 11.
Figure 12.
Copyright © 2013, Texas Instruments Incorporated
11
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25 °C (unless otherwise noted)
OUTPUT CURRENT
vs
AMBIENT TEMPERATURE
VOLTAGE RIPPLE AT INTPUT (IO=6.5A)
7
6
5
4
3
2
1
0
Vo = 1.05 V
Io = 6.5 A
Vi (50 mV/div)
SW (5 V/div)
Vo = 1.05 V
Vo = 1.8 V
Vo = 2.5 V
Vo = 3.3 V
Vo = 5 V
Time (1 ms/div)
0
20
40
60
80
100
L001_SLVSC34
Ambient Temperature (C)
C011
Figure 13.
Figure 14.
VOLTAGE RIPPLE AT OUTPUT (IO=6.5A)
Vo = 1.05 V
Io = 6.5 A
Vo (10 mV/div)
SW (5 V/div)
Time (100 μs/div)
L002_SLVSC34
Figure 15.
12
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
U1
TPS54626PWP
1.05V, 6.5A
Figure 16. Schematic
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1
VOUT = 0.765 •
(
1 +
)
R2
(3)
Output Filter Selection
The output filter used with the TPS54626 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54626. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Copyright © 2013, Texas Instruments Incorporated
13
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
Table 1. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
6.81
8.25
12.7
21.5
30.1
49.9
73.2
124
R2 (kΩ)
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
C4 (pF)(1)
5 - 220
5 - 220
5 - 100
5 - 68
L1 (µH)
C8 + C9 (µF)
1
1.05
1.2
1.5
1.8
2.5
3.3
5
1.0 - 1.5 - 4.7
1.0 - 1.5 - 4.7
1.0 - 1.5 - 4.7
1.0 - 1.5 - 4.7
1.2 - 1.5 - 4.7
1.5 - 2.2 – 4.7
1.8 - 2.2 – 4.7
2.5 - 3.3 – 4.7
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
5 - 22
5 - 22
5 - 22
5 - 22
(1) Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW
.
Use 650 kHz for fSW. and also use 1.5µH for LO Make sure the chosen inductor is rated for the peak current of
Equation 6 and the RMS current of Equation 7.
VIN (max) - VOUT
LO · fSW
VOUT
VIN (max)
·
Ilp - p =
(5)
(6)
(7)
Ilp - p
Ilpeak = IO +
2
2
IO +
√
Ilp - p2
1
12
ILo(RMS)
=
For this design example, the calculated peak current is 7.01 A and the calculated RMS current is 6.51 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54626 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor
•
VOUT
√12 •
(VIN - VOUT)
ICO(RMS)
=
•
• fSW
VIN
LO
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.
Input Capacitor Selection
The TPS54626 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 uF. is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1-μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
14
Copyright © 2013, Texas Instruments Incorporated
TPS54626
www.ti.com.cn
ZHCSBE3 –AUGUST 2013
THERMAL INFORMATION
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
14
Thermal Pad
2.46
°
7
1
2.31
Figure 17. Thermal Pad Dimensions
Copyright © 2013, Texas Instruments Incorporated
15
TPS54626
ZHCSBE3 –AUGUST 2013
www.ti.com.cn
LAYOUT CONSIDERATIONS
1. A top side area should be filled with ground as much as possible due to relatively higher current output
device.
2. The ground area under the device thermal pad should be large as possible and directly connect to the
thermal pad. Also 2nd, 3rd and 4th PCB layer should be connected to ground directly from the thermal pad.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.
VIN
Additional
Thermal
Vias
VIN
INPUT
BYPASS
CAPACITOR
VIN OVER
CURRENT
STABILITY
CAPACITOR
EXPOSED
POWERPAD
AREA
FEEDBACK
RESISTORS
VOUT
VFB
VREG5
SS
VIN2
VIN1
BOOST
CAPACITOR
VBST
SW1
VOUT
BIAS
CAP
GND
PG
SW2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
PGND1
PGND2
SLOW
START
CAP
EN
Connection to
POWER GROUND
on internal or
ANALOG
GROUND
TRACE
Additional
Thermal
Vias
bottom layer
To Enable
Control
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 18. PCB Layout for PWP Package
16
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54626PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
14
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
PS54626
PS54626
TPS54626PWPR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X (0.6)
NOTE 5
2X (0.4)
NOTE 5
THERMAL
PAD
7
8
0.25
1.2 MAX
GAGE PLANE
2.59
1.89
15
0.15
0.05
0.75
0.50
0 -8
A
20
1
14
DETAIL A
TYPICAL
2.6
1.9
4229706/A 06/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.6)
METAL COVERED
BY SOLDER MASK
SYMM
14X (1.5)
(1.2) TYP
14
14X (0.45)
1
(5)
NOTE 9
(R0.05) TYP
SYMM
(0.6)
15
(2.59)
12X (0.65)
7
8
(
0.2) TYP
VIA
SEE DETAILS
(1.1) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4229706/A 06/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.6)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
14X (1.5)
14X (0.45)
14
1
(R0.05) TYP
(2.59)
SYMM
15
BASED ON
0.125 THICK
STENCIL
12X (0.65)
7
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 12X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 2.90
2.60 X 2.59 (SHOWN)
2.37 X 2.36
0.125
0.15
0.175
2.20 X 2.19
4229706/A 06/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023,德州仪器 (TI) 公司
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