TPS54680MPWPREP_技术文档

Typical Size

6,4 mm X 9,7 mm

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SGLS212 − OCTOBER 2003

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FEATURES

APPLICATIONS

D

Low-Voltage, High-Density Distributed Power

Systems

D

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors Requiring Sequencing

D

Extended Temperature Performance of −40°C

to 125°C

D

Broadband, Networking and Optical

Communications Infrastructure

Enhanced Diminishing Manufacturing

Sources (DMS) Support

D

Enhanced Product-Change Notification

DESCRIPTION

(1)

Qualification Pedigree

As a member of the SWIFT family of dc/dc regulators,

the TPS54680 low-input voltage high-output current

synchronous buck PWM converter integrates all

required active components. Using the TRACKIN pin

with other regulators, simultaneous power up and down

are easily implemented. Included on the substrate with

the listed features are a true, high performance, voltage

error amplifier that enables maximum performance and

flexibility in choosing the output filter L and C

components; an under-voltage-lockout circuit to

prevent start-up until the input voltage reaches 3 V; an

internally or externally set slow-start circuit to limit

inrush currents; and a power good output useful for

processor/logic reset.

Power Up/Down Tracking For Sequencing

30-mΩ, 12-A Peak MOSFET Switches for High

Efficiency at 6-A Continuous Output Source

or Sink Current

D

Wide PWM Frequency:

Fixed 350 kHz or Adjustable 280 kHz to

700 kHz

D

Power Good and Enable

Load Protected by Peak Current Limit and

Thermal Shutdown

D

Integrated Solution Reduces Board Area and

Component Count

The TPS54680 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD package, which

eliminates bulky heatsinks. TI provides evaluation

modules and the SWIFT designer software tool to aid

in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

(1)

Componentqualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetalliclife, and mold compound life. Such qualification testing

should not be viewed as justifying use of this component beyond

specified performance and environmental limits.

ORDERING INFORMATION

T

J

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

(1)

−40°C to 125°C

0.9 V to 3.3 V

Plastic HTSSOP (PWP)

TPS54680QPWPREP

(1)

See the application section of the data sheet for PowerPAD drawing and layout information.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of Texas Instruments.

ꢁꢒ ꢌ ꢛꢏ ꢓ ꢀꢍ ꢌꢎ ꢛ ꢑꢀꢑ ꢡꢢ ꢣꢤ ꢥ ꢦꢧ ꢨꢡꢤꢢ ꢡꢝ ꢩꢪ ꢥ ꢥ ꢫꢢꢨ ꢧꢝ ꢤꢣ ꢬꢪꢭ ꢮꢡꢩ ꢧꢨꢡ ꢤꢢ ꢯꢧ ꢨꢫꢰ ꢁꢥ ꢤꢯꢪ ꢩꢨꢝ

ꢩ ꢤꢢ ꢣꢤꢥ ꢦ ꢨꢤ ꢝ ꢬꢫ ꢩ ꢡ ꢣꢡ ꢩ ꢧ ꢨꢡ ꢤꢢꢝ ꢬ ꢫꢥ ꢨꢱꢫ ꢨꢫ ꢥ ꢦꢝ ꢤꢣ ꢀꢫꢲ ꢧꢝ ꢍꢢꢝ ꢨꢥ ꢪꢦ ꢫꢢꢨ ꢝ ꢝꢨ ꢧꢢꢯ ꢧꢥ ꢯ ꢳ ꢧꢥ ꢥ ꢧ ꢢꢨꢴꢰ

ꢁꢥ ꢤ ꢯꢪꢩ ꢨ ꢡꢤ ꢢ ꢬꢥ ꢤ ꢩ ꢫ ꢝ ꢝ ꢡꢢ ꢵ ꢯꢤ ꢫ ꢝ ꢢꢤꢨ ꢢꢫ ꢩꢫ ꢝꢝ ꢧꢥ ꢡꢮ ꢴ ꢡꢢꢩ ꢮꢪꢯ ꢫ ꢨꢫ ꢝꢨꢡ ꢢꢵ ꢤꢣ ꢧꢮ ꢮ ꢬꢧ ꢥ ꢧꢦ ꢫꢨꢫ ꢥ ꢝꢰ

Copyright  2003, Texas Instruments Incorporated

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SGLS212 − OCTOBER 2003

SIMPLIFIED SCHEMATIC

STARTUP TIMING

I/O Supply

I/O

V

= 5 V

I

Input

Core Supply

f

= 700 kHz

s

VIN

PH

CORE

TPS54680

BOOT

PGND

TRACKIN

VSENSE

AGND COMP

VBIAS

PWRGD(I/O)

PWRGD(CORE)

t − Time − 500 µs/div

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

TPS54680-EP

−0.3 V to 7 V

−0.3 V to 6 V

−0.3 V to 4V

−0.3 V to 17 V

−0.3 V to 7 V

−0.6 V to 10 V

UNIT

VIN, ENA

RT

Input voltage range, V

V

I

VSENSE, TRACKIN

BOOT

VBIAS, COMP, PWRGD

Output voltage range, V

V

O

PH

Internally Limited

Source current, I

O

COMP, VBIAS

PH

6

mA

A

12

6

COMP

Sink current, I

S

mA

ENA, PWRGD

AGND to PGND

10

Voltage differential

0.3

V

Operating virtual junction temperature range, T

(2)

−40 to 150

−65 to 150

300

°C

J

Storage temperature, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

(2)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Long term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall

device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Input voltage, V

3

6

V

I

Operating junction temperature, T

−40

125

°C

J

2

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SGLS212 − OCTOBER 2003

DISSIPATION RATINGS⁽¹⁾⁽²⁾

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T

= 25°C

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING POWER RATING POWER RATING

(3)

28 Pin PWP with solder

18.2 °C/W

40.5 °C/W

5.49 W

3.02 W

1.36 W

2.20 W

0.99 W

28 Pin PWP without solder

2.48 W

(1)

(2)

For more information on the PWP package, refer to TI technical brief, literature number SLMA002. Also see Application Report SLVA113 for

additional information on thermal performace.

Test board conditions:

1. 3” x 3”, 4 layers, thickness: 0.062”

2. 1.5 oz. copper traces located on the top of the PCB

3. 1.5 oz. copper ground plane on the bottom of the PCB

4. 0.5 oz. copper ground planes on the 2 internal layers

5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)

Maximum power dissipation may be limited by over current protection.

(3)

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

SUPPLY VOLTAGE, VIN

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range, VIN

3.0

6.0

V

f = 350 kHz, RT open,

PH pin open

s

11

15.8

I

Quiescent current

mA

(Q)

f = 500 kHz, RT = 100 kΩ, PH pin open

16

1

23.5

1.4

s

Shutdown, ENA = 0 V

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

2.95

2.80

0.16

2.5

3.0

V

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.70

0.14

V

(1)

Rising and falling edge deglitch, UVLO

µs

BIAS VOLTAGE

Output voltage, VBIAS

Output current, VBIAS

I

= 0

2.70

2.80

2.90

100

V

(VBIAS)

(2)

µA

CUMULATIVE REFERENCE

V

ref

Accuracy

0.882 0.891

0.900

V

REGULATION

I

L

I

L

I

L

I

L

= 3 A, f = 350 kHz, T = 125°C

0.04

0.03

s

J

(1)(3)

Line regulation

%/V

%/A

= 3 A, f = 550 kHz, T = 125°C

s

J

= 0 A to 6 A, f = 350 kHz, T = 125°C

s

J

(1)(3)

Load regulation

= 0 A to 6 A, f = 550 kHz, T = 125°C

s

J

OSCILLATOR

Internally set—free running frequency

RT open

280

252

460

663

350

280

500

700

0.75

1

450

308

540

762

kHz

RT = 180 kΩ (1% resistor to AGND)

RT = 100 kΩ (1% resistor to AGND)

RT = 68 kΩ (1% resistor to AGND)

Externally set—free running frequency range

(1)

Ramp valley

(1)

Ramp amplitude (peak-to-peak)

V

(1)

Minimum controllable on time

Maximum duty cycle

200

ns

90%

(1)

(2)

(3)

Specified by design

Static resistive loads only

Specified by the circuit used in Figure 9

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SGLS212 − OCTOBER 2003

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER

(1)

Error amplifier open loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND

90

3

110

5

dB

(1)

Parallel 10 kΩ, 160 pF COMP to AGND

MHz

Error amplifier common mode input voltage

range

(1)

Powered by internal LDO

0

VBIAS

250

V

Input bias current, VSENSE

VSENSE = V

ref

60

nA

Output voltage slew rate (symmetric), COMP

1.0

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay time,

PWM comparator input to PH pin (excluding

deadtime)

(1)

10-mV overdrive

70

85

ns

ENABLE

Enable threshold voltage, ENA

Enable hysteresis voltage, ENA

0.82

1.20

0.03

2.5

1.40

V

(1)

Falling edge deglitch, ENA

µs

µA

Leakage current, ENA

V = 5.5 V

I

1

POWER GOOD

Power good threshold voltage

VSENSE falling

90

3

%V

ref

(1)

Power good hysteresis voltage

ref

(1)

Power good falling edge deglitch

35

µs

Output saturation voltage, PWRGD

Leakage current, PWRGD

I

= 2.5 mA

0.18

0.3

1

V

(sink)

V = 5.5 V

µA

I

CURRENT LIMIT

(1)

V = 3 V Output shorted

7.2

10

12

I

Current limit trip point

A

V = 6 V Output shorted

I

Current limit leading edge blanking time

Current limit total response time

100

200

ns

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

135

150

10

165

°C

Thermal shutdown hysteresis

OUTPUT POWER MOSFETS

(4)

V = 6 V

26

36

47

65

I

r

Power MOSFET switches

mΩ

DS(on)

V = 3 V

I

TRACKIN

Input offset, TRACKIN

V

= TRACKIN = 1.25 V

−1.5

0

1.5

mV

V

SENSE

See Note 1

Input voltage range, TRACKIN

Specified by design

V

ref

(1)

(2)

(3)

(4)

Static resistive loads only

Specified by the circuit used in Figure 9

Matched MOSFETs low-side r

DS(on)

production tested, high-side r specified by design

DS(on)

4

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SGLS212 − OCTOBER 2003

PWP PACKAGE

(TOP VIEW)

1

28

AGND

VSENSE

COMP

PWRGD

BOOT

PH

RT

ENA

TRACKIN

VBIAS

VIN

PGND

2

27

26

25

24

23

22

21

20

19

18

17

16

15

3

4

5

6

7

PH

THERMAL

PAD

8

9

10

11

12

13

14

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

AGND

NO.

1

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor.

Connect PowerPAD to AGND.

BOOT

5

Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

COMP

ENA

3

Error amplifier output. Connect frequency compensation network from COMP to VSENSE

27

Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and

places device in low quiescent current state.

PGND

15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas

to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection

to AGND is recommended.

PH

6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

PWRGD

RT

4

Power good open drain output. High when VSENSE ≥ 90% V , otherwise PWRGD is low.

ref

28

26

25

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.

External reference input. High impedance input to internal reference/multiplexer and error amplifier circuits.

TRACKIN

VBIAS

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

VIN

package with a high quality, low-ESR 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect to output voltage through compensation network/output divider.

5

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INTERNAL BLOCK DIAGRAM

VBIAS

AGND

VBIAS

Enable

Comparator

REG

Falling

Edge

Deglitch

SHUTDOWN

ENA

VIN

ILIM

1.2 V

VIN

Comparator

Thermal

Shutdown

150°C

Hysteresis: 0.03 V

Leading

Edge

Blanking

2.5 µs

VIN UVLO

Comparator

Falling

and

100 ns

VIN

BOOT

Rising

Edge

2.95 V

sense Fet

Deglitch

Hysteresis: 0.16 V

30 mΩ

I/O

2.5 µs

SS_DIS

SHUTDOWN

L

OUT

Core

PH

TRACKIN

Multiplexer

Reference

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

Error

Amplifier

PWM

Comparator

VIN

25 ns Adaptive

Dead Time

30 mΩ

PGND

OSC

Powergood

Comparator

PWRGD

VSENSE

Falling

Edge

Deglitch

0.90 V

ref

Hysteresis: 0.03 Vref

TPS54680

SHUTDOWN

35 µs

VSENSE

COMP

RT

6

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SGLS212 − OCTOBER 2003

TYPICAL CHARACTERISTICS

INTERNALLY SET

DRAIN-SOURCE

OSCILLATOR FREQUENCY

vs

ON-STATE RESISTANCE

vs

ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

60

50

40

750

650

550

60

VIN = 3.3 V

VIN = 5 V

I

= 6 A

O

50

I

= 6 A

O

40

30

20

30

20

450

350

250

10

0

10

0

−40

0

25

85

125

−40

0

25

85

125

−40

0

25

85

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1

Figure 2

Figure 3

EXTERNALLY SET

OSCILLATOR FREQUENCY

vs

DEVICE POWER LOSSES AT T = 125°C

J

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

vs

LOAD CURRENT

JUNCTION TEMPERATURE

5

0.895

0.893

0.891

0.889

800

700

600

T

= 125°C

= 700 kHz

J

4.5

4

f

s

RT = 68 k

RT = 100 k

RT = 180 k

V

= 3.3 V

I

3.5

3

2.5

2

500

400

300

200

1.5

1

V

I

= 5 V

0.887

0.885

0.5

0

1

2

3

4

5

6

7

8

−40

0

25

85

125

−40

0

25

85

125

I

− Load Current − A

L

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 6

Figure 4

Figure 5

OUTPUT VOLTAGE REGULATION

ERROR AMPLIFIER

OPEN LOOP RESPONSE

vs

INPUT VOLTAGE

0

140

120

0.895

0.893

0.891

0.889

R

C

T

= 10 kΩ,

= 160 pF,

= 25°C

L

A

T

= 85°C,

= 3 A

A

−20

−40

−60

−80

I

O

100

80

60

40

20

Phase

f

= 550 kHz

s

−100

−120

−140

−160

−180

−200

Gain

0.887

0.885

0

−20

1

10 100 1 k 10 k 100 k 1 M 10 M

3

3.5

4

4.5

5

5.5

6

f − Frequency − Hz

V − Input Voltage − V

I

Figure 7

Figure 8

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APPLICATION INFORMATION

Figure 9 shows the schematic diagram for a typical

TPS54680 application. The TPS54680 (U1) can provide

greater than 6 A of output current at a nominal output

voltage of 1.8 V. For proper thermal performance, the

exposed thermal PowerPAD underneath the integrated

circuit package must be soldered to the printed-circuit

board. To provide power up tracking, the enable of the I/O

supply should be used. If the I/O enable is not used to

power up, then devices with similar undervoltage lockout

thresholds need to be implemented to ensure power up

tracking. To ensure power down tracking, the enable pin

should be used.

TPS54610

I/O Power Supply

VOUT_I/O

R1

10 kΩ

U1

R2

28

1

2

3

4

5

6

7

RT

AGND

R3

R4

10 kΩ

27

26

25

24

23

22

21

20

19

18

17

16

15

71.5 kΩ

ENA

VSENSE

R5

C1

10 kΩ

TRACKIN COMP

10 kΩ

R7

VBIAS

VIN

470 pF

C4

PWRGD

BOOT

PH

C3

C2

R6

301 Ω

470 pF

C5

VIN

1 µF

9.76 kΩ

R8

12 pF

0.047 µF

VIN

PH

8

9.76 kΩ

PH

9

PH

10

11

12

PGND

PH

VOUT_CORE

VIN

L1

0.65 µH

PH

R9

2.2 Ω

PH

C7

10 µF

C9

C10

22 µF 22 µF

C6

10 µF

C8

22 µF

13

14

PH

C11

PwrPad

3300 pF

Analog and Power Grounds are Tied at

the Power Pad Under the Package of IC

Figure 9. Application Circuit

at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form the

loop compensation network for the circuit. For this design,

a Type 3 topology is used.

COMPONENT SELECTION

The values for the components used in this design

example were selected for low output ripple voltage and

small PCB area. Additional design information is available

at www.ti.com.

OPERATING FREQUENCY

In the application circuit, the 350 kHz operation is selected

by leaving RT open. Connecting a 180 kΩ to 68 kΩ resistor

between RT (pin 28) and analog ground can be used to set

the switching frequency to 280 kHz to 700 kHz. To

calculate the RT resistor, use the equation below:

INPUT FILTER

The input voltage is a nominal 5 Vdc. The input filter C6 is

a 10-µF ceramic capacitor (Taiyo Yuden). C7 also a 10-µF

ceramic capacitor (Taiyo Yuden) provides high frequency

decoupling of the TPS54680 from the input supply and

must be located as close as possible to the device. Ripple

current is carried in both C6 and C7, and the return path to

PGND must avoid the current circulating in the output

capacitors C8, C9, and C10.

500 kHz

Switching Frequency

R +

100 [kW]

(1)

OUTPUT FILTER

The output filter is composed of a 0.65-µH inductor and 3

x 22-µF capacitor. The inductor is a low dc resistance

(0.017 Ω) type, Pulse Engineering PA0227. The

capacitors used are 22-µF, 6.3 V ceramic types with X5R

dielectric. The feedback loop is compensated so that the

unity gain frequency is approximately 75 kHz.

FEEDBACK CIRCUIT

The values for these components have been selected to

provide low output ripple voltage. The resistor divider

network of R3 and R8 sets the output voltage for the circuit

8

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GROUNDING AND POWERPAD LAYOUT

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

The TPS54680 has two internal grounds (analog and

power). Inside the TPS54680, the analog ground ties to all

of the noise sensitive signals, while the power ground ties

to the noisier power signals. The PowerPAD must be tied

directly to AGND. Noise injected between the two grounds

can degrade the performance of the TPS54680,

particularly at higher output currents. However, ground

noise on an analog ground plane can also cause problems

with some of the control and bias signals. Therefore,

separate analog and power ground planes are

recommended. These two planes must tie together

directly at the IC to reduce noise between the two grounds.

The only components that must tie directly to the power

ground plane are the input capacitor, the output capacitor,

the input voltage decoupling capacitor, and the PGND pins

of the TPS54680. The layout of the TPS54680 evaluation

module is representative of a recommended layout for a

4-layer board. Documentation for the TPS54680

evaluation module can be found on the Texas Instruments

web site under the TPS54680 product folder. See the

TPS54680 EVM user’s guide.

For operation at full rated load current, the analog ground

plane must provide an adequate heat dissipating area. A

3-inch by 3-inch plane of 1 ounce copper is recommended,

though not mandatory, depending on ambient temperature

and airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD must be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

any area available must be used when 6 A or greater

operation is desired. Connection from the exposed area of

the PowerPAD to the analog ground plane layer must be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Eight vias must be in the

PowerPAD area with four additional vias located under the

device package. The size of the vias under the package,

but not in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the twelve recommended

that enhance thermal performance must be included in

areas not under the device package.

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

Powerpad Area 4 x 0.018 Diameter Under Device as Shown.

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

Area Is Extended.

Ø0.0130

8 PL

4 PL Ø0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0339

0.0650

0.0500

0.3820 0.3478

0.2090

0.0256

0.0500

0.0650

0.0339

Minimum Recommended Exposed

Copper Area for Powerpad. 5mil

Stencils May Require 10 Percent

0.1700

Larger Area

0.1340

0.0630

Minimum Recommended Top

Side Analog Ground Area

0.0400

Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD

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PERFORMANCE GRAPHS

EFFICIENCY

vs

LOAD REGULATION

vs

LINE REGULATION

vs

OUTPUT CURRENT

INPUT VOLTAGE

0.20

0.15

0.10

0.05

95

0.20

0.15

T

A

= 25°C,

V

= 0.9 V

F

S

= 700 kHz,

O

V

= 1.8 V

O

90

85

80

75

70

V

= 1.8 V

O

V

= 1.2 V

O

0.10

I

= 6 A

O

V

= 1.8 V

O

0.05

0

V

= 1.2 V

O

0

V

= 0.9 V

I

= 0 A

O

−0.05

−0.10

T

A

= 25°C,

−0.10

V

= 3.3 V,

V

F

= 3.3 V,

I

65

60

F

S

= 700 kHz,

−0.15

−0.20

= 700 kHz,

−0.15

−0.20

S

V

= 0.9 V, 1.2 V and 1.8 V

V

= 0.9 V, 1.8 V and 2.5 V

O

3

3.5

4

4.5

5

5.5

6

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

I

− Output Current − A

I

− Output Current − A

O

V − Input Voltage − V

I

O

Figure 11

Figure 13

Figure 12

AMBIENT TEMPERATURE

vs

LOAD CURRENT

OUTPUT AND INPUT RIPPLE

LOOP RESPONSE

125

115

105

95

180

150

120

90

60

T

J

= 125°C

50

f

= 700 kHz

s

40

30

20

10

V

= 5 V

Phase

I

60

85

30

(1)

Safe Operating Area

75

Gain

0

−10

−30

65

V

= 3.3 V

I

−20

−60

55

−30

−40

−50

−90

45

V

I

f

= 5 V,

= 0 A,

= 700 kHz

I

O

S

−120

35

−150

−180

25

−60

0

1

2

3

4

5

6

7

8

t − Time − 1 µs/div

100

1 k

10 k

100 k

1 M

I

− Output Current − A

f − Frequency − Hz

O

Figure 14

Figure 16

Figure 15

STARTUP TIMING

LOAD TRANSIENT RESPONSE

POWER DOWN TIMING

I/O

V

f

= 5 V

= 700 kHz

I

s

V

= 5 V,

I

= 1.8 V

O

CORE

PWRGD(I/O)

PWRGD(CORE)

t − Time − 500 µs/div

t − Time −20 µs/div

Figure 19

Figure 17

Figure 18

(1)

10

Safe operating area is applicable to the test board conditions in the Dissipation Ratings

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈꢉ ꢁ

SGLS212 − OCTOBER 2003

Figure 20 shows the schematic diagram for a power

supply tracking design using a TPS2034 high side power

switch and a TPS54680 device. The TPS2034 power

switch ensures the I/O voltage is not applied to the load

before U1 has enough bias voltage to operate and

generate the core voltage.

TPS2034

Distribution Switch

VOUT_I/O

R1

10 kΩ

U1

R2

28

1

2

3

4

5

6

7

RT

AGND

R3

R4

10 kΩ

27

26

25

24

23

22

21

20

19

18

17

16

15

71.5 kΩ

ENA

VSENSE

R5

C1

10 kΩ

TRACKIN COMP

10 kΩ

R7

VBIAS

VIN

470 pF

C4

PWRGD

BOOT

PH

C3

C2

R6

301 Ω

470 pF

C5

VIN

1 µF

9.76 kΩ

R8

12 pF

0.047 µF

VIN

PH

8

9.76 kΩ

PH

9

PH

10

11

12

PGND

PH

VOUT_CORE

VIN

L1

0.65 µH

PH

R9

2.2 Ω

PH

C7

10 µF

C9

C10

22 µF 22 µF

C6

10 µF

C8

22 µF

13

14

PH

C11

PwrPad

3300 pF

Analog and Power Grounds are Tied at

the Power Pad Under the Package of IC

Figure 20. 3.3-V Small Size, High Frequency Design

11

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LOAD TRANSIENT RESPONSE

V

= 3.3 V,

I

= 1.8 V

O

t − Time −20 µs/div

Figure 21

EFFICIENCY

LOAD REGULATION

vs

LINE REGULATION

vs

OUTPUT CURRENT

INPUT VOLTAGE

100

95

0.20

0.15

0.20

0.15

0.10

0.05

V

T

= 1.8 V,

25°C,

= 700 kHz

O

A

V

= 5 V,

I

= 1.8 V,

O

V

= 1.8 V

O

90

F

S

T

A

= 25°C,

0.10

0.05

0

F

S

= 700 kHz

85

80

I

= 6 A

O

V

= 0.9 V

O

75

70

0

I

= 0 A

V

= 1.2 V

O

−0.05

65

60

−0.10

−0.15

−0.20

−0.10

−0.15

−0.20

V

= 5 V,

= 25°C,

= 700 kHz

I

T

A

55

50

F

S

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8

0

1

2

3

4

5

6

7

8

4

4.5

5

5.5

6

I

− Output Current − A

I

− Output Current − A

O

V − Input Voltage − V

I

Figure 22

Figure 24

Figure 23

AMBIENT TEMPERATURE

vs

LOAD CURRENT

LOOP RESPONSE

OUTPUT AND INPUT RIPPLE

125

115

105

95

180

150

120

90

60

50

T

J

= 125°C

f

= 700 kHz

s

40

30

20

10

Phase

V = 5 V

I

60

85

30

(1)

Safe Operating Area

Gain

75

0

−10

−30

65

V

= 3.3 V

I

−20

−60

55

−30

−40

−50

−90

V

I

f

= 3.3 V,

= 0 A,

= 700 kHz

I

O

S

45

−120

35

−150

−180

25

−60

0

1

2

3

4

5

6

7

8

100

1 k

10 k

100 k

1 M

t − Time − 1 µs/div

I

− Output Current − A

f − Frequency − Hz

O

Figure 25

Figure 27

Figure 26

12

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SLOW-START TIMING

V = 5 V,

I

0.04 µF

Slow-start Cap

V

= 5 V,

I

0.04 µF

Slow-start Cap

4.0 ms/div

Figure 28

Figure 29

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DETAILED DESCRIPTION

VOLTAGE REFERENCE

The voltage reference system produces a precise V

ref

UNDERVOLTAGE LOCK OUT (UVLO)

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precision regulation of the TPS54680, since it cancels

offset errors in the scale and error amplifier circuits.

The TPS54680 incorporates an under voltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs

rising and falling edge deglitch circuit reduce the likelihood

of shutting the device down due to noise on VIN.

OSCILLATOR AND PWM RAMP

The oscillator frequency is set internally to 350 kHz. If a

different frequency of operation is required for the

application, the oscillator frequency can be externally

adjusted from 280 to 700 kHz by connecting a resistor

between the RT pin and AGND. The switching frequency

is approximated by the following equation, where R is the

resistance from RT to AGND:

TRACKIN/INTERNAL SLOW-START

The internal slow-start circuit provides start-up slope

control of the output voltage. The nominal internal

slow-start rate is 25 V/ms. When the voltage on TRACKIN

rises faster than the internal slope or is present when

device operation is enabled, the output rises at the internal

rate. If the reference voltage on TRACKIN rises more

slowly, then the output rises at about the same rate as

TRACKIN.

(2)

100 kW

Switching Frequency +

500 [kHz]

R

SWITCHING FREQUENCY

350 kHz, internally set

RT PIN

Float

R = 180 kΩ to 68 kΩ

Externally set 280 kHz to 700 kHz

Once the voltage on the TRACKIN pin is greater than the

internal reference of 0.891 V, the multiplexer switches the

noninverting node to the high precision reference.

ERROR AMPLIFIER

The high performance, wide bandwidth, voltage error

amplifier sets the TPS54680 apart from most dc/dc

converters. The user is given the flexibility to use a wide

range of output L and C filter components to suit the

ENABLE (ENA)

The enable pin, ENA, provides a digital control enable or

disable (shut down) for the TPS54680. An input voltage of

1.4 V or greater ensures that the TPS54680 is enabled. An

input of 0.82 V or less ensures that device operation is

disabled. These are not standard logic thresholds, even

though they are compatible with TTL outputs.

particular application needs. Type

2 or type 3

compensation can be employed using external

compensation components.

PWM CONTROL

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately reset and set the PWM latch. Once

the PWM latch is reset, the low-side FET remains on for a

minimum duration set by the oscillator pulse width. During

this period, the PWM ramp discharges rapidly to its valley

voltage. When the ramp begins to charge back up, the

low-side FET turns off and high-side FET turns on. As the

PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

When ENA is low, the oscillator, slow-start, PWM control

and MOSFET drivers are disabled and held in an initial

state ready for device start-up. On an ENA transition from

low to high, device start-up begins with the output starting

from 0 V.

VBIAS REGULATOR (VBIAS)

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommended because their values are more stable over

temperature. The bypass capacitor must be placed close

to the VBIAS pin and returned to AGND.

External loading on VBIAS is allowed, with the caution that

internal circuits require a minimum VBIAS of 2.70 V, and

external loads on VBIAS with ac or digital switching noise

may degrade performance. The VBIAS pin may be useful

as a reference voltage for external circuits.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

latch is never reset, and the high-side FET remains on until

14

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the oscillator pulse signals the control logic to turn the

high-side FET off and the low-side FET on. The device

operates at its maximum duty cycle until the output voltage

rises to the regulation set-point, setting VSENSE to

approximately the same voltage as VREF. If the error

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54680 is capable of sinking current continuously

until the output reaches the regulation set-point.

OVERCURRENT PROTECTION

The cycle-by-cycle current limiting is achieved by sensing

the current flowing through the high-side MOSFET and

comparing this signal to a preset overcurrent threshold.

The high side MOSFET is turned off within 200 ns of

reaching the current limit threshold. A 100-ns leading edge

blanking circuit prevents the current limit from false

tripping. Current limit detection occurs only when current

flows from VIN to PH when sourcing current to the output

filter. Load protection during current sink operation is

provided by thermal shutdown.

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and

low-side FET turns on to decrease the energy in the output

inductor and consequently the output current. This

process is repeated each cycle in which the current limit

comparator is tripped.

THERMAL SHUTDOWN

The device uses the thermal shutdown to turn off the power

MOSFETs and disable the controller if the junction

temperature exceeds 150°C. The device is released from

shutdown automatically when the junction temperature

decreases to 10°C below the thermal shutdown trip point,

and starts up under control of the slow-start circuit.

DEAD-TIME CONTROL AND MOSFET

DRIVERS

Thermal shutdown provides protection when an overload

condition is sustained for several milliseconds. With a

persistent fault condition, the device cycles continuously;

starting up by control of the soft-start circuit, heating up due

to the fault condition, and then shutting down upon

reaching the thermal shutdown trip point. This sequence

repeats until the fault condition is removed.

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

turnon times of the MOSFET drivers. The high-side driver

does not turn on until the voltage at the gate of the low-side

FET is below 2 V. While the low-side driver does not turn

on until the voltage at the gate of the high-side MOSFET

is below 2 V.

POWER-GOOD (PWRGD)

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold or ENA is low, or a thermal

shutdown occurs. When VIN ≥ UVLO threshold, ENA ≥

The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is supplied

from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

enable threshold, and VSENSE > 90% of V , the open

ref

drain output of the PWRGD pin is high. A hysteresis

voltage equal to 3% of V and a 35 µs falling edge deglitch

ref

circuit prevent tripping of the power good comparator due

to high frequency noise.

15

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

TPS54680QPWPREP

V62/04641-01XE

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

28

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

HTSSOP

PWP

28

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54680-EP :

Catalog: TPS54680

Automotive: TPS54680-Q1

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54680QPWPREP HTSSOP PWP

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 28

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS54680QPWPREP

2000

Pack Materials-Page 2

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www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

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Communications and Telecom www.ti.com/communications

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www.ti.com/consumer-apps

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dsp.ti.com

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power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

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OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS54680MPWPREP
厂家：	TEXAS INSTRUMENTS
描述：	3V 至 6V 输入增强型产品跟踪同步降压 Pwm 转换开关 \| PWP \| 28 \| -55 to 125 开关控制器开关式稳压器开关式控制器光电二极管电源电路开关式稳压器或控制器
文件：	总22页 (文件大小：796K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS54680MPWPREP [TI]

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