TPS54973PWP_技术文档

Typical Size

6,4 mm X 9,7 mm

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TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK

SWITCHER WITH DISABLED SINKING DURING START-UP

FEATURES

DESCRIPTION

D

15-mΩ MOSFET Switches for High Efficiency

at 9-A Continuous Output Source or Sink

Current

As a member of the SWIFT™ family of dc/dc regulators,

the TPS54973 low-input voltage high-output current

synchronous buck PWM converter integrates all

required active components. Included on the substrate

with the listed features are a true, high performance,

voltage error amplifier that enables maximum

performance and flexibility in choosing the output filter

L and C components; an undervoltage-lockout circuit to

prevent start-up until the input voltage reaches 3 V; an

internally or externally set slow-start circuit to limit

in-rush currents; and a power good output useful for

processor/logic reset, fault signaling, and supply

sequencing.

D

Disabled Current Sinking During Start-Up

0.9-V to 2.5-V Adjustable Output Voltage

Range With 1.0% Accuracy

Wide PWM Frequency:

Fixed 350 kHz, 550 kHz or

Adjustable 280 kHz to 700 kHz

D

Synchronizable to 700 kHz

Load Protected by Peak Current Limit and

Thermal Shutdown

Integrated Solution Reduces Board Area and

Component Count

For reliable power up in output precharge applications,

the TPS54973 is designed to only source current during

startup.

APPLICATIONS

D

Low-Voltage, High-Density Distributed Power

Systems

The TPS54973 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD™ package, which

eliminates bulky heatsinks. TI provides evaluation

modules and the SWIFT™ designer software tool to aid

in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors

D

Broadband, Networking and Optical

Communications Infrastructure

Power PC Series Processors

TYPICAL APPLICATION

START-UP WAVEFORM

*

R

L

= 1 Ω

I/O Supply

Core Supply

VIN

PH

V

= 3.3 V

TPS54973

I/O

BOOT

PGND

VSENSE

VBIAS

AGND COMP

V

= 1.8 V

(core)

t − Time − 10 ms/div

* Optional

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

(1)

−40°C to 85°C

0.9 V to 2.5 V

Plastic HTSSOP (PWP)

TPS54973PWP

(1)

(2)

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54973PWPR). See the application section of

the data sheet for PowerPAD drawing and layout information.

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at

www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

TPS54973

−0.3 V to 4.5 V

−0.3 V to 7 V

−0.3 V to 6 V

−0.3 V to 4V

−0.3 V to 10 V

−0.3 V to 7 V

−0.6 V to 6 V

Internally limited

6 mA

VIN

SS/ENA, SYNC

RT

Input voltage range, V

I

VSENSE

BOOT

VBIAS, COMP, PWRGD

Output voltage range, V

O

PH

Source current, I

O

COMP, VBIAS

PH

16 A

COMP

6 mA

Sink current, I

S

SS/ENA, PWRGD

AGND to PGND

10 mA

Voltage differential

Operating virtual junction temperature range, T

0.3 V

−40°C to 125°C

−65°C to 150°C

300°C

J

Storage temperature, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Input voltage, V

3

4

V

I

Operating junction temperature, T

−40

125

°C

J

(1)(2)

DISSIPATION RATINGS

PACKAGE

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T = 25°C

T = 70°C

T = 85°C

A

POWER RATING POWER RATING POWER RATING

(3)

28 Pin PWP with solder

14.4 °C/W

27.9 °C/W

6.94 W

3.58 W

3.81 W

1.97 W

2.77 W

1.43 W

28 Pin PWP without solder

(1)

For more information on the PWP package, refer to TI technical brief, literature number SLMA002.

Test board conditions:

(2)

1. 3” x 3”, 4 layers, thickness: 0.062”

2. 1.5 oz. copper traces located on the top of the PCB

3. 1.5 oz. copper ground plane on the bottom of the PCB

4. 0.5 oz. copper ground planes on the two internal layers

5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)

Maximum power dissipation may be limited by over current protection.

(3)

2

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TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

ELECTRICAL CHARACTERISTICS

TJ = −40°C to 125°C, V = 3 V to 4 V (unless otherwise noted)

I

PARAMETER

SUPPLY VOLTAGE, VIN

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range, VIN

3.0

4.0

17

V

f = 350 kHz, SYNC ≤ 0.8 V, RT open,

PH pin open

s

9.8

f = 550 kHz, SYNC ≥ 2.5 V, RT open,

PH pin open

I

Quiescent current

mA

s

(Q)

14

1

23

Shutdown, SS/ENA = 0 V

1.4

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

2.95

2.80

0.16

2.5

3.0

V

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.70

0.14

V

(1)

Rising and falling edge deglitch, UVLO

µs

BIAS VOLTAGE

Output voltage, VBIAS

Output current, VBIAS

I

= 0

2.70

2.80

2.90

100

V

(VBIAS)

(2)

µA

CUMULATIVE REFERENCE

V

ref

Accuracy

0.882 0.891 0.900

V

REGULATION

I = 3 A, f = 350 kHz, T = 85°C

0.04

0.03

L

s

J

(1)(3)

Line regulation

%/V

%/A

I = 3 A, f = 550 kHz, T = 85°C

L

s

J

I = 0 A to 6 A, f = 350 kHz, T = 85°C

L

s

J

Load regulation

OSCILLATOR

Internally set—free running frequency

I = 0 A to 6 A, f = 550 kHz, T = 85°C

L

s

J

SYNC ≤ 0.8 V,

SYNC ≥ 2.5 V,

RT open

280

440

252

460

663

2.5

350

550

280

500

700

420

660

308

540

762

kHz

RT = 180 kΩ (1% resistor to AGND)

RT = 100 kΩ (1% resistor to AGND)

RT = 68 kΩ (1% resistor to AGND)

Externally set—free running frequency range

High level threshold, SYNC

V

Low level threshold, SYNC

0.8

(1)

Pulse duration, external synchronization, SYNC

50

ns

kHz

V

(1)

Frequency range, SYNC

330

700

(1)

Ramp valley

0.75

1

(1)

Ramp amplitude (peak-to-peak)

V

(1)

Minimum controllable on time

200

ns

Maximum duty cycle

90%

(1)

(2)

(3)

Specified by design

Static resistive loads only

Specified by the circuit used in Figure 9

3

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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ELECTRICAL CHARACTERISTICS (continued)

TJ = −40°C to 125°C, V = 3 V to 4 V (unless otherwise noted)

I

PARAMETER

ERROR AMPLIFIER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Error amplifier open loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND

90

3

110

5

dB

MHz

V

(1)

Parallel 10 kΩ, 160 pF COMP to AGND

(1)

Error amplifier common mode input voltage range Powered by internal LDO

0

VBIAS

250

Input bias current, VSENSE

VSENSE = V

60

nA

ref

Output voltage slew rate (symmetric), COMP

1.0

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay time,

PWM comparator input to PH pin (excluding

deadtime)

(1)

10-mV overdrive

70

85

ns

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA

0.82

1.20

0.03

2.5

3.35

5

1.40

V

(1)

Falling edge deglitch, SS/ENA

µs

ms

µA

mA

Internal slow-start time

2.6

3

4.1

8

Charge current, SS/ENA

Discharge current, SS/ENA

SS/ENA = 0 V

SS/ENA = 1.3 V, V = 1.5 V

2.0

2.3

4.0

I

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage

VSENSE falling

90

3

%V

ref

(1)

%V

ref

Power good falling edge deglitch

35

µs

V

Output saturation voltage, PWRGD

Leakage current, PWRGD

I

= 2.5 mA

0.18

0.3

1

(sink)

V = 5.5 V

I

µA

CURRENT LIMIT

(1)

Current limit trip point

V = 3.3 V Output shorted

I

11

15

100

200

A

Current limit leading edge blanking time

Current limit total response time

ns

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

135

150

10

165

°C

Thermal shutdown hysteresis

OUTPUT POWER MOSFETS

(4)

V = 3.0 V

15

14

30

28

I

r

Power MOSFET switches

Specified by design

Static resistive loads only

Specified by the circuit used in Figure 9

mΩ

DS(on)

(4)

V = 3.6 V

I

(1)

(2)

(3)

(4)

Matched MOSFETs low-side r

production tested, high-side r

specified by design

DS(on)

4

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TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

PWP PACKAGE

(TOP VIEW)

1

2

3

28

AGND

VSENSE

COMP

PWRGD

BOOT

PH

RT

27

26

25

24

23

22

21

20

19

18

17

16

15

SYNC

SS/ENA

VBIAS

VIN

4

5

6

7

8

9

PH

THERMAL

PAD

VIN

10

11

12

13

14

PGND

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

AGND

NO.

1

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and

SYNC pin. Connect PowerPAD to AGND.

BOOT

5

3

Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

COMP

PGND

Error amplifier output. Connect frequency compensation network from COMP to VSENSE

15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas

to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection

to AGND is recommended.

PH

6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

PWRGD

4

Power good open drain output. High when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when

ref

SS/ENA is low, or the internal shutdown signal is active.

RT

28

26

27

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the

SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.

SS/ENA

SYNC

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select

between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be

connected to the RT pin.

VBIAS

25

Internalbias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low-ESR 10-µF ceramic capacitor.

VIN

VSENSE

2

Error amplifier inverting input. Connect to output voltage through compensation network/output divider.

5

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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INTERNAL BLOCK DIAGRAM

VBIAS

AGND

VBIAS

VIN

Enable

Comparator

SS/ENA

REG

Falling

SHUTDOWN

Edge

1.2 V

ILIM

Comparator

Deglitch

Thermal

VIN

Hysteresis: 0.03

Leading

Edge

Blanking

Shutdown

150°C

2.5 µs

V

VIN UVLO

Comparator

Falling

100 ns

SHUTDOWN

and

Rising

Edge

VIN

BOOT

2.95 V

Deglitch

Hysteresis: 0.16

V

15 mΩ

Start-Up

Driver

Suppression

2.5 µs

SS_DIS

L

OUT

V

O

PH

Internal/External

Slow-Start

(Internal Slow-Start Time = 3.35 ms

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

Error

Amplifier

PWM

Comparator

Reference

VIN

VREF = 0.891 V

15 mΩ

PGND

OSC

Powergood

Comparator

PWRGD

VSENSE

0.90 V

Falling

Edge

ref

Deglitch

TPS54973

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

SYNC

VSENSE

COMP

RT

6

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TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS

INTERNALLY SET

OSCILLATOR FREQUENCY

vs

DRAIN-SOURCE

ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

25

20

750

650

550

VIN = 3.0 V

I

= 9 A

O

SYNC ≥ 2.5 V

SYNC ≤ 0.8 V

15

10

450

5

0

350

250

−40

0

25

85

125

−40

0

25

85

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1

Figure 2

EXTERNALLY SET

OSCILLATOR FREQUENCY

vs

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

DEVICE POWER LOSSES

vs

LOAD CURRENT

JUNCTION TEMPERATURE

8

7

6

5

4

3

2

1

0

0.895

0.893

0.891

0.889

800

700

600

V = 3.3 V

I

T

J

= 125°C

RT = 68 k

RT = 100 k

RT = 180 k

500

400

300

200

0.887

0.885

0

2

4

6

8

10 12 14 16

−40

0

25

85

125

−40

0

25

85

125

I

− Load Current − A

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

L

Figure 5

Figure 3

Figure 4

OUTPUT VOLTAGE REGULATION

INTERNAL SLOW-START TIME

vs

JUNCTION TEMPERATURE

ERROR AMPLIFIER

OPEN LOOP RESPONSE

vs

INPUT VOLTAGE

0.895

0

140

3.80

R

C

T

= 10 kΩ,

= 160 pF,

= 25°C

L

−20

−40

−60

−80

120

100

80

3.65

3.50

0.893

0.891

0.889

A

Phase

Gain

3.35

−100

−120

−140

−160

−180

−200

60

3.20

3.05

40

20

0.887

0.885

2.90

2.75

0

−20

1

10 100 1 k 10 k 100 k 1 M 10 M

3

3.1

3.2

3.3

3.4

3.5

3.6

−40

0

25

85

125

V − Input Voltage − V

I

f − Frequency − Hz

T

J

− Junction Temperature − °C

Figure 6

Figure 7

Figure 8

7

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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APPLICATION INFORMATION

Figure 9 shows the schematic diagram for a typical

TPS54973 application. The TPS54973 (U1) can provide

up to 9 A of output current at a nominal output voltage of

0.9 V to 2.5 V, and for this application, the output voltage

is set at 2.5 V and the input voltage is 3.3 V. For proper

operation, the PowerPAD underneath the integrated

circuit TPS54973 must be soldered properly to the

printed-circuit board.

U1

TPS54973

R6

28

27

24

RT

VIN

3.3 V

23

71.5 kΩ

VIN

C10

C12

22

21

20

14

13

SYNCH

SS/ENA

VBIAS

VIN

10 µF

C6

26

PH

0.047 µF

C3

25

4

12

11

10

9

1 µF

VIN

R3

10 kΩ

R5

PWRGD

R1

3

C4

COMP

8

10 kΩ

470 pF

12 pF

7

R2

301 Ω

C1

C2

6

PH

1 A, 200 V

D1

2

1

5

C9

0.047 µF

470 pF

VSENSE

AGND

BOOT

PGND

19

18

17

16

15

R4

5.49 kΩ

PGND

1 A, 200 V

D2

PwrPad

VOUT

2.5 V

R7

C13

C5

C7

C8

2.4 kΩ

L1

0.65 µH

0.1 µF

22 µF

C11

3300 pF

Figure 9. Application Circuit

the input supply, must be located as close as possible to

the device. Ripple current is carried in both C10 and C12,

and the return path to PGND should avoid the current

circulating in the output capacitors C5, C7, C8 and C13.

COMPONENT SELECTION

The values for the components used in this design

example are selected for low output ripple and small PCB

area. Ceramic capacitors are utilized in the output filter

circuit. A small size, small value output inductor is also

used. Compensation network components are chosen to

maximize closed loop bandwidth and provide good

transient response characteristics. Additional design

information is available at www.ti.com.

FEEDBACK CIRCUIT

The values for these components are selected to provide

fast transient response times. R1, R2, R3, R4, C1, C2, and

C4 forms the loop-compensation network for the circuit.

For this design, a Type 3 topology is used. The transfer

function of the feedback network is chosen to provide

maximum closed loop gain available with open loop

characteristics of the internal error amplifier. Closed loop

crossover frequency is typically between 80 kHz at 3.3 V

input.

INPUT VOLTAGE

The input voltage is a nominal 3.3 VDC. The input filter

(C12) is a 10-µF ceramic capacitor (Taiyo Yuden). C10,

also a 10-µF ceramic capacitor (Taiyo Yuden) that

provides high frequency decoupling of the TPS54973 from

8

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TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

The TPS54973 has two internal grounds (analog and

power). Inside the TPS54973, the analog ground ties to all

of the noise sensitive signals, while the power ground ties

to the noisier power signals. Noise injected between the

two grounds can degrade the performance of the

TPS54973, particularly at higher output currents. Ground

noise on an analog ground plane can also cause problems

with some of the control and bias signals. For these

reasons, separate analog and power ground traces are

recommended. There is an area of ground on the top layer

directly under the IC, with an exposed area for connection

to the PowerPAD. Use vias to connect this ground area to

any internal ground planes. Additional vias are also used

at the ground side of the input and output filter capacitors.

The AGND and PGND pins are tied to the PCB ground by

connecting them to the ground area under the device as

shown. The only components that tie directly to the power

ground plane are the input capacitors, the output

capacitors, the input voltage decoupling capacitor, and the

PGND pins of the TPS54973. Use a separate wide trace

for the analog ground signal path. The analog ground is

used for the voltage set point divider, timing resistor RT,

slow-start capacitor and bias capacitor grounds. Connect

this trace directly to AGND (Pin 1).

OPERATING FREQUENCY

In the application circuit, the RT pin is grounded through a

71.5-kΩ resistor (R6) to select the operating frequency of

700 kHz. To set a different frequency, place a 68-kΩ to

180-kΩ resistor between RT (pin 28) and analog ground or

leave RT floating to select the default of 350 kHz. The

resistance can be approximated using the following

equation:

500 kHz

Switching Frequency

R +

100 [kW]

(1)

OUTPUT FILTER

The output filter is composed of a 0.65-µH inductor (L1)

and 3 x 22-µF capacitors (C5, C7, and C8). The inductor

is a low dc resistance (.017 Ω) type, Pulse PA0277 0.65

µH. The capacitors used are 22-µF, 6.3-V ceramic types

with X5R dielectric. An additional high frequency bypass

capacitor, C13 is also used.

PRECHARGE CIRCUIT

The PH pins are tied together and routed to the output

inductor. Since the PH connection is the switching node,

the inductor is located close to the PH pins. The area of the

PCB conductor is minimized to prevent excessive

capacitive coupling.

VIN precharges the output of the application circuit

through series diodes (D1 and D2) during start-up. As the

input voltage increases at start-up, the output is

precharged to VIN minus the forward bias voltage of the

two diodes. When the internal reference has ramped up to

a value greater than the voltage fed back to the VSENSE

pin, the output of the internal error amplifier begins to

increase. When this output reaches the maximum ramp

amplitude, the output of the PWM comparator reaches 100

percent duty cycle, and the internal logic enables the

high-side FET driver, and switching begins. The output

tracks the internal reference until the preset output voltage

is reached. Under no circumstances should the precharge

voltage be allowed to increase above the preset output

value.

Connect the boot capacitor between the phase node and

the BOOT pin as shown Keep the boot capacitor close to

the IC and minimize the conductor trace lengths.

Connect the output filter capacitor(s) as shown between

the VOUT trace and PGND. It is important to keep the loop

formed by the PH pins, L , C

OUT OUT

and PGND as small as

practical.

Place the compensation components from the VOUT trace

to the VSENSE and COMP pins. Do not place these

components too close to the PH trace. Due to the size of

the IC package and the device pin-out, they must be routed

close, but maintain as much separation as possible while

still keeping the layout compact.

PCB LAYOUT

Figure 10 shows a generalized PCB layout guide for the

TPS54973

Connect the bias capacitor from the VBIAS pin to analog

ground using the isolated analog ground trace. If a

slow-start capacitor or RT resistor is used, or if the SYNC

pin is used to select 350-kHz operating frequency, connect

them to this trace.

The VIN pins are connected together on the printed-circuit

board (PCB) and bypassed with

a

low-ESR

ceramic-bypass capacitor. Care should be taken to

minimize the loop area formed by the bypass capacitor

connections, the VIN pins, and the TPS54873 ground

pins. The minimum recommended bypass capacitance is

10-µF ceramic capacitor with a X5R or X7R dielectric and

the optimum placement is closest to the VIN pins and the

PGND pins.

If pre−charge diodes are used, keep the path from the

voltage source to the output filter capacitor short. Make

sure the etch is wide enough to carry the pre−charge

current.

9

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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OPTIONAL PRE−CHARGE DIODES

ANALOG GROUND TRACE

FREQUENCY SET RESISTOR

AGND

RT

SYNC

SLOW START

CAPACITOR

VSENSE

COMP

COMPENSATION

NETWORK

SS/ENA

VBIAS

BIAS CAPACITOR

PWRGD

BOOT

CAPACITOR

VIN

EXPOSED

POWERPAD

AREA

PH

VOUT

VIN

PH

VIN

PGND

OUTPUT INDUCTOR

OUTPUT

FILTER

CAPACITOR

INPUT

BYPASS

CAPACITOR

INPUT

BULK

FILTER

TOPSIDE GROUND AREA

VIA to Ground Plane

Figure 10. TPS54973 PCB Layout

10

www.ti.com

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

any area available should be used when 9 A or greater

operation is desired. Connection from the exposed area of

the PowerPAD to the analog ground plane layer should be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Eight vias should be in the

PowerPAD area with four additional vias located under the

device package. The size of the vias under the package,

but not in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the ten recommended

that enhance thermal performance should be included in

areas not under the device package.

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

For operation at full rated load current, the analog ground

plane must provide adequate heat dissipating area. A 3

inch by 3 inch plane of 1 ounce copper is recommended,

though not mandatory, depending on ambient temperature

and airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

Powerpad Area 4 x 0.018 Diameter Under Device as Shown.

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

Area Is Extended.

Ø0.0130

8 PL

4 PL Ø0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0339

0.0650

0.0500

0.3820 0.3478

0.2090

0.0256

0.0500

0.0650

0.0339

Minimum Recommended Exposed

Copper Area for Powerpad. 5-mil

Stencils May Require 10 Percent

0.1700

Larger Area

0.1340

0.0630

0.0400

Minimum Recommended Top

Side Analog Ground Area

Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD

11

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

www.ti.com

PERFORMANCE GRAPHS

Data shown is for the circuit in Figure 9 with precharge disabled (D1 and D2 removed) except for slow-start timing

of Figure 18. All data is for V = 3.3 V, V = 2.5 V, fs = 700 kHz and T = 25°C, unless otherwise specified.

I

O

A

OUTPUT VOLTAGE

vs

INPUT VOLTAGE

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

1.81

100

95

1.808

1.806

1.804

1.802

1.8

1.806

1.804

1.802

90

V = 3.3 V

I

V = 3.3 V

85

80

75

70

I

= 0 A

O

1.8

I

= 4.5 A

O

1.798

1.796

1.794

1.796

1.794

65

60

55

50

I

= 9 A

3.5

O

1.792

1.79

1.792

1.79

3

3.25

3.75

4

0

2

4

6

8

10

0

2

4

6

8

10

V

− Input Voltage − V

I

− Output Current − A

I

− Output Current − A

O

Figure 12

Figure 13

Figure 14

AMBIENT TEMPERATURE

vs

(1)

LOOP RESPONSE

LOAD CURRENT

OUTPUT AND INPUT RIPPLE

60

50

180

125

115

105

95

f

= 700 kHz,

s

150

120

90

T

J

= 125°C,

Gain

40

30

20

10

V = 3.3 V,

I

V

= 1.8 V

O

Phase

60

85

30

0

75

0

−10

−20

65

−30

−60

55

45

−30

−40

−90

35

−120

1 M

25

100

1 k

10 k

100 k

0

2

4

6

8

10 12 14 16

t − Time − 1 µs/div

f − Frequency − Hz

I

− Output Current − A

O

Figure 15

Figure 16

Figure 17

LOAD TRANSIENT RESPONSE

SLOW-START TIMING

I = 2.25 A to 6.75 A

V

= 3.3 V

I/O

V

= 1.8 V

(core)

t − Time − 10 ms/div

t − Time −100 µs/div

Figure 18

Figure 19

(1)

Safe operating area is applicable to the test board conditions in the Dissipation Ratings

12

www.ti.com

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

(2)

DETAILED DESCRIPTION

1.2 V

5 mA

t + C

d

(SS)

DISABLED SINKING DURING START-UP

(DSDS)

Second, as the output becomes active, a brief ramp-up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

The DSDS feature enables minimal voltage drooping of

output precharge capacitors at start-up. The TPS54973 is

designed to disable the low-side MOSFET to prevent

sinking current from a precharge output capacitor during

start-up. Once the high-side MOSFET has been turned on

to the maximum duty cycle limit, the low-side MOSFET is

allowed to switch. Once the maximum duty cycle condition

is met, the converter functions as a sourcing converter until

the SS/ENA is pulled low.

(3)

0.7 V

5 mA

t

+ C

(SS)

The actual slow-start time is likely to be less than the above

approximation due to the brief ramp-up at the internal rate.

The low side MOSFET is off during the slow-start

sequence.

VBIAS REGULATOR (VBIAS)

UNDERVOLTAGE LOCK OUT (UVLO)

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommended because their values are more stable over

temperature. The bypass capacitor must be placed close

to the VBIAS pin and returned to AGND.

The TPS54973 incorporates an undervoltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs

rising and falling edge deglitch circuit reduce the likelihood

of shutting the device down due to noise on VIN.

External loading on VBIAS is allowed, with the caution that

internal circuits require a minimum VBIAS of 2.70 V, and

external loads on VBIAS with ac or digital switching noise

may degrade performance. The VBIAS pin may be useful

as a reference voltage for external circuits.

SLOW-START/ENABLE (SS/ENA)

The slow-start/enable pin provides two functions. First, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start-up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.

VOLTAGE REFERENCE

The voltage reference system produces a precise V

ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precision regulation of the TPS54973, since it cancels

offset errors in the scale and error amplifier circuits.

OSCILLATOR AND PWM RAMP

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the SYNC pin as a

static digital input. If a different frequency of operation is

required for the application, the oscillator frequency can be

externally adjusted from 280 to 700 kHz by connecting a

resistor between the RT pin and AGND and floating the

SYNC pin. The switching frequency is approximated by

the following equation, where R is the resistance from RT

to AGND:

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and

AGND.

Adding a capacitor to the SS/ENA pin has two effects on

start-up. First, a delay occurs between release of the

SS/ENA pin and start-up of the output. The delay is

proportional to the slow-start capacitor value and lasts

until the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

(4)

100 kW

Switching Frequency +

500 [kHz]

R

13

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

www.ti.com

External synchronization of the PWM ramp is possible

over the frequency range of 330 kHz to 700 kHz by driving

a synchronization signal into SYNC and connecting a

resistor from RT to AGND. Choose a resistor between the

RT and AGND which sets the free running frequency to

80% of the synchronization signal. The following table

summarizes the frequency selection configurations:

latch is never reset, and the high-side FET remains on until

the oscillator pulse signals the control logic to turn the

high-side FET off and the low-side FET on. The device

operates at its maximum duty cycle until the output voltage

rises to the regulation set-point, setting VSENSE to

approximately the same voltage as VREF. If the error

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54973 is capable of sinking current continuously

until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and

low-side FET turns on to decrease the energy in the output

inductor and consequently the output current. This

process is repeated each cycle in which the current limit

comparator is tripped.

SWITCHING

FREQUENCY

SYNC PIN

Float or AGND

≥ 2.5 V

RT PIN

350 kHz, internally

set

Float

550 kHz, internally

set

Externally set 280

kHz to 700 kHz

Float

R = 180 kΩ to 68 kΩ

Externally

synchronized

frequency

Synchronization

signal

R = RT value for 80%

of external synchro-

nization frequency

ERROR AMPLIFIER

DEAD-TIME CONTROL AND MOSFET

DRIVERS

The high performance, wide bandwidth, voltage error

amplifier sets the TPS54973 apart from most dc/dc

converters. The user is given the flexibility to use a wide

range of output L and C filter components to suit the

particular application needs. Type

compensation can be employed using external

compensation components.

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

turnon times of the MOSFET drivers. The high-side driver

does not turn on until the voltage at the gate of the low-side

FET is below 2 V. While the low-side driver does not turn

on until the voltage at the gate of the high-side MOSFET

is below 2 V.

2 or type 3

PWM CONTROL

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately reset and set the PWM latch. Once

the PWM latch is reset, the low-side FET remains on for a

minimum duration set by the oscillator pulse width. During

this period, the PWM ramp discharges rapidly to its valley

voltage. When the ramp begins to charge back up, the

low-side FET turns off and high-side FET turns on. As the

PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is supplied

from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

OVERCURRENT PROTECTION

The cycle-by-cycle current limiting is achieved by sensing

the current flowing through the high-side MOSFET and

comparing this signal to a preset overcurrent threshold.

The high side MOSFET is turned off within 200 ns of

reaching the current limit threshold. A 100-ns leading edge

blanking circuit prevents current limit false tripping.

Current limit detection occurs only when current flows from

VIN to PH when sourcing current to the output filter. Load

protection during current sink operation is provided by

thermal shutdown.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

14

www.ti.com

TPS54973

SLVS453A − FEBRUARY 2003 − REVISED FEBRUARY 2005

THERMAL SHUTDOWN

POWER-GOOD (PWRGD)

The power good circuit monitors for undervoltage

conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold or SS/ENA is low, or a

thermal shutdown occurs. When VIN ≥ UVLO threshold,

The device uses the thermal shutdown to turn off the power

MOSFETs and disable the controller if the junction

temperature exceeds 150°C. The device is released from

shutdown automatically when the junction temperature

decreases to 10°C below the thermal shutdown trip point,

and starts up under control of the slow-start circuit.

Thermal shutdown provides protection when an overload

condition is sustained for several milliseconds. With a

persistent fault condition, the device cycles continuously;

starting up by control of the soft-start circuit, heating up due

to the fault condition, and then shutting down upon

reaching the thermal shutdown trip point. This sequence

repeats until the fault condition is removed.

SS/ENA ≥ enable threshold, and VSENSE > 90% of V ,

the open drain output of the PWRGD pin is high. A

hysteresis voltage equal to 3% of V and a 35 µs falling

edge deglitch circuit prevent tripping of the power good

comparator due to high frequency noise.

ref

15

PACKAGE OPTION ADDENDUM

www.ti.com

14-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TPS54973PWP

TPS54973PWPR

TPS54973PWPRG4

ACTIVE

HTSSOP

PWP

28

50

None

CU NIPDAU Level-1-220C-UNLIM

PWP

2000

PWP

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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Post Office Box 655303 Dallas, Texas 75265


型号：	TPS54973PWP
厂家：	TEXAS INSTRUMENTS
描述：	3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK SWITCHER WITH DISABLED SINKING DURING START-UP 3 V至4 V输入， 9 -A输出同步降压有残疾塌陷SWITCHER易电源启动时稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管输出元件输入元件 PC
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