TPS54A24 [TI]
4.5V 至 17V、10A 同步 SWIFT™ 降压转换器;
| 型号： | TPS54A24 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5V 至 17V、10A 同步 SWIFT™ 降压转换器 转换器 |
| 文件： | 总42页 (文件大小：2224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54A24
ZHCSJP6 –MAY 2019
TPS54A24 4.5V 至 17V 输入、10A 同步
SWIFT™ 降压转换器
1 特性
3 说明
1
•
•
•
•
•
•
标准 4mm × 4mm WQFN 封装
TPS54A24 是一款全功能 17V、10A 同步降压直流/直
流转换器，采用标准 4mm × 4mm WQFN 封装。
-40°C 至 +150°C 的工作结温范围
200kHz 至 1.6MHz 的固定开关频率
峰值电流模式控制
该器件专门进行了优化，具有高效率并集成了高侧和低
侧 MOSFET，适用于小型解决方案。它还通过使用峰
值电流模式控制（可减少组件数量）并选择高开关频率
（缩小电感器尺寸）进一步节省了空间。
与外部时钟同步
0.6V 电压基准，在广泛的温度范围内提供 ±0.85%
的精度
峰值电流模式控制简化了环路补偿并可提供快速瞬态响
应。在器件过载的情况下，针对高侧和低侧拉电流限制
的逐周期峰值电流限制功能可保护器件。断续模式可在
短路或者过载故障持续存在的情况下限制 MOSFET 功
率损耗。
•
•
•
•
•
•
•
•
•
•
0.6V 至 12V 的输出电压范围
安全启动至预偏置输出电压
断续电流限制
可调软启动和电源排序
可调输入欠压锁定
针对欠压和过压问题的电源正常输出监控
3µA 关断电流
电源正常监控电路会对稳压器输出进行监控。PGOOD
引脚是一个开漏输出，会在输出电压调节过程中进入高
阻抗。除非出现故障，否则内部抗尖峰脉冲时间会阻止
拉低 PGOOD 引脚。
输出过压保护
非锁存热关断保护
使用 TPS54A24 并借助 WEBENCH® 电源设计器
进行定制设计
专用 EN 引脚可以用于控制稳压器开/关，并调节输入
欠压锁定。输出电压启动斜坡由 SS/TRK 引脚控制，
此引脚既支持独立电源运行，也支持跟踪模式。
2 应用
•
•
•
•
•
有线网络（开关）
器件信息(1)
无线基础设施
器件型号
TPS54A24
封装
RTW (24)
封装尺寸（标称值）
测试和测量
4.00mm × 4.00mm
医疗成像设备
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
为 FPGA、SoC、DSP 和处理器供电
空白
空白
效率（VIN = 12V，fSW = 500kHz）
100
简化原理图
95
90
85
80
75
TPS54A24
BOOT
CBT
LO
VIN
VOUT
VIN
SW
CI
EN
COUT
RFBT
PGOOD
SS/TRK
RT/CLK
COMP
70
VO = 1 V, L = 680 nH, XAL8080-681
VO = 1.8 V, L = 1 mH, 74439358010
VO = 3.3 V, L = 2.2 mH, L = 74439358022
FB
65
60
RFBB
0
1
2
3
4
5
6
7
8
9
10
CSS
Output Current (A)
AGND
D001
RC
CZ
RT
PGND
CP
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEQ0
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
Power Supply Recommendations...................... 34
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
8
9
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 器件和文档支持 ..................................................... 36
11.1 器件支持................................................................ 36
11.2 接收文档更新通知 ................................................. 36
11.3 社区资源................................................................ 36
11.4 商标....................................................................... 36
11.5 静电放电警告......................................................... 36
11.6 Glossary................................................................ 36
12 机械、封装和可订购信息....................................... 36
7
4 修订历史记录
日期
修订版本
说明
2019 年 5 月
*
初始发行版
2
Copyright © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
Top View
AGND
VIN
1
2
3
4
5
6
18
17
16
15
14
13
BOOT
VIN
VIN
VIN
Thermal
Pad
PGND
PGND
PGND
PGND
PGND
PGND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Ground of internal analog circuitry. AGND must be connected to PGND for proper operation.
Connect to PGND in a region outside of the critical switching loop.
AGND
1
–
I
Input voltage supply pin. Power for the internal circuit and the connection to drain of high-
side MOSFET. Connect both pins to the input power source with a low impedance
connection. Connect both pins and their neighboring PGND pins.
VIN
2, 3, 16, 17
4, 5, 6, 7, 12,
13, 14, 15
PGND
SW
–
O
I
Ground return for low-side power MOSFET and its drivers.
Switching node. Connected to the source of the high-side MOSFET and drain of the low-side
MOSFET.
8, 9, 10, 11
Floating supply voltage for high-side MOSFET gate drive circuit. Connect a 0.1-µF ceramic
capacitor between BOOT and SW pins.
BOOT
PGOOD
EN
18
19
20
21
Open-drain power good indicator. It is asserted low if output voltage is outside if the PGOOD
thresholds, VIN is low, EN is low, device is in thermal shutdown or device is in soft start.
O
I
Enable pin. Float or pull high to enable the device. Connect a resistor divider to this pin to
implement adjustable under voltage lockout and hysteresis.
Soft-start and tracking pin. Connecting an external capacitor sets the soft-start time. This pin
can also be used for tracking and sequencing.
SS/TRK
I
Error amplifier output and input to the PWM modulator. Connect loop compensation to this
pin.
COMP
FB
22
23
24
I
I
I
Converter feedback input. Connect to the output voltage with a resistor divider.
Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching
frequency. In CLK mode, the device synchronizes to an external clock input to this pin.
RT/CLK
Exposed thermal pad. Connect to PGND pins and to internal ground planes using multiple
vias for good thermal performance.
Thermal PAD
–
–
Copyright © 2019, Texas Instruments Incorporated
3
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–1
MAX
19
UNIT
VIN
BOOT
27
BOOT (10 ns transient)
30
Voltage
BOOT (vs SW)
7
V
SW
20
SW (10 ns transient)
–3
23
EN, SS/TRK, PGOOD, RT/CLK, FB, COMP
–0.3
-40
6.5
150
150
Operating junction temperature, TJ
Storage temperature, TSTG
°C
°C
-55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Input voltage range
Output Voltage
MIN
4.5
NOM
MAX
17
UNIT
V
VIN
VOUT
IOUT
TJ
0.6
12
V
Output current
10
A
Operating junction temperature
-40
150
°C
Switching Frequency (RT mode and PLL
mode)
fSW
200
1600
kHz
6.4 Thermal Information
TPS54A24
THERMAL METRIC(1)
RTW
24 PINS
37.5
21
UNIT
RΘJA
Junction-to-ambient thermal resistance JEDEC
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJA
Junction-to-ambient thermal resistance EVM
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RΘJC(top)
RΘJB
22.8
12.5
0.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
12.5
1.5
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
6.5 Electrical Characteristics
TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
UVLO_rise
UVLO_fall
UVLO_hys
Ivin
V(VIN) rising
4.1
3.9
0.2
580
3
4.3
V
V
VIN undervoltage lockout
V(VIN) falling
3.7
Hysteresis VIN voltage
V(EN) = 5 V, V(FB) = 1.5 V
V(EN) = 0 V
V
Operating non-switching supply current
Shutdown supply current
800
11
µA
µA
Ivin_sdn
ENABLE
Ven_rise
Ven_fall
Ven_hys
Ip
V(EN) rising
V(EN) falling
1.20
1.15
50
1.26
V
V
EN threshold
1.1
EN pin threshold voltage hysteresis
EN pin sourcing current
mV
µA
µA
µA
V(EN) = 1.1V
V(EN) = 1.3V
1.2
Iph
EN pin sourcing current
4.8
Ih
EN pin hysteresis current
3.6
FB
TJ = 25°C
596
595
600
600
604
605
mV
mV
VFB
Regulated FB voltage
ERROR AMPLIFIER
gmea
Error amplifier transconductance (gm)
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V
1100
80
µA/V
dB
Error amplifier DC gain
Icomp_src
Icomp_snk
gmps
Error amplifier source current
Error amplifier sink current
Power stage transconductance
V(FB) = 0 V
V(FB) = 2 V
100
-100
17
µA
µA
A/V
SS/TRK
Iss
Soft start current
5
µA
V(SS/TRK) to V(FB) matching
V(SS/TRK) = 0.4 V
30
mV
MOSFET
TA = 25°C, V(VIN) = 12 V
21
23
8
mΩ
mΩ
mΩ
mΩ
V
High-side switch resistance (VIN pins to SW
pins)
Rds(on)_h
TA = 25°C, V(VIN) = 4.5 V, V(BOOT-SW) = 4.5 V
TA = 25°C, V(VIN) = 12 V
Low-side switch resistance (SW pins to
PGND pins)
Rds(on)_l
TA = 25°C, V(VIN) = 4.5 V
9
BOOT UVLO Falling
2.2
2.6
15.8
14.6
CURRENT LIMIT
Ioc_HS_pk
Ioc_LS_snk
Ioc_LS_src
RT/CLK
High-side peak current limit
Low-side sinking current limit
Low-side sourcing current limit
V(VIN) = 12 V, TJ = 25℃
V(VIN) = 12 V
13.4
10
2
14.6
-3.4
12.9
A
A
A
V(VIN) = 12 V
VIH
Logic high input voltage
Logic low input voltage
V
V
VIL
0.8
PGOOD
V(FB) rising (fault)
V(FB) falling (good)
V(FB) rising (good)
V(FB) falling (fault)
104%
108%
106%
91%
Power good threshold
89%
95%
Leakage current into PGOOD pin when
pulled high
Ipg_lkg
V(PGOOD) = 5 V
5
nA
Vpg_low
PGOOD voltage when pulled low
Minimum VIN for valid output
I(PGOOD) = 2 mA
0.18
0.9
0.22
1
V
V
V(PGOOD) < 0.5 V, I(PGOOD) = 2.5 mA
THERMAL PROTECTION
TTRIP
Thermal protection trip point
Thermal protection hysteresis
Temperature rising
170
15
°C
°C
THYST
Copyright © 2019, Texas Instruments Incorporated
5
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
6.6 Timing Requirements
TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
Minimum synchronization signal pulse width
(PLL mode)
35
ns
6.7 Switching Characteristics
TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN
EN to start of switching
135
µs
PGOOD
Deglitch time PGOOD going high
Deglitch time PGOOD going low
272
16
Cycles
Cycles
SW
Measured at 50% to 50% of V(VIN), L = 1.0
µH, IOUT = 0 A
ton_min
Minimum on time
90
ns
ns
(1)
toff_min
RT/CLK
fsw_min
Minimum off time
V(BOOT-SW) ≥ 2.6 V
0
Minimum switching frequency (RT mode)
Switching frequency (RT mode)
R(RT/CLK) = 250 kΩ
R(RT/CLK) = 100 kΩ
R(RT/CLK) = 30.1 kΩ
200
500
1.6
kHz
kHz
MHz
450
200
550
fsw_max
fsw_clk
Maximum switching frequency (RT mode)
Switching frequency synchronization range
(PLL mode)
1600
kHz
ns
RT/CLK falling edge to SW rising edge
delay (PLL mode)
Measure at 500kHz with RT resistor in
series with RT/CLK
70
HICCUP
Wait time before hiccup
Hiccup time before restart
512
Cycles
Cycles
16384
(1) Specified by design.
6
版权 © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
6.8 Typical Characteristics
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
60
VO = 1 V, L = 680 nH, XAL8080-681
VO = 1.8 V, L = 1.0 mH, 74439358010
VO = 3.3 V, L = 2.2 mH, 74439358022
65
60
VO = 5 V, L = 2.2 mH, 74439358022
VO = 9 V, L = 4.7 mH, 74439358047
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Current (A)
Output Current (A)
D003
D008
VIN = 5 V
fSW = 500 kHz
VIN = 12 V
fSW = 500 kHz
图 1. Efficiency with 5-V Input and 500-kHz Switching
图 2. Efficiency With 5-V and 9-V Output
Frequency
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
VO = 1 V, L = 820 nH, XEL6060-821
VO = 1.2 V, L = 820 nH, XEL6060-821
VO = 1.8 V, L = 820 nH, XEL6060-821
VO = 1 V, L = 820 nH, XEL6060-821
VO = 1.2 V, L = 820 nH, XEL6060-821
VO = 1.8 V, L = 820 nH, XEL6060-821
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Current (A)
Output Current (A)
D010
D009
VIN = 5 V
fSW = 500 kHz
VIN = 12 V
fSW = 500 kHz
图 3. Efficiency With 5-V Input, 500-kHz Switching
图 4. Efficiency With 12-V Input, 500-kHz Switching
Frequency and 6.36-mm × 6.56-mm Inductor
Frequency and 6.36 mm × 6.56 mm Inductor
100
95
90
85
80
75
70
65
60
620
610
600
590
580
570
560
550
540
530
520
510
500
VIN = 4.5 V
VIN = 12 V
VIN = 17 V
VO = 1 V, L = 400 nH, 744308040
VO = 1.2 V, L = 400 nH, 744308040
VO = 1.8 V, L = 400 nH, 744308040
VO = 2.5 V, L = 400 nH, 744308040
0
1
2
3
4
5
6
7
8
9
10
-50
-25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (èC)
D005
D011
V(EN) = 5 V
V(FB) = 0.8 V
VIN = 5 V
fSW = 1 MHz
图 6. VIN Pin Nonswitching Supply Current vs Junction
图 5. Efficiency With 5-V Input and 1 MHz Switching
Temperature
Frequency
版权 © 2019, Texas Instruments Incorporated
7
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Typical Characteristics (接下页)
10
1.22
1.21
1.2
VIN = 4.5 V
VIN = 12 V
9
VIN = 17 V
8
7
6
5
4
3
2
1
0
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
EN Rising
EN Falling
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (
è
C)
Junction Temperature (èC)
D006
D007
V(EN) = 0.4 V
图 7. VIN Pin Shutdown Current vs Junction Temperature
图 8. EN Pin Voltage Threshold vs Junction Temperature
6
5.5
5
0.605
0.604
0.603
0.602
0.601
0.6
4.5
4
3.5
3
2.5
2
V(EN) = 1.1 V
V(EN) = 1.3 V
0.599
0.598
0.597
0.596
0.595
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (
è
C)
D009
D0087
图 10. Regulated FB Voltage vs Junction Temperature
图 9. EN Pin Current vs Junction Temperature
40
35
30
25
20
15
10
5
1400
High-side, V(BOOT-SW) = 4.5 V
High-side, V(IN) = 12 V
Low-side, V(IN) = 4.5 V
Low-side, V(IN) = 12 V
1350
1300
1250
1200
1150
1100
1050
1000
950
900
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D004
D011
图 11. MOSFET RDS(on) vs Junction Temperature
图 12. Error Amplifier Transconductance vs Junction
Temperature
8
版权 © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
Typical Characteristics (接下页)
19
5.3
5.25
5.2
18
17
16
15
14
13
12
5.15
5.1
5.05
5
4.95
4.9
4.85
4.8
4.75
4.7
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
Junction Temperature (èC)
D009
D013
图 13. V(COMP) to I(SW) Transconductance vs Ambient
图 14. SS/TRK Current vs Junction Temperature
Temperature
0.7
0.65
0.6
40
38
36
34
32
30
28
26
24
22
20
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
0.2
0.4
0.6
0.8
V(SS/TRK) (V)
1
1.2
1.4
1.6
1.8
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D002
D014
V(SS/TRK) = 0.4 V
图 16. FB voltage vs SS/TRK Voltage
图 15. SS/TRK to FB Offset vs Junction Temperature
16
110
108
106
104
102
100
98
15.5
15
14.5
14
V(FB) falling (fault)
V(FB) rising (good)
V(FB) rising (fault)
V(FB) falling (good)
96
13.5
13
94
92
V(VIN) = 4.5 V
V(VIN) = 12 V
V(VIN) = 17 V
90
12.5
12
88
86
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
Junction Temperature (èC)
D005
D016
L = 1.0 µH
图 17. High-side Peak Current Limit vs Ambient Temperature
图 18. PGOOD Thresholds vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
9
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Typical Characteristics (接下页)
2
1.8
1.6
1.4
1.2
1
1100
1000
900
800
700
600
500
400
300
200
100
0
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
-50
-25
0
25
50
75
100
125
150
I(PGOOD) (mA)
Junction Temperature (èC)
D006
D017
TJ = 25 °C
V(PGOOD) < 0.5 V
V(FB) = 0.6 V
V(PGOOD) = 5 V
图 20. Minimum Input Voltage for Valid PGOOD Output vs
图 19. PGOOD Leakage Current vs Junction Temperature
PGOOD Current
120
520
515
510
505
500
495
490
485
480
IOUT = 0 A
IOUT = 0.1 A
IOUT = 0.5 A
115
110
105
100
95
90
85
80
75
70
65
60
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
Junction Temperature (
èC)
D007
D020
V(VIN) = 12 V
L = 1.0 µH
R(RT/CLK) = 100 kΩ
图 21. Minimum on-time vs Ambient Temperature
图 22. Switching Frequency vs Junction Temperature (500
kHz)
650
600
550
500
450
400
350
300
250
200
1660
1650
1640
1630
1620
1610
1600
1590
1580
1570
1560
1550
1540
-50
-25
0
25
50
75
100
125
150
80
100 120 140 160 180 200 220 240 260
Junction Temperature (èC)
R(RT/CLK) (kW)
D021
D023
R(RT/CLK) = 30.1 kΩ
图 23. Switching Frequency vs Junction Temperature (1600
图 24. Switching Frequency vs RT/CLK Resistor (Low
kHz)
Range)
10
版权 © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
Typical Characteristics (接下页)
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
25 30 35 40 45 50 55 60 65 70 75 80 85
R(RT/CLK) (kW)
D024
图 25. Switching Frequency vs RT/CLK Resistor (High Range)
版权 © 2019, Texas Instruments Incorporated
11
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS54A24 is a 17-V, 10-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients the device implements a constant frequency,
peak current mode control which also simplifies external frequency compensation. The wide switching frequency
of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components.
The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The TPS54A24 also has an
internal phase lock loop (PLL) connected to the RT/CLK pin that can be used to synchronize the switching cycle
to the falling edge of an external system clock.
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 10
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. The device
reduces the external component count by integrating a bootstrap recharge circuit. The bias voltage for the
integrated high-side MOSFET is supplied by a capacitor between the BOOT and SW pins. The BOOT capacitor
voltage is monitored by a BOOT to SW UVLO (BOOT-SW UVLO) circuit allowing SW pin to be pulled low to
recharge the BOOT capacitor. The device can operate at 100% duty cycle as long as the BOOT capacitor
voltage is higher than the preset BOOT-SW UVLO threshold which is typically 2.2 V.
The TPS54A24 has been designed for safe startup into pre-biased loads. The default start up is when VIN is
typically 4.1 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage
under voltage lockout (UVLO) with two external resistors. In addition, the internal pullup current of the EN pin
allows the device to operate with the EN pin floating. The operating current for the TPS54A24 is typically 580 μA
when not switching and under no load. When the device is disabled, the supply current is typically 3 μA.
The SS/TRK (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor or resistor divider should be coupled to the pin for soft start or critical
power supply sequencing requirements. The output voltage can be stepped down to as low as the 0.6 V voltage
reference (VREF). The device has a power good comparator (PGOOD) with hysteresis which monitors the output
voltage through the FB pin. The PGOOD pin is an open drain MOSFET which is pulled low when the FB pin
voltage is less than 89% or greater than 108% of the reference voltage VREF and asserts high when the FB pin
voltage is 91% to 106% of VREF
.
The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the FB pin voltage is lower than 106% of the VREF. The device implements both high-side MOSFET over
current protection and bidirectional low-side MOSFET over current protections which help control the inductor
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal
shutdown trip point. The device is restarted under control of the soft start circuit automatically when the junction
temperature drops 15°C typically below the thermal shutdown trip point.
12
版权 © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
7.2 Functional Block Diagram
PGOOD
EN
VIN
Thermal
Shutdown
UVLO
Shutdown
Enable
Comparator
Ip
Ih
Shutdown
Shutdown
Logic
UV
Logic
Hiccup
Shutdown
Enable
Threshold
OV
BOOT
Charge
Minimum
Clamp
Pulse Skip
Current
Sense
ERROR
AMPLIFIER
FB
BOOT
Boot
UVLO
SS/TRK
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
& Deadtime
Control
SW
Logic
Slope
Compensation
VIN
Regulator
Hiccup
Shutdown
LS
Oscillator
with PLL
Maximum
Clamp
Overload
Recovery
MOSFET
Current
Limit
Current
Sense
PGND
COMP
RT/CLK
AGND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The device uses an adjustable fixed-frequency, peak-current-mode control. The output voltage is compared
through external resistors on the FB pin to an internal voltage reference by an error amplifier which drives the
COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is
converted into a current reference which compares to the high-side power switch current. When the power switch
current reaches current reference generated by the COMP voltage level the high-side power switch is turned off
and the low-side power switch is turned on.
The device adds an internal slope compensation ramp to prevent subharmonic oscillations. The peak inductor
current limit remains constant over the full duty cycle range.
7.3.2 Continuous Conduction Mode Operation (CCM)
As a synchronous buck converter, the device works in continuous conduction mode (CCM) under all load
conditions.
版权 © 2019, Texas Instruments Incorporated
13
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Feature Description (接下页)
7.3.3 VIN Pins and VIN UVLO
The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power
converter system. The input voltage for VIN can range from 4.5 V to 17 V. The device implements internal UVLO
circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO
threshold. The internal VIN UVLO threshold has a hysteresis of 200 mV. A voltage divider connected to the EN
pin can adjust the input voltage UVLO appropriately. See Enable and Adjustable UVLO for more details.
7.3.4 Voltage Reference and Adjusting the Output Voltage
The voltage reference system produces a precise ±0.85%, 0.6-V voltage reference over temperature by scaling
the output of a temperature stable band gap circuit. The output voltage is set with a resistor divider from the
output (VOUT) to the FB pin shown in 图 26. TI recommends using 1%-tolerance or better divider resistors. Start
with a fixed value for the bottom resistor in the divider, typically 5.1 kΩ or less, then use 公式 1 to calculate the
top resistor in the divider. If the values are too high the regulator is more susceptible to noise and voltage errors
from the FB input current are noticeable. If the values too high and if switching stops after low-side reverse
current limit trips or when in thermal shutdown, bias current out of the SW pin can charge up the output voltage.
Using 5.1-kΩ bottom resistance or less prevents the bias current out of the SW pin from charging the output
voltage above the set value. Larger resistance may be used if his bias current is accounted for. The minimum
output voltage and maximum output voltage can be limited by the minimum on time of the high-side MOSFET
and bootstrap voltage (BOOT-SW voltage), respectively.
VOUT
TPS54A24
RFBT
FB
+
0.6 V
RFBB
Copyright © 2018, Texas Instruments Incorporated
图 26. FB Resistor Divider
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(1)
7.3.5 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower
of the SS/TRK pin voltage or the internal 0.6-V voltage reference. The transconductance of the error amplifier is
1100 μA/V. The frequency compensation network is connected between the COMP pin and ground.
When operating at current limit the COMP pin voltage is clamped to a maximum level to improve response when
the load current decreases. When FB is greater than the internal voltage reference or SS/TRK the COMP pin
voltage is clamped to a minimum level and the devices enters a high-side skip mode.
14
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TPS54A24
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ZHCSJP6 –MAY 2019
Feature Description (接下页)
7.3.6 Enable and Adjustable UVLO
The EN pin provides on/off control of the device. Once the EN pin voltage exceeds its threshold voltage, the
device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching
and enters low operating current state. The EN pin has an internal pullup current source, Ip, allowing the user to
float the EN pin for enabling the device. If an application requires controlling the EN pin, an open drain or open
collector output logic can be interfaced with the pin.
An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown
in 图 27. The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no
external components are connected. The pullup current is also used to control the voltage hysteresis for the
UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can
be calculated using 公式 2 and 公式 3. When using the adjustable UVLO function, 500 mV or greater hysteresis
is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN
pin to ground to filter any glitches on the input voltage.
TPS54A24
VIN
EN
Ip
Ih
RENT
+
RENB
Copyright © 2018, Texas Instruments Incorporated
图 27. Adjustable UVLO Using EN
- V
≈
∆
«
’
÷
VENFALLING
VSTART
ì
STOP
VENRISING ◊
RENT
=
≈
’
÷
VENFALLING
I ì 1-
+I
h
∆
p
VENRISING ◊
«
(2)
(3)
vertical spacer
RENB
RENT ì VENFALLING
=
VSTOP - VENFALLING + RENT ì I +I
p
h
版权 © 2019, Texas Instruments Incorporated
15
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Feature Description (接下页)
7.3.7 Soft Start and Tracking
The TPS54A24 regulates to the SS/TRK pin while its voltage is lower than the internal reference to implement
soft start. A capacitor on the SS/TRK pin to ground sets the soft start time. The SS/TRK pin has an internal
pullup current source of 5 μA that charges the external soft start capacitor. 公式 4 calculates the required soft
start capacitor value. The FB voltage will follow the SS/TRK pin voltage with a 25 mV offset up to 90% of the
internal voltage reference. When the SS/TRK voltage is greater than 90% of the internal reference voltage the
offset increases as the effective system reference transitions from the SS/TRK voltage to the internal voltage
reference.
ISS µA ì t
ms
(
)
(
)
= 8.3ì tSS ms
SS
CSS nF =
(
)
(
)
VREF
V
(
)
(4)
If during normal operation, VIN goes below the UVLO, EN pin pulled below 1.15 V, or a thermal shutdown event
occurs, the TPS54A24 stops switching and the SS/TRK pin floats. When the VIN goes above UVLO, EN goes
above 1.2 V, or a thermal shutdown is exited, the SS/TRK pin is discharged to near ground before reinitiating a
powering up sequence.
When the COMP pin voltage is clamped by the maximum COMP clamp in an overload condition the SS/TRK pin
is discharged to near the FB voltage. When the overload condition is removed, the soft-start circuit controls the
recovery from the fault output level to the nominal output regulation voltage. At the beginning of recovery a spike
in the output voltage may occur while the COMP voltage transitions from the maximum clamp to the value
determined by the loop.
If a nominal SS/TRK capacitance of 22 nF or greater is used, TI recommends adding a 470-kΩ to 1-MΩ resistor
in parallel with the SS/TRK capacitor. With higher SS/TRK capacitance and if the EN pin voltage goes low then
high quickly, the SS/TRK capacitor may not fully discharge before switching begins. Adding this resistor helps
discharge the SS/TRK capacitor. For the SS capacitor to fully discharge, disable the TPS54A24 for a time period
equal to 3 times the RC time constant of the SS/TRK capacitor and the added resistor.
7.3.8 Safe Start-Up Into Prebiased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
prebiased startup, the low-side MOSFET is not allowed to sink current until the SS/TRK pin voltage is higher
than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if the BOOT-SW
voltage is below the UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed to turn on to
charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another layer of
protection for the device after the high-side MOSFET begins to switch.
7.3.9 Power Good
The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the FB
pin is between 91% and 106% of the internal voltage reference and SS/TRK is greater than 0.75 V, after a 272
cycle deglitch time the PGOOD pin is de-asserted and the pin floats. A pullup resistor between the values of 10
kΩ and 100 kΩ to a voltage source that is 6.5 V or less is recommended. PGOOD is in a defined state once the
VIN input voltage is greater than 1 V but with reduced current sinking capability.
When the FB is lower than 89% or greater than 108% of the nominal internal reference voltage, after a 16 cycle
deglitch time the PGOOD pin is pulled low. PGOOD is immediately pulled low if VIN falls below its UVLO, EN pin
is pulled low or the TPS54A24 enters thermal shutdown.
16
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TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
Feature Description (接下页)
7.3.10 Sequencing (SS/TRK)
Many of the common power supply sequencing methods can be implemented using the SS/TRK, EN and
PGOOD pins.
The sequential method is illustrated in 图 28 using two TPS54A24 or similar devices. The power good of the first
device is coupled to the EN pin of the second device which enables the second power supply once the primary
supply reaches regulation.
图 29 shows the method implementing ratiometric sequencing by connecting the SS/TRK pins of two devices
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start
time the current source must be doubled in 公式 4.
TPS54A24
PGOOD
TPS54A24
TPS54A24
EN
EN
EN
SS/TRK
PGOOD
SS/TRK
SS/TRK
PGOOD
Copyright © 2018, Texas Instruments Incorporated
TPS54A24
EN
SS/TRK
PGOOD
Copyright © 2018, Texas Instruments Incorporated
图 28. Sequential Start-Up Sequence
图 29. Ratiometric Start-Up Sequence
版权 © 2019, Texas Instruments Incorporated
17
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Feature Description (接下页)
Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of RTRT and RTRB shown in 图 30 to the output of the power supply that needs to be tracked or another voltage
reference source. Using 公式 6 and 公式 7, the tracking resistors can be calculated to initiate the VOUT2 slightly
before, after or at the same time as VOUT1. 公式 5 is the voltage difference between VOUT1 and VOUT2
.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in 公式 6 and 公式 7 for ΔV. 公式 5 results in a positive number for
applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TRK to FB
offset (Vssoffset = 25 mV) in the soft-start circuit and the offset created by the pullup current source (Iss = 5 μA)
and tracking resistors, the Vssoffset and Iss are included as variables in the equations.
When the TPS54A24 is enabled, an internal switch at the SS/TRK pin turns on to discharge the SS/TRK voltage
to near ground as described in Soft Start and Tracking. The SS/TRK pin voltage must discharge low enough
before the TPS54A24 starts up. If there is voltage on VOUT1 and the upper resistor at the SS/TRK pin is too
small, the SS/TRK pin cannot discharge low enough and VOUT2 does not ramp up. The upper resistor in the
SS/TRK divider may need to be increased to allow the SS/TRK pin to drop close enough to ground. To ensure
proper startup of VOUT2 , the calculated RTRT value from 公式 6 must be greater than the value calculated in 公式
8. Calculate RTRB using the final value of RTRT
.
DV = VOUT1 - VOUT2
(5)
vertical spacer
VOUT2 + DV
Vssoffset
Iss
RTRT
vertical spacer
RTRB
=
ì
VREF
(6)
VREF ìRTRT
VOUT2 + DV - VREF
=
(7)
(8)
vertical spacer
RTRT > 20000ì VOUT1
As described in Power Good, for the PGOOD output to be active the SS/TRK voltage must be above 0.75 V. The
external divider may prevent the SS/TRK voltage from charging above the threshold. For the SS/TRK pin to
charge above the threshold, a switch may be needed to disconnect the resistor divider or modify the resistor
divider ratio of the VOUT2 converter after start-up is complete. The PGOOD pin of the VOUT1 converter could be
used for this. One solution is to add a resistor from SS/TRK of the VOUT2 converter to the PGOOD of the VOUT1
converter. While the PGOOD of VOUT1 pulls low, this resistor is in parallel with RTRB. When VOUT1 is in regulation
its PGOOD pin will float. If the PGOOD pin of VOUT1 is connected to a pullup voltage, make sure to include this in
calculations. A second option is to use the PGOOD pin to turn on or turn off the external switch to change the
divide ratio.
18
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TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
Feature Description (接下页)
TPS54A24
VOUT1
EN
SS/TRK
PGOOD
TPS54A24
VOUT2
EN
RTRT
SS/TRK
PGOOD
RFBT
RFBB
RTRB
Copyright © 2018, Texas Instruments Incorporated
图 30. Ratiometric and Simultaneous Start-Up Sequence
7.3.11 Adjustable Switching Frequency (RT Mode)
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and AGND. The switching frequency
of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 250 kΩ and minimum of 30.1 kΩ
respectively. To determine the RT resistance for a given switching frequency, use 公式 9. To reduce the solution
size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and
minimum controllable on-time must be considered. 公式 10 can be used to calculate the switching frequency for
a given RT resistance.
-1.028
RT kW = 58650 ì f
kHz
(
)
(
)
SW
(9)
vertical spacer
fSW kHz = 43660 ìRT kW
-0.973
(
)
(
)
(10)
7.3.12 Synchronization (CLK Mode)
An internal phase locked loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz,
and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square
wave clock signal to the RT/CLK pin with a duty cycle from 20% to 80%. If the clock signals rising edge occurs
near the falling edge of SW, increased SW jitter may occur. Use 公式 11 to calculate the maximum clock pulse
width to minimize jitter in CLK mode. The clock signal amplitude must transition lower than 0.8 V and higher than
2 V. The start of the switching cycle is synchronized to the falling edge of the RT/CLK pin.
æ
ö
÷
V
OUT
ç
0.75´ 1-
ç
è
V
÷
IN min
(
)
ø
CLK _PW
=
MAX
f
SW
(11)
19
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TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
Feature Description (接下页)
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in 图
31. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin
is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock.
If the input clock goes away the internal clock frequency begins to drop and after 10 µs without a clock the
device returns to RT mode. Output undershoot while the switching frequency drops can occur. Output overshoot
can also occur when the switching frequency steps back up to the RT mode frequency. A high impedance tri-
state buffer as shown in 图 33 is recommended for best performance during the transition from CLK mode to RT
mode because it minimizes the loading on the RT/CLK pin allowing faster transition back to RT mode. 图 34
shows the typical performance for the transition from RT mode to CLK mode then back to RT mode.
A series RC circuit as shown in 图 32 can also be used to interface the RT/CLK pin but the capacitive load slows
down the transition back to RT mode. The series RC circuit is not recommended if the transition from CLK mode
to RT mode is important. A capacitor in the range of 47 pF to 470 pF is recommended. When using the series
RC circuit verify the amplitude of the signal at the RT/CLK pin goes above the high threshold.
RT/CLK Mode Select
TPS54A24
TPS54A24
RT/CLK
RT/CLK
2 kꢀ
47 pF
RT
RT
Copyright © 2018, Texas Instruments Incorporated
Copyright © 2018, Texas Instruments Incorporated
图 31. Simplified Circuit When Using Both RT Mode 图 32. Interfacing to the RT/CLK Pin with Series RC
and CLK Mode
CH2: VOUT DC OFFSET
TPS54A24
OE
RT/CLK
RT
CH3: RT/CLK
CH1: SW
Copyright © 2018, Texas Instruments Incorporated
VIN = 12 V, IOUT = 4 A,
VOUT = 3.3 V, fsw = 1.2 MHz
图 33. Interfacing to the RT/CLK Pin with Buffer
图 34. RT to CLK to RT Transition with Buffer
20
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ZHCSJP6 –MAY 2019
Feature Description (接下页)
7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
The device provides an integrated bootstrap-voltage regulator. A small capacitor between the BOOT and SW
pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the low-
side MOSFET is on. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R
or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over
temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the device operate
at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.2 V. The device begins to transition
to 100% duty cycle operation when the high-side MOSFET off-time is less than 200 ns typical. 公式 12 can be
used to estimate the input voltage the switching frequency begins to decrease. When the switching frequency
decreases the BOOT to SW capacitor is not recharged as often so the BOOT to SW voltage will start to
decrease. If the voltage from BOOT to SW drops below 2.2 V, the high-side MOSFET is turned off due to BOOT
UVLO and the low-side MOSFET pulls SW low to recharge the BOOT capacitor. When operating at 100% duty
cycle the high-side MOSFET can remain on for many switching cycles before the MOSFET is turned off to
refresh the capacitor because the gate drive current sourced by the BOOT capacitor is small. The effective
switching frequency reduced and the effective maximum duty cycle of the switching regulator is near 100%. The
output voltage of the converter during dropout is mainly influenced by the voltage drops across the power
MOSFET, the inductor resistance, and the printed circuit board resistance.
VOUT + RDS(LS) + RDCR ìI
(
)
OUT
V
=
+ RDS(HS) -RDS(LS) ìI
OUT
(
)
IN
1- tOFF ì fSW
where
•
•
•
•
RDS(LS) = low-side MOSFET RDS(on)
RDS(HS) = high-side MOSFET RDS(on)
RDCR = DC resistance of inductor
tOFF = off-time that 100% duty cycle operation begins
(12)
7.3.14 Output Overvoltage Protection (OVP)
The TPS54A24 incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. The OVP
threshold is the same as the 108% PGOOD threshold. If the FB pin voltage is greater than the OVP threshold
the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output
overshoot. When the high-side MOSFET turns off, the low-side MOSFET turns on and the current in the inductor
discharges. The output voltage can overshoot the OVP threshold as the current in the inductor discharges to 0 A.
When the FB voltage drops lower than the 106% PGOOD threshold, the high-side MOSFET is allowed to turn on
at the next clock cycle.
7.3.15 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET. In an extended overcurrent condition the device enters hiccup to reduce
power dissipation. 图 35 shows the typical response with an overload on the output. At time (1) the high-side
MOSFET peak current limit starts to limit the peak inductor current. At time (2) the low-side MOSFET forward
current limit starts to cause the switching frequency to drop to prevent current runaway.
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21
TPS54A24
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Feature Description (接下页)
(1)
(2)
图 35. Example Current Limit Waveform
7.3.15.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turnoff of the high-
side MOSFET and the turnon of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference the high-side switch is turned off. The maximum peak switch current through the
high-side MOSFET for overcurrent protection is done by limiting the current reference internally. If the peak
current required to regulate the output is greater than the internal limit, the output voltage is pulled low and the
error amplifier responds by driving the COMP pin high. The maximum COMP voltage is then clamped by an
internal COMP clamp circuit. If the COMP voltage is clamped high for more than the hiccup wait time of 512
switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles.
7.3.15.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on the current through it is monitored. During normal operation the low-
side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing
current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is
exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The
high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at
the start of a cycle. The low-side sourcing current limit prevents current runaway.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle. If the low-side MOSFET turns off due to sinking current limit protection, the
low-side MOSFET can only turn on again after the high-side MOSFET turns on then off or if the device enters
BOOT UVLO.
7.4 Device Functional Modes
The EN pin and a VIN UVLO is used to control turn on and turn off of the TPS54A24. The device becomes active
when V(VIN) exceeds the 4.1 V typical UVLO and when V(EN) exceeds 1.20 V typical. The EN pin has an internal
current source to enable the output when the EN pin is left floating. If the EN pin is pulled low the device is put
into a low quiescent current state.
22
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TPS54A24
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ZHCSJP6 –MAY 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54A24 is a synchronous buck converter designed for 4.5 V to 17 V input and 10-A load. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Alternatively the
WEBENCH® software can be used to generate a complete design. The WEBENCH® software uses an interactive
design procedure and accesses a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
8.2 Typical Application
图 36. TPS54A24 4.5-V to 17-V Input, 1.8-V Output Converter Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters shown in 表 1.
表 1. Design Parameters
PARAMETER
EXAMPLE VALUE
4.5 to 17 V, 12 V nominal
1.8 V
Input voltage range (VIN
)
Output voltage (VOUT
)
Transient response
± 4%, ± 72 mV
0.5%, 9 mV
Output ripple voltage
Output current rating (IOUT
Operating frequency (fSW
)
10 A
)
500 kHz
版权 © 2019, Texas Instruments Incorporated
23
TPS54A24
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54A24 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency
The first step is to decide on a switching frequency for the converter. The TPS54A24 is capable of running from
200 kHz to 1.6 MHz. Typically the highest switching frequency possible is desired because it produces the
smallest solution size. A high switching frequency allows for smaller inductors and output capacitors compared to
a power supply that switches at a lower frequency. The main trade off made with selecting a higher switching
frequency is extra switching power loss, which hurt the converter’s efficiency.
The maximum switching frequency for a given application is limited by the minimum on-time of the converter and
is estimated with 公式 13. Using a maximum minimum on-time of 150 ns for the TPS54A24 and 17 V maximum
input voltage for this application, the maximum switching frequency is 706 kHz. The selected switching frequency
must also consider the 10% tolerance of the switching frequency. A switching frequency of 500 kHz was selected
for a good balance of solution size and efficiency. 公式 14 calculates R7 (RT) to be 97.6 kΩ. A standard 1% value
of 100 kΩ was chosen in the design.
VOUT
max
1
fSW max =
ì
(
)
tonmin
V
IN
(13)
(14)
vertical spacer
-1.028
RT kW = 58650 ì f
kHz
(
)
(
)
SW
8.2.2.3 Output Inductor Selection
To calculate the value of the output inductor, use 公式 15. KIND is a ratio that represents the amount of inductor
ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.
Additionally with current mode control the sensed inductor current ripple is used in the PWM modulator.
Choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the
high-side MOSFET on-time. The inductor ripple, KIND, is normally from 0.1 to 0.4 for the majority of applications
giving a peak to peak ripple current range of 1 A to 4 A. For applications requiring operation near the minimum
on-time, with on-times less than 200 ns, the target Iripple must be 2 A or larger for best performance. For other
applications the target Iripple must be 1 A or larger.
For this design example, KIND = 0.3 is used and the inductor value is calculated to be 1.07 µH. The nearest
standard value 1 µH is selected. It is important that the RMS (Root Mean Square) current and saturation current
ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from 公式 17 and 公式
18. For this design, the RMS inductor current is 10 A, and the peak inductor current is 11.6 A. The chosen
inductor is a 74437358010. It has a saturation current rating of 32.5 A and a RMS current rating of 14 A. The DC
series resistance is 3.65 mΩ typical.
24
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TPS54A24
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in 公式 18. In transient conditions, the inductor current can increase up to the switch current limit
of the device. For this reason, the most conservative approach is to specify the ratings of the inductor based on
the switch current limit rather than the steady-state peak inductor current.
Vinmax - Vout
Vout
L1 =
´
Io ´ Kind
Vinmax ´ ¦sw
(15)
vertical spacer
Vinmax - Vout
Vout
Iripple =
´
L1
Vinmax ´ ¦sw
(16)
vertical spacer
æ
ö2
÷
1
Vo ´ (Vinmax - Vo)
Vinmax ´ L1 ´ ¦sw
ILrms = Io2
+
´
ç
12
è
ø
(17)
(18)
vertical spacer
ILpeak = Iout +
Iripple
2
8.2.2.4 Output Capacitor
There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple
and how the regulator responds to a large change in load current. The output capacitance needs to be selected
based on the more stringent of these two criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to
sense the change in the output voltage then adjust the peak switch current in response to the change in load.
The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically the loop
bandwidth is near fSW/10. 公式 19 estimates the minimum output capacitance necessary, where ΔIOUT is the
change in output current and ΔVOUT is the allowable change in the output voltage.
For this example, the transient load response is specified as a 4% change in VOUT for a load step of 5 A.
Therefore, ΔIOUT is 5 A and ΔVOUT is 72 mV. Using this target gives a minimum capacitance of 221 μF. This
value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic
capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response.
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公式 20 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the target maximum output voltage ripple is 9 mV. Under this requirement, 公
式 20 yields 89.4 µF.
vertical spacer
DIOUT
DVOUT
1
COUT
>
ì
fSW
2pì
10
(19)
vertical spacer
1
1
Co >
´
Voripple
Iripple
8 ´ ¦sw
where
•
•
•
ΔIOUT is the change in output current
ΔVOUT is the allowable change in the output voltage
fsw is the regulators switching frequency
(20)
公式 21 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple
specification, and this shows the ESR should be less than 3 mΩ. In this case ceramic capacitors are used, and
the combined ESR of the ceramic capacitors in parallel is much less than 3 mΩ. Capacitors also have limits to
the amount of ripple current they can handle without producing excess heat and failing. An output capacitor that
can support the inductor ripple current must be specified. The capacitor datasheet specifies the RMS value of the
maximum ripple current. 公式 22 can be used to calculate the RMS ripple current the output capacitor needs to
support. For this application, 公式 22 yields 930 mA and ceramic capacitors typically have a ripple current rating
much higher than this.
Voripple
Resr <
Iripple
(21)
vertical spacer
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(22)
Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high
capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected
with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic
capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website.
For this application example, three 100 µF 6.3 V 1210 X7S ceramic capacitors each with 2 mΩ of ESR are used.
The estimated capacitance after derating using the capacitor manufacturer's website is 64 µF each. With three
parallel capacitors the total effective output capacitance is 192 µF and the ESR is 0.7 mΩ. Although this is below
the estimated value of 221 µF to meet the load step response requirement, bench evaluation showed this
amount of capacitance to be sufficient.
8.2.2.5 Input Capacitor
The TPS54A24 requires input decoupling ceramic capacitors type X5R, X7R or similar from VIN to PGND placed
as close as possible to the IC. A total of at least 10 µF of capacitance is required and some applications may
require a bulk capacitance. At least 1 µF of bypass capacitance is recommended near both VIN pins to minimize
the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed by both VIN pins 2-3 and 16-17 to provide
high frequency bypass to reduce the high frequency overshoot and undershoot on VIN and SW pins. The voltage
rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a
ripple current rating greater than the maximum RMS input current of the TPS54A24. The RMS input current can
be calculated using 公式 23.
26
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For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the
maximum input voltage. Two 10-µF, 1210, X7R, 25-V and two 0.1-μF, 0603, X7R 25-V capacitors in parallel has
been selected to be placed on both sides of the TPS54A24 near both VIN pins to PGND pins. Based on the
capacitor manufacturer's website, the total ceramic input capacitance derates to 14 µF at the nominal input
voltage of 12 V. A 100-µF bulk capacitance is also used in this circuit to bypass long leads when connected a lab
bench top power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 公式 24. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the
nominal design example values of Ioutmax = 10 A, CIN = 14 μF, and fSW = 500 kHz, the input voltage ripple with
the 12 V nominal input is 150 mV and the RMS input ripple current with the 4.5 V minimum input is 4.9 A.
Vinmin - Vout
(
)
Vout
Icirms = Iout ´
vertical spacer
´
Vinmin
Vinmin
(23)
Vout
Vin
Vout
≈
«
’
◊
Ioutmaxì 1-
ì
∆
÷
Vin
DVin =
Cinì fSW
(24)
8.2.2.6 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by R8 (RFBT) and R6 (RFBB) from the output node to the
FB pin. It is recommended to use 1% tolerance or better resistors. For this example design, 6.04 kΩ was
selected for R8. Using 公式 25, R6 is calculated as 12.08 kΩ. The nearest standard 1% resistor is 12.1 kΩ.
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(25)
8.2.2.7 Soft-Start Capacitor Selection
The soft-start capacitor (CSS = C16) determines the amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54A24 reach its current limit or cause the input voltage rail to sag due excessive current draw from the input
power supply. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor value
can be calculated using 公式 26. For the example circuit, the soft-start time is not critical because the output
capacitor value of 3 × 100 μF does not require much current to charge to 1.8 V. The example circuit has the soft-
start time set to an arbitrary value of 1.2 ms, which requires a 0.01-µF capacitor. With this soft-start time the
current required to charge the output capacitors is only 0.18 A.
ISS µA ì t
ms
(
)
(
)
= 8.3ì tSS ms
SS
CSS nF =
(
)
(
)
VREF
V
(
)
(26)
8.2.2.8 Undervoltage Lockout Setpoint
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R2 (RENT) and R9
(RENB). The UVLO has two thresholds; one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. For the example design, the supply must turn on and start
switching once the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 4.0 V (UVLO stop or disable). 公式 2 and 公式 3
can be used to calculate the values for the upper and lower resistor values. For the voltages specified, the
standard resistor value used for RENT is 86.6 kΩ and for RENB is 30.9 kΩ.
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8.2.2.9 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. A 1 Ω to 5.6
Ω resistor can be added in series with the BOOT capacitor to slow down the turn on of the high-side MOSFET.
This can reduce voltage spikes on the SW node with the trade off of more power loss and lower efficiency.
8.2.2.10 PGOOD Pullup Resistor
A 100-kΩ resistor is used to pull up the power good signal when FB conditions are met. The pullup voltage
source must be less than the 6.5 V absolute maximum of the PGOOD pin.
8.2.2.11 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation internal to the device. Because the slope
compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency
used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low
ESR output capacitors. Use the WEBENCH® software for more accurate loop compensation. These tools include
a more comprehensive model of the control loop.
To get started, the modulator pole, fpmod, and the ESR zero, fzmod must be calculated using 公式 27 and 公式
28. For COUT, use a derated value of 192 μF and an ESR of 0.7 mΩ. Use equations 公式 29 and 公式 30, to
estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design,
fpmod is 7.2 kHz and fzmod is 1940 kHz. 公式 29 is the geometric mean of the modulator pole and the ESR
zero. 公式 30 is the mean of modulator pole and one half the switching frequency. 公式 29 yields 118 kHz and 公
式 30 yields 42.4 kHz. Use the lower value of 公式 29 or 公式 30 for an initial crossover frequency. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout
(27)
vertical spacer
1
¦z mod =
2 ´ p ´ Resr × Cout
(28)
(29)
vertical spacer
fco
vertical spacer
fco fpmod´
=
fpmod´ fzmod
fsw
=
2
(30)
To determine the compensation resistor (RCOMP = R5) use 公式 31. RCOMP is calculated to be 5.26 kΩ and the
closest standard value 5.23 kΩ. Use 公式 32 to set the compensation zero to the modulator pole frequency. 公式
32 yields 2120 pF for compensating capacitor (CCOMP = C14); round this up to the next standard value of 2200
pF.
≈
∆
«
’ ≈
’
÷
2ì pì fCO ìCOUT
VOUT
RCOMP
=
ì
÷ ∆
gmPS
VREF ì gmEA ◊
◊ «
where
•
•
•
•
Power stage transconductance, gmPS = 17 A/V
VOUT = 1.8 V
VREF = 0.6 V
Error amplifier transconductance, gmEA = 1100 µA/V
(31)
(32)
1
CCOMP
=
2ì pìRCOMP ì fPMOD
28
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TPS54A24
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ZHCSJP6 –MAY 2019
A compensation pole is implemented using an additional capacitor (CHF = C13) in parallel with the series
combination of RCOMP and CCOMP. This capacitor is recommended to help filter any noise that may couple to the
COMP voltage signal. Use the larger value of 公式 33 and 公式 34 to calculate the CHF and to set the
compensation pole. CHF is calculated to be the largest of 16 pF and 112 pF. Round this down to the next
standard value of 100 pF.
COUT ìRESR
CHF
=
RCOMP
(33)
vertical spacer
CHF
1
=
pìRCOMP ì fSW
(34)
Type III compensation can be used by adding the feed forward capacitor (CFF = C15) in parallel with the upper
feedback resistor. Type III compensation adds phase boost above what is possible from type II compensation
because it places an additional zero/pole pair. The zero/pole pair is not independent. As a result once the zero
location is chosen, the pole is fixed as well. The zero is placed at 1/2 the fSW by calculating the value of CFF with
公式 35. The calculated value is 53 pF — round this down to the closest standard value of 47 pF. It is possible to
use larger feedforward capacitors to further improve the transient response but take care to ensure there is a
minimum of -10 dB gain margin at 1/2 the fSW in all operating conditions. The feedforward capacitor injects noise
on the output into the FB pin and this added noise can result in more jitter at the switching node. To little gain
margin can cause a repeated wide and narrow pulse behavior.
(35)
The initial compensation based on these calculations is RCOMP = 5.23 kΩ, CCOMP = 2200 pF, CHF = 100 pF and
CFF = 47 pF. These values yield a stable design but after testing the real circuit these values were changed to
target a higher crossover frequency to improve transient response performance. The crossover frequency is
increased by increasing the value of R5 and decreasing the value of the compensation capacitors. The final
values used in this example are RCOMP = 10.0 kΩ, CCOMP = 2700 pF, CHF = 22 pF and CFF = 100 pF.
版权 © 2019, Texas Instruments Incorporated
29
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8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 12 V
VIN = 17 V
VIN = 5 V
VIN = 12 V
VIN = 17 V
0
1
2
3
4
5
6
7
8
9
10
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
2 3 45 7 10
Output Current (A)
D001
D002
TA = 25°C
VOUT = 1.8 V
fSW = 500 kHz
TA = 25°C
VOUT = 1.8 V
fSW = 500 kHz
图 37. Efficiency
图 38. Efficiency (Log Scale)
50
45
40
35
30
25
20
15
10
5
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
VIN = 5 V
VIN = 12 V
VIN = 17 V
TPS54A24
Inductor
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Current (A)
VOUT = 1.8 V
4 layers
Output Current (A)
D006
D003
VIN = 12 V
fSW = 500 kHz
TA = 25°C
VOUT = 1.8 V
fSW = 500 kHz
3 inch × 3 inch
EVM
2 ounce copper
图 40. Load Regulation
图 39. Thermal Performance
0.5
0.4
0.3
0.2
0.1
0
60
40
180
120
60
20
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-20
-40
-60
-60
-120
IO = 0 A
IO = 5 A
IO = 10 A
Gain
Phase
-180
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
100 200 5001000
10000
100000
1000000
Input Voltage (V)
Frequency (Hz)
D004
D005
TA = 25°C
VOUT = 1.8 V
fSW = 500 kHz
VIN = 12 V
VOUT = 1.8 V
ROUT = 0.3 Ω
图 41. Line Regulation
图 42. Loop Response
30
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TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
VIN = 12 V
VOUT = 1.8 V
VIN = 12 V
VIN = 12 V
ROUT = 1 Ω
VOUT = 1.8 V
IOUT = 0 A
图 43. Transient Response
图 44. Output Ripple, No Load
VIN = 12 V
VOUT = 1.8 V
IOUT = 10 A
VOUT = 1.8 V
IOUT = 0 A
图 45. Output Ripple, 10-A Load
图 46. Input Ripple, No Load
VIN = 12 V
VOUT = 1.8 V
IOUT = 10 A
图 47. Input Ripple, 10-A Load
图 48. VIN Start-up
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ROUT = 1 Ω
ROUT = 1 Ω
图 49. VIN Shutdown
图 50. EN Start-up
ROUT = 1 Ω
图 51. EN Shutdown
图 52. EN Start-up With Prebiased Output
VIN = 12 V
Load = short
VIN = 12 V
Load = short
图 53. Output Short-Circuit Response
图 54. Hiccup Current Limit
32
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TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
VIN = 12 V
Load = short
图 55. Hiccup Recovery
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33
TPS54A24
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www.ti.com.cn
9 Power Supply Recommendations
The TPS54A24 is designed to be powered by a well-regulated DC voltage between 4.5 and 17 V. The
TPS54A24 is a buck converter so the input supply voltage must be greater than the desired output voltage to
regulate the output voltage to the desired value. If the input supply voltage is not high enough the output voltage
begins to drop. Input supply current must be appropriate for the desired output current.
10 Layout
10.1 Layout Guidelines
•
•
VIN and PGND traces must be as wide as possible to reduce trace impedance and improve heat dissipation.
At least 1 µF of input capacitance is required on both VIN pins of the IC and must be placed as close as
possible to the IC. The input capacitors must connect directly to the adjacent PGND pins.
•
•
Connect the PGND pins on both sides of the IC to the thermal pad with a trace as wide as possible to reduce
trace impedance and improve heat dissipation.
The PGND trace between the output capacitor and the PGND pin must be as wide as possible to minimize its
trace impedance.
•
•
•
Provide sufficient vias for the input capacitor and output capacitor.
Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
Minimize the length of the trace connected to the BOOT pin and the BOOT capacitor to minimize radiated
emissions.
•
•
Connect a separate VOUT path to the upper feedback resistor.
Place voltage feedback loop away from the high-voltage switching trace. It is preferable to use ground copper
near it as a shield.
•
•
The trace connected to the FB node must be as small as possible to avoid noise coupling.
Place components connected to the RT/CLK, FB, COMP and SS/TRK pins as close to the IC as possible and
minimize traces connected to these pins to avoid noise coupling.
•
AGND must be connected to PGND on the PCB. Connect AGND to PGND in a region away from switching
currents.
10.2 Layout Example
图 56 through 图 59 shows an example PCB layout and the following list provides a description of each layer.
•
The top layer has all components and the main traces for VIN, SW, VOUT and PGND. Both VIN pins are
bypassed with two input capacitors placed as close as possible to the IC and are connected directly to the
adjacent PGND pins. Multiple vias are placed near the input and output capacitors. The Net Tie (NT)
connects AGND to PGND near CIN4.
•
•
Midlayer 1 has a solid PGND plane to aid with thermal performance. The other trace on this layer to connect
the PGOOD pin to the pullup resistor.
Midlayer 2 has a wide trace connecting both VIN pins of the IC. It is also used to route the BOOT-SW
capacitor (CBT) to the SW node. It also has a parallel trace for VOUT to minimize trace resistance. The rest
of this layer is covered with PGND.
•
The bottom layer has the trace connecting the FB resistor divider to VOUT at the point of regulation. PGND is
filled into the rest of this layer to aid with thermal performance.
34
版权 © 2019, Texas Instruments Incorporated
TPS54A24
www.ti.com.cn
ZHCSJP6 –MAY 2019
Layout Example (接下页)
图 56. TPS54A24 Layout Top
图 57. TPS54A24 Layout Midlayer 1
图 58. TPS54A24 Layout Midlayer 2
图 59. TPS54A24 Layout Bottom
版权 © 2019, Texas Instruments Incorporated
35
TPS54A24
ZHCSJP6 –MAY 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，以使用 TPS54A24 器件并借助 WEBENCH® 电源设计器进行定制设计。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
36
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54A24RTWR
ACTIVE
WQFN
RTW
24
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
S54A24
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
4.15
3.85
A
B
4.15
3.85
PIN 1 INDEX AREA
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
2X 2.5
EXPOSED
THERMAL PAD
12
7
20X 0.5
6
13
25
SYMM
2X
2.5
2.45±0.1
1
18
0.3
24X
0.18
19
0.5
24
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.05
C
24X
0.3
4219135/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.24)
(0.97)
25
SYMM
(3.8)
20X (0.5)
(R0.05)
TYP
13
6
(Ø0.2) TYP
VIA
7
12
(0.97)
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219135/B 11/2016
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
4X( 1.08)
(0.64) TYP
19
24
(R0.05) TYP
24X (0.6)
25
1
18
(0.64)
TYP
24X (0.24)
SYMM
(3.8)
20X (0.5)
13
6
7
12
METAL
TYP
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4219135/B 11/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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