TPS55165QPWPRQ1 [TI]
2V 至 36V、1A 输出、2MHz、5V 或 12V 固定输出电压、升压和降压转换器 | PWP | 20 | -40 to 125;型号: | TPS55165QPWPRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 2V 至 36V、1A 输出、2MHz、5V 或 12V 固定输出电压、升压和降压转换器 | PWP | 20 | -40 to 125 开关 光电二极管 转换器 |
文件: | 总48页 (文件大小:2585K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS55160-Q1, TPS55162-Q1, TPS55165-Q1
ZHCSH41A –NOVEMBER 2017 –REVISED DECEMBER 2021
TPS5516x-Q1 36V、1A 输出、2MHz、单电感器、同步升压
和降压稳压器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性:
– 器件温度等级1:–40°C 至+125°C 的工作环
境温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 提供功能安全
TPS5516x-Q1 系列器件是一款高电压同步降压/升压直
流/直流转换器。该器件通过多种不同的输入电源(如
汽车电池)提供稳定的电源输出。降压/升压重叠控制
可确保以最佳的效率在降压和升压模式之间自动转换。
TPS55165-Q1 输出电压可以设置为 5V 或 12V 固定电
平。TPS55160-Q1 和 TPS55162-Q1 器件具有通过外
部电阻分压器设置的5.7V 至9V 可配置输出电压。
– 可帮助进行功能安全系统设计的文档
• VOUT = 5V 时的输入电压范围为2V 至36V
• 5V 或12V 固定输出电压(TPS55165-Q1)
• 5.7V 至9V 可调输出电压选项
(TPS55160-Q1 和TPS55162-Q1)
• 效率高达85%
• VOUT = 5V 且VIN ≥5.3V 时的输出电流为1A
• VOUT = 5V 且VIN ≥3.8V 时的输出
电流为0.8A
• VOUT = 5V 且VIN ≥2.3V 时的输出
电流为0.4A
• 在降压和升压模式之间自动转换
• 低功耗模式,可在轻负载情况下提高效率
(TPS55160-Q1/TPS55165-Q1)
对于常规汽车电池电压,输出电流可高至 1A,并且能
够针对更低的输入电压(如用于实现常见电池启动曲线
的电压)保持在 0.4A。该降压/升压转换器基于一个使
用同步整流的固定频率、脉宽调制 (PWM) 控制电路来
获得最高效率。开关频率设置为2MHz(典型值),从
而允许使用小型电感器(布板空间更少)。
器件信息
封装(1)
封装尺寸(标称值)
器件型号
TPS55160-Q1
TPS55162-Q1
TPS55165-Q1
HTSSOP (20)
6.50mm x 4.40mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 在低功耗模式下器件静态电流小于15μA
(TPS55160-Q1/TPS55165-Q1)
简化版原理图
• 器件关断电流小于3μA
VOUT = 5 V
4.7 µF
• 2MHz 强制固定运行频率
0.1 µF
BST1 L1
0.1 µF
1 A at VIN
ꢀ 5.3 V
0.8 A at VIN
0.4 A at VIN
ꢀ
3.8 V
2.3 V
• 可选展频(TPS55160-Q1 和TPS55165-Q1)
• 通过具有电源锁存功能的IGN 唤醒
• 具有可配置延迟时间的智能电源正常输出
• 过热保护和输出过压保护
2V≤VIN≤36V
L2 BST2
ꢀ
VINP
VOUT
10 µF
VINL
100 k
22 µF
PG
VOUT_SENSE
Power
Latch
ON
IGN_PWRL
IGN
SS_EN
100 nF
• 采用易于使用的20 引脚HTSSOP PowerPAD™ 封
VOS_FB
装
OFF
VREG
VREG_Q
PG_DLY
Low-
Power
Mode
PS
2 应用
PGND
GND
RDLY
4.7 µF
TPS5516x-Q1
• 启停敏感型汽车电源应用
– 信息娱乐系统与仪表组
– 车身电子装置和网关模块
• 具有波动输入电压的工业应用
– 太阳能和电池充电
– 锂离子电池组
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSD46
TPS55160-Q1, TPS55162-Q1, TPS55165-Q1
ZHCSH41A –NOVEMBER 2017 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics —External Components.... 6
7.6 Electrical Characteristics —Supply Voltage
7.17 Switching Characteristics —IGN Wakeup..............11
7.18 Switching Characteristics —Logic Pins PS,
IGN_PWRL, SS_EN....................................................11
7.19 Switching Characteristics –Power Good.............. 12
7.20 Typical Characteristics............................................13
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................19
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 32
10 Power Supply Recommendations..............................36
11 Layout...........................................................................37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................39
12.1 Device Support....................................................... 39
12.2 Documentation Support.......................................... 39
12.3 接收文档更新通知................................................... 39
12.4 支持资源..................................................................39
12.5 Trademarks.............................................................39
12.6 Electrostatic Discharge Caution..............................39
12.7 术语表..................................................................... 39
13 Mechanical, Packaging, and Orderable
(VINP, VINL pins).......................................................... 6
7.7 Electrical Characteristics —Reference Voltage
(VOS_FB Pin) and Output Voltage (VOUT Pin)............ 7
7.8 Electrical Characteristics —Buck-Boost.....................8
7.9 Electrical Characteristics —Undervoltage and
Overvoltage Lockout..................................................... 9
7.10 Electrical Characteristics —IGN Wakeup.................9
7.11 Electrical Characteristics —Logic Pins PS,
IGN_PWRL, SS_EN......................................................9
7.12 Electrical Characteristics –Overtemperature
Protection.................................................................... 10
7.13 Electrical Characteristics –Power Good...............10
7.14 Switching Characteristics —Reference Voltage
(VOS_FB Pin) and Output Voltage (VOUT Pin).......... 10
7.15 Switching Characteristics —Buck-Boost................11
7.16 Switching Characteristics —Undervoltage and
Overvoltage Lockout....................................................11
Information.................................................................... 39
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2017) to Revision A (December 2021)
Page
• 添加了功能安全项目符号.................................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更改了原理图以显示与器件引脚正确对应的关-开波形........................................................................................1
• 删除了预发布说明...............................................................................................................................................1
• Updated Overcurrent Protection section...........................................................................................................18
• Changed 方程式5 solution from "0.458 A" to "0.229 A"...................................................................................33
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5 说明(续)
可选的扩频选项(TPS55160-Q1 和 TPS55165-Q1)有助于降低辐射电磁干扰 (EMI)。利用内部环路补偿,无需
使用外部补偿组件。在低功耗模式(TPS55160-Q1 和 TPS55165-Q1)下,该器件可实现小于 15µA 的静态电
流,从而使汽车电子控制单元(ECU) 能够保持在待机模式(例如侦听CAN 模式),同时可满足OEM 静态电流要
求。可以禁用低功耗模式,从而强制转换器针对整个负载电流范围以 2MHz(典型值)的固定开关频率在完全连
续模式下运行。电感器中的最大平均电流被限制在2A 的典型值。
可以通过禁用转换器来最大限度地减少电池消耗。此外,该器件还提供电源正常(PG) 引脚,以指示输出轨何时低
于指定的容差。该器件还具有电源锁存功能,以允许外部微控制器单元 (MCU) 使输出电压在所需的时长内保持可
用。
该器件采用20 引脚HTSSOP PowerPAD 封装。
6 Pin Configuration and Functions
PGND
L1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
L2
BST2
BST1
GND
VINP
VOUT
VOUT_SENSE
PG
VINL
Thermal
Pad
IGN
PS
VOS_FB
GND
IGN_PWRL
SS_EN
PG_DLY
VREG
VREG_Q
Not to scale
图6-1. PWP PowerPAD™ Package 20-Pin HTSSOP With Exposed Thermal Pad Top View
表6-1. Pin Functions
PIN
I/O(1) TYPE(2)
DESCRIPTION
NAME
NO.
PGND
1
G
A
Power-ground pin
—
Buck power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the
L1 and L2 pins.
L1
2
3
I
Bootstrap node for the buck power stage. Connect a 100-nF capacitor between this pin and the L1
pin.
BST1
I
A
VINP
VINL
4
5
P
P
Supply-power input voltage. Connect this pin to the input supply line.
—
—
Supply-input voltage for internal biasing. Connect this pin to the input supply line.
Ignition-enable input signal. The ignition is enabled when this pin is high (1) and is disabled when
this pin is low (0).
IGN
PS
6
7
8
9
I
I
I
I
D
D
D
D
Logic-level input signal to enable and disable low-power mode. The power mode is low-power
mode when this pin is high (1) and is normal mode when this pin is low (1).
Logic-level IGN power-latch signal. The IGN pin is latched when this pin is high (1) and is not
latched when this pin is low (0).
IGN_PWRL
SS_EN
Configuration pin to enable and disable the spread-Spectrum. The spread-spectrum feature is
enabled when this pin is open and disabled when this pin is low.
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表6-1. Pin Functions (continued)
PIN
I/O(1) TYPE(2)
DESCRIPTION
NAME
NO.
Configuration pin for power-good delay time. Connect this pin to a resistor with a value from 10kΩ
to 100kΩto configure the PG delay time from 0.5 ms to 40 ms. Connect this pin to ground for the
default PG delay time which is 2 ms (typical).
PG_DLY
10
I
I
A
A
Quiet feedback pin for the gate-drive supply of the buck-boost power stages. This pin must be
connected close to the top side of the 4.7-µF (typical) decoupling capacitor at the VREG output
pin.
VREG_Q(3)
11
Gate-drive supply for the buck-boost power stages. Apply a 4.7-µF (typical) decoupling capacitor
at this pin to the power ground. The VREG pin cannot drive external loads in the application.
VREG
GND
12
13
O
A
G
Analog ground
—
For the TPS55160-Q1 and TPS55162-Q1 devices, this pin is used to adjust the VOUT
configuration. Connect this pin to a resistive feedback network with less than 1-MΩtotal
resistance between the VOUT pin, FB pin, and GND pin (analog ground).
For the TPS55165-Q1 device, this pin is used to select the output voltage. The output voltage is
set to 5 V when this pin is connected to the GND pin. The output voltage is 12 V when this pin is
connected to the VREG pin.
VOS_FB
PG
14
I
A
Output power good pin. This pin is an open-drain pin. The status of the power-good output is good
when this pin is high (1) and has a failure when this pin is low (0)
15
16
O
I
D
A
VOUT_SEN
SE
Sense pin for the buck-boost converter output voltage. This pin must be connected to the VOUT
pin.
VOUT
GND
17
18
O
A
Buck-boost converter output voltage
Analog ground
G
—
Bootstrap node for the boost power-stage. Connect a typical 100-nF capacitor between this pin
and the L2 pin.
BST2
19
20
I
I
A
A
Boost power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the
L1 and L2 pins.
L2
The thermal pad must be soldered to the power ground to achieve the appropriate power
dissipation through the analog ground plane.
PowerPAD
—
—
(1) I = Input Pin, O = Output Pin
(2) A = Analog Pin, D = Digital Pin, G = Ground Pin, P = Power Pin
(3) The VREG_Q pin must be connected to the VREG pin at all times while the device is in operation to prevent possible electrostatic
overstress (EOS) damage to the device.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
POS
MIN
–0.3
–0.3
-0.3
MAX
40
UNIT
V
M1.1
M1.2
M1.3
M1.4
M1.5
M1.6
M1.7
M1.8
M1.9
Protected battery voltage
Feedback voltage
VINP, VINL
VOS_FB
5.5
40
V
Low-power mode input
Low-voltage inputs
PS
V
IGN_PWRL, SS_EN, PG_DLY
5.5
40
V
–0.3
–7
Ignition enable input
IGN
V
Buck-boost output voltage
Gate-driver supply
VOUT, VOUT_SENSE
20
V
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
VREG, VREG_Q
5.5
40
V
Buck switching node voltage
Boost switching node voltage
L1
V
L2
20
V
M1.10 Boot-strap overdrive voltage
M1.11 Power-good output voltage
M1.12 Ground
BST1-L1, BST2-L2
PG
5.5
15
V
V
PGND, GND
0.3
150
175
V
–0.3
–40
–65
M2
M3
Junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
M4
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
M5.1
M5.2
V(ESD)
All pins
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 10, 11, and 20)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
POS
R1.1a
R1.1b
MIN
2
MAX UNIT
TPS55165-Q1 with VOS_FB pin connected to
GND
36
36
V
V
Supply voltage at VINP and VINL pins (after wake-
up)
TPS55165-Q1 with VOS_FB pin connected to
VREG
4
R1.1c
R1.2a
R1.2b
R1.3
TPS55160-Q1 and TPS55162-Q1
3.6
36
12
5
V
V
V
V
V
V
V
Output voltage at VOUT and VOUT_SENSE pins
Output voltage at PG pin
0
0
0
Input voltage on IGN pin
36
5
R1.4
Input voltage on logic pins IGN_PWRL, PS and SS_EN
0
R1.5a
R1.5b
R2.1
TPS55165-Q1
TPS55160/2-Q1
0
5
Input voltage on VOS_FB pin
0
0.8
125
150
Operating free air temperature, TA
–40
–40
℃
℃
R2.2
Operating virtual junction temperature, TJ
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7.4 Thermal Information
TPS5516x-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
20 PINS
35.4
19.8
16.8
0.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
16.5
0.9
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics —External Components
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AN.1 COUT
Value of output ceramic capacitor Connect between VOUT and PGND
18
22
47
µF
Value of ESR of output capacitor,
COUT
AN.1a ESR COUT
AN.2 CBST
0
100
mΩ
Value of bootstrap ceramic
capacitor
ESR < 10 mΩ. Connect between BST1 and
L1 with respect to BST2 and L2
100
nF
Value of ESR of bootstrap ceramic
capacitor, CBST
AN.2a ESR CBST
0
10
mΩ
AN3
L
Value of inductor
3.3
0
4.7
10
6.2
40
µH
Saturation current > 2.5 A, ESR < 30 mΩ
AN.3a DCR L
AN.4 CIN
Value of DCR of inductor
mΩ
Value of supply input ceramic
capacitor
40-V compliant. Connect between VIN and
PGND
8.2
0
µF
mΩ
µF
Value of ESR of input capacitor,
CIN
AN.4a ESR CIN
AN.5 CVREG
100
5.6
10
Decoupling capacitor on VREG
pin to ground
Connect between VREG and PGND
3.9
0
4.7
Value of ESR of input capacitor,
CVREG
AN.5a ESR CVREG
mΩ
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.6 Electrical Characteristics —Supply Voltage (VINP, VINL pins)
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
TPS55165-Q1 with
1.1a
VOS_FB pin connected to
GND
2
14
36
V
Operating supply input Applied at VINP and VINL
1.1b
VIN
TPS55165-Q1 with
VOS_FB pin connected to
VREG
voltage
pins, after device startup
4
3.6
5.3
14
14
36
1.1c
1.2
TPS55160/2-Q1
36
V
V
Applied at VINP and VINL pins; TJ = 25°C. This minimum
voltage is required until VOUT > PGTH_UV
IVOUT < 400 mA, CVOUT = 22 µF
Minimum input voltage
for startup
VIN_startup
;
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Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
µA
VIN Shutdown supply
current
1.3
ISD
VIN = 12 V, VIGN= 0 V, VPS= 0 V, VIGN_PWRL = 0 V, TJ = 25°C
3
TPS55165-Q1:
VIN Quiescent supply
current
VIN = VIGN = 12 V, VOUT = 5 V, IOUT = 0 mA, TJ = 25°C
Device in low-power mode, Non-switching
VOS_FB pin connected to GND
1.4
IQ
0
15 µA
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.7 Electrical Characteristics —Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT
Pin)
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
TPS55160/2-Q1:
Measured at VOS_FB pin
Feedback voltage in normal mode
for adjustable VOUT setting(2)
Resistive divider with total resistance < 1
MΩconnected between VOUT, VOS_FB,
and GND pins
2.1a
VFB_NM_adj
0.784
0.8 0.816
V
TPS55165-Q1:
Feedback voltage in normal mode Measured at VOUT_SENSE pin
2.1b
2.1c
VFB_NM_5V
4.9
5
5.1
V
V
for VOUT in fixed 5-V setting(2)
VOS_FB pin connected to GND; VOUT pin
connected to VOUT_SENSE
TPS55165-Q1:
Feedback voltage in normal mode Measured at VOUT_SENSE pin
VFB_NM_12V
11.76
0.776
12 12.24
0.8 0.824
for VOUT in fixed 12-V setting(2)
VOS_FB pin connected to VREG; VOUT
pin connected to VOUT_SENSE
TPS55160/2-Q1:
Measured at VOS_FB pin
Resistive divider with total resistance < 1
MΩconnected between VOUT, VOS_FB,
and GND pins
Feedback voltage in low-power
2.2a
VFB_PS_adj
V
mode for adjustable VOUT setting(3)
TPS55165-Q1:
Feedback voltage in low-power
mode for VOUT in 5-V setting(3)
Measured at VOUT_SENSE pin
VOS_FB pin connected to GND; VOUT pin
connected to VOUT_SENSE
2.2b
2.2c
VFB_PS_5V
4.85
5
5.15
V
V
TPS55165-Q1:
Feedback voltage in low-power
mode for VOUT in 12-V setting(3)
Measured at VOUT_SENSE pin
VOS_FB pin connected to VREG; VOUT
pin connected to VOUT_SENSE
VFB_PS_12V
11.64
12 12.36
TPS55160/2-Q1:
Measured at VOUT_SENSE pin
2.3
2.6
VOUT_OL
Adjustable output voltage range
5.7
9
V
Device in OFF state, INIT state, or
PRE_RAMP state; VIGN = 0 V, VPS = 0 V,
VIGN_PWRL = 0 V
Pulldown discharge resistance at
VOUT
RpdVOUT
250
365
850
Ω
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
(2) VPS= 0 V; Average DC value excluding ripple and load transients for VIN and load current ranges as specified in IVOUT. Inclusive DC
line and load regulation, temperature drift, and long term drift.
(3) VPS= 5 V; Average DC value excluding ripple and load transients for VIN and load current ranges as specified in IVOUT. Inclusive DC
line and load regulation, temperature drift, and long term drift.
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7.8 Electrical Characteristics —Buck-Boost
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
3.1a
1
A
6 V ≤VIN; DCR ≤40 mΩ
3.8 V ≤VIN ≤6 V; DCR ≤40 mΩ
TPS55165-Q1 with
3.1b
800
Max output current in
normal operation for
VOUT in 5-V setting
IOUT_5V
VOS_FB pin
2.3 V ≤VIN < 3.8 V; DCR ≤40
mΩ
3.1c
400
mA
connected to GND
3.1d
3.1e
200
800
2 V ≤VIN < 2.3 V; DCR ≤40 mΩ
14 V ≤VIN; DCR ≤40 mΩ
9.2 V≤VIN ≤14 V; DCR ≤40
mΩ
TPS55165-Q1 with
VOS_FB pin
connected to
VREG
3.1f
600
Max output current in
normal operation for
VOUT in 12-V setting
IOUT_12V
5.6 V≤VIN < 9.2 V; DCR ≤40
mΩ
3.1g
3.1h
3.2a
300
150
800
mA
4 V ≤VIN < 5.6 V; DCR ≤40 mΩ
(VOUT + 2V) ≤VIN; DCR ≤40
mΩ
Max output current in
normal operation for
adjustable
0.76 * VOUT ≤VIN ≤(VOUT + 2V);
DCR ≤40 mΩ
3.2b
3.2c
3.2d
3.2e
3.2f
600
300
150
800
600
300
50
mA
mA
mA
TPS55160-Q1 and
TPS55162-Q1,
8V < VOUT ≤9V
IOUT_adj_VoutH
0.46 * VOUT ≤VIN < 0.76 * VOUT
DCR ≤40 mΩ
;
configuration, 8V <
V
OUT ≤9V
3.6 V ≤VIN < 0.46 * VOUT; DCR ≤
40 mΩ
(VOUT + 1V) ≤VIN; DCR ≤40
mΩ
Max output current in
normal operation for
adjustable
TPS55160-Q1 and
TPS55162-Q1,
0.76 * VOUT ≤VIN < (VOUT + 1V);
DCR ≤40 mΩ
IOUT_adj_VoutL
5.7V ≤VOUT
≤
configuration, 5.7V ≤
mA
8V
V
OUT ≤8V
3.6 V ≤VIN < 0.76 * VOUT; DCR ≤
40 mΩ
3.2g
3.11
Max output current in
low-power mode
IOUT_PS
On-resistance buck-
3.3
3.4
Rdson_ BUCK_HS stage high-side (HS)
FET
150
150
300
300
mΩ
mΩ
On-resistance buck-
Rdson_ BUCK_LS stage low-side (LS)
FET
Rdson_
On-resistance boost-
stage HS FET
3.5
3.6
150
150
300
300
mΩ
mΩ
BOOST_HS
Rdson_
On-resistance boost-
stage LS FET
BOOST_LS
Peak current limit for
3.7
3.9
ISW_limit
HS buck, LS buck, and Device in normal operating mode
LS boost
2
3.5
2
4.5
2.8
A
A
Average coil current
ICoilAvglimit
Device in normal operating mode; L = 4.7 µH
limit
Transient load step
3.20a VTLDSR_5V_100 response for VOUT in
5-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12 V, IOUT = 0.1 A
to 0.5 A, TR = TF = 1 µs, COUT = 47 µF
5
Transient load step
3.20b VTLDSR_5V_500 response for VOUT in
5-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12 V, IOUT = 0.5 A
to 1 A, TR = TF = 1 µs, COUT = 47 µF
5
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Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12V, IOUT = 1 A,
SS_EN = low
Output ripple for VOUT
in 5-V setting
3.21a VRIPPLE_5V
5.5
mVpp
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to VREG; VIN = 14V, IOUT = 0.8
A, SS_EN = low
Output ripple for VOUT
in 12-V setting
3.21b VRIPPLE_12V
5
mVpp
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.9 Electrical Characteristics —Undervoltage and Overvoltage Lockout
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
TPS55165-Q1 with
VOS_FB pin connected to
GND
VIN voltage decreasing;
Device turned-off when VIN
< UVLO
Device is in normal
operating mode
4.1a
1.8
2
4
V
V
VIN Undervoltage (UV)
lockout threshold
UVLO
TPS55165-Q1 with
VOS_FB pin connected to
VREG
4.1b
4.1c
3.6
1.8
36
VIN voltage decreasing;
Device turned-off when VIN TPS55162-Q1
< UVLO
Device is in normal
operating mode
TPS55160-Q1 and
VIN Undervoltage (UV)
lockout threshold
UVLO
OVLO
2
V
V
VIN voltage increasing; Device stops switching when VIN
> OVLO, and recovers when VIN < OVLO and IGN = 1
Device is in normal operating mode
VIN Overvoltage (OV)
lockout threshold
4.2
4.9
40
VOUT_PROT_OV VOUT OV protection
Device is in normal operating mode
110%
125%
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.10 Electrical Characteristics —IGN Wakeup
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
5.1a
IGNWAKE
IGNPD
IGN wake-up threshold
VIGN voltage increasing to wake-up device
2.5
3.1
3.7
2.7
V
V
VIGN voltage decreasing to power-down
device
5.1b
5.2
IGN power-down threshold
IGN wake-up hysteresis
1.5
0.76
11
2.1
1
IGNHYST
I_IGN36V
1.35
30
V
IGN pin forward input current
at 36 V
5.3a
VIGN = 36 V
17
µA
IGN pin forward input current
at 12 V
5.3b
5.5
I_IGN12V
I_IGNrev
VIGN = 12 V
2.3
3.7
7.1
µA
µA
IGN pin reverse current
370
650
VIGN = –7 V
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.11 Electrical Characteristics —Logic Pins PS, IGN_PWRL, SS_EN
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Logic input low-to-high
6.1
VLOGIC_IN_HIGH
threshold for pins
Device in power-up condition
2
V
IGN_PWRL PS, and SS_EN
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Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Logic Input high-to-low
6.2
VLOGIC_IN_LOW
threshold for pins
IGN_PWRL, PS, and SS_EN
Device in power-up condition
0.74
0.39
V
V
Logic input hysteresis for
pins IGN_PWRL, PS, and
SS_EN
6.3
VLOGIC_IN_HYST
Device in power-up condition
0.15
Pulldown resistance on PS
pin to GND
6.4
6.5
6.6
RLOGIC_IN_PD
Ipull-up_SS_EN
35
85
1
70
111
266
8
kΩ
µA
µA
Pullup current on SS_EN pin
Pullup current on
IGN_PWRL pin
Ipull-up_IGN_PWRL
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.12 Electrical Characteristics –Overtemperature Protection
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
7.1
7.2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
210
Overtemperature shutdown
protection threshold
TPROT
THYS
175
℃
Overtemperature shutdown
hysteresis
30
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.13 Electrical Characteristics –Power Good
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Deviation from nominal VOUT to assert PG
low, in normal mode
–10%
–5%
Deviation from nominal VOUT to assert PG
low, during low power mode to normal mode
transition
8.1
PGTH_UV
PG threshold undervoltage
-12%
Deviation from nominal VOUT to assert PG
low, in low power mode
-20%
-5%
8.2
VPG_LOW
PG output-low voltage
0.4
V
IPGL ≤1mA
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.14 Switching Characteristics —Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT
Pin)
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
L = 4.7 µH, COUT = 22 µF; VOUT rising from 10%
to 90% of final value
2.5
tstart_VOUT
VOUT startup time
1.5
ms
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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7.15 Switching Characteristics —Buck-Boost
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
70 ns
Time until peak current limit is
active
3.8
tblank_Iswlim
ƒSW
VIN = 14 V
VIN_max = 27 V
40
Switching frequency without
Spread-Spectrum
3.11
3.12
3.14
3.15
3.16
1860 2000
1800 2100
55
2140 kHz
2400 kHz
Switching frequency with Spread- VIN_max = 27 V; SS_EN pin not connected to
Spectrum Enabled
ƒSW_SS
GND; Device in buck operation
Minimum on time in buck
operation
ton_Min_Buck
ton_Max_Boost
Device in normal operation mode
65
ns
ns
µs
Maximum on time in boost
operation
Device in normal operation mode
350
400
4
450
ton_Max_Bst_LP Maximum boost on time in power
save mode
M
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.16 Switching Characteristics —Undervoltage and Overvoltage Lockout
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
4.3
4.8
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
tdegl_VINUVOV
VIN UV and OV deglitch time
40
50
10
60
µs
µs
tdegl_VREGUVOV VREG UV and OV deglitch time
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.17 Switching Characteristics —IGN Wakeup
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
5.6
IGN_deg
IGN deglitch filter time
7.5
22
25
ms
ms
Time from IGN high till VOUT
crossing 95% of the end-value
5.7
IGNstartup_time
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.18 Switching Characteristics —Logic Pins PS, IGN_PWRL, SS_EN
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Delay time betweein the toggling of the
IGN_PWRL pin and the state change of the
signal inside the device
Input Delay time for IGN_PWRL
pin
6.7
tDelay_IGN_PWRL
tDelay_PS_L2H
tDelay_PS_H2L
213
256
272
136
510
µs
µs
µs
Input Delay time for PS pin
pulling high
Delay time between pullping the PS high
and the device enters low-power mode
6.8a
6.8b
59
Delay time between releasing the PS pin
and the device enters normal mode from
low-power mode
Input Delay time for PS pin going
low
262
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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7.19 Switching Characteristics –Power Good
Over operating free air temperature range –40°C ≤TA ≤125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
50
40
30
4
MAX UNIT
8.3
PGDeglitch
PG deglitch filter time
45
55
µs
8.4a
8.4b
8.4c
8.4d
PG_DLY Shorted to VREG
ms
100 kΩbetween PG_DLY and GND
10 kΩbetween PG_DLY and GND
PG_DLY grounded
PG extension time (rising edge
only)
PGexttime
ms
ms
0.7
(1) The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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7.20 Typical Characteristics
3.5
2.2
2.15
2.1
3
2.5
2
2.05
2
1.5
1
1.95
1.9
0.5
0
1.85
1.8
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Dt0p0s52
Temperature (èC)
D001
VIN = 12 V
图7-1. Shutdown IQ vs Temperature
图7-2. Switching Frequency vs Temperature
5.08
5.08
5.06
5.04
5.02
5
5.06
5.04
5.02
5
VIN = 3.8 V
VIN = 6 V
VIN = 12 V
VIN = 36 V
IOUT = 0 A
IOUT = 0.3 A
IOUT = 0.5 A
IOUT = 1 A
4.98
4.96
4.98
4.96
0
0.2
0.4 0.6
Output Current (A)
0.8
1
0
5
10
15
Input Voltage (V)
20
25
30
35
40
D003
D004
图7-3. 5-V Output Regulation vs Load Current
图7-4. 5-V Output Regulation vs Input Voltage
12.5
12.4
12.3
12.2
12.1
12
12.5
12.4
12.3
12.2
12.1
12
11.9
11.8
11.7
11.6
11.5
11.9
11.8
11.7
11.6
11.5
VIN = 4 V
IOUT = 0 A
VIN = 5.6 V
VIN = 14 V
VIN = 36 V
IOUT = 0.3 A
IOUT = 0.5 A
IOUT = 0.8 A
0
0.2
0.4
Output Current (A)
0.6
0.8
0
5
10
15
20
Input Voltage (V)
25
30
35
40
D005
D006
图7-5. 12-V Output Regulation vs Load Current
图7-6. 12-V Output Regulation vs Input Voltage
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7.20 Typical Characteristics (continued)
L1
L1
VOUT
VOUT
PG_DLY
PG_DLY
VIN = 12 V
VOUT = 5 V
VIN = 12 V
VOUT = 5 V
图7-7. Power-Good Delay When PGDLY Is Grounded
图7-8. Power-Good Delay When PGDLY Connects to 100-kΩ
Resistor
L1
VOUT
L1
VOUT
PG_DLY
IGN
VIN = 12 V
VOUT = 5 V
VIN = 14 V
VOUT = 5 V
IOUT = 0 A
图7-9. Power-Good Delay When PGDLY Connects to VREG
图7-10. Ignition Shutdown Sequence
VOUT
VIN
VOUT
PS
L1
L1
L2
L2
VIN = 12 V
VOUT = 5 V
IOUT = 50 mA
VOUT = 5 V
IOUT = 0.5 A
4 V ≤VIN ≤12 V
图7-11. Low-Power Mode Enabling
图7-12. Step-Up to Step-Down Mode Transition
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7.20 Typical Characteristics (continued)
1.2
1
VIN
VOUT
L1
0.8
0.6
0.4
0.2
0
L2
IOUT = 5 V
IOUT = 12 V
0
5
10
15
20
25
Input Voltage (V)
30
35
40
D007
A.
VOUT = 5 V
IOUT = 0.5 A
4 V ≤VIN ≤8 V
图7-14. Load Current Derating vs Input Voltage
图7-13. Step-Down to Step-Up Mode Transition
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8 Detailed Description
8.1 Overview
The control circuit of the TPS5516x-Q1 buck-boost converter is based on an average current-mode topology.
The control circuit also uses input and output voltage feedforward. Changes of input and output voltage are
monitored and the duty cycle in the modulator is immediately adapted to achieve a fast response to those
changes. The voltage error amplifier gets its feedback input from the VOS_FB pin. The feedback voltage is
compared with the internal reference voltage to generate a stable and accurate output voltage.
The buck-boost converter uses four internal N-channel MOSFETs to maintain synchronous power conversion at
all possible operating conditions. This feature enables the device to keep high efficiency over a wide input
voltage and output power range. To avoid ground shift problems caused by the high currents in the switches,
separate ground pins (GND and PGND) are used. The reference for all control functions are the GND pins. The
power switches are connected to the PGND pins. Both grounds must be connected on the PCB at only one point
which is ideally close to the GND pin. Because of the 4-switch topology, the load is always disconnected from
the input during shutdown of the converter.
To drive the high-side switches of the buck and the boost power stages, the buck-boost converter requires
external boot-strapping ceramic capacitors with low ESR. These bootstrap capacitors are charged by the VREG
supply. The VREG supply requires a low-ESR ceramic capacitor for loop stabilization, and must not be loaded by
the external application. The VREG supply is also used to drive the low-side switches of the buck and boost
power stages. At device start-up, the VREG pin is supplied by the input voltage. When the buck-boost output
voltage is greater than its power-good threshold (the PG pin is high), the VREG pin is supplied by the output
voltage to reduce power dissipation.
The device can be enabled with the IGN pin, and, when enabled, the device has a power-latch function which
can be selected with the IGN_PWRL pin. This function allows an external MCU to keep TPS5516x-Q1 device on
even after the IGN pin goes low.
For the TPS55160-Q1 and TPS55165-Q1 devices, the operation mode of the buck-boost converter can be
selected through the PS pin. When the PS pin is low, the buck-boost operates in normal mode with a constant
fixed switching frequency. When the PS pin is high, the buck-boost operates in low-power mode with pulse-
frequency modulation.
The TPS55160-Q1 and TPS55165-Q1 devices also have a frequency spread-spectrum option that can be
enabled or disabled through the SS_EN pin.
The output voltage of the TPS55165-Q1 device is selected as a fixed 5 V or fixed 12 V through the VOS_FB pin.
The TPS55160-Q1 and TPS55162-Q1 devices have an adjustable output voltage from 5.7 V to 9 V through an
external feedback network.
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8.2 Functional Block Diagram
VIN
VINP
VINL
VOUT
BST2
VOUT
Current
Sense
BST1
VVREG
VVREG
L2
L1
Buck-Boost
Overlap Control
VVREG
VVREG
PGND
VINL
UVLO and
VOUT
OVLO
Device Type?
VREG
IGN
VOUT_SENSE
Power Up and
IGN_PWRL
Shutdown Logic
VOS_FB
Device Type?
Thermal
Shutdown
FBint
œ
Vref
PS
+
Low-Power
Mode select
Output
Voltage
Select
SS_EN
Spread-
GND
Spectrum Select
VOUT_SENSE
VINL
Power-Good
Comparator
Vref
Power
Select
Internal
Reference
FBint
PG
VREG
Gate-Driver
Supply
Delay
Filter
VREG_Q
TPS55160-Q1
TPS55162-Q1
TPS55165-Q1
GND
PG_DLY
GND
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8.3 Feature Description
8.3.1 Spread-Spectrum Feature
The TPS55160-Q1 and TPS55165-Q1 devices have a spread-spectrum feature to modulate the switching
frequency through a pseudo-random algorithm.
This spread-spectrum feature is enabled and disabled through the SS_EN pin. When the SS_EN pin is
unconnected, the spread-spectrum feature is enabled. The SS_EN pin is internally pulled up with a pullup
current between 100 µA and 200 µA. When the SS_EN pin is connected to ground, the spread-spectrum feature
is disabled.
This feature can only be enabled when the device is in normal mode with step-down operation. This feature
cannot be enabled in low-power mode.
8.3.2 Overcurrent Protection
The buck-boost regulator has two ways of protecting against overcurrent conditions. When the buck-boost is in
regulation (essentially the output voltage is at the target voltage), the average current limit provides the
protection against overcurrent conditions. When the average current limit is activated (essentially the maximum
inductor average current is reached), the output voltage gradually decreases, but the control loop tries to
maintain the target output voltage. So when the overcurrent condition clears before the buck-boost control circuit
gets too far out of regulation, the output voltage gradually reaches its target voltage level again.
The buck-boost regulator limits the peak-overcurrent in the power MOSFETs. When such a peak-overcurrent
event occurs, the device goes into the PRE_RAMP state and a 12-ms time-out is started. The device restarts
and goes from the PRE_RAMP state to the RAMP state after this 12-ms time-out expires and the IGN pin is
high.
When the device operates in low-power mode, both the average current limit and the peak-current limit
protection functions are disabled.
8.3.3 Overtemperature Protection
The internal power MOSFETs are protected against excess power dissipation with junction overtemperature
protection. In case of a detected overtemperature condition, the TPS55165-Q1 device goes to the PRE_RAMP
state (the buck-boost regulator is switched off and the VREG supply is enabled) and a 12-ms time-out is started
when the overtemperature condition is cleared. The device restarts in the PRE_RAMP state after this 12-ms
time-out expires, the overtemperature condition disappeared, and the IGN pin is high.
When the device operates in low-power mode, this overtemperature protection function is disabled.
8.3.4 Undervoltage Lockout and Minimum Start-Up Voltage
The TPS55165-Q1 device has an undervoltage lockout (UVLO) function. When the device operates in normal
mode (the PS pin is low), this UVLO function puts the device in the OFF state when the input voltage is less than
the UVLO threshold. The device restarts when the IGN pin is high and the input voltage is greater than or equal
to the minimum input voltage for start-up, which must be maintained until the output voltage is greater than the
PG undervoltage threshold.
When the device operates in low-power mode, this UVLO function is disabled.
8.3.5 Overvoltage Lockout
The TPS55165-Q1 device has an overvoltage lockout (OVLO) function. When the input voltage is greater than
the OVLO threshold while the device operates in normal mode (the PS pin is low), this OVLO function puts the
device in the PRE_RAMP state (the buck-boost regulator is switched off and the VREG supply is enabled), and
a 12-ms time-out starts. The device restarts in the PRE_RAMP state after this 12-ms time-out expires, the input
voltage is less than the OVLO threshold, and the IGN pin is high.
When the device operates in low-power mode, this OVLO function is disabled.
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8.3.6 VOUT Overvoltage Protection
When the device operates in normal mode (the PS pin is low) and the output voltage is greater than or equal to
the VOUT overvoltage protection, the device goes to the PRE_RAMP state (the buck-boost regulator is
switched-off and the VREG supply is enabled) and a 12-ms time-out starts when the output voltage is less than
the VOUT overvoltage protection. The device restarts in the PRE_RAMP state after this 12-ms time-out expires,
the output voltage is less than the VOUT overvoltage protection, and the IGN pin is high.
When the device operates in low-power mode, this VOUT overvoltage protection function is disabled.
8.3.7 Power-Good Pin
The power-good (PG) pin is a low-side FET open-drain output which is released as soon as the output voltage is
greater than the PG undervoltage threshold (essentially the output voltage is rising) and the extension time
(PGexttime) is expired. The intended usage of this pin is to release the reset of an external MCU. Therefore, the
logic-input signals (IGN_PWRL and PS) are considered to be valid only when the PG pin reaches the high level.
When the output voltage is less than the PG undervoltage threshold (essentially the output voltage is falling) for
a time longer than the PG deglitch filter time, the PG pin is pulled low. When the PG pin is low, the level of the
PS and IGN_PWRL pins is interpreted as low, regardless of the actual level. The device goes to the OFF state if
the IGN pin is low under this condition. For more information on the behavior of the PG pin for rising and falling
output voltage, see 图8-2 through 图8-6.
The PG pin is operational in low-power mode. The PG extension time can be configured by connecting the
PG_DLY pin to the VREG pin, the GND pin, or through an external resistor with a value from 10 kΩ to 100 kΩ
to the GND pin. The extension time is as follows for the listed configurations:
• When the PG_DLY pin is shorted to the VREG pin, the typical PG extension time is 40 ms.
• When the PG_DLY pin is connected to the GND pin, the typical PG extension time is 0.6 ms.
• When the external resistor between the PG_DLY and GND pins has a value of 10 kΩ, the typical PG
extension time is 3 ms.
• When the external resistor between pin the PG_DLY and GND pins has a value of 100 kΩ, the typical PG
extension time is 30 ms.
8.4 Device Functional Modes
8.4.1 State Diagram
图8-1 shows the state diagram.
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PRE_RAMP
• VREG enabled
• Buck-boost disabled
• Keeps count of RAMP to
PRE_RAMP
VOUT (normal mode) > VOUT_ABSMAX
RAMP
• VREG enabled
• VOS pin state sampled and
latched
• SS_EN pin state sampled
and latched
• Buck-Boost ramping up
INIT
NORMAL MODE
OFF
NPOR
• Loading EEPROM
• Buck-boost disabled
• VREG enabled
• VREG enabled
• Buck-boost enabled in
normal mode
Not Pre-Power-Good
Off Condition AND
Not Pre-Ramp
Condition AND
PG = High
Not Pre-Power-Good
Off condition AND
VREG > VREG_UV
AND
EEPROM Load
Complete
• Device disabled
Not Pre-Power-Good
off condition
IGN_CLR
• Clears IGN signal
LOW-POWER MODE
Pre-Power-Good Off Condition: IGN = Low OR VINL < VIN_startup OR VREG > VREG_OV
Normal Off Condition: (IGN = Low AND IGN_PWRL= Low) OR VINL < UVLO OR VREG > VREG_OV
Low-Power Off Condition: IGN = Low AND IGN_PWRL = Low AND PS = Low
• VREG enabled
• Buck-boost enabled in low-
power mode
Pre-Ramp Condition: VREG < VREG_UV OR Overtemperature Shutdown OR IOUT > ISW_limit OR VINL > OVLO OR VOUT (normal mode) > VOUT_PROT_OV
Valid IGN_PWRL: IGN_PWRL= High AND PG = High AND PG pin is not pulled down
Valid PS: PS = High AND PG = High AND PG pin is not pulled down
•
•
The 12-ms time-out from the PRE_RAMP state to the RAMP state starts only when all conditions for going to the RAMP state are
satisfied. As soon as one of these conditions is violated, the 12-ms time-out is reset.
The oscillator is turned off in low-power mode. The oscillator is turned back on upon detecting a negative edge on the PS pin, or a
negative edge on the PG pin which requires the device to go out of low-power mode and enter normal mode again.
图8-1. State Diagram
8.4.2 Modes of Operation
The operational mode of the buck-boost converter is selected through the PS pin. When the PS pin is low, the
buck-boost operates in normal mode with a constant fixed switching frequency. When the PS pin is high, the
buck-boost operates in low-power mode with pulse-frequency modulation.
8.4.2.1 Normal Mode
To regulate the output voltage at all possible input voltage conditions, the buck-boost converter automatically
switches from step-down operation to boost operation and back as required by the configuration. The regulator
always uses one active switch, one rectifying switch, one always-on switch, and one always-off switch.
Therefore, the regulator operates as a step-down converter (buck) when the input voltage is higher than the
output voltage, and as a boost converter when the input voltage is lower than the output voltage. In normal
mode, no mode of operation is available in which all four switches are permanently switching. Controlling the
switches in this way allows the converter to maintain high efficiency at the most important point of operation;
when the input voltage is close to the output voltage. The RMS current through the switches and the inductor is
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kept at a minimum to minimize switching and conduction losses. For the remaining two switches, one is kept
permanently on and the other is kept permanently off which causes no switching losses.
In normal mode, the converter operates in full continuous mode at a fixed switching frequency of 2 MHz (typical)
for the entire load-current range, even with no load at the output. No pulse-skipping should occur for supply
voltages from 2 V to 27 V.
8.4.2.2 Low-Power Mode
When the buck-boost converter is in low-power mode, the output voltage is monitored with a comparator with its
threshold at the regulation target voltage. When the buck-boost regulator goes to low-power mode, the converter
temporary stops operating and the output voltage drops. The slope of the output voltage depends on the load
and output capacitance. As the output voltage decreases to less than the regulation target voltage, the device
ramps up the output voltage again by giving one or several pulses until the output voltage exceeds the regulation
target voltage. In low-power mode, the buck-boost operates in 4-switch mode, which allows regulation at the
target output voltage regardless of whether the input voltage is greater than or less than the target output voltage
value.
After the device enters low-power mode, the internal oscillator is turned off. As a result of the oscillator being
turned off, all signal deglitching functions are disabled while the device is in low-power mode. These functions
include the VIN and VREG OV and UV signal deglitch functions, and the IGN input signal deglitch function.
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8.4.3 Power-Up and Power-Down Sequences
图8-2 shows the power-up and power-down sequence without the usage of the IGN_PWRL pin.
IGN
Deglitch time
7.5 ms (min) to 22 ms (max)
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN_PWRL
PS
tDelay_PS_L2H
tDelay_PS_H2L
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5 V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
2 ms (typ)
VOUTTstart
2 ms (typ)
PGdeglitch
PG
PGdeglitch
Load
EEPROM
Operation Mode
NORMAL
MODE
LOW-POWER
MODE
OFF
INIT
NORMAL MODE
OFF
RAMP
A. The actual ramp-down time of the output voltage depends on external load conditions.
图8-2. Power-Up and Power-Down Sequence With Normal Mode and Low-Power Mode, Without Usage of
IGN_PWRL
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图8-3 shows the power-up and power-down sequence with usage of the IGN_PWRL pin.
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN
tDelay_IGN_PWRL
tDelay_IGN_PWRL
IGN_PWRL
tDelay_PS_L2H
tDelay_PS_H2L
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5 V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
2 ms (typ)
VOUTTstart
2 ms (typ)
PG
PGdeglitch
PGdeglitch
Load
EEPROM
Operation Mode
LOW-POWER
MODE
OFF
INIT
RAMP
NORMAL MODE
NORMAL MODE
OFF
A. The actual ramp-down time of the output voltage depends on external load conditions.
图8-3. Power-Up and Power-Down Sequence With Normal Mode and Low-Power Mode, With Usage of
IGN_PWRL
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图8-4 shows a power-up and power-down sequence in low-Power mode with the IGN pin low. 图8-4 shows that
after the device is powered on in the OFF state, the device is in low-power mode when the PS pin is high
regardless of what was applied on the IGN and IGN_PWRL input pins.
Deglitch time
IGN
7.5 ms (min) to 22 ms (max)
tDelay_IGN_PWRL
tDelay_IGN_PWRL
IGN_PWRL
tDelay_PS_H2L
tDelay_PS_L2H
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5 V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
2 ms (typ)
VOUTTstart
2 ms (typ)
PG
PGdeglitch
PGdeglitch
Load
EEPROM
Operation Mode
LOW-POWER
MODE
OFF
OFF
INIT
RAMP
NORMAL MODE
A. The actual ramp-down time of the output voltage depends on external load conditions.
图8-4. Power-Up and Power-Down Sequence With Low-Power Mode When IGN and IGN_PWRL are Low
(Essentially When the ECU is in Sleep or Standby Mode)
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图 8-5 shows that when the device starts in the OFF state, the buck-boost converter always enters normal mode
first, even when the PS pin was previously set high. The device can only enter low-power mode when the PG
output pin is set high. 图8-5 also shows that the device does not start-up as long as the IGN pin is low.
IGN
Deglitch time
7.5 ms (min) to 22 ms (max)
tDelay_IGN_PWRL
tDelay_IGN_PWRL
IGN_PWRL
tDelay_PS_L2H
tDelay_PS_H2L
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5 V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
VOUTTstart 2 ms (typ)
2 ms (typ)
PG
PGdeglitch
PGdeglitch
Operation Mode
Load
EEPROM
NORMAL
MODE
OFF
INIT
RAMP
LOW-POWER MODE
OFF
A. The actual ramp-down time of the output voltage depends on external load conditions.
The buck-boost converter always enters normal mode first after ramp up before it can enter low-power mode.
图8-5. Power-Up Behavior With PS Pin Previously Set High
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图8-6 shows that the device only can start-up in the OFF state when the IGN pin is high. Setting the IGN_PWRL
pin before the IGN pin is high does not start-up the device. 图 8-6 also shows that the IGN_PWRL signal is only
valid after the PG pin is high and the PGDeglitch time has elapsed.
Deglitch time
IGN
7.5 ms (min) to 22 ms (max)
tDelay_IGN_PWRL
tDelay_IGN_PWRL
IGN_PWRL
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5 V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
2 ms (typ)
VOUTTstart
2 ms (typ)
PG
PGdeglitch
PGdeglitch
Operation Mode
Load
EEPROM
NORMAL MODE
OFF
INIT
RAMP
OFF
A. The actual ramp-down time of the output voltage depends on external load conditions.
The device does not start-up until the IGN pin is high. The IGN power-latch is only be set after the PG pin is high.
图8-6. Power-Up Behavior With IGN_PWRL Set High Prior to High IGN
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8.4.4 Soft-Start Feature
On power up, the device has a soft-start feature which ramps the output of the regulator at a steady slew rate.
The soft-start ramp time is 0.5 ms by default. When the device pulls the PG pin low because of a VOUT
undervoltage condition while the device is in normal mode, the device stays in normal mode and tries to get to
the VOUT level again without soft-start slew-ramp control.
8.4.5 Pulldown Resistor on VOUT
When the buck-boost regulator is disabled (in the OFF state, INIT state, and PRE_RAMP state), an internal
active pulldown circuit (specified as RpdVOUT in 节7.7) pulls down the VOUT pin.
8.4.6 Output Voltage Selection
The configuration of the output voltage is selectable through the VOS_FB pin.
The fixed output voltage of the TPS55165-Q1 device is 5 V when the VOS_FB pin is connected to ground and is
12 V when the VOS_FB pin is connected to the VREG pin. For the TPS55165-Q1 device in the 5-V configuration
(VOS_FB pin connected to ground), the UVLO threshold is set to less than 2 V. When the TPS55165-Q1 device
is in the 12-V configuration (VOS_FB pin connected to the VREG pin), the UVLO threshold is set to less than 3.6
V. For the TPS55162-Q1 device, the UVLO threshold is also set to less than 3.6 V.
For the adjustable output voltage of the TPS55160-Q1 and TPS55162-Q1 devices, connect the VOS_FB pin to
the external feedback network. The total resistance of this external feedback network must be less than 1 MΩ
(essentially, this value must be similar to or less than the implemented total resistance of the implemented
internal feedback network for the 12 V setting).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The TPS5516x-Q1 family of devices is a high-voltage synchronous buck-boost DC-DC converter with all four
power MOSFETs integrated. Each device in the device family can produce a well-regulated output voltage from a
widely-varying input voltage source such as an automotive car battery. If the input voltage is higher than the
output voltage, the TPS5516x-Q1 device operates in step-down mode. If the input voltage is lower than the
output, the device operates in step-up mode. If the input voltage is equal or close to the output voltage, the
device operates between the step-down and step-up mode. The buck-boost overlap control ensures automatic
and smooth transition between step-down and step-up (this is okay. Step-up and step-down modes were
mentioned in the first page of the spec) modes with optimal efficiency. The output voltage of the TPS55165-Q1
device can be set to a fixed level of 5 V or 12 V. The output voltage of the TPS55160-Q1 and TPS55162-Q1
devices is programmable from 5.7 V to 9 V.
9.1.1 Application Circuits for Output Voltage Configurations
图9-1 and 图9-2 show the application diagrams for the adjustable output configuration.
4.7 µH
0.1 µF
0.1 µF
2V VIN 36V
10 µF
BST1 L1
L2 BST2
5.7V VOUT 9V
VINP
VOUT
VOUT_SENSE
22 µF
VINL
100 k
R1
R2
100 nF
Power
Latch
PG
IGN_PWRL
VOS_FB
ON
IGN
PS
ON
OFF
OFF
Low-
SS_EN
Power
Mode
VREG
PGND
GND
VREG_Q
PG_DLY
4.7 µF
TPS55160-Q1
RDLY
图9-1. TPS55160-Q1 Application Diagram for Adjustable Output Voltage
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4.7 µH
0.1 µF
0.1 µF
BST1 L1
L2 BST2
VOUT
2V VIN 36V
10 µF
5.7V VOUT 9V
VINP
VOUT_SENSE
22 µF
VINL
100 k
R1
R2
100 nF
Power
Latch
PG
IGN_PWRL
IGN
VOS_FB
ON
OFF
VREG
PGND
GND
VREG_Q
PG_DLY
4.7 µF
TPS55162-Q1
RDLY
图9-2. TPS55162-Q1 Application Diagram for Adjustable Output Voltage
Use 方程式1 to calculate the output voltage.
R1+ R2
R2
VOUT
=
ì VFB
(1)
where
• VFB is 0.8 V (see 节7.7).
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图9-3 shows the TPS55165-Q1 device in the 5-V configuration.
4.7 µH
0.1 µF
0.1 µF
V
OUT = 5 V
1 A at VIN ꢀ 5.3 V
0.8 A at VIN ꢀ 3.8 V
0.4 A at VIN ꢀ 2.3 V
BST1 L1
L2 BST2
2V VIN 36V
10 µF
VINP
VOUT
22 µF
VINL
100 k
PG
VOUT_SENSE
Power
Latch
IGN_PWRL
100 nF
ON
ON
SS_EN
IGN
PS
OFF
OFF
VOS_FB
Low-
Power
Mode
VREG
PGND
GND
VREG_Q
PG_DLY
4.7 µF
TPS55165-Q1
RDLY
图9-3. TPS55165-Q1 Application Diagram for 5-V Voltage
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图9-4 shows the TPS55165-Q1 device in the 12-V configuration.
4.7 µH
0.1 µF
0.1 µF
5-V Supply
100 k
BST1 L1
L2 BST2
2V VIN 36V
10 µF
VINP
PG
VINL
VOUT = 12 V
22 µF
VOUT
VOUT_SENSE
SS_EN
Power
Latch
ON
IGN_PWRL
100 nF
ON
IGN
PS
OFF
OFF
Low-
Power
Mode
VOS_FB
VREG
PGND
GND
VREG_Q
PG_DLY
4.7 µF
TPS55165-Q1
RDLY
图9-4. TPS55165-Q1 Application Diagram for 12-V Voltage
CAUTION
For TPS55165-Q1 in 12-V configuration (VOS_FB is shorted to VREG), the PG pin must be tied to
an external 5-V supply through a pullup resistor. Tying the PG pin to a supply greater than 5.5 V
could damage the device in the unlikely event of a shortage between the PG pin and the adjacent
VOS_FB pin, which is tied to the VREG pin in the 12-V output configuration. The absolute-maximum
voltage rating of the VREG pin is 5.5 V.
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9.2 Typical Application
The TPS5516x-Q1 family of devices requires a minimum number of external components to implement a buck-
boost converter. 图9-5 shows the typical schematic for the TPS55165-Q1 device in the 5-V configuration.
L
2V≤VIN≤36V
CBST2
CBST1
VOUT = 5 V
0.1 µF
0.1 µF
1 A at VIN ³ 5.3 V
0.8 A at VIN ³ 3.8 V
0.4 A at VIN ³ 2.3 V
CIN
CINP
BST1 L1
L2 BST2
20 µF
0.1 µF
VINP
VOUT
COUT
22 µF
RPG
100 kΩ
VINL
CINL
0.47 µF
PG
VOUT_SENSE
CVOSN
0.1 µF
Power
Latch
IGN_PWRL
ON
ON
SS_EN
IGN
PS
OFF
OFF
VOS_FB
Low
Power
Mode
VREG
VREG_Q
PGND
GND
PG_DLY
CVREG
4.7 µF
TPS55165-Q1
RDLY
图9-5. TPS55165-Q1 Buck-Boost Converter for Fixed 5-V Output
9.2.1 Design Requirements
表9-1 lists the design requirements for 图9-5.
表9-1. Design Requirements
PARAMETER
VALUE
The least input voltage after start-up.
VIN_MIN
2 V
The IOUT_MAX load current deratings listed in this table apply for VIN < 5.3 V.
The minimum input voltage required for start-up
The greatest input voltage after start-up
VIN_startup
VIN_MAX
VOUT
> 5.3 V
36 V
5 V
The output voltage
1 A
The maximum output current at VIN ≥5.3 V
The maximum output current at 3.8 V ≤VIN < 5.3 V
The maximum output current at 2.3 V ≤VIN < 3.8 V
IOUT_MAX
0.8 A
0.4 A
9.2.2 Detailed Design Procedure
9.2.2.1 Power-Circuit Selections: CIN, L, COUT
The TPS5516x-Q1 family of devices integrates not only the power switches but also the loop compensation
network as well as many other control circuits which reduces the number of required external components. For
the internal loop compensation to be effective, the selection of the external power circuits (power inductor and
capacitor) must be confined. TI strongly recommends users selecting the component values as follows: 3.3-µH
to 6.2-µH power inductor, 18-µF to 47-µF output capacitor, and 8.2-µF or greater input capacitor. Because the
TPS5516x-Q1 device switches at about 2 MHz, a shielded inductor and X5R-type or X7R-type ceramic
capacitors should be used for the power circuit.
Considering the component tolerance, the following power component values were selected for this design
example:
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• CIN = 20 µF
• COUT = 22 µF
• L = 4.7 µH
For the input capacitor (CIN), the voltage rating should be greater than the maximum input voltage (VIN_MAX).
Therefore, two, 10-µF X7R capacitors rated for 50 V were selected for this design example. Adding a small,
high-frequency decoupling ceramic capacitor (CVINP with a value of 100 nF typical) in parallel with the input
capacitor is recommended to better filter out the switching noises at the VINP pin. Adding another decoupling
ceramic capacitor (CVINL with a value of 470 nF typical) is also recommended for the VINL pin.
The output capacitor (COUT), receives a voltage of 5 V. Considering some voltage-rating margin, two 10-µF X7R
capacitors rater for 10 V or greater and one, 2.2-µF X7R-type capacitor rated for 10 V or greater in parallel were
selected for the output capacitor. Adding a small, high-frequency decoupling ceramic capacitor (CVOSN with a
value of 100 nF typical) in parallel with the output capacitor is recommended to better filter out the switching
noises at the VOUT_SENSE pin.
The power inductor (L) should be a shielded type, and it should not saturate during operation. The inductor
should also be able to support the power dissipation under the maximum load. Use the calculations in the
following sections to find the required current capabilities for the inductor.
9.2.2.1.1 Inductor Current in Step-Down Mode
Use 方程式2 to calculate inductor peak-ripple current in the step-down, or buck, mode (Ipk_buck).
VOUT 1-Dbuck
1
2
Ipk _buck
=
ì
ì
L
fS
(2)
where
• VOUT is the output voltage.
• L is the value of the inductor.
• Dbuck is the duty cycle (refer to 方程式3).
• fS is the switching frequency.
VOUT
Dbuck
=
V
IN
(3)
The maximum peak-ripple current of the inductor (Ipk) occurs when the duty cycle is at the minimum value,
specifically when the input voltage (VIN) is at the maximum value which yields the value shown in 方程式4.
5 V
Dbuck
=
= 0.139
36 V
(4)
Substitute the values for fS, L, and Dbuck, in 方程式2 to find the peak-ripple current as shown in 方程式5.
1
2
5 V
1- 0.139
Ipk _buck
=
ì
ì
= 0.229 A
4.7 mH 2 MHz
(5)
The power dissipations can be determined by the RMS current of the inductor. Use 方程式 6 to calculate the
RMS current of the inductor in buck mode (Irms_buck).
1
3
1
2
I
= IO2 UT
+
ìIpk _buck = 1A2 + ì0.458 A2 = 1.1A
rms _buck
3
(6)
Use 方程式7 to calculate the approximate power dissipation of the inductor in buck-mode (Ploss_L_buck).
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P
= Ir2ms _ buck ìRdc
loss _L _ buck
(7)
9.2.2.1.2 Inductor Current in Step-Up Mode
Use 方程式8 to calculate the inductor peak-ripple current in the step-up, or boost, mode (Ipk_boost).
V
Dboost
fsw
1
2
IN
Ipk _ boost
=
ì
ì
L
(8)
where
• Dboost is the duty cycle in boost mode (refer to 方程式9).
VOUT - V
VVOUT
IN
Dboost
=
(9)
In general, the maximum peak-ripple current occurs at 50% duty cycle. In this example, because of the power
derating versus the input voltage, a few calculations can find that the maximum RMS current occurs when the
input voltage is approximately 3.8 V, of which the load current is 0.8 A, according to 表 9-1. 方程式 10 and 方程
式11 show the peak-ripple current under this condition.
5 V - 3.8 V
5 V
Dboost
=
= 0.240
(10)
1
2
3.8 V 0.240
ì = 0.049 A
Ipk _ boost
=
ì
4.7 mH 2 MHz
(11)
The power dissipations can be determined by the RMS current of the inductor. Use 方程式 12 to calculate the
RMS current of the inductor in buck mode (Irms_boost).
2
2
≈
∆
«
’
÷
IOUT
1
3
0.8 A
1
3
≈
’
2
Irms _ boost
=
+
ìIpk _ boost
=
+
ì0.049 A2 = 1.053 A
∆
«
÷
◊
1- Dboost ◊
1- 0.24
(12)
Use 方程式13 to calculate the approximate power dissipation of the inductor in boost-mode (Ploss_L_boost).
= Ir2ms _ boost ìRdc
P
loss _L _ boost
(13)
9.2.2.1.3 Inductor Current in Buck-Boost Overlap Mode
When input voltage is very close to the output voltage, the device operates in buck-boost overlap mode, and the
L1 and L2 pins are switched alternatively in consecutive cycles. The small voltage difference between the input
and output voltage leads to a small amount of ripple current through the inductor. Therefore, the total inductor
current is essentially the load current with small ripples superimposed onto it, and the RMS current is
approximately the same as the load current, which is 1 A.
P
= Io2 ìRdc
loss _L _ buckboost
(14)
9.2.2.1.4 Inductor Peak Current
Because the TPS5516x-Q1 device has internal peak current limit (ISW_limit) of 4.5 A (maximum), this current
should be considered when selecting the power inductor. Select the inductor of the saturation current (ISAT) with
a minimum value of 4.5 A so that the inductor never gets saturated. TI recommends using a shielded inductor.
For this design example, select an AEC-Q200 Grade 0, shielded inductor with the following characteristics:
• Is a surface-mount device (SMD)
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• Has an inductance of 4.7 µH
• Supports a saturation current (ISAT) of 4.8 A
• Is rated for an RMS current (Irms) of 1.5 A or larger
• Is rated for a DC load (Rdc) of 0.04 Ωor smaller
9.2.2.2 Control-Circuit Selections
9.2.2.2.1 Bootstrap Capacitors
The bootstrap capacitors (CBST1 and CBST2) supply the internal high-side MOSFET driver. TI recommends using
a 0.1-µF, X7R-type ceramic capacitor rated for 15 V or larger for the bootstrap capacitors.
9.2.2.2.2 VOUT-Sense Bypass Capacitor
To improve noise immunity, connect a 0.1-µF, X7R-type ceramic capacitor rated for 25 V or greater to the VOUT
pin.
9.2.2.2.3 VREG Bypass Capacitor
The VREG supplies the internal control circuit as well as the drivers for the integrated low-side driver. To improve
noise immunity and stabilize the internal VREG regulator, TI recommends connecting a 4.7-µF, X7R-type
ceramic capacitor rated for 25 V or greater between the VREG and GND pins.
9.2.2.2.4 PG Pullup Resistor and Delay Time
The power-good indicator pin (PG) is an open-drain output pin. The PG pin requires an external pullup resistor to
flag the power-good status. For this design example, select a 100-kΩ resistor to pull up the PG pin from the
output rail.
The PG_DLY pin sets the delay time for the PG status to flip. Follow the instructions listed in the 节 8.3.7 to
program the delay.
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9.2.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
36-V Supply Voltage
18-V Supply Voltage
12-V Supply Voltage
5-V Supply Voltage
3-V Supply Voltage
20%
10%
0%
VIN = 12 V
IOUT = 1 A
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
图9-7. Start-Up Procedure
图9-6. Efficiency vs Load
VIN = 12 V IOUT step change from 0.25 A to 0.75 A
IOUT = 0.5 A
VIN transient rom 12 V to 4 V
图9-8. Step Load Response
图9-9. Battery-Voltage Cranking Response
10 Power Supply Recommendations
The TPS5516x-Q1 family of devices is a power-management device. The power supply for the device is any DC-
voltage source within the specified input range. The supply should also be capable of supplying sufficient current
based on the maximum inductor current in boost-mode operation. When connecting to the power supply and
load, try to use short and solid wires. Twisting the pair of wires for the input and output helps minimize the line
impedance and avoid adversary interference with the circuit operation.
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11 Layout
11.1 Layout Guidelines
The layout of the printed-circuit board (PCB) is critical to achieve low EMI and stable power-supply operation as
well as optimal efficiency. Make the high frequency current loops as small as possible, and follow these
guidelines of good layout practices;
• The TPS5516x-Q1 family of devices is a high-frequency switching converter. Because the four switch
MOSFETs are integrated, the device should be located at the center of the DC-DC power stage. Separate the
power ground and analog ground such that the control circuit can be connected to the relatively quieter
analog ground without being contaminated by the noisy power ground. Use the PGND pin, GND pin, and the
device PowerPAD as the single-point connection between the analog and power grounds.
• Identify the high-frequency switched AC-current loops. In step-down mode, the AC current loop is along the
path of the input capacitor (CIN), L1 pin, internal buck-switch leg, and PGND pin, and closes at the input
capacitor. In step-up mode, the AC current loop is along the path of the output capacitor (COUT), L2 pin,
internal boost-switch leg, and PGND pin, and closes at the output capacitor. These two AC-current loops are
both involved in buck-boost overlap mode.
• Optimize component placement and orientation before routing any traces. Place the input and output filter
capacitors, the device, and the power inductor close together such that the AC-current loops are short, direct,
and the spatial areas enclosed by the loops are minimized. Make the power flow in a straight path rather than
a zigzag path on the board.
• Place the high frequency decoupling ceramic capacitors for the input and output as close as possible to the
device with the main input and output ceramic capacitors placed next to the high-frequency capacitors. This
placement helps confine the high switching noises within a very small area around the device.
• Place the VREG decoupling capacitor close to the VREG pin because it serves as the supply to the internal
low-side MOSFETs drivers. Because the VREG pin receives power from the output rail, the ground lead of
the VREG decoupling capacitor should connect directly to the COUT ground to improve device noise immunity.
备注
The VREG_Q pin must always connect to the VREG pin. Both pins should have a Kelvin
connection to the decoupling capacitor.
• Place the bootstrap capacitors (CBST1 and CBST2) close to the device with short and direct traces to connect
to the corresponding device pins becuase these capacitors serve as the supplies to the internal high-side
MOSFETs drivers
• Place the VOUT_SENSE decoupling capacitor (CVOSN) close to the device. Give the placement of this
capacitor priority over the main output capacitors.
• For TPS55160-Q1 or TPS55162-Q1, place the sense-resistor divider for the output voltage close to the
device.
• Use eight to nine via holes with a 0.3 mm diameter in the device PowerPAD to help dissipate heat through
the layers of the ground plane. Additional vias holes around the device PowerPAD can further enhance heat
dissipation.
• Use at least ten via holes with a 0.3 mm diameter around the input and output capacitors that are connected
to ground-plane layers to minimize the PCB impedance for power current flows.
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11.2 Layout Example
图11-1. Example Circuit Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
TPS55160-Q1 PSpice Transient Model
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, TPS5516xQ1-EVM Evaluation Module for 1-A Single- Inductor Buck-Boost-Converter user's
guide
12.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.5 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS55160QPWPRQ1
TPS55160QPWPTQ1
TPS55162QPWPRQ1
TPS55162QPWPTQ1
TPS55165QPWPRQ1
TPS55165QPWPTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
PWP
PWP
20
20
20
20
20
20
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS55160
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TPS55160
TPS55162
TPS55162
TPS55165
TPS55165
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS55160QPWPRQ1 HTSSOP PWP
TPS55162QPWPRQ1 HTSSOP PWP
TPS55165QPWPRQ1 HTSSOP PWP
20
20
20
2000
2000
2000
330.0
330.0
330.0
16.4
16.4
16.4
6.95
6.95
6.95
7.1
7.1
7.1
1.6
1.6
1.6
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS55160QPWPRQ1
TPS55162QPWPRQ1
TPS55165QPWPRQ1
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
20
20
20
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0020U
PowerPAD TM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
PIN 1 ID
SEATING PLANE
A
0.1 C
AREA
18X 0.65
20
1
2X
6.6
6.4
NOTE 3
5.85
10
11
0.30
0.19
0.1
20X
4.5
4.3
B
C A B
(0.15) TYP
SEE DETAIL A
4X 0.23 MAX
NOTE 5
2X 0.95 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
21
3.43
2.65
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.75
1.98
4224609/A 09/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PWP0020U
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.75)
20X (1.5)
SYMM
SEE DETAILS
1
20
20X (0.45)
(1.3)
TYP
(6.5)
NOTE 9
21
SYMM
(3.43)
18X (0.65)
(
0.2) TYP
VIA
10
11
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
EXPOSE METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-20
4224609/A 09/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0020U
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.75)
BASED ON
0.125 THICK
STENCIL
20X (1.5)
(R0.05) TYP
1
20
20X (0.45)
(3.43)
21
SYMM
BASED ON
0.125 THICK
STENCIL
18X (0.65)
11
10
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.07 X 3.83
2.75 X 3.43 (SHOWN)
2.51 X 3.13
0.125
0.15
0.175
2.32 X 2.90
4224609/A 09/2018
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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