TPS55288RPMR_技术文档

TPS55288

ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

TPS55288 具有I²C 接口的36V、16A 降压/升压转换器

1 特性

3 说明

• 可编程电源(PPS) 支持USB 供电(USB PD)

TPS55288 是一款同步四开关降压/升压转换器，能够

将输出电压稳定在等于、高于或低于输入电压的某一电

压值上。TPS55288 在2.7V 至36V 的宽输入电压范围

内工作，可输出0.8V 至22V 电压以支持各种不同的应

用。

– 宽输入电压范围：2.7V 至36V

– 可编程输出电压范围：0.8V 至22V，步长为

20mV

– ±1% 基准电压精度

– 电缆上压降的可调输出电压补偿

– 可编程输出电流限值高达6.35A，阶跃为50mA

– ±5% 精密输出电流监测

TPS55288 集成了两个 16A MOSFET，其中的升压桥

臂可实现解决方案尺寸和效率间的平衡。通过I²C 接口

对输出电压和输出电流限制进行编程，TPS55288 完全

符合 USB PD 规范。TPS55288 能够通过 12V 输入电

压提供100W 的功率。

– I²C 接口

• 在整个负载范围内具有高效率

– V_IN= 12V、V_OUT= 20V 且I_OUT= 3A 时效率为

97%

– 轻负载状态下的可编程PFM 和FPWM 模式

• 避免频率干扰和串扰

TPS55288 采用平均电流模式控制方案。开关频率可通

过外部电阻在 200 kHz 至 2.2 MHz 之间进行编程，并

且可与外部时钟同步。TPS55288 还提供展频选项，从

而更大限度地减少峰值EMI。

– 可选的时钟同步

– 可编程开关频率范围为200 kHz 至2.2 MHz

• 降低EMI

TPS55288 提供输出过压保护、平均电感器电流限制、

逐周期峰值电流限制和输出短路保护。TPS55288 还通

过可选输出电流限制和断续模式保护，在持续过载情况

下确保安全运行。

– 可选可编程扩展频谱

– 无引线封装

• 丰富的保护特性

TPS55288 可在高开关频率下使用小型电感器和小型电

容器。此器件采用4.0mm × 3.5mm QFN 封装。

– 输出过压保护

– 利用断续模式实现输出短路保护

– 热关断保护

器件信息

封装⁽¹⁾

– 可编程平均电感器电流限制高达16A

• 小解决方案尺寸

器件型号

TPS55288

封装尺寸

VQFN-HR

4.00mm × 3.50mm

– 开关频率高达2.2 MHz（最大值）

– 4.0mm × 3.5mm HotRod^™QFN 封装

• 固定4ms 软启动时间

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

L1

4.7µH

• 使用TPS55288 并借助WEBENCH^®Power

Designer 创建定制设计

C5

0.1µF

C4

0.1µF

2 应用

VIN = 2.7V to 36V

SW1

SW2

BOOT2

DR1H DR1L BOOT1

VIN

VOUT =0.8V to 22V

VOUT

• USB PD

• 集线站

• 工业PC

• 移动电源

• 显示器

C1

R1

10mΩ

C2

C3

4.7µF

VCC

PGND

AGND

ISP

SCL

SDA

ON

EN/UVLO

TPS55288

ISN

OFF

MODE

FB/INT

COMP

CDC

R6

• 无线充电器

DITH/SYNC

FSW

C6

R3

C7

R4

C8

ILIM

R5

R2

典型应用电路

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSF01

TPS55288

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

Table of Contents

7.5 I²C Serial Interface....................................................22

7.6 Register Maps...........................................................26

8 Application and Implementation..................................35

8.1 Application Information............................................. 35

8.2 Typical Application.................................................... 35

9 Power Supply Recommendations................................43

10 Layout...........................................................................44

10.1 Layout Guidelines................................................... 44

10.2 Layout Example...................................................... 45

11 Device and Documentation Support..........................46

11.1 Device Support........................................................46

11.2 接收文档更新通知................................................... 46

11.3 支持资源..................................................................46

11.4 Trademarks............................................................. 46

11.5 静电放电警告...........................................................46

11.6 术语表..................................................................... 46

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 I²C Timing Characteristics.......................................... 9

6.7 Typical Characteristics..............................................10

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................15

7.3 Feature Description...................................................15

7.4 Device Functional Modes..........................................22

Information.................................................................... 46

4 Revision History

Changes from Revision A (August 2020) to Revision B (December 2020)

Page

• Updated thermal information footnote................................................................................................................ 6

• Updated Output Current Limit section.............................................................................................................. 21

• Updated CDC Register (Address = 5h) [reset = 11100000h] section............................................................... 31

• Updated MODE Register (Address = 6h) [reset = 00100000h] section............................................................32

Changes from Revision * (November 2018) to Revision A (August 2020)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

2

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

5 Pin Configuration and Functions

1

2

19

18

DR1L

DR1H

VCC

COMP

ILIM

3

4

5

6

17

16

15

14

VIN

EN/UVLO

CDC

SCL

MODE

SDA

FB/INT

7

13

DITH/SYNC

ISN

图5-1. 26-pin VQFN-HR, RPM Package (Transparent Top View)

表5-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

DR1L

DR1H

VIN

O

Gate driver output for low-side MOSFET in buck side

2

Gate driver output for high-side MOSFET in buck side

Input power supply for the IC

3

PWR

Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high

level enables the device. Logic low level disables the device and turns it into shutdown mode. After

the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as

programmable UVLO input with 1.23-V internal reference.

4

EN/UVLO

I

5

6

SCL

SDA

I

Clock of I²C interface

Data of I²C interface

I/O

Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and

ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is

no dithering function. An external clock can be applied at this pin to synchronize the switching

frequency.

7

DITH/SYNC

I

8

FSW

PGND

AGND

VOUT

O

The switching frequency is programmed by a resistor between this pin and the AGND pin.

Power ground of the IC. It is connected to the source of the low-side MOSFET.

Signal ground of the IC

9, 24

10

PWR

11, 26

Output of the buck-boost converter

Positive input of the current sense amplifier. An optional current sense resistor connected between

the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current

limit setting value in the register, a slow constant current control loop becomes active and starts to

regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin

together with the VOUT pin can disable the output current limit function.

12

ISP

I

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

表5-1. Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

Negative input of the current sense amplifier. An optional current sense resistor connected between

the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current

limit setting value in the register, a slow constant current control loop becomes active and starts to

regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin

together with the VOUT pin can disable the output current limit function.

13

ISN

I

When the device is set to use external output voltage feedback, connect to the center tap of a

resistor divider to program the output voltage. When the device is set to use internal feedback, this

pin is a fault indicator output. When there is an internal fault happening, this pin outputs logic low

level.

14

FB/INT

I/O

Set the operation modes of the TPS55288 by a resistor between this pin and AGND to select PFM

mode, or forced PWM mode in light load condition to select the internal LDO or external 5 V for VCC,

and to select different I²C address.

15

16

MODE

CDC

I

Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a

resistor between this pin and AGND to increase the output voltage to compensate voltage droop

across the cable caused by the cable resistance.

O

Average inductor current limit setting pin. Connect an external resistor between this pin and the

AGND pin.

17

ILIM

COMP

VCC

O

I

Output of the internal error amplifier. Connect the loop compensation network between this pin and

the AGND pin.

18

Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this

pin and the AGND pin.

19

O

I

Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be

connected between this pin and the SW2 pin.

20

BOOT2

SW2

The switching node pin of the boost side. It is connected to the drain of the internal low-side power

MOSFET and the source of internal high-side power MOSFET.

21, 25

22

Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be

connected between this pin and the SW1 pin.

BOOT1

SW1

I

The switching node pin of the buck side. It is connected to the drain of the external low-side power

MOSFET and the source of external high-side power MOSFET.

23

I

4

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

40

UNIT

V

VIN, SW1

DRH1, BOOT1

SW1+6

V

SW1–0.3

VCC, DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE,

CDC, DITH/SYNC

6

V

–0.3

VOUT, SW2, ISP, ISN

Voltage range

25

VOUT+6

20

V

–0.3

VOUT-6

-0.3

at terminals⁽²⁾

ISP, ISN

EN

BOOT2

SW2+6

SW2–0.3

DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE, CDC, DITH/

SYNC

VCC+0.3

V

–0.3

(3)

T_J

Operating Junction, T_J

Storage temperature

150

°C

–40

–65

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground terminal.

(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM) ESD stress voltage⁽²⁾

±2000

(1)

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM) ESD stress

voltage⁽³⁾

±500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

NOM

MAX

36

UNIT

V

V_IN

V_OUT

L

Input voltage range

Output voltage range

0.8

22

V

Effective inductance range

Effective input capacitance range

Effective output capacitance range

Operating junction temperature

0.7

4.7

22

13

µH

µF

°C

C_IN

C_OUT

T_J

4.7

10

100

1000

125

–40

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

6.4 Thermal Information

TPS55288

THERMAL METRIC⁽¹⁾

VQFN-HR (RPM)-26 PINS VQFN-HR (RPM)-26 PINS

UNIT

Standard

47.5

23.8

12.8

0.5

EVM⁽²⁾

25.8

N/A

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

N/A

0.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

11.6

N/A

12.7

7.8

Ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Measured on TPS55288EVM-045, 4-layer, 2-oz/2-oz/2-oz/2-oz copper 112-mm×71-mm PCB.

6.5 Electrical Characteristics

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_IN

Input voltage range

2.7

2.8

2.6

36

3.0

2.7

V

V_INrising

2.9

V_{VIN_UVLO}

Under voltage lockout threshold

V_INfalling

2.65

IC enabled, no load, no switching. V_IN

= 3V to 24V, V_OUT= 0.8V, V_FB= V_REF

+ 0.1V, R_FSW=100kΩ, T_Jup to 125°C

Quiescent current into the VIN pin

Quiescent current into the VOUT pin

760

860

µA

I_Q

IC enabled, no load, no switching, V_IN

= 2.9V, V_OUT= 3V to 20V, V_FB= V_REF

+ 0.1V, R_FSW=100kΩ, T_Jup to 125°C

760

6.8

860

10

µA

IC disabled, V_IN= 2.9V to 14V, T_Jup

to 125°C

I_SD

Shutdown current into the VIN pin

Internal regulator output

V_CC

I_VCC= 50mA, V_IN= 8V, V_OUT= 20V

V_IN= 5.0V, V_OUT= 20V I_VCC= 60mA

V_IN= 14V, V_OUT= 5.0V, I_VCC= 60mA

5.0

5.2

200

110

5.4

320

170

V

mV

V_{CC_DO}

VCC dropout

EN/UVLO

V_{EN_H}

EN Logic high threshold

EN Logic low threshold

Enable threshold hysteresis

V_CC= 2.7V to 5.5V

1.15

V

V_{EN_L}

0.4

V_{EN_HYS}

0.05

0.12

1.23

UVLO rising threshold at the EN/UVLO

V_UVLO

V_CC= 3.0V to 5.5V

1.20

1.26

V

V_{UVLO_HYS}

I_UVLO

UVLO threshold hysteresis

8

14

5

20

mV

µA

Sourcing current at the EN/UVLO pin V_EN/UVLO= 1.3V

4.5

5.5

OUTPUT

V_OUT

Output voltage range

0.8

22

V

Output overvoltage protection

threshold

V_OVP

22.5

23.5

1

24.5

V_{OVP_HYS}

I_{FB_LKG}

Over voltage protection hysteresis

V

Leakage current at the FB pin

Leakage current into the VOUT pin

Output discharge current

T_Jup to 125°C

100

20

nA

IC disabled, V_OUT= 20V, V_SW2= 0V,

T_Jup to 125°C

I_{VOUT_LKG}

I_DISCHG

1

µA

V_OUT= 20V, V_CC= 5.2V

40

100

170

mA

INTERNAL REFERENCE DAC

6

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T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

Resolution of reference voltage DAC

Integral non-linearity

10

INL

4

2

LSB

–4

–1

DNL

Differential non-linearity

VOUT_FS=03h, REF=03C0h,

V_REF=1.129V

19.7

14.78

9.85

4.93

0.74

0.56

0.37

0.18

20

15

10

5

20.3

15.22

10.15

5.07

V

VOUT_FS=02h, REF=03C0h,

V_REF=1.129V

Output voltage when V_REFis set to

1.129V

V_{OUT_FULL}

VOUT_FS=01h, REF=03C0h,

V_REF=1.129V

VOUT_FS=00h, REF=03C0h,

V_REF=1.129V

VOUT_FS=03h, REF=0000h,

V_REF=45mV

0.8

0.6

0.4

0.2

0.86

VOUT_FS=02h, REF=0000h,

V_REF=45mV

0.64

Output voltage when V_REFis set to

45mV

V_{OUT_ZERO}

VOUT_FS=01h, REF=0000h,

V_REF=45mV

0.43

VOUT_FS=00h, REF=0000h,

V_REF=45mV

0.22

REFERENCE VOLTAGE

External feedback with REF=03C0h

External feedback with REF=02C6h

External feedback with REF=019Ah

External feedback with REF=00D2h

1.117

0.837

0.502

0.276

1.129

0.846

0.508

0.282

1.141

0.855

0.514

0.288

V

Reference voltage at the FB/INT pin

when using external feedback

V_REF

POWER SWITCH

Low-side MOSFET on resistance on

V_OUT= 20V, V_CC= 5.2V

7.1

7.6

mΩ

boost side

R_DS(on)

High-side MOSFET on resistance on

boost side

INTERNAL CLOCK

180

200

2200

100

90

220

2400

145

kHz

ns

R_FSW= 100kΩ

R_FSW= 9.09kΩ

Boost mode

f_SW

Switching frequency

2000

t_{OFF_min}

t_{ON_min}

V_FSW

Min. off time

Min. on time

Buck mode

130

ns

Voltage at the FSW pin

1

V

CURRENT LIMIT

R_ILIM= 20kΩ, V_IN= 8V, V_OUT= 20V,

f_SW= 400kHz, FPWM

14

4

16.5

5.5

19

A

R_ILIM= 20kΩ, V_IN= 8V, V_OUT= 20V,

f_SW= 400kHz, PFM

I_{LIM_AVG}

Average inductor current limit

R_ILIM= 60kΩ, V_IN= 5V, V_OUT= 14V,

f_SW= 2.2MHz, FPWM

R_ILIM= 60kΩ, V_IN= 5V, V_OUT= 14V,

f_SW= 2.2MHz, PFM

4

5.5

R_ILIM= 20kΩ, V_IN= 8V, V_OUT= 20V,

f_SW= 400kHz, FPWM

25

I_{LIM_PK}

Peak inductor current limit at high side

Voltage at the ILIM pin

R_ILIM= 20kΩ, V_IN= 8V, V_OUT= 20V,

25

A

V

f_SW= 400kHz, PFM

V_ILIM

VOUT = 3V

0.6

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ZHCSKY4B –NOVEMBER 2018 –REVISED DECEMBER 2020

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_ISN= 2V to 21V,IOUT_LIMIT Register

= 11100100b

48

50

52

mV

Current loop regulation voltage

between the ISP and ISN pins

V_SNS

V_ISN= 2V to 21V,IOUT_LIMIT Register

= 10111100b

28

30

32

mV

CABLE VOLTAGE DROOP COMPENSATION

R_CDC= 20kΩ or floating, V_ISP–V_ISN

0.95

1

40

700

30

100

20

7.5

0

1.05

75

V

= 50mV

V_CDC

Voltage at the CDC pin

R_CDC= 20kΩ or floating, V_ISP–V_ISN

= 2mV

mV

µA

Internal output feedback,

CDC[2:0]=111, V_ISP–V_ISN= 50mV

650

70

750

60

Internal output feedback,

CDC[2:0]=111, V_ISP–V_ISN= 2mV

VOUT increase for cable droop

compensation

V_{OUT_CDC}

Internal output feedback,

CDC[2:0]=001, V_ISP–V_ISN= 50mV

130

40

Internal output feedback,

CDC[2:0]=001, V_ISP–V_ISN= 10mV

External output feedback, R_CDC

20kΩ, V_ISP–V_ISN= 50mV

=

7.23

7.87

0.3

External output feedback, R_CDC

20kΩ, V_ISP–V_ISN= 0mV

I_{FB_CDC}

FB/INT pin sinking current

µA

External output feedback, R_CDC

0

µA

floating, V_ISP–V_ISN= 50mV

ERROR AMPLIFIER

V_FB= V_REF+ 400mV, V_COMP=1.5V,

V_CC=5V

I_SINK

COMP pin sink current

20

60

µA

V_FB= V_REF- 400mV, V_COMP=1.5V,

V_CC=5V

I_SOURCE

COMP pin source current

V_CCLPH

V_CCLPL

G_EA

High clamp voltage at the COMP pin

Low clamp voltage at the COMP pin

Error amplifier transconductance

1.8

0.7

V

190

µA/V

SOFT START

t_SS

Soft-start time

3

4

5

ms

DR1H GATE DRIVER

V_{DR1H_L}Low-state voltage drop

V_{DR1H_H}High-state voltage drop

DR1L GATE DRIVER

V_{DR1L_L}Low-state voltage drop

V_{DR1L_H}High-state voltage drop

SPREAD SPECTRUM

0.1

0.2

V

_DR1H–V_SW1, 100-mA sinking

_BOOT1–V_DR1H, 100-mA sourcing

100-mA sinking

0.1

0.2

V

V_CC–V_DR1L, 100-mA sourcing

V_DITH/SYNC= 1.0V, R_FSW=49.9kΩ,

voltage rising from 0.85V

I_{DITH_CHG}

I_{DITH_DIS}

Dithering charge current

2

µA

V_DITH/SYNC= 1.0V, R_FSW=49.9kΩ,

voltage falling from 1.15V

Dithering discharge current

V_{DITH_H}

V_{DITH_L}

Dither high threshold

Dither low threshold

1.07

0.93

V

SYNCHRONOUS CLOCK

V_{SNYC_H}Sync clock high voltage threshold

V_{SYNC_L}Sync clock low voltage threshold

1.2

V

0.4

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T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_{SYNC_MIN}

HICCUP

t_HICCUP

Minimum sync clock pulse width

50

ns

Hiccup off time

76

ms

MODE RESISTANCE DETECTION

I_MODE

Sourcing current from the MODE pin

V_MODE= 2.5V

9

1.147

0.824

0.571

0.321

0.168

0.080

0.014

10

1.220

0.88

11

1.293

0.936

0.657

0.381

0.210

0.114

0.040

µA

V

V_{MODE_DT1}

V_{MODE_DT2}

V_{MODE_DT3}

V_{MODE_DT4}

V_{MODE_DT5}

V_{MODE_DT6}

V_{MODE_DT7}

V

0.614

0.351

0.189

0.097

0.027

V

Detection threshold voltage at the

MODE pin

V

LOGIC INTERFACE

V_{I2C_IO}

V_{I2C_H}

V_{I2C_L}

IO voltage range for I²C

1.7

0.4

5.5

1.2

V

I²C input high threshold

I²C input low threshold

V_CC= 2.7V to 5.5V

Leakage current into FB/INT pin when

outputting high impedance

I_{FB/INT_H}

V_{FB/INT_L}

V_FB/INT= 5V

100

0.1

nA

V

Output low voltage range of the FB/

INT pin

Sinking 4mA current

0.03

PROTECTION

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

T_Jrising

175

20

°C

T_{SD_HYS}

T_Jfalling below TSD

6.6 I²C Timing Characteristics

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I²C TIMING

f_SCL

SCL clock frequency

100

0.5

1000

kHz

µs

Bus free time between a STOP and

START condition

t_BUF

Fast mode plus

t_HD(STA)

t_LOW

Hold time (repeated) START condition

Low period of the SCL clock

260

0.5

ns

µs

ns

t_HIGH

High period of the SCL clock

260

Setup time for a repeated START

condition

t_SU(STA)

260

ns

t_SU(DAT)

t_HD(DAT)

t_RCL

Data setup time

50

0

ns

µs

ns

Data hold time

Rise time of SCL signal

120

Rise time of SCL signal after a

repeated START condition and after

an ACK bit

t_RCL1

ns

t_FCL

Fall time of SCL signal

120

ns

pF

t_RDA

t_FDA

t_SU(STO)

C_B

Rise time of SDA signal

Fall time of SDA signal

Setup time of STOP condition

Capacitive load for SDA and SCL

260

200

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6.7 Typical Characteristics

V_IN= 12 V, T_A= 25°C, f_SW= 400 kHz, unless otherwise noted.

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

30%

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

20%

10%

0

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D001

D002

图6-1. Efficiency vs Output Current,

图6-2. Efficiency vs Output Current,

V_OUT= 5 V, FPWM

V_OUT= 5 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D003

D004

图6-3. Efficiency vs Output Current,

图6-4. Efficiency vs Output Current,

V_OUT= 9 V, FPWM

V_OUT= 9 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D005

D006

图6-5. Efficiency vs Output Current,

图6-6. Efficiency vs Output Current,

V_OUT= 12 V, FPWM

V_OUT= 12 V, PFM

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100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D007

D008

图6-7. Efficiency vs Output Current,

图6-8. Efficiency vs Output Current,

V_OUT= 15 V, FPWM

V_OUT= 15 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D009

D010

图6-9. Efficiency vs Output Current,

图6-10. Efficiency vs Output Current,

V_OUT= 20 V, FPWM

V_OUT= 20 V, PFM

18

17

16

15

14

13

12

11

10

9

2200

2000

1800

1600

1400

1200

1000

800

V_IN= 20 V, V_OUT= 5 V

V_IN= 12 V, V_OUT= 12 V

V_IN= 5 V, V_OUT= 20 V

8

7

600

6

5

400

4

200

3

2

0

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90 100

Resistance (kW)

图6-11. Average Inductor Current Limit vs Setting

图6-12. Switching Frequency vs Setting

Resistance

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0.2865

0.285

0.514

0.512

0.51

0.2835

0.282

0.508

0.506

0.504

0.502

0.2805

0.279

0.2775

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D013

D014

图6-13. Reference Voltage vs Temperature (V_REF

=

图6-14. Reference Voltage vs Temperature (V_REF

0.508 V)

=

0.282 V)

0.855

0.852

0.849

0.846

0.843

0.84

1.146

1.14

1.134

1.128

1.122

1.116

1.11

0.837

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D015

D016

图6-15. Reference Voltage vs Temperature (V_REF

=

图6-16. Reference Voltage vs Temperature (V_REF=

0.846 V)

1.129 V)

780

775

770

765

760

755

7.5

7.25

7

6.75

6.5

6.25

6

750

Into V_IN, V_IN= 24 V, V_OUT= 3 V

Into V_OUT, V_IN= 3.1 V, V_IN= 20 V

745

-40

5.75

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D017

D018

图6-17. Quiescent Current vs Temperature

图6-18. Shutdown Current vs Temperature

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1.2355

1.235

2500

2000

1500

1000

500

1.2345

1.234

1.2335

1.233

1.2325

1.232

f_SW= 200 kHz

f_SW= 2200 kHz

1.2315

1.231

1.2305

1.23

-40

0

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D019

D020

图6-19. ENABLE/UVLO Rising Threshold vs

图6-20. Switching Frequency vs Temperature

Temperature

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

1

2

3

4

5

Output Current (A)

6

7

8

D021

图6-21. CDC Voltage vs Output Current with R_SENSE= 10 mΩ

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7 Detailed Description

7.1 Overview

The TPS55288 is a 16-A buck-boost DC-to-DC converter with the two boost MOSFETs integrated. The

TPS55288 can operate over a wide range of 2.7-V to 36-V input voltage and an output voltage of 0.8 V to 22 V. It

can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage

and the set output voltage. The TPS55288 operates in buck mode when the input voltage is greater than the

output voltage and in boost mode when the input voltage is less than the output voltage. When the input voltage

is close to the output voltage, the TPS55288 operates in one-cycle buck and one-cycle boost mode alternately.

The TPS55288 uses an average current mode control scheme. Current mode control provides simplified loop

compensation, rapid response to the load transients, and inherent line voltage rejection. An error amplifier

compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines

the average inductor current.

An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.2 MHz. The

internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the

TPS55288 can dither the switching frequency at ±7% of the set frequency.

The TPS55288 works in fixed-frequency PWM mode at moderate to heavy load currents. In light load condition,

the TPS55288 can be configured to automatically transition to PFM mode or be forced in PWM mode by either

connecting a resistor at the MODE pin or setting the corresponding bit in an internal register.

The output voltage of the TPS55288 is adjustable by setting the internal register through I²C interface. An

internal 10-bit DAC adjusts the reference voltage related to the value written into the REF register. The device

can also limit the output current by placing a current sense resistor in the output path. These two functions

support the programmable power supply (PPS) feature of the USB PD.

The TPS55288 provides average inductor current limit set by a resistor at the ILIM pin. In addition, it provides

cycle-by-cycle peak inductor current limit during transient to protect the device against overcurrent condition

beyond the capability of the device.

A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable

input undervoltage lockout (UVLO) with hysteresis. The output overvoltage protection (OVP) feature turns off the

high-side FETs to prevent damage to the devices powered by the TPS55288.

The device provides hiccup mode option to reduce the heating in the power components when output short

circuit happens. When the hiccup mode is enabled, the TPS55288 turns off for 76 ms and restarts at soft start-

up.

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7.2 Functional Block Diagram

L1

VIN

C3

C4

C8

SW1

BOOT1

BOOT2

SW2

R1

VOUT

C2

VIN

VOUT

LDO

Current

Sense

C1

VCC

CDC

R7

I-V

C5

DL

I_limit

ISP

ISN

Buck-Boost

Control

DH

Iref

FB/INT

COMP

Gm

MODE

ADC

BOOST

BUCK

R3

R2

C6

Vref

DAC

SDA

SCL

PGND

AGND

ILIM

Logic Core

EN/UVLO

Iref

Vref

V_SYNC/DITH

1.0V

I_limit

VIN

VCC

VIN UVLO

VOUT OVP

Thermal

FSW

VOUT

R5

f_MOD

R4

DITH/SYNC

C7

7.3 Feature Description

7.3.1 VCC Power Supply

An internal LDO to supply the TPS55288 outputs regulated 5.2-V voltage at the VCC pin with 60-mA output

current capability. When V_INis less than V_OUT, the internal LDO selects the power supply source by comparing

V_INto a rising threshold of 6.2 V with 0.3-V hysteresis. When V_INis higher than 6.2 V, the supply for LDO is V_IN.

When V_INis lower than 5.9 V, the supply for LDO is V_OUT. When V_OUTis less than V_IN, the internal LDO selects

the power supply source by comparing V_OUTto a rising threshold of 6.2 V with 0.3-V hysteresis. When V_OUTis

higher than 6.2 V, the supply for LDO is V_OUT. When V_OUTis lower than 5.9 V, the supply for LDO is V_IN. 表 7-1

shows the supply source selection for the internal LDO.

表7-1. V_CCPower Supply Logic

V_IN

V_OUT

INPUT for V_CCLDO

V_IN> 6.2 V

V_IN< 5.9 V

V_IN> V_OUT

V_OUT>V_IN

V_OUT> 6.2 V

V_OUT< 5.9 V

V_IN

V_OUT

V_IN

To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an

external 5-V power source can be applied at the VCC pin to supply the TPS55288. The external 5-V power

supply must have at least 100-mA output current capability and must be within the 4.75-V to 5.5-V regulation

range. To use an external power supply for V_CC, a resistor with proper resistance must be connected to the

MODE pin.

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7.3.2 Operation Mode Setting

By placing different resistors between the MODE pin and AGND pin, the TPS55288 selects the internal power

supply or external power supply for V_CC, selects one of two different I²C addresses, and selects the PFM mode

or the forced PWM mode in light load conditions. 表7-2 shows the resistance values for each selection. After the

TPS55288 is enabled, an I²C master device can control these three operating modes by writing the

corresponding value into the internal registers regardless the resistance settings at the MODE pin. See details in

节7.6.

表7-2. V_CCSource, I²C Slave Address and PFM/PWM Programming

RESISTOR VALUE

OPERATING MODE AT LIGHT

LOAD

V_CCSOURCE

I²C SLAVE ADDRESS

(kΩ)

0

Internal

External

74h

75h

74h

75h

PWM

PFM

PWM

PFM

PWM

PFM

PWM

PFM

6.19

14.3

24.9

51.1

75.0

105

Open

7.3.3 Input Undervoltage Lockout

When the input voltage is below 2.6 V, the TPS55288 is disabled. When the input voltage is above 3 V, the

TPS55288 can be enabled by pulling the EN pin to a high voltage above 1.3 V.

7.3.4 Enable and Programmable UVLO

The TPS55288 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage at

the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V but less

than the enable UVLO threshold of 1.23 V, the TPS55288 is enabled but still in standby mode. The TPS55288

starts to detect the resistance between the MODE pin and ground. After that, the TPS55288 selects the power

supply for V_CC, the I²C slave address, and the PFM or FPWM mode for light load condition accordingly.

The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout

with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS55288 is

enabled for I²C communication and switching operation. A hysteresis current I_{UVLO_HYS}is sourced out of the EN/

UVLO pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing

input voltage.

By using resistor divider as shown in 图7-1, the turnon threshold is calculated using 方程式1.

R1

8

= 8

× (1 +

)

+0(78.1 _10)

78.1

42

(1)

where

• V_UVLOis the UVLO threshold of 1.23 V at the EN/UVLO pin

The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/

UVLO resistor divider and is given by the Equation 2.

¿8

= +_{78.1_*;5}× 41

+0(78.1)

(2)

where

• I_{UVLO_HYS}is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above

V_UVLO

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VIN

I_{UVLO_HYS}

R1

EN/UVLO

Enable

R2

C1

UVLO Comparator

1.23V

图7-1. Programmable UVLO With Resistor Divider at the EN/UVLO pin

Using an NMOSFET together with a resistor divider can implement both logic enable and programmable UVLO

as shown in 图7-2. The EN logic high level must be greater than enable threshold plus the V_thof the NMOSFET

Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor divider during

shutdown mode.

VIN

R1

I_{UVLO_HYS}

EN

EN/UVLO

Enable

R2

C1

UVLO Comparator

1.23V

图7-2. Logic Enable and Programmable UVLO

7.3.5 Soft Start

When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable

UVLO threshold, the TPS55288 is ready to accept the command from I²C master device. An I²C master device

can configure the internal registers of the TPS55288 before setting the OE bit of the register 06h. Once an I²C

master device sets the OE bit to 1, the TPS55288 starts to ramp up the output voltage by ramping an internal

reference voltage from 0 V to a voltage set in the internal registers 00h and 01h within typical 4 ms.

7.3.6 Shutdown and Load Discharge

When the EN/UVLO pin voltage is pulled below 0.4 V, the TPS55288 is in shutdown mode, and all functions are

disabled. All internal registers are reset to default values.

When the EN/UVLO pin is at high logic level and the OE bit is cleared to 0, the TPS55288 turns off the switching

operation but keeps the I²C interface active. Simultaneously, if the DISCHG bit in the register 06h is set to 1, the

TPS55288 discharges the output voltage below 0.8 V by an internal constant current.

7.3.7 Switching Frequency

The TPS55288 uses a fixed frequency average current control scheme. The switching frequency is between 200

kHz and 2.2 MHz set by placing a resistor at the FSW pin. An internal amplifier holds this pin at a fixed voltage of

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1 V. The setting resistance is between maximum of 100kΩ and minimum of 9.09kΩ. Use Equation 3 to calculate

the resistance by a given switching frequency.

1000

B

=

(MHz)

59

0.05 × 4₍₅₉+ 20

(3)

where

• R_FSWis the resistance at the FSW pin

For noise-sensitive applications, the TPS55288 can be synchronized to an external clock signal applied to the

DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. A resistor

also must be connected to the FSW pin when the TPS55288 is switching by the external clock. The external

clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within ±30% of

the corresponding frequency set by the resistor. 图7-3 is a recommended configuration.

External Clock

DITH/SYNC

FSW

R_FSW

图7-3. External Clock Configuration

7.3.8 Switching Frequency Dithering

The TPS55288 provides an optional switching frequency dithering that is enabled by connecting a capacitor from

the DITH/SYNC pin to ground. 图7-4 illustrates the dithering circuit. By charging and discharging the capacitor, a

triangular waveform centered at 1 V is generated at the DITH/SYNC pin. The triangular waveform modulates the

oscillator frequency by ±7% of the nominal frequency set by the resistance at the FSW pin. The capacitance at

the DITH/SYNC pin sets the modulation frequency. A small capacitance modulates the oscillator frequency at a

fast rate than a large capacitance. For the dithering circuit to effectively reduce peak EMI, the modulation rate

normally is below 1 kHz. Equation 4 calculates the capacitance required to set the modulation frequency, F_MOD

.

1

%

=

(()

&+6*

2.8 × 4₍₅₉× (_/1&

(4)

where

• R_FSWis the switching frequency setting resistance (Ω) at the FSW pin

• F_MODis the modulation frequency (Hz) of the dithering

Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering

function also is disabled when an external synchronous clock is used.

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1.07V

1.0V

0.93V

DITH/SYNC

C_DITH

F_MOD

FSW

R_FSW

图7-4. Switching Frequency Dithering

7.3.9 Inductor Current Limit

The TPS55288 implements both peak current and average inductor current limit by a resistor connected to the

ILIM pin. The average current mode control loop uses the current sense information at the high-side MOSFET of

the boost leg to clamp the maximum average inductor current to 16.5 A (typical) when the resistor is 20 kΩ. Use

large resistance to get smaller average inductor current limit. Use Equation 5 to calculate the resistance for a

desired average inductor current limit.

min(1,0.6 ×8₁₇₆)× 330000

+

=

(#)

#8)_.+/+6

4_+.+/

(5)

where

• I_{AVG_LIMIT}is the average inductor current limit

• R_ILIMis the resistance (Ω) between the ILIM pin and analog ground

Besides the average current limit, a peak current limit protection is implemented during transient to protect the

device against over current condition beyond the capability of the device.

7.3.10 Internal Charge Path

Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally re-

charged by V_CCthrough both the external and internal bootstrap diodes when the low-side MOSFET is turned

on. When the TPS55288 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is

constantly on. An internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2,

charges the bootstrap capacitor to V_CCso that the high-side MOSFET remains on.

7.3.11 Output Voltage Setting

There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage.

The TPS55288 has a 10-bit DAC to program the reference voltage from 45 mV to 1.2 V. The TPS55288 also can

select an internal feedback resistor divider or an external resistor divider by setting the FB bit in register 04h.

When the FB bit is set to 0, the output voltage feedback ratio is set in internal register 04h. When the FB bit is

set to 1, the output voltage feedback ratio is set by an external resistor divider.

When using internal output voltage feedback settings, there are four feedback ratios programmable by writing

the INTFB[1:0] bits of register 04h. With this function, the TPS55288 can limit the maximum output voltage to

different values. In addition, the minimum step of the output voltage change is also programmed to 20 mV, 15

mV, 10 mV, and 5 mV, accordingly.

When using an external output voltage feedback resistor divider as shown in 图 7-5, use Equation 6 to calculate

the output voltage with the reference voltage at the FB/INT pin.

4_{($_72}

V₁₇₆= 8 × (1 +

)

4'(

4_{($_$6}

(6)

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R_SNS

V_OUT

VOUT

ISP

R_{FB_UP}

ISN

FB/INT

R_{FB_BT}

图7-5. Output Voltage Setting by External Resistor Divider

TI recommends using 100 kΩ for the up resistor R_{FB_UP}. The reference voltage V_REFat the FB/INT pin is

programmable from 45 mV to 1.2 V by writing a 10-bit data into register 00h and 01h.

7.3.12 Output Current Monitoring and Cable Voltage Droop Compensation

The TPS55288 outputs a voltage at the CDC pin proportional to the sensed voltage across a output current

sensing resistor between the ISP pin and the ISN pin. Equation 7 shows the exact voltage at the CDC pin

related to the sensed output current.

V_%&%= 20 × (8 F 8

)

+52

+50

(7)

To compensate the voltage droop across a cable from the output of the USB port to its powered device, the

TPS55288 can lift its output voltage in proportion to the load current. There are two methods in the TPS55288 to

implement the compensation: by setting internal register 05h or by placing a resistor between the CDC pin and

AGND pin.

When using internal output voltage feedback, it is recommended to use the internal compensation setting. When

using an external resistor divider at the FB/INT pin to set the output voltage, it is recommended to use the

external compensation setting by placing a resistor at the CDC pin.

By default, the internal cable voltage droop compensation function is enabled with 0 V added to the output

voltage. Write the value into the bit CDC [2:0] in register 05h to get the desired voltage compensation.

When using external output voltage feedback, external compensation is better than the internal register for its

high accuracy. The output voltage rises in proportion to the current sourcing from the CDC pin through the

resistor at the CDC pin. It is recommended to use 100-kΩ resistance for the up resistor of the feedback resistor

divider. Equation 8 shows the output voltage rise related to the sensed output current, the resistance at the CDC

pin, and the up resistor of the output voltage feedback resistor divider.

8

F 8

+50

+52

V_{176_%&%}= 3 × 4_{($_72}× (

)

4_%&%

(8)

where

• R_{FB_UP}is the up resistor of the resistor divider between the output and the FB/INT pin

• R_CDCis the resistor at the CDC pin

When RFB_UP is 100 kΩ, the output voltage rise versus the sensed output current and the resistor at the CDC

pin is shown in 图7-6.

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V_{OUT_CDC}(V)

0.8

R_CDC=20K

0.75V

0.5V

0.2V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

R_CDC=30K

R_CDC=75K

R_CDC=150K

R_CDC=floating

40

0.1V

V_ISPœ V_ISN

(mV)

10

20

30

50

图7-6. Output Voltage Rise vs Output Current

7.3.13 Integrated Gate Drivers

The TPS55288 provides two N-channel MOSFET gate drivers for buck side. Each driver is capable of sourcing

1-A and sinking 1.8-A peak current. In buck operation, the DR1H pin and the DR1L pin are switched by the PWM

controller. In boost mode, the DR1H pin remains at continuously high voltage to turn on the high-side MOSFET

of the buck side, and the DR1L pin remains at continuously low voltage to turn off the low-side MOSFET of the

buck side.

In DCM buck mode operation, the DR1L turns off the low-side FET when the inductor current drops to zero.

The low-side gate driver is powered from the VCC pin, and the high-side gate driver is powered from the

bootstrap capacitor C_BOOT1, which is between the BOOT1 pin and the SW1 pin.

7.3.14 Output Current Limit

The output current limit is programmable from 0 A to 6.35 A by placing a 10-mΩ current sensing resistor

between the ISP pin and the ISN pin. Smaller resistance results in a higher current limit and bigger resistance

results in a lower current limit. An internal register sets the current sense voltage across the ISP pin and the ISN

pin. The programmable voltage step between the ISP pin and the ISN pin is 0.5 mV.

Connecting the ISP and the ISN pin together to the VOUT pin disables the output current limit because the

sensed voltage is always zero. The output current limit can also be disabled by reset the Current_Limit_EN bit in

the Current_Limit register to 0.

When the OE bit or the Current_Limit_EN bit is changed from 0 to 1, the OCP_MASK must be 0. After the OE bit

and the Current_Limit_EN bit are set, set the OCP_MASK to 1 to enable the OCP fault indication output.

7.3.15 Overvoltage Protection

The TPS55288 has output overvoltage protection. When the output voltage at the VOUT pin is detected above

23.5 V typically, the TPS55288 turns off two high-side FETs and turns on two low-side FETs until its output

voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function prevents

overvoltage on the output and secures the circuits connected to the output from excessive overvoltage.

7.3.16 Output Short Circuit Protection

In addition to the average inductor current limit, the TPS55288 implements the output short-circuit protection by

entering hiccup mode. To enable hiccup mode, the HICCUP bit in register 06h must be set. After soft start-up

time of 4 ms, the TPS55288 monitors the average inductor current and output voltage. Whenever the output

short circuit happens, causing the average inductor current hitting the set limit and the output voltage below 0.8

V, the TPS55288 shuts down the switching for 76 ms (typical) and then repeats the soft start for 4 ms. The

hiccup mode helps reduce the total power dissipation on the TPS55288 in the output short-circuit or overcurrent

condition.

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7.3.17 Thermal Shutdown

The TPS55288 is protected by a thermal shutdown circuit that shuts down the device when the internal junction

temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers values remain

unchanged when thermal shutdown is triggered. The converter automatically restarts when the junction

temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown threshold.

7.4 Device Functional Modes

In light load condition, the TPS55288 can work in PFM or forced PWM mode to meet different application

requirements. The PFM mode decreases switching frequency to reduce the switching loss thus it gets high

efficiency at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired

low switching frequency but the efficiency becomes lower than that of PFM mode.

7.4.1 PWM Mode

In FPWM mode, the TPS55288 keeps the switching frequency unchanged in light load condition. When the load

current decreases, the output of the internal error amplifier decreases as well to reduce the average inductor

current down to deliver less power from input to output. When the output current further reduces, the current

through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned off

even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to

zero. The power flow is from output side to input side. The efficiency is low in this condition. However, with the

fixed switching frequency, there is no audible noise or other problems that might be caused by low switching

frequency in light load condition.

7.4.2 Power Save Mode

The TPS55288 improves the efficiency at light load condition with the PFM mode. By connecting an appropriate

resistor at the MODE pin or enabling the PFM function in the internal register, the TPS55288 can work in PFM

mode at light load condition. When the TPS55288 operates at light load condition, the output of the internal error

amplifier decreases to make the inductor peak current down to deliver less power to the load. When the output

current further reduces, the current through the inductor will decrease to zero during the switch-off time. When

the TPS55288 works in buck mode, once the inductor current becomes zero, the low-side switch of the buck

side is turned off to prevent the reverse current from output to ground. When the TPS55288 works in boost

mode, once the inductor current becomes zero, the high side-switch of the boost side is turned off to prevent the

reverse current from output to input. The TPS55288 resumes switching until the output voltage drops. Thus the

PFM mode reduces switching cycles and eliminates the power loss by the reverse inductor current to get high

efficiency in light load condition.

7.5 I²C Serial Interface

The TPS55288 uses I²C interface for flexible converter parameter programming. I²C is a bi-directional 2-wire

serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I²C

devices can be considered as masters or slaves when performing data transfers. A master is the device that

initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any

device addressed is considered a slave.

The TPS55288 operates as a slave device with address 74h and 75h set by a different resistor at the MODE pin.

Receiving control inputs from the master device like a microcontroller or a digital signal processor reads and

writes the internal registers 00h through 07h. The I²C interface of the TPS55288 supports both standard mode

(up to 100 kbit/s) and fast mode plus (up to 1000 kbit/s). Both SDA and SCL must be connected to the positive

supply voltage through current sources or pullup resistors. When the bus is free, both lines are in high voltage.

7.5.1 Data Validity

The data on the SDA line must be stable during the high level period of the clock. The high level or low level

state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is

generated for each data bit transferred.

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SDA

SCL

Data line stable

Data valid

Change of data

allowed

图7-7. I²C Data Validity

7.5.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A high level to low level transition

on the SDA line while SCL is at high level defines a START condition. A low level to high level transition on the

SDA line when the SCL is at high level defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

START (S)

STOP (P)

图7-8. I²C START and STOP Conditions

7.5.3 Byte Format

Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit

(MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other

function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer

then continues when the slave is ready for another byte of data and release the clock line SCL.

Acknowledgement signal

from slave

Acknowledgement signal

from receiver

MSB

SDA

SCL

1

2

7

8

9

1

2

8

9

S or Sr

P or Sr

START or

Repeated

START

STOP or

Repeated

START

图7-9. Byte Format

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7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9^thclock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

to low level and it remains stable low level during the high level period of this clock pulse.

The Not Acknowledge signal is when SDA remains high level during the 9^thclock pulse. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

7.5.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is seven bits long followed by the eighth bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

SCL

1 - 7

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

图7-10. Slave Address and Data Direction

7.5.6 Single Read and Write

图7-11 and 图7-12 show the single-byte write and single-byte read format of the I²C communication.

1

7

1

8

1

8

1

S

Slave Address

0

ACK

Register Address

ACK

Data to Address

ACK

P

图7-11. Single-byte Write

1

7

1

0

1

8

1

7

1

S

Slave Address

ACK

Register Address

ACK

S

Slave Address

ACK

From master to slave

From slave to master

8

1

Data from Address

NACK

P

图7-12. Single-byte Read

If the register address is not defined, the TPS55288 sends back NACK and goes back to the idle state.

7.5.7 Multi-Read and Multi-Write

The TPS55288 supports multi-read and multi-write.

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1

7

1

0

1

8

1

S

Slave Address

ACK

Register Address

ACK

8

1

8

1

8

1

Data to Address

ACK Data to Address + 1 ACK

······

Data to Address + N ACK

P

图7-13. Multi-byte Write

1

7

1

0

1

8

1

7

1

S

Slave Address

ACK

Register Address

ACK

S

Slave Address

ACK

8

1

8

1

8

1

NACK

Data from Address

ACK Data from Address + 1 ACK

······

Data from Address + N

P

图7-14. Multi-byte Read

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7.6 Register Maps

表 7-3 lists the memory-mapped registers for the device registers. All register offset addresses not listed in 表

7-3 should be considered as reserved locations, and the register contents should not be modified.

表7-3. Device Registers

Address

0h, 1h

2h

Acronym

REF

Register Name

Reference Voltage

Current Limit Setting

Slew Rate

Section

Go

IOUT_LIMIT

VOUT_SR

VOUT_FS

CDC

Go

3h

Go

4h

Feedback Selection

Cable Compensation

Mode Control

Go

5h

Go

6h

MODE

Go

7h

STATUS

Operating Status

Go

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7.6.1 REF Register (Address = 0h, 1h) [reset = 11010010h, 00000000h]

REF is shown in 图7-15 and 图7-16 described in 表7-4.

Return to Summary Table.

REF sets the internal reference voltage of the TPS55288. The 01h register is the high byte and the 00h register

is the low byte. One LSB of register 00h stands for 1.129 mV of the internal reference voltage. The default

register value is 00000000 11010010b of 282 mV. When the register value is 00000000 00000000b, the

reference voltage is 45 mV. When the register value is 00000011 11000000b, the reference voltage is 1.129 V.

The output voltage of the TPS55288 also depends on the output feedback ratio, which is either set in register

04h or set by an external resistor divider.

Writing register 01h enables the TPS55288 to load the 01h and 00h data into the internal 10-bit DAC. Writing the

register 00h does not impact the internal reference voltage.

图7-15. REF_LSB

7

6

5

4

3

2

1

0

VREF

R/W-11010010b

图7-16. REF_MSB

15

14

13

12

11

10

9

8

Reserved

VREF

R/W-000000b

R/W-00b

表7-4. REF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15-10

9-0

Reserved

VREF

000000b

Reserved

00 11010010b Sets the internal reference voltage

00 00000000b = 45-mV reference voltage

00 00000001b = 46.129-mV reference voltage

00 00000010b = 47.258-mV reference voltage

...... = ......

00 11010010b = 282-mV reference voltage (Default)

...... = ......

01 10011010b = 508-mV reference voltage

...... = ......

10 11000110b = 846-mV reference voltage

...... = ......

11 11000000b = 1129-mV reference voltage

...... = ......

11 11111111b = 1200-mV reference voltage

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7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]

IOUT_LIMIT is shown in 图7-17 and described in 表7-5.

Return to Summary Table.

IOUT_LIMIT sets the current limit target voltage between the ISP pin and the ISN pin. The default value in the

current limit register is 11100100b standing for 50 mV. 1 LSB stands for 0.5 mV. The bit7 enables the current limit

or disables the current limit.

图7-17. IOUT_LIMIT Register

7

6

5

4

3

2

1

0

Current_Limit_EN

R/W-1b

Current_Limit_Setting

R/W-1100100b

表7-5. IOUT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Current_Limit_EN

R/W

1b

Enable or disable current limit.

0b = Current limit disabled

1b = Current limit enabled (Default)

6-0

Current_Limit_Setting

R/W

1100100b

Sets the current limit target voltage between the ISP pin and the ISN

0000000b = V_ISP-V_ISN= 0 (mV)

0000001b = V_ISP-V_ISN= 0.5 (mV)

0000010b = V_ISP-V_ISN= 1 (mV)

0000011b = V_ISP-V_ISN= 1.5 (mV)

0000100b = V_ISP-V_ISN= 2.0 (mV)

1100100b = V_ISP-V_ISN= 50.0 (mV) (Default)

1111111b = V_ISP-V_ISN= 63.5 (mV)

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7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]

VOUT_SR is shown in 图7-18 and described in 表7-6.

Return to Summary Table.

Register 03h sets the slew rate of the output voltage change and the response delay time after the output

current exceeds the setting output current limit.

The OCP_DELAY [1:0] bits set the response time of the TPS55288 when the output overcurrent limit is hit. This

allows the TPS55288 to output high current in a relative short duration time. The default setting is 128 µs so that

the TPS55288 immediately limits the output current.

The SR [1:0] bits set 1.25mV/μs, 2.5mV/μs, 5mV/μs, and 10mV/μs slew rate for output voltage change.

图7-18. VOUT_SR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

OCP_DELAY

R/W-00b

RESERVED

R/W-00b

SR

R/W-01b

表7-6. VOUT_SR Register Field Descriptions

Bit

7-6

5-4

Field

Type

R/W

Reset

Description

RESERVED

OCP_DELAY

00b

Reserved

00b

Sets the response time of the device when the output overcurrent

limit is reached.

00b = 128 µs (Default)

01b = Delay 1.024 x 3 ms

10b = Delay 1.024 x 6 ms

11b = Delay 1.024 x 12 ms

3-2

1-0

RESERVED

SR

R/W

00b

01b

Reserved

Sets slew rate for output voltage change.

00b = 1.25 mV/µs output change slew rate

01b = 2.5 mV/µs output change slew rate (Default)

10b = 5 mV/µs output change slew rate

11b = 10 mV/µs output change slew rate

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7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]

VOUT_FS is shown in 图7-19 and described in 表7-7.

Return to Summary Table.

Register 04h sets the selection for the output feedback voltage, either by an internal resistor divider or external

resistor divider, and sets the internal feedback ratio when using internal feedback resistor divider.

图7-19. VOUT_FS Register

7

6

5

4

3

2

1

0

FB

RESERVED

R/W-00000b

INTFB

R/W-0b

R/W-11b

表7-7. VOUT_FS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

FB

R/W

0b

Output feedback voltage

0b = Use internal output voltage feedback. The FB/INT pin is the

indicator for output short circuit protection, overcurrent status, and

overvoltage status (Default).

1b = Use external output voltage feedback. The FB/INT pin is the

feedback input of the output voltage.

6-2

1-0

RESERVED

INTFB

R

00000b

11b

Reserved

R/W

Internal feedback ratio

00b = Set internal feedback ratio to 0.2256

01b = Set internal feedback ratio to 0.1128

10b = Set internal feedback ratio to 0.0752

11b = Set internal feedback ratio to 0.0564(Default)

表7-8. Output Voltage vs Internal Reference

INTFB1 INTFB0

REF=0000h

REF=000Dh

REF=0028h

REF=0078h

REF=03C0h

5 V

Output Voltage Step

0

1

0

1

0

1

0.8 V

5 mV

10 mV

15 mV

20 mV

0.8 V

10 V

0.8 V

15 V

0.8 V

20 V

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7.6.5 CDC Register (Address = 5h) [reset = 11100000h]

CDC is shown in 图7-20 and described in 表7-9.

Return to Summary Table.

Register 05h sets masks for SC bit, OCP bit, and OVP bit in register 07h. In addition, register 05h sets the

voltage rise added to the setting output voltage with respect to the sensed differential voltage between the ISP

pin and the ISN pin.

The OCP_MASK must be 0 when the OE bit or the Current_Limit_EN bit is changed from 0 to 1. After the OE bit

and the Current_Limit_EN bit are set, set the OCP_MASK to 1 to enable the OCP fault indication output.

图7-20. CDC Register

7

6

5

4

3

2

1

0

SC_MASK

R/W-1b

OCP_MASK

R/W-1b

OVP_MASK

R/W-1b

RESERVED

R/W-0b

CDC_OPTION

R/W-0b

CDC

R/W-000b

表7-9. CDC Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

SC_MASK

R/W

1b

Short circuit mask

0b = Disabled SC indication

1b = Enable SC indication (Default)

OCP_MASK

OVP_MASK

R/W

1b

Overcurrent mask

0b = Disabled OCP indication

1b = Enable OCP indication (Default)

Overvoltage mask

0b = Disabled OVP indication

1b = Enable OVP indication (Default)

4

3

RESERVED

R/W

0b

Reserved

CDC_OPTION

Select the cable voltage droop compensation approach.

0b = Internal CDC compensation by the register 05H (Default)

1b = External CDC compensation by a resistor at the CDC pin

2-0

CDC

R/W

000b

Compensation for voltage droop over the cable

000b = 0-V output voltage rise with 50 mV at V_ISP- V_ISN(Default)

001b = 0.1-V output voltage rise with 50 mV at V_ISP- V_ISN

010b = 0.2-V output voltage rise with 50 mV at V_ISP- V_ISN

011b = 0.3-V output voltage rise with 50 mV at V_ISP- V_ISN

100b = 0.4-V output voltage rise with 50 mV at V_ISP- V_ISN

101b = 0.5-V output voltage rise with 50 mV at V_ISP- V_ISN

110b = 0.6-V output voltage rise with 50 mV at V_ISP- V_ISN

111b = 0.7-V output voltage rise with 50 mV at V_ISP- V_ISN

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7.6.6 MODE Register (Address = 6h) [reset = 00100000h]

MODE is shown in 图7-21 and described in 表7-10.

Return to Summary Table.

MODE controls the operating mode of the TPS55288.

图7-21. MODE Register

7

6

5

4

3

2

1

0

OE

FSWDBL

R/W-0b

HICCUP

R/W-1b

DISCHG

R/W-0b

VCC

I2CADD

R/W-0b

PFM

MODE

R/W-0b

表7-10. MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OE

R/W

0b

Output enable

0b = Output disabled (Default)

1b = Output enable

6

FSWDBL

R/W

0b

Switching frequency doubling in buck-boost mode

TI does not recommend using double frequency function at switching

frequency above 1.6 MHz.

0b = Keep the switching frequency unchanged during buck-boost

mode (Default)

1b = Double the switching frequency during buck-boost mode.

5

4

HICCUP

DISCHG

R/W

1b

0b

Hiccup mode

0b = Disable the hiccup during output short circuit protection.

1b = Enable the hiccup during output short circuit protection (Default)

Output discharge

0b = Disabled VOUT discharge when the device is in shutdown

mode (Default)

1b = Enable VOUT discharge. VOUT is discharged to ground by an

internal 100-mA current sink

3

2

1

0

VCC

R/W

0b

V_CCoption

0b = Select internal LDO for V_CC(Default)

1b = Select external 5-V power supply for V_CC

I2CADD

PFM

I²C address

0b = Set I²C slave address to 74h (Default)

1b = Set I²C slave address to 75h

Select operating mode at light load condition

0b = PFM operating mode at light load condition (Default)

1b = FPWM operating mode at light load condition

MODE

Mode control approach

0b = Set VCC, I2CADD, and PFM controlled by external resistor

(Default)

1b = Set VCC, I2CADD, and PFM controlled by internal register

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7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]

STATUS is shown in 图7-22 and described in 表7-11.

Return to Summary Table.

The STATUS register stores the operating status of the TPS55288. When any of the SCP bit, the OCP bit, or the

OVP bit are set, and the corresponding mask bit in register 05h is set as well, the FB/INT pin outputs low logic

̅

level to indicate the situation. Reading register 07h clears the SCP bit, OCP bit, and OVP bit. After the SCP bit,

OCP bit, or OVP bit is set, it does not reset until the register is read. If the situation still exists, the corresponding

bit is set again.

图7-22. STATUS Register

7

6

5

4

3

2

1

0

SCP

R-0b

OCP

R-0b

OVP

R-0b

Reserved

R/W-0b

Reserved

R/W-0b

Reserved

R/W-0b

STATUS

R-11b

表7-11. STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SCP

R

0b

Short circuit protection

0b = No short circuit

1b = Short circuit happens. Does not reset until it is read.

6

5

OCP

OVP

R

0b

Overcurrent protection

0b = No output overcurrent

1b = Output current hits the current limit sensed at the ISP and the

ISN pin. Does not reset until it is read.

Overvoltage protection

0b = No OVP

1b = Output voltage exceeds the OVP threshold. Does not reset until

it is read.

4

RESERVED

STATUS

R

0b

Reserved

3

0b

2

0b

1-0

11b

Operating status

00b = Boost

01b = Buck

10b = Buck-Boost

11b = Reserved

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7.6.8 Register Summary

The 表7-12 summarizes the default settings of the registers in the TPS55288.

表7-12. Default Settings of Registers

Register Address

Register Name

VREF_LSB

VREF_MSB

IOUT_LIMIT

VOUT_SR

VOUT_FS

CDC

R/W

R

Default Values

11010010

00000000

11100100

00000001

00000011

11100000

00100000

00000011

00h

01h

02h

03h

04h

05h

06h

07h

MODE

STATUS

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The TPS55288 can operate over a wide range of 2.7-V to 36-V input voltage and output 0.8 V to 22 V. It can

transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage and the

setting output voltage. The TPS55288 operates in buck mode when the input voltage is greater than the output

voltage and in boost mode when the input voltage is less than the output voltage. When the input voltage is

close to the output voltage, the TPS55288 operates in one-cycle buck and one-cycle boost mode alternately.

The switching frequency is set by an external resistor. To reduce the switching power loss in high power

conditions, it is recommended to set the switching frequency below 500 kHz. If a system requires higher

switching frequency above 500 kHz, it is recommended to set the lower switch current limit for better thermal

performance.

8.2 Typical Application

The TPS55288 provides a small size solution for USB PD power supply application with the input voltage

ranging from 9 V to 20 V.

L1

4.7µH

C5

C4

0.1µF

SW1

BOOT2

DR1H

VIN

DR1L BOOT1

SW2

VIN = 9V to 20V

VOUT = 5V to 20V

VOUT

R1

10mΩ

C1

C2

4 x 10µF

VCC

C3

4.7µF

4 x 22µF

PGND

AGND

ISP

SCL

SDA

ON

EN/UVLO

MODE

TPS55288

ISN

OFF

FB/INT

COMP

CDC

R6

20kΩ

DITH/SYNC

FSW

C6

R3

C7

R4

C8

0.01µF

100kΩ

ILIM

R5

R2

49.9kΩ

20kΩ

图8-1. USB PD Power Supply With 9-V to 20-V Input Voltage

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8.2.1 Design Requirements

The design parameters are listed in 表8-1:

表8-1. Design Parameters

PARAMETERS

Input voltage

VALUES

9 V to 20 V

5 V to 20 V

5 A

Output voltage

Output current limit

Output voltage ripple

Operating mode at light load

±50 mV

PFM

8.2.2 USB PD Power Supply Detailed Design Procedure

8.2.2.1 Switching Frequency

The switching frequency of the TPS55288 is set by a resistor at the FSW pin. Use Equation 3 to calculate the

resistance for the desired frequency. To reduce the switching power loss with such a high current application, a

1% standard resistor of 49.9 kΩ is selected for 400-kHz switching frequency for this application.

8.2.2.2 Output Voltage Setting

The TPS55288 has I²C interface to set the internal reference voltage. A microcontroller can easily set the

desired output voltage by writing the proper data into the reference voltage registers through I²C bus.

8.2.2.3 Inductor Selection

Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the

inductor is the most important component in power regulator design. There are three important inductor

specifications: inductance, saturation current, and DC resistance.

The TPS55288 is designed to work with inductor values between 1 µH and 10 µH. The inductor selection is

based on consideration of both buck and boost modes of operation.

For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum

inductor current at the maximum input voltage. In CCM, Equation 9 shows the relationship between the

inductance and the inductor ripple current.

k

o

V_IN(MAX)-V_OUT×V_OUT

L=

∆I_L(P-P)×f_SW×V_{IN MAX}

:

;

(9)

where

• V_IN(MAX)is the maximum input voltage

• V_OUTis the output voltage

• ΔI_L(P-P)is the peak to peak ripple current of the inductor

• f_SWis the switching frequency

For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals half of the

maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller

inductance gets larger inductor current ripple.

For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum

inductor current at the maximum output voltage. In CCM, Equation 10 shows the relationship between the

inductance and the inductor ripple current.

k

V_IN× V_OUT(MAX)-V_IN

o

L=

∆I_L(P-P)×f_SW×V_OUT(MAX)

(10)

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where

• V_INis the input voltage

• V_OUT(MAX)is the maximum output voltage

• ΔI_L(P-P)is the peak to peak ripple current of the inductor

• f_SWis the switching frequency

For a certain inductor, the inductor ripple current achieves maximum value when V_INequals to the half of the

maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller

inductance gets larger inductor current ripple.

For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor

current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average

inductor current in boost mode.

In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can

be calculated with Equation 11.

V_OUT×I_OUT

I_L(DC)

=

V_IN×ꢀ

(11)

where

• V_OUTis the output voltage

• I_OUTis the output current

• V_INis the input voltage

• ηis the power conversion efficiency

For a given maximum output current of the buck-boost converter TPS55288, the maximum inductor DC current

happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the

TPS55288 higher than the calculated maximum inductor DC current to make sure the TPS55288 has the desired

output current capability.

In boost mode, the inductor ripple current is calculated with Equation 12.

:

V_IN× V_OUT-V_IN

;

∆I_L(P-P)

=

L×f_SW×V_OUT

(12)

where

• ΔI_L(P-P)is the inductor ripple current

• L is the inductor value

• f_SWis the switching frequency

• V_OUTis the output voltage

• V_INis the input voltage

Therefore, the inductor peak current is calculated with Equation 13.

∆I_L(P-P)

I_L(P)= I_L(DC)

+

2

(13)

Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor

current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic

hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The

selected inductor must have higher saturation current than the calculated peak current.

The conversion efficiency is dependent on the resistance of its current path. The switching loss associated with

the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the inductor

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DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss. 表 8-2

lists recommended inductors for the TPS55288. In this application example, the Coilcraft inductor XAL1010-472

is selected for its small size, high saturation current, and small DCR.

表8-2. Recommended Inductors

DCR

(MAXIMUM)

(mΩ)

SATURATION

CURRENT / HEAT

RATING CURRENT (A)

PART NUMBER

L (µH)

SIZE (L x W x H mm)

⁽¹⁾VENDOR

XAL1010-472ME

IHLP5050EZER4R7

125CDMCCDS-4R7MC

4.7

10

10.1

10

25.4/17.5

17.8/15.3

22/14

11.3 × 10 × 10

13.5 × 12.9 × 5

13.5 × 12.6 × 5

Coilcraft

Vishay

Sumida

(1) See the Third-party Products disclaimer.

8.2.2.4 Input Capacitor

In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given

by Equation 14.

:

V_OUT× V_IN-V_OUT

;

¨

I_{CIN RMS}_;= I

:

×

OUT

V_IN×V_IN

(14)

where

• I_CIN(RMS)is the RMS current through the input capacitor

• I_OUTis the output current

The maximum RMS current occurs at the output voltage is half of the input voltage, which gives I_CIN(RMS)= I_OUT

/

2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20 µF

effective capacitance is a good starting point for this application.

8.2.2.5 Output Capacitor

In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is

given by Equation 15, where the minimum input voltage and the maximum output voltage correspond to the

maximum capacitor current.

V_OUT

¨

I_{COUT RMS}_;= I

:

×

-1

OUT

V_IN

(15)

where

• I_COUT(RMS)is the RMS current through the output capacitor

• I_OUTis the output current

In this example, the maximum output ripple RMS current is 5.5 A.

The ESR of the output capacitor causes an output voltage ripple given by Equation 16 in boost mode.

I_OUT×V_OUT

V_RIPPLE(ESR)

=

×R_COUT

V_IN

(16)

where

• R_COUTis the ESR of the output capacitance

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The capacitance also causes a capacitive output voltage ripple given by Equation 17 in boost mode. When input

voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest

output voltage ripple caused by the capacitance.

V_IN

V_OUT

l

I_OUT× 1-

p

V_RIPPLE(CAP)

=

C_OUT×f_SW

(17)

Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR,

high ripple current, and small output voltage ripple. From the required output voltage ripple, use Equation 16 and

Equation 17 to calculate the minimum required effective capacitance of the C_OUT

.

8.2.2.6 Output Current Limit

The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins along

with setting a limit voltage between the ISP pin and the ISN pin through register 02h. The maximum value of the

limit voltage between the ISP and ISN pins is 63.5 mV. The default limit voltage is 50 mV. The current sense

resistor between the ISP and ISN pins should be selected to ensure that the output current limit is set high

enough for output. The output current limit setting resistor is given by Equation 18.

V_SNS

R_SNS

=

I_{OUT_LIMIT}

(18)

where

• V_SNSis the current limit setting voltage between the ISP and ISN pins

• I_{OUT_LIMIT}is the desired output current limit

Because the power dissipation is large, make sure the current sense resistor has enough power dissipation

capability with large package.

8.2.2.7 Loop Stability

The TPS55288 uses average current control scheme. The inner current loop uses internal compensation and

requires the inductor value must be larger than 1.2/f_SW. The outer voltage loop requires an external

compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation

network comprised of resistor and ceramic capacitors is connected to the COMP pin.

The TPS55288 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require

loop compensations. The restrictive one of both compensations is selected as the overall compensation from a

loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost

mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).

The power stage in boost mode can be modeled by Equation 19.

s

l

p l

× 1-

p

1+

:

R_LOAD× 1-D

;

2N×f_ESRZ

2N×f_RHPZ

G_PS(s) =

×

s

2×R_SENSE

1+

2N×f_P

(19)

where

• R_LOADis the output load resistance

• D is the switching duty cycle in boost mode

• R_SENSEis the equivalent internal current sense resistor, which is 0.055 Ω

The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use 方程式

20 to Equation 22 to calculate them.

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2

f_P=

2N×R_LOAD×C_OUT

(20)

(21)

(22)

1

f_ESRZ

=

2N×R_COUT×C_OUT

2

:

R_LOAD× 1-D

;

f_RHPZ

=

2N×L

The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the

control portion of the loop. The transfer function of the control portion is shown by Equation 23.

s

l

p

1+

G_EA×R_EA×V_REF

V_OUT

2N×f_COMZ

G_C(s) =

×

s

l

p

l

× 1 +

p

1+

2N×f_COMP1

2N×f_COMP2

(23)

where

• G_EAis the transconductance of the error amplifier

• R_EAis the output resistance of the error amplifier

• V_REFis the reference voltage input to the error amplifier

• V_OUTis the output voltage

• f_COMP1and f_COMP2are the pole’s frequency of the compensation network

• f_COMZis the zero’s frequency of the compensation network

The total open-loop gain is the product of G_PS(s) and G_C(s). The next step is to choose the loop crossover

frequency, f_C, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain

stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain

cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, f_SWor 1/5 of

the RHPZ frequency, f_RHPZ

.

Then, set the value of R_C, C_Cand C_Pby Equation 24 to Equation 26.

2N×V_OUT×R

×C_OUT×f_C

SENSE

R_C=

: ;

1-D ×V_REF×G_EA

(24)

where

• f_Cis the selected crossover frequency

R_LOAD×C_OUT

C_C=

2×R_C

(25)

(26)

R_COUT×C_OUT

C_P=

R_C

If the calculated C_Pis less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output

voltage ringing during the line and load transient.

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8.2.3 Application Curves

图8-2. Switching Waveforms in V_IN= 12 V, V_OUT= 5

图8-3. Switching Waveforms in V_IN= 12 V, V_OUT= 5

V, I_O= 5 A, FPWM

V, I_O= 0 A, PFM

图8-4. Switching Waveforms in V_IN= 12 V, V_OUT

=

图8-5. Switching Waveforms in V_IN= 12 V, V_OUT

=

12 V, I_O= 5 A, FPWM

12 V, I_O= 0 A, PFM

图8-7. Switching Waveforms in V_IN= 12 V, V_OUT

=

图8-6. Switching Waveforms in V_IN= 12 V, V_OUT

=

20 V, I_O= 0 A, PFM

20 V, I_O= 5 A, FPWM

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图8-9. Shutdown Waveforms in V_IN= 12 V, V_OUT= 5

图8-8. Start-up Waveforms in V_IN= 12 V, V_OUT= 5

V, I_OUT= 5 A, FPWM

V, I_O= 5 A, FPWM

图8-10. Line Transient Waveforms in V_IN= 9 V to

20 V, V_OUT= 12 V, I_O= 5 A with 200-μs Slew Rate,

FPWM

图8-11. Load Transient Waveforms in V_IN= 12 V,

V

_OUT= 5 V, I_O= 2.5 A to 5 A with 20-μs Slew Rate,

FPWM

图8-12. 3-A Output Current Limit Waveforms in V_IN= 12 V, V_OUT= 5 V, R_LOAD= 1.2 Ω, FPWM

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V to 36 V. This input supply

must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk

capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum

electrolytic capacitor with a value of 100 μF.

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10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents,

layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and

noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation of

high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential.

Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane

under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN

pin and the PGND to reduce the input supply current ripple.

The most critical current path for buck converter portion is from the switching FET at the buck side, through the

rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET.

This high current path contains nanosecond rise time and fall time, and should be kept as short as possible.

Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND

terminal of the rectifier FET.

The most critical current path for boost converter portion is from the switching FET at the boost side, through the

rectifier FET at boost side, then the output capacitors, and back to ground of the switching FET. This high current

path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output

capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the

SW2 pin and the VOUT pin.

The traces from the output current sensing resistor to the ISP pin and the ISN pin must be in parallel and close

to each other to avoid noise coupling.

The PGND plane and the AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the

noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal

control circuit.

To get good thermal performance, it is recommended to use thermal vias beneath the TPS55288 connecting the

PGND pin to the PGND plane, and the VOUT pin to a large VOUT area separately.

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10.2 Layout Example

trace on bottom layer

AGND plane on an inner layer

The first inner layer is the PGND plane

VOUT

AGND plane connects to PGND plane at the terminal of the capacitor at the VCC pin

AGND

PGND

18 17 16 15 14 13

19

12

11

20

26

25

24

21

22

10

9

23

1

8

VIN

2

3

4

5

6

7

NMOSFET

PGND

AGND

图10-1. Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

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11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

46

Submit Document Feedback

Product Folder Links: TPS55288

GENERIC PACKAGE VIEW

RPM 26

3.5 x 4, 0.5 mm pitch

VQFN-HR - 1 mm max height

VERY THIN QUAD FLATPACK-HotRod

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226451/A

www.ti.com

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

A

4.1

3.9

B

3.6

3.4

PIN 1 INDEX AREA

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5X 0.25±0.05

2X 0.35±0.05

0.1

C A B

0.1

C A B

0.05

C

0.05

C

5X

6X 0.4±0.1

0.425±0.1

2X (0.150 X 0.150)

TYP

(0.1) TYP

6X 0.525±0.1

7

2X 1.4875

13

6X 0.25±0.05

0.1

C A B

2X 0.225±0.05

2X 1

0.05

C

2X 0.5

PKG

6X 0.25±0.05

3X

0.1

C A B

1.425±0.1

24

25

26

0.05

C

2X 0.225±0.05

2X 1.4875

19

1

2X (0.175 X 0.150)

TYP

2X 0.475±0.1

PKG

2X 0.25±0.05

2X 0.4±0.05

0.1

C

A

B

3X 0.375±0.05

0.05

C

0.1

C A B

0.05

C

4224618/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

3X (0.375)

PKG

2X (0.4)

1

2X (0.25)

2X (0.675)

19

2X (1.4875)

2X (0.225)

(R0.05) TYP

(1.6125)

(1.65)

3X (1.425)

PKG

24

25

26

2X (0.5)

2X (1)

(1.6375)

6X (0.25)

13

2X (1.4875)

2X (0.225)

7

6X (0.725)

6X (0.6)

5X (0.625)

5X (0.25)

2X (0.35)

(3.675)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.05 MAX

ALL AROUND

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4224618/A 10/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

3X (0.375)

PKG

2X (0.4)

1

2X (0.25)

2X (0.675)

19

2X (1.4875)

2X (0.225)

(R0.05) TYP

(1.6125)

(1.65)

3X (1.425)

PKG

24

25

26

2X (0.5)

2X (1)

(1.6375)

6X (0.25)

13

2X (1.4875)

2X (0.225)

7

6X (0.725)

6X (0.6)

5X (0.625)

5X (0.25)

2X (0.35)

(3.675)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 20X

4224618/A 10/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS55288RPMR
厂家：	TEXAS INSTRUMENTS
描述：	具有 PPS 控制的 36V、16A 降压/升压转换器 \| RPM \| 26 \| -40 to 150 升压转换器
文件：	总54页 (文件大小：3053K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS55288RPMR [TI]

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