TPS560200-Q1 [TI]
具有高级 Eco-Mode™ 的 4.5V 至 17V 输入、500mA 同步降压转换器;
| 型号： | TPS560200-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高级 Eco-Mode™ 的 4.5V 至 17V 输入、500mA 同步降压转换器 转换器 |
| 文件： | 总23页 (文件大小：1367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
具有高级 Eco-mode™ 的 TPS560200-Q1 4.5V 至 17V 输入、500mA 同
步降压转换器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
TPS560200-Q1 是一款集成 MOSFET 的 17V、
500mA、低 Iq 自适应导通时间 D-CAP2 模式同步单片
降压转换器，采用简单易用的 8 引脚 MSOP 封装。
–
–
温度范围：等级 1，-40°C 至 125°C
人体模型 (HBM) 静电放电 (ESD) 分类等
级：H2
TPS560200-Q1 有助于系统设计人员通过具备成本效
益、所用组件较少并且待机电流较低的解决方案完成各
种终端设备的电源总线调节器集。器件主控制回路采用
D-CAP2 模式控制，无需外部补偿元件即可实现快速瞬
态响应。自适应导通时间控制支持器件在高负载条件下
的 PWM 模式与轻负载条件下的高级 Eco-mode 工作
模式之间实现无缝切换。
–
带电器件模型 (CDM) 静电放电 (ESD) 分类等
级：C4B
•
•
•
•
•
集成单片 0.95Ω 高侧和 0.33Ω 低侧 MOSFET
500mA 持续输出电流
输出电压范围：0.8V 至 6.5V
0.8V 基准电压，温度范围内的精度为 ±1.3%
高级自动跳跃 Eco-mode™用于在轻负载时实现高
效率
TPS560200-Q1 的专有电路还可使其适应低等效串联
电阻 (ESR) 输出电容（如导电性聚合物钽固体电解电
容 (POSCAP) 和导电性聚合物铝电解电容 (SP-
CAP)）以及超低 ESR 陶瓷电容。该器件由 4.5V 至
17V 范围内的输入电压供电。输出电压可在 0.8 V 至
6.5V 范围内进行编程。该器件还 具有 2ms 固定软启
动时间。该器件采用 8 引脚 MSOP 封装。
•
•
•
•
•
•
•
•
D-CAP2™模式启用快速瞬态响应
无需外部补偿
600kHz 开关频率
2ms 内部软启动
安全启动至预偏置 VOUT
热关断
-40°C 至 125°C 的工作结温范围
采用 8 引脚微型小外形尺寸封装 (MSOP)
器件信息(1)
器件型号
封装
VSSOP (8)
封装尺寸（标称值）
TPS560200-Q1
3.00mm x 3.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
电动汽车 (EV) 充电站
信息娱乐系统
简化原理图
VOUT
Lo
VIN
VIN
EN
PH
Cin
Co
R1
R2
VSENSE
GND
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCW4
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
8
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 器件和文档支持 ..................................................... 15
11.1 接收文档更新通知 ................................................. 15
11.2 社区资源................................................................ 15
11.3 商标....................................................................... 15
11.4 静电放电警告......................................................... 15
11.5 Glossary................................................................ 15
12 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (May 2016) to Revision B
Page
•
仅限编辑更新；无技术性更改 ................................................................................................................................................ 1
Changes from Original (April 2016) to Revision A
Page
•
器件状态从：预览更改为：生产 ............................................................................................................................................ 1
2
Copyright © 2016–2019, Texas Instruments Incorporated
TPS560200-Q1
www.ti.com.cn
ZHCSF66B –APRIL 2016–REVISED MAY 2019
5 Pin Configuration and Functions
DGK Package
8- Pin VSSOP
(Top View)
GND
PH
VIN
NC
5
8
7
6
1
2
3
4
EN
GND VSENSE NC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
1
I
—
I
Enable pin. Float to enable
Return for control circuitry and low-side power MOSFET
GND
VSENSE
NC
2, 8
3
Converter feedback input. Connect to output voltage with feedback resistor divider
No connection inside, can be connected to any node or can be floating
Supplies the control circuitry of the power converter
The switch node
4, 5
6
—
I
VIN
PH
7
O
Copyright © 2016–2019, Texas Instruments Incorporated
3
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–0.6
–2
MAX
19
UNIT
V
VIN
Input voltage
EN
7
V
VSENSE
3
V
PH
19
V
Output voltage
PH 10-ns transient
21
V
EN
PH
PH
±100
µA
A
Source current
Sink current
Current limit
Current limit
A
Operating junction temperature
Storage temperature, Tstg
–40
–65
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000, 2000 pins(1)
Charged-device model (CDM), per AEC Q100-011, all pins
V(ES Electrostatic
V
discharge
D)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
17
UNIT
V
VI
Input voltage range
4.5
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS560200-Q1
DGK (VSSOP)
8 Pins
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
184.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
76.8
106.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
14.4
ψJB
104.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016–2019, Texas Instruments Incorporated
TPS560200-Q1
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ZHCSF66B –APRIL 2016–REVISED MAY 2019
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
VIN Operating input voltage
VIN Internal UVLO wakeup
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
17
V
V
VIN Rising
4.35
4.15
3.7
4.5
VIN Internal UVLO shutdown
VIN Shutdown supply current
VIN Operating – non switching supply current
ENABLE (EN PIN)
VIN Fallling
3.9
2.0
35
V
EN = 0 V, VIN = 12 V
VSENSE = 850 mV, VIN = 12 V
9
µA
µA
60
95
Rising
1.16
1.13
2
1.29
V
V
Enable threshold
Falling
1.05
Internal Soft-Start
VSENSE ramps from 0 V to 0.8 V
ms
OUTPUT VOLTAGE
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 5
mA, Pulse-Skipping
0.796
0.792
0.804
0.800
0.812
0.808
V
V
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 100
mA, Continuous current mode
Voltage reference
VIN = 12 V, VOUT = 1.05 V, IOUT = 100 mA,
Continuous current mode
0.789
0.800
0.811
V
MOSFET
High-side switch resistance(1)
Low-side switch resistance(1)
CURRENT LIMIT
VIN = 12 V
VIN = 12 V
0.50
0.20
0.95
0.33
1.50
0.55
Ω
Ω
Low-side switch sourcing current limit
THERMAL SHUTDOWN
Thermal shutdown
LOUT = 10 µH, Valley current, VOUT = 1.05 V
570
670
795
mA
160
10
°C
°C
Thermal shutdown hysteresis
ON-TIME TIMER CONTROL
On time
VIN = 12 V
130
56
165
250
200
400
ns
ns
Minimum off time
25°C, VSENSE = 0.5 V
OUTPUT UNDERVOLTAGE PROTECTION
Output UVP threshold
Hiccup time
Falling
63
15
69 %VREF
ms
(1) Not production tested
版权 © 2016–2019, Texas Instruments Incorporated
5
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted).
100
80
60
40
20
0
6
5
4
3
2
1
0
EN = 0 V
œ50
0
50
100
150
œ50
0
50
100
150
C001
C002
TJ Junction Temperature (°C)
TJ Junction Temperature (°C)
图 1. Supply Current vs Junction Temperature
图 2. Shutdown Current vs Junction Temperature
40
30
20
10
0
700
675
650
625
600
575
550
525
500
VOUT=1.05V
IOUT = 500mA
VOUT=1.05V
VOUT=1.8V
VOUT=3.3V
-10
0
2
4
6
8
10
4
6
8
10
12
14
16
18
EN Input Voltage (V)
VIN - Input Voltage (V)
D000
D001
图 3. EN Input Current vs EN Input Voltage
图 4. Switching Frequency vs Input Voltage
0.806
0.804
0.802
0.800
0.798
0.796
0.794
800
700
600
500
400
300
200
100
0
IO = 100 mA
Vout=1.05
Vout=1.8
Vout=3.3
œ50
0
50
100
150
C006
TJ Junction Temperature (°C)
0
0.1
0.2
0.3
0.4
0.5
IOUT - Output Current (A)
D002
图 6. VSENSE Voltage vs Junction Temperature
版权 © 2016–2019, Texas Instruments Incorporated
图 5. Switching Frequency vs Output Current
6
TPS560200-Q1
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ZHCSF66B –APRIL 2016–REVISED MAY 2019
7 Detailed Description
7.1 Overview
The TPS560200-Q1 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel
MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the
output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use
of low-ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
VIN
VREF
HS
Drive
VSS
VSENSE
VREF
Soft
Start
SSDONE
START
EN
VIN
XCON
PH
UVLO
VREF
Control
Logic
VIN
LS
Drive
TON
One-Shot
PGND
GND
AGND
PH
Thermal
Shutdown
ZCD
ZCD
Bandgap
Reference
LS
OCP
VREF
VREF
PGND
BGOK
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS560200-Q1 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VOUT, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2 mode control.
版权 © 2016–2019, Texas Instruments Incorporated
7
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
Feature Description (接下页)
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS560200-Q1 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator.
The TPS560200-Q1 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output
voltage to set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and
proportional to the output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Advanced Auto-Skip Eco-Mode Control
The TPS560200-Q1 is designed with advanced auto-skip Eco-Mode to increase higher light-load efficiency. As
the output current decreases from heavy-load condition, the inductor current is also reduced. If the output current
is reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in 公式 1.
V -V
IN OUT
×V
)
OUT
(
1
IOUT(LL)
=
×
2×LOUT×fsw
V
IN
(1)
7.3.4 Soft-Start and Prebiased Soft-Start
The TPS560200-Q1 has an internal 2-ms soft-start. When the EN pin becomes high, internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS560200-Q1 contains a unique circuit to prevent current from being pulled from the output during start-up
if the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft-
start becomes greater than feedback voltage VVSENSE), the controller slowly activates synchronous rectification by
starting the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VOUT) starts and
ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to
normal mode operation.
7.3.5 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS560200-Q1
constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-
side on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is
incremented per each switching cycle and the converter maintains the low-side switch on until the measured
voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and
a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current
is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This protection is nonlatching. When the VSENSE voltage becomes lower than 63% of the target
voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts
after hiccup time.
When the overcurrent condition is removed, the output voltage returns to the regulated value.
8
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TPS560200-Q1
www.ti.com.cn
ZHCSF66B –APRIL 2016–REVISED MAY 2019
Feature Description (接下页)
7.3.6 Thermal Shutdown
TPS560200-Q1 monitors the temperature of itself. If the temperature exceeds the threshold value
(typically 160°C), the device is shut off. This is nonlatch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS560200-Q1 can operate in its normal switching modes. Normal continuous conduction mode (CCM) occurs
when the minimum switch current is above 0 A. In CCM, the TPS560200-Q1 operates at a quasi-fixed frequency
of 600 kHz.
7.4.2 Eco-Mode Operation
When the TPS560200-Q1 is in the normal CCM operating mode and the switch current falls to 0 A, the
TPS560200-Q1 begins operating in pulse-skipping Eco-Mode. Each switching cycle is followed by a period of
energy-saving sleep time. The sleep time ends when the VFB voltage falls below the Eco-Mode threshold
voltage. As the output current decreases the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS560200-Q1 is operating in either normal CCM or Eco-Mode, it may be placed in standby by
asserting the EN pin low.
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9
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS560200-Q1 is used as a step-down converter which converts a voltage of 4.5 V to 17 V to a lower
voltage. WEBENCH® software is available to aid in the design and analysis of circuits.
8.2 Typical Application
U1
TPS560200
L1 10µH
VIN 4.5-17V
VOUT 1.05V, 0.5 A
6
1
3
7
VIN
PH
C5
R1
C1
C2
C3
C4
open
6.19k
10µF
10µF
10µF
0.1µF
EN
R2
20.0k
2,8
VSENSE
GND
Copyright © 2016, Texas Instruments Incorporated
图 7. Typical Application Schematic
8.2.1 Design Requirements
For this design example, refer to the application parameters shown in 表 1.
表 1. Design Parameters
PARAMETER
Input voltage range
VALUES
4.5 V to 17 V
1.05 V
Output voltage
Output current
500 mA
Output voltage ripple
30 mV/pp
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using 公式 2 to calculate VOUT
.
To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VSENSE input current are more noticeable.
R1´0.8 V
R2 =
VOUT -0.8V
(2)
8.2.2.2 Output Filter Selection
The output filter used with the TPS560200-Q1 is an LC circuit. This LC filter has double pole at:
1
F
P
=
2p L
x C
OUT
OUT
(3)
10
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TPS560200-Q1
www.ti.com.cn
ZHCSF66B –APRIL 2016–REVISED MAY 2019
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS560200-Q1. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of 公式 3 is located below the high frequency zero but close enough that the phase boost provided by the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in 表 2.
表 2. Recommended Component Values
L1
(µH)
Output Voltage
(V)
R1
(kΩ)
R2
(kΩ)
C5
(pF)
C3 + C4
(µF)
MIN
TYP
10
10
10
10
10
10
10
10
MAX
1.0
1.05
1.2
1.5
1.8
2.5
3.3
5.0
4.99
6.19
10.0
17.4
24.9
42.2
61.9
105
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
10 + 10
10 + 10
10 + 10
10 + 10
10 + 10
10 + 10
10 + 10
10 + 10
optional
optional
optional
optional
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feed-forward capacitor (C5) in parallel
with R1. The feed-forward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using 公式 4, 公式 5, and
公式 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current. Use 600 kHz for fSW
.
Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of 公式 5 and the RMS current
of 公式 6.
V
- V
V
IN(max)
OUT
OUT
I
=
x
LPP
V
L
x
fsw
IN(max)
OUT
(4)
(5)
ILPP
I
= I
OUT
+
LPEAK
2
1
2
2
I
=
I
+
I
LOUT(RMS)
OUT
LPP
12
(6)
For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The
inductor used is a Würth 744777910 with a peak current rating of 2.6 A and an RMS current rating of 2 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS560200-Q1 is intended for
use with ceramic or other low-ESR capacitors. The recommended values are given in 表 2. Use 公式 7 to
determine the required RMS current rating for the output capacitor.
V
x (V - V
)
OUT
IN
OUT
I
=
COUT(RMS)
12 x V x L
x fsw
IN
OUT
(7)
For this design two MuRata GRM32DR61E106KA12L 10-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.047 A and each output capacitor is rated for 3 A.
8.2.2.3 Input Capacitor Selection
The TPS560200-Q1 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF
capacitor (C2) from pin 6 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating must be greater than the maximum input voltage.
版权 © 2016–2019, Texas Instruments Incorporated
11
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
8.2.3 Application Curves
VIN = 12 V, VOUT = 1.05 V, TA = 25°C (unless otherwise noted).
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
VIN=5V
VIN=12V
VIN=5V
VIN=12V
10
0
0
100
200
300
400
500
1
10
100
1000
Output Current (mA)
Output Current (mA)
D003
D004
图 8. Efficiency
图 9. Light-Load Efficiency
1.1025
1.092
1.1025
1.092
1.0815
1.071
1.0815
1.071
1.0605
1.05
1.0605
1.05
1.0395
1.029
1.0395
1.029
1.0185
1.008
1.0185
1.008
VIN=5V
VIN=12V
IOUT=0.25A
0.9975
0.9975
0
100
200
300
400
500
4
6
8
10
12
14
16
18
Output Current (mA)
Input Voltage (V)
D005
D013
图 10. Load Regulation
图 11. Line Regulation
60
180
800
700
600
500
400
300
200
100
0
40
20
120
60
VOUT (ac coupled)
0
0
-20
-40
-60
-60
-120
IOUT
Gain
Phase
Time (10Ps/div)
-180
1000000
D007
10 20 50 100
1000
Frequency (Hz)
10000
100000
图 13. Transient Response, 25% to 75% Load Step
D006
图 12. Loop Response, IOUT = 0.25 A
12
版权 © 2016–2019, Texas Instruments Incorporated
TPS560200-Q1
www.ti.com.cn
ZHCSF66B –APRIL 2016–REVISED MAY 2019
800
700
600
500
400
300
200
100
0
10.0
5.0
0
VOUT (ac coupled)
VEN
-5.0
1.5
1.0
0.5
0
VOUT
IOUT
-0.5
Time (10Ps/div)
Time (2ms/div)
D008
D009
图 14. Transient Response, 2% to 50% Load Step
图 15. Start-Up Relative to EN
VOUT (ac coupled)
VOUT (ac coupled)
VPH
VPH
Time (1ms/div)
Time (4ms/div)
D010
D011
图 16. Output Ripple, IOUT = 500 mA
图 17. Output Ripple, IOUT = 30 mA
VOUT (ac coupled)
VPH
Time (2ms/div)
D012
图 18. Output Ripple, IOUT = 0 mA
版权 © 2016–2019, Texas Instruments Incorporated
13
TPS560200-Q1
ZHCSF66B –APRIL 2016–REVISED MAY 2019
www.ti.com.cn
9 Power Supply Recommendations
The TPS560200-Q1 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck
converters require the input voltage to be higher than the output voltage for proper operation. The maximum
recommended operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO /
0.75.
10 Layout
10.1 Layout Guidelines
The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Take care to minimize the
loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical
recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is
closest to the VIN and GND pins of the device. An additional high-frequency bypass capacitor may be added.
See for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. The
PH pin should be routed to a small copper area directly adjacent to the pin. Make the circulating loop from PH to
the output inductor, output capacitors and back to GND as tight as possible while preserving adequate etch width
to reduce conduction losses in the copper. Use vias adjacent to the IC to tie top-side ground copper plane to the
internal or bottom layer ground planes. The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate layout schemes; however, this layout
produced good results and is intended as a guideline.
10.2 Layout Example
OUTPUT
GND
FILTER
CAPACITOR
TO ENABLE
OUTPUT
EN
GND
GND
PH
CONTROL
INDUCTOR
VOUT
VSENSE
NC
VIN
NC
VIN
VIN
HIGH FREQENCY
BYPASS
FEEDBACK
RESISTORS
CAPACITOR
OPTIONAL
FEED FORWARD
CAPACITOR
VIN
INPUT
BYPASS
CAPACITOR
VIA to Ground Plane
图 19. Layout Schematic
14
版权 © 2016–2019, Texas Instruments Incorporated
TPS560200-Q1
www.ti.com.cn
ZHCSF66B –APRIL 2016–REVISED MAY 2019
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
Eco-mode, D-CAP2, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
15
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS560200QDGKRQ1
TPS560200QDGKTQ1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
ZDNK
ZDNK
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS560200QDGKRQ1 VSSOP
TPS560200QDGKTQ1 VSSOP
DGK
DGK
8
8
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS560200QDGKRQ1
TPS560200QDGKTQ1
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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