TPS560430-Q1 [TI]

通过汽车级认证的 SIMPLE SWITCHER® 4V 至 36V、600mA 同步降压转换器;


型号：	TPS560430-Q1
厂家：	TEXAS INSTRUMENTS
描述：	通过汽车级认证的 SIMPLE SWITCHER® 4V 至 36V、600mA 同步降压转换器转换器
文件：	总33页 (文件大小：1352K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS560430-Q1

ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

TPS560430-Q1 SIMPLE SWITCHER^®4V 至 36V、600mA 同步降压转换

器

1 特性

2 应用

•

符合汽车类应用要求

•

摄像头

符合 AEC-Q100 标准

- 温度等级 1：–40°C 至 125°C 环境工作温度范围

- ESD HBM 分类等级 2

车载充电器

汽车音响主机

USB 充电器

通用宽输入电压电源

- ESD CDM 分类等级 C5

•

专用于条件严苛的汽车类应用

–

输入电压范围：4V 至 36V

600mA 持续输出电流

最短打开时间：60ns

2.1MHz 固定频率

3 说明

TPS560430-Q1 是一款简单易用的宽 V_IN同步降压转

换器，能够驱动高达 600mA 的负载电流。该器件具有

4V 至 36V 的宽输入范围，适用于汽车应用，可从非

稳压源进行电源调节。

98% 最大占空比

支持带预偏置输出的启动

具有断续模式的短路保护

室温下 ±0.5% 容差电压基准

精密使能端

TPS560430-Q1 以 2.1MHz 的开关频率运行，支持使

用相对较小的电感器，以实现经优化的解决方案尺寸。

它具有 Eco-mode 版本，可在轻负载时实现高效率；

还具有 FPWM 版本，可在整个负载范围内实现恒定频

率和小输出电压纹波。在内部实现了软启动和补偿电

路，从而最大限度地减少了器件所用的外部组件。

•

解决方案小巧且易于使用

–

集成同步整流

内置补偿功能，便于使用

SOT-23-6 封装

该器件具有内置的保护功能，例如逐周期电流限制、

间断模式短路保护以及在出现过多功率损耗时执行的热

关断功能。TPS560430-Q1 采用 SOT-23-6 封装。

•

采用引脚对引脚兼容封装，具有两种模式

–

PFM 和强制 PWM (FPWM) 选项

使用 TPS560430-Q1 并借助 WEBENCH^®电源设

计器创建定制设计方案

器件信息 ⁽¹⁾

器件型号

封装

封装尺寸（标称值）

TPS560430-Q1

SOT-23-6

2.90mm × 1.60mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

效率与输出电流间的关系

V_OUT= 5V，2100kHz，PFM

简化原理图

V_INup to 36 V

100

VIN

C_IN

C_BOOT

V_OUT

R_FBT

VIN=8V

VIN=12V

VIN=24V

VIN=36V

GND

C_OUT

R_FBB

0.001

0.01

0.1

I_OUT(A)

D001

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDF5

TPS560430-Q1

ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

www.ti.com.cn

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements................................................ 6

7.7 Switching Characteristics.......................................... 6

7.8 Typical Characteristics.............................................. 7

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ......................................... 9

10 Power Supply Recommendations ..................... 22

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................. 22

11.2 Layout Example .................................................... 23

12 器件和文档支持 ..................................................... 24

12.1 器件支持................................................................ 24

12.2 文档支持................................................................ 24

12.3 接收文档更新通知 ................................................. 24

12.4 社区资源................................................................ 24

12.5 商标....................................................................... 24

12.6 静电放电警告......................................................... 24

12.7 Glossary................................................................ 25

13 机械、封装和可订购信息....................................... 25

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (January 2019) to Revision A

Page

•

已更改将营销状态从“预告信息”更改成了“生产数据”。........................................................................................................... 1

TPS560430-Q1

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ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

5 Device Comparison Table

ORDERABLE PART NUMBER

TPS560430YQDBVRQ1

Frequency

2.1 MHz

PFM or FPWM

PFM

Output

Adjustable

TPS560430YFQDBVRQ1

2.1 MHz

FPWM

6 Pin Configuration and Functions

DBV Package

6-Pin SOT-23-6

Top View

GND

VIN

Pin Functions

(1)

TYPE

DESCRIPTION

NAME

Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100nF

capacitor from this pin to the SW pin.

Power ground terminals, connected to the source of low-side FET internally. Connect to system

ground, ground side of C_INand C_OUT. Path to C_INmust be as short as possible.

GND

Feedback input to the converter. Connect a resistor divider to set the output voltage. Never

short this terminal to ground during operation.

Precision enable input to the converter. Do not float. High = on, Low = off. Can be tied to VIN.

Precision enable input allows adjustable UVLO by external resistor divider.

Supply input terminal to internal bias LDO and high-side FET. Connect to input supply and

input bypass capacitors C_IN. Input bypass capacitors must be directly connected to this pin and

GND.

VIN

Switching output of the converter. Internally connected to source of the high-side FET and drain

of the low-side FET. Connect to power inductor.

(1) A = Analog, P = Power, G = Ground.

TPS560430-Q1

ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40 °C to 125 °C (unless otherwise noted)

(1)

PARAMETER

VIN to GND

MIN

–0.3

–3.5

–0.3

–40

MAX

UNIT

Input Voltages

EN to GND

FB to GND

SW to GND

V_IN+ 0.3

5.5

V_IN+ 0.3

Output Voltages SW to GND less than 10 ns transient

CB to SW

5.5

(2)

T_J

Junction temperature

Storage temperature

150

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.

7.2 ESD Ratings

VALUE

±2500

±750

UNIT

(1)

Human-body model (HBM), per AEC Q100-002

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)

(1)

PARAMETER

MIN

MAX

UNIT

VIN to GND

Input Voltages

V_IN

4.5

Output Voltage

Output Current

Temperature

V_OUT

1.0

95% of V_IN

600

I_OUT

°C

Operating junction temperature range, T_J

–40

+125

(1) Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific

performance limits. For guaranteed specifications, see Electrical Characteristics

7.4 Thermal Information

(1)

THERMAL METRIC

DBV (6 PINS)

UNIT

°C/W

(2)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (TOP) thermal resistance

Junction-to-case (BOTTOM) thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

173

116

R_{θJC_T}

R_{θJC_B}

ψ_JT

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953

(2) The value of R_θJAgiven in this table is only valid for comparison with other packages and can not be used for design purposes. These

values were calculated in accordance with JESD 51-7, and simulated on a specified JEDEC board. They do not represent the

performance obtained in an actual application.

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7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 4 V to 36 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

V_IN

Operation input voltage

3.55

3.25

4.00

3.65

Rising threshold

3.75

3.45

0.3

V_{IN_UVLO}

Undervoltage lockout thresholds

Falling threshold

Hysteresis

I_Q

Operating quiescent current (non-

switching)

PFM version, V_EN= 3.3 V, V_FB

1.1V

120

µA

I_SHDN

Shutdown current

V_EN= 0 V

ENABLE (EN PIN)

V_{EN_H}

V_{EN_L}

V_{EN_HYS}

I_EN

Enable rising threshold voltage

1.1

1.23

1.1

1.36

1.22

Enable falling threshold voltage

Enable hysteresis voltage

Leakage current at EN pin

0.95

0.13

V_EN= 3.3 V

200

VOLTAGE REFERENCE (FB PIN)

T_J= 25 °C

0.995

0.985

1.00

0.2

1.005

1.015

V_REF

I_FB

Reference voltage

T_J= –40 °C to 125 °C

V_FB= 1.2 V

Leakage current at FB pin

CURRENT LIMITS AND HICCUP

I_{HS_LIMIT}

I_{LS_LIMIT}

I_{LS_ZC}

Peak inductor current limit

0.8

1.1

0.8

1.4

Valley inductor current limit

0.62

0.98

Zero cross current (PFM version)

I_{LS_NEG}

Negative current limit (FPWM

version)

-0.7

-0.5

-0.3

V_HICCUP

Hiccup threshold of FB pin

% of reference voltage

40%

INTEGRATED MOSFETS

R_{DS_ON_HS}

High-side MOSFET ON-resistance T_J= 25 °C, V_IN= 12 V

Low-side MOSFET ON-resistance T_J= 25 °C, V_IN= 12 V

450

240

mΩ

R_{DS_ON_LS}

(1)

THERMAL SHUTDOWN

T_SHDN

T_HYS

Thermal shutdown threshold

Hysteresis

170

°C

(1) Ensured by design.

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ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

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7.6 Timing Requirements

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 4 V to 36 V.

PARAMETER

Internal soft-start time

Hiccup time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT START

The time of internal reference to

increase from 10% to 90% of V_REF

V_IN= 12 V

T_SS

1.8

HICCUP

T_HICCUP

V_IN= 12 V

135

7.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 4 V to 36 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SWITCHING NODE (SW PIN)

t_{ON_MIN}

Minimum turn-on time

Minimum turn-off time

Maximum turn-on time

I_OUT= 600 mA

100

7.5

µs

t_{OFF_MIN}

t_{ON_MAX}

OSCILLATOR

f_SW

I_OUT= 600 mA

Oscillator frequency

2.1-MHz version

1.785

2.1

2.415

MHz

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ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

7.8 Typical Characteristics

V_IN= 12 V, T_A= 25°C, unless otherwise specified.

100

FPWM, 8 V_IN

FPWM, 12 V_IN

FPWM, 24 V_IN

PFM, 8 V_IN

PFM, 12 V_IN

PFM, 24 V_IN

FPWM, 12 V_IN

FPWM, 24 V_IN

PFM, 8 V_IN

PFM, 12 V_IN

PFM, 24 V_IN

0.0001

0.001

0.01

I_OUT(A)

0.1

0.0001

0.001

0.01

I_OUT(A)

0.1

D011

D012

V_OUT= 3.3 V

V_OUT= 5 V

图 1. Efficiency vs Load Current

图 2. Efficiency vs Load Current

3.37

V_IN=8V

I_OUT=0mA

V_IN=12V

V_IN=24V

V_IN=36V

I_OUT=100mA

I_OUT=300mA

I_OUT=600mA

3.36

3.35

3.34

3.33

3.36

3.35

3.34

3.33

0.1

0.2

0.3

I_OUT(A)

0.4

0.5

0.6

V_IN(V)

SLUS

V_OUT= 3.3 V

FPWM version

V_OUT= 3.3 V

FPM version

图 3. Load Regulation

图 4. Line Regulation

1/16/2019

5.4

4.6

4.2

3.8

3.4

I_OUT=0mA

I_OUT=100mA

I_OUT=300mA

I_OUT=600mA

-50

Temperature (èC)

100

150

4.5

5.5

V_IN(V)

6.5

SLUS

D007

V_OUT= 5 V

FPWM version

V_FB= 1.1 V

PFM verison

图 5. Dropout

图 6. I_Qvs Temperature

TPS560430-Q1

ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

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Typical Characteristics (接下页)

V_IN= 12 V, T_A= 25°C, unless otherwise specified.

3.9

1.0002

3.8

3.7

3.6

3.5

3.4

3.3

0.9998

0.9996

0.9994

0.9992

0.999

0.9988

0.9986

Rising

Falling

-50

Temperature (èC)

100

150

-50

Temperature (èC)

100

150

D008

D009

图 7. V_INUVLO vs Temperature

图 8. Reference Voltage vs Temperature

1.2

1.1

0.9

0.8

0.7

-50

Temperature (èC)

100

150

D010

图 9. HS and LS Current Limit vs Temperature

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ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

8 Detailed Description

8.1 Overview

The TPS560430-Q1 converter is an easy to use synchronous step-down DC-DC converter operating from 4-V to

36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution size. The

family has two versions applicable to various applications, refer to Device Comparison Table for detailed

information.

The TPS560430-Q1 employs fixed-frequency peak-current mode control. The device enters PFM Mode at light

load to achieve high efficiency for PFM version. FPWM version is provided to achieve low output voltage ripple,

tight output voltage regulation, and constant switching frequency at light load. The device is internally

compensated, which reduces design time, and requires few external components.

Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for

a wide range of applications. Protection features include thermal shutdown, V_INunder-voltage lockout, cycle-by-

cycle current limit, and hiccup mode short-circuit protection.

The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.

8.2 Functional Block Diagram

VCC

Enable

LDO

VIN

Precision

Enable

HSI Sense

Internal

REF

R_C

C_C

TSD

UVLO

PWM CONTROL LOGIC

PFM

Detector

Slope

Comp

Ton_min/Toff_min

Detector

Freq

Foldback

HICCUP

Detector

Zero

Cross

LSI Sense

Oscillator

GND

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8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control

The following operation description of TPS560430-Q1 will refer to the Functional Block Diagram and to the

waveforms in 图 10. TPS560430-Q1 is a step-down synchronous buck converter with integrated high-side (HS)

and low-side (LS) switches (synchronous rectifier). The TPS560430-Q1 supplies a regulated output voltage by

turning on the high-side and low side NMOS switches with controlled duty cycle. During high-side switch ON

time, the SW pin voltage swings up to approximately V_IN, and the inductor current i_Lincreases with linear slope

(V_IN– V_OUT) / L. When the high-side switch is turned off by the control logic, the low-side switch is turned on after

an anti-shoot-through dead time. Inductor current discharges through the low-side switch with a slope of –V_OUT

L. The control parameter of a buck converter is defined as Duty Cycle D = t_ON/ T_SW, where t_ONis the high-side

switch ON time and T_SWis the switching period. The converter control loop maintains a constant output voltage

by adjusting the duty cycle D. In an idea Buck converter, where losses are ignored, D is proportional to the

output voltage and inversely proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

V_IN

D = t_ON/ T_SW

t_ON

t_OFF

T_SW

i_L

I_LPK

I_OUT

∆i_L

图 10. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS560430-Q1 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get

accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak

inductor current is sensed from the high-side switch and compared to the peak current threshold to control the

ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer

external components, makes it easy to design, and provides stable operation with almost any combination of

output capacitors. The converter operates with fixed switching frequency at normal load condition. At light-load

condition, the TPS560430-Q1 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM

mode for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM

version).

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Feature Description (接下页)

8.3.2 Adjustable Output Voltage

A precision 1.0-V reference voltage (V_REF) is used to maintain a tightly regulated output voltage over the entire

operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It

is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the

bottom-side resistor R_FBBfor the desired divider current and use 器件支持 to calculate top-side resistor R_FBT

R_FBTin the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower R_FBTvalue can be used

if static loading is desired to reduce V_OUToffset in PFM operation. Lower R_FBTreduces efficiency at very light

load. Less static current goes through a larger R_FBTand might be more desirable when light-load efficiency is

critical. But R_FBTlarger than 1 MΩ is not recommended because it makes the feedback path more susceptible to

noise. Larger R_FBTvalue requires more carefully designed feedback path on the PCB. The tolerance and

temperature variation of the resistor dividers affect the output voltage regulation.

V_OUT

R_FBT

R_FBB

图 11. Output Voltage Setting

V_OUT- V_REF

R_FBT

× R_FBB

V_REF

(1)

8.3.3 Enable

The voltage on the EN pin controls the ON or OFF operation of TPS560430-Q1. A voltage of less than 0.95 V

shuts down the device, while a voltage of more than 1.36 V is required to start the converter. The EN pin is an

input and cannot be left open or floating. The simplest way to enable the operation of the TPS560430-Q1 is to

connect the EN to VIN. This allows self-start-up of the TPS560430-Q1 when V_INis within the operating range.

Many applications will benefit from the employment of an enable divider R_ENTand R_ENB(图 12) to establish a

precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility

power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,

such as a battery discharge level. An external logic signal can also be used to drive EN input for system

sequencing and protection. Kindly note that, the EN pin voltage should never be higher than V_IN+ 0.3 V. It is not

recommended to apply EN voltage when V_INis 0 V.

VIN

R_ENT

R_ENB

图 12. System UVLO by Enable Divider

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Feature Description (接下页)

8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback

Minimum ON-time(T_{ON_MIN}) is the smallest duration of time that the high-side switch can be on. T_{ON_MIN}is

typically 60 ns in the TPS560430-Q1. Minimum OFF-time( T_{OFF_MIN}) is the smallest duration that the high-side

switch can be off. T_{OFF_MIN}is typically 100 ns. In CCM operation, T_{ON_MIN}and T_{OFF_MIN}limit the voltage

conversion range without switching frequency foldback.

The minimum duty cycle without frequency foldback allowed is

D_MIN= T_{ON_MIN}X f_SW

(2)

(3)

The maximum duty cycle without frequency foldback allowed is

D_MAX= 1 - T_{OFF_MIN}X f_SW

Given a required output voltage, the maximum V_INwithout frequency foldback can be found by

V_OUT

V_{IN_MAX}

f_SW× T_{ON_MIN}

(4)

(5)

The minimum V_INwithout frequency foldback can be calculated by

V_OUT

V_{IN_MIN}

1- f_SW× T_{OFF_MIN}

In the TPS560430-Q1, a frequency foldback scheme is employed once the T_{ON_MIN}or T_{OFF_MIN}is triggered,

which may extend the maximum duty cycle or lower the minimum duty cycle.

The on-time decreases while V_INvoltage increases. Once the on-time decreases to T_{ON_MIN}, the switching

frequency starts to decrease while V_INcontinues to go up, which lowers the duty cycle further to keep V_OUTin

regulation according to 公式 2.

The frequency foldback scheme also works once larger duty cycle is needed under low V_INcondition. The

frequency decreases once the device hits its T_{OFF_MIN}, which extends the maximum duty cycle according to 公式

3. In such condition, the frequency can be as low as about 133 kHz minimum. Wide range of frequency foldback

allows the TPS560430-Q1 output voltage stay in regulation with a much lower supply voltage V_IN, which leads to

a lower effective drop-out.

With frequency foldback, V_{IN_MAX}is raised, and V_{IN_MIN}is lowered by decreased f_SW

2.2

1.9

1.6

1.3

2.2

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

I_OUT=0mA

I_OUT=300mA

I_OUT=600mA

I_OUT=100mA

I_OUT=300mA

I_OUT=600mA

V_IN(V)

5.25

5.5

5.75

V_IN(V)

6.25

6.5

6.75

D001

SLUS

V_OUT= 3.3 V

f_SW= 2.1 MHz

V_OUT= 5 V

f_SW= 2.1 MHz

图 13. Frequency Foldback at T_{ON_MIN}

图 14. Frequency Foldback at T_{OFF_MIN}

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Feature Description (接下页)

8.3.5 Bootstrap Voltage

The TPS560430-Q1 provides an integrated bootstrap voltage converter. A small capacitor between the CB and

SW pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when

the high-side MOSFET is off and the low-side switch conducts. The recommended value of the bootstrap

capacitor is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or

higher is recommended for stable performance over temperature and voltage.

8.3.6 Over Current and Short Circuit Protection

The TPS560430-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak

and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating.

High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The

high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch

current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.

Please refer to Functional Block Diagram for more details. The peak current of high-side switch is limited by a

clamped maximum peak current threshold I_{high side_LIMIT}which is constant.

The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on,

the inductor current begins to ramp down. The low-side switch will not be turned OFF at the end of a switching

cycle if its current is above the low-side current limit I_{LS_LIMIT}. The low-side switch is kept ON so that inductor

current keeps ramping down, until the inductor current ramps below the I_{LS_LIMIT}. Then the low-side switch will be

turned OFF and the high-side switch will be turned on after a dead time. This is somewhat different to the more

typical peak current limit, and results in 公式 6 for the maximum load current.

- V_OUT

V_OUT

V_IN

(

)

I_{OUT_MAX}= I_LS

2 × f_SW× L

(6)

If the feedback voltage is lower than 40% of the V_REF, the current of the low-side switch triggers I_{LS_LIMIT}for 256

consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the converter shuts down and

keeps off for a period of hiccup, T_HICCUP(135 ms typical), before the TPS560430-Q1 tries to start again. If over-

current or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode

reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to

the device.

For FPWM version, the inductor current is allowed to go negative. When this current exceed the low-side

negative current limit I_{LS_NEG}, the low-side switch is turned off and high-side switch is turned on immediately. This

is used to protect the low-side switch from excessive negative current.

8.3.7 Soft Start

The integrated soft-start circuit prevents input inrush current impacting the TPS560430-Q1 and the input power

supply. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled

or powered up. The typical soft-start time is 1.8 ms.

The TPS560430-Q1 also employs over-current protection blanking time T_{OCP_BLK}(33 ms typical) at the beginning

of power-up. Without this feature, in applications with a large amount of output capacitors and high V_OUT, the

inrush current is large enough to trigger the current-limit protection, which may make the device entering into

hiccup mode. The device tries to restart after the hiccup period, then hit current-limit and enter into hiccup mode

again, so V_OUTcannot ramp up to the setting voltage ever. By introducing OCP blanking feature, the hiccup

protection function is disabled during T_{OCP_BLK}, and TPS560430-Q1 charges the V_OUTwith its maximum limited

current, which maximizes the output current capacity during this period. Kindly note that, the peak current limit

(I_{HS_LIMIT}) and valley current limit (I_{LS_LIMIT}) protection function are still available during T_{OCP_BLK}, so there is no

concern of inductor current running away.

8.3.8 Thermal Shutdown

The TPS560430-Q1 provides an internal thermal shutdown to protect the device when the junction temperature

exceeds 170°C. Both high-side and low-side FETs stop switching in thermal shutdown. Once the die temperature

falls below 158°C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPS560430-Q1. When V_ENis below 0.95 V, the

device is in shutdown mode. The TPS560430-Q1 also employs V_INunder voltage lock out protection (UVLO). If

V_INvoltage is below its UVLO threshold 3.25 V, the converter is turned off.

8.4.2 Active Mode

The TPS560430-Q1 is in Active Mode when both V_ENand V_INare above their respective operating threshold.

The simplest way to enable the TPS560430-Q1 is to connect the EN pin to VIN pin. This allows self-startup when

the input voltage is in the operating range: 4.0 V to 36 V. Please refer to Enable section for details on setting

these operating levels.

In Active Mode, depending on the load current, the TPS560430-Q1 will be in one of four modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple (for both PFM and FPWM versions).

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation (only for PFM version).

3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for

PFM version).

4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for

FPWM version).

8.4.3 CCM Mode

Continuous Conduction Mode (CCM) operation is employed in the TPS560430-Q1 when the load current is

higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed,

output voltage ripple is at a minimum in this mode and the maximum output current of 600 mA can be supplied

by the TPS560430-Q1.

8.4.4 Light-Load Operation (PFM Version)

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the

TPS560430-Q1 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode

(DEM). In DCM operation, the low-side switch is turned off when the inductor current drops to I_{LS_ZC}(20 mA

typical) to improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to

forced PWM operation at light load.

At even lighter current load, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency

operation. When either the minimum high-side switch ON time t_{ON_MIN}or the minimum peak inductor current

I_{PEAK_MIN}(150mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode,

switching frequency is decreased by the control loop to maintain output voltage regulation when load current

reduces. Switching loss is further reduced in PFM operation due to less frequent switching actions.

8.4.5 Light-Load Operation (FPWM Version)

For FPWM version, TPS560430-Q1 is locked in PWM mode at full load range. This operation is maintained, even

in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced

light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching

frequency.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS560430-Q1 is a step down DC-to-DC converter. It is typically used to convert a higher DC voltage to a

lower DC voltage with a maximum output current of 600 mA. The following design procedure can be used to

select components for the TPS560430-Q1. Alternately, the WEBENCH® software may be used to generate

complete designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and

accesses comprehensive databases of components. Please go to ti.com for more details.

9.2 Typical Application

The TPS560430-Q1 only requires a few external components to convert from a wide voltage range supply to a

fixed output voltage. 图 15 shows a basic schematic.

V_IN12 V

VIN

C_BOOT

0.1 µF

C_IN

2.2 µF

10 µH

V_OUT5 V

R_FBT

88.7 kΩ

C_OUT

22 µF

GND

R_FBB

22.1 kΩ

图 15. Application Circuit

The external components have to fulfill the needs of the application and the stability criteria of the device's

control loop. 表 1 can be used to simplify the output filter component selection.

表 1. L and C_OUTTypical Values

f_SW(MHz)

V_OUT(V)

L (µH)

6.8

C_OUT(µF)

10 µF / 10 V

10 µF / 25 V

R_FBT(kΩ)

R_FBB(kΩ)

22.1

3.3

2.1

88.7

22.1

243

22.1

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9.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表 2 as the input parameters.

表 2. Design Example Parameters

PARAMETER

VALUE

Input voltage, V_IN

12 V typical, range from 6 V to 36 V

Output voltage, V_OUT

5 V ±3%

600 mA

30 mA

Maximum output current, I_{OUT_MAX}

Minimum output current, I_{OUT_MIN}

Output overshoot/ undershoot (0mA to 600mA )

Output voltage ripple

0.5%

Operating frequency

2.1 MHz

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS560430-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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9.2.2.2 Output Voltage Set-Point

The output voltage of the TPS560430-Q1 device is externally adjustable using a resistor divider network. The

divider network is comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. 公式 7 is used to

determine the output voltage of the converter:

V_OUT- V_REF

R_FBT

× R_FBB

V_REF

(7)

Choose the value of R_FBBto be 22.1 kΩ. With the desired output voltage set to 5 V and the V_REF= 1.0 V, the

R_FBTvalue can then be calculated using 公式 7. The formula yields to a value 88.4 kΩ, a standard value of 88.7

kΩ is selected.

9.2.2.3 Switching Frequency

The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in

smaller solution size and lower component cost. However higher switching frequency brings more switching loss,

which makes the solution less efficient and produce more heat. The switching frequency is also limited by the

minimum on-time of the integrated power switch, the input voltage, the output voltage and the frequency shift

limitation as mentioned in Minimum ON-Time, Minimum OFF-Time and Frequency Foldback section. For this

example, a switching frequency of 2.1 MHz is selected.

9.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The

inductance is based on the desired peak-to-peak ripple current Δi_L. Since the ripple current increases with the

input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use 公式 9

to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the amount of inductor

ripple current relative to the maximum output current of the device. A reasonable value of K_INDshould be 20% to

60%. During an instantaneous over current operation event, the RMS and peak inductor current can be high. The

inductor current rating should be a bit higher than current limit.

V_OUT

- V_OUT

IN_MAX

(

)

ûi_L=

V_{IN_MAX}× L × f_SW

(8)

V_{IN_MAX}- V_OUT

V_OUT

L_MIN

I_OUT× K _IND

V_{IN_MAX}× f_SW

(9)

In general, it is preferable to choose lower inductance in switching power supplies, because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low

of an inductance can generate too large of an inductor current ripple such that over current protection at the full

load could be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger

inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current

mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple

improves the comparator signal to noise ratio.

For this design example, choose K_IND= 0.4, the minimum inductor value is calculated to be 8.6µH. Choose the

nearest standard 8.2-µH ferrite inductor with a capability of 1-A RMS current and 1.5-A saturation current.

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9.2.2.5 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output

capacitance as possible to keep cost and size down. The output capacitor (s), C_OUT, should be chosen with care

since it directly affects the steady state output voltage ripple, loop stability, output voltage overshoot and

undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One is

caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output

capacitors:

ûV_{OUT_ESR}= ûi_L× ESR = K_IND×I_OUT× ESR

(10)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

ûi_L

K_IND×I_OUT

ûV_{OUT_C}

8×f_SW× C_OUT8×f_SW× C_OUT

(11)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation with presence of large current steps and fast slew rate. When a large load step happens, output

capacitors provide the required charge before the inductor current can slew up to the appropriate level. The

converter’s control loop usually needs 8 or more clock cycles to regulate the inductor current equal to the new

load level. The output capacitance must be large enough to supply the current difference for 8 clock cycles to

maintain the output voltage within the specified range. 公式 12 shows the minimum output capacitance needed

for specified V_OUTovershoot and undershoot.

8 × I_OH-I_OL

(

)

C_OUT

f_SW× ûV_{OUT_SHOOT}

(12)

where

•

K_IND= Ripple ratio of the inductor current (Δi_L/ I_OUT)

I_OL= Low level output current during load transient

I_OH= High level output current during load transient

V_{OUT_SHOOT}= Target output voltage overshoot or undershoot

For this design example, the target output ripple is 30 mV. Presuppose ΔV_{OUT_ESR}= ΔV_{OUT_C}= 30 mV, and

chose K_IND= 0.4. 公式 10 yields ESR no larger than 125 mΩ and 公式 11 yields C_OUTno smaller than 0.91 µF.

For the target overshoot and undershoot limitation of this design, ΔV_{OUT_SHOOT}= 5% × V_OUT= 250 mV. The C_OUT

can be calculated to be no smaller than 4.3 µF by 公式 12. In summary, the most stringent criteria for the output

capacitor is 4.3 µF. Consider of derating, one 10-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR is used.

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9.2.2.6 Input Capacitor Selection

The TPS560430-Q1 device requires high frequency input decoupling capacitor(s). The typical recommended

value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type X5R or X7R

with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input

voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage

is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is used for the input

decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the current rating is 1

A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the

device pins.

9.2.2.7 Bootstrap Capacitor

Every TPS560430-Q1 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor is

0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The

bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

9.2.2.8 Under Voltage Lockout Set-Point

The system under voltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brown outs when the input voltage is falling. The following equation can be used to determine the V_INUVLO

level.

R_ENT+ R_ENB

V_{IN_RISING}= V_ENH

R_ENB

(13)

The EN rising threshold (V_ENH) for TPS560430-Q1 is set to be 1.23 V (typical). Choose the value of R_ENBto be

200 kΩ to minimize input current from the supply. If the desired V_INUVLO level is at 6.0 V, then the value of R_ENT

can be calculated using 公式 14:

≈

’

◊

V_{IN_RISING}

R_ENT

-1 × R

∆

ENB

V_ENH

(14)

The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling

UVLO threshold, equals 5.3 V, can be calculated by 公式 15, where EN hysteresis voltage, V_{EN_HYS}, is 0.13 V

(typical).

R_ENT+ R_ENB

V_{IN_FALLING}= V

(

- V_{EN_HYS}×

)

ENH

R_ENB

(15)

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, V_OUT= 5 V, f_SW= 2.1 MHz, L = 8.2 µH, C_OUT= 10 µF,

T_A= 25 °C

V_SW[5V/div]

V_OUT(AC)[10mV/div]

i_L[200mA/div]

V_OUT(AC)[10mV/div]

Time[1us/div]

I_OUT= 0 mA

FPWM Version

I_OUT= 600 mA

FPWM Version

图 16. Ripple at No Load

图 17. Ripple at Full Load

V_IN[10V/div]

EN[2V/div]

V_OUT[2V/div]

i_L[500mA/div]

Time[100ms/div]

Time[1ms/div]

I_OUT= 600 mA

FPWM Version

I_OUT= 600 mA

FPWM Version

图 18. Start Up by V_IN

图 19. Start-Up by EN

I_OUT[200mA/div]

V_OUT[2V/div]

i_L[500mA/div]

V_OUT(AC)[200mV/div]

Time[200µs/div]

Time[100ms/div]

I_OUT= 0 to 600

mA, 100 mA / µs

FPWM Version

I_OUT= 0 mA to

short

FPWM Version

图 20. Load Transient

图 21. Short Protection

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Unless otherwise specified the following conditions apply: V_IN= 12 V, V_OUT= 5 V, f_SW= 2.1 MHz, L = 8.2 µH, C_OUT= 10 µF,

T_A= 25 °C

V_OUT[2V/div]

i_L[500mA/div]

Time[100ms/div]

I_OUT= short to 0 mA

FPWM Version

图 22. Short Recovery

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10 Power Supply Recommendations

The TPS560430-Q1 is designed to operate from an input voltage supply range between 4.0 V and 36 V. This

input supply should be well regulated and able to withstand maximum input current and maintain a stable

voltage. The resistance of the input supply rail should be low enough that an input current transient does not

cause a high enough drop at the TPS560430-Q1 supply voltage that can cause a false UVLO fault triggering and

system reset. If the input supply is located more than a few inches from the TPS560430-Q1 additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not

critical, but a 10-µF or 22-µF electrolytic capacitor is a typical choice.

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB

with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The input bypass capacitor C_INmust be placed as close as possible to the VIN and GND pins. Grounding for

both the input and output capacitors should consist of localized top side planes that connect to the GND pin.

2. Minimize trace length to the FB pin net. Both feedback resistors, R_FBTand R_FBBshould be located close to

the FB pin. If V_OUTaccuracy at the load is important, make sure V_OUTsense is made at the load. Route V_OUT

sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.

3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.

4. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

5. Provide adequate device heat-sinking. GND, VIN and SW pins provide the main heat dissipation path, make

the GND, VIN and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top

side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these

thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area

is used for heat-sinking to keep the junction temperature below 125 °C.

11.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass

capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing

ceramic bypass capacitor(s) as close as possible to the VIN and GND pins is the key to EMI reduction.

The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load

current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current

conduction path to minimize parasitic resistance. The output capacitors should be placed close to the V_OUTend

of the inductor and closely grounded to GND pin.

11.1.2 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider close

to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace

length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from

V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct

for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider should be routed away from the SW node path and the inductor to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high value resistors are used to set the output voltage. It is recommended to route the voltage

sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that

there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further

shielding for the voltage feedback path from EMI noises.

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11.2 Layout Example

VOUT

Output Bypass

Capacitor

Output

Inductor

BOOT

Capacitor

GND

VIN

Input Bypass

Capacitor

Output Voltage

Set Resistor

GND

VIA (Connect to GND Plane)

图 23. Layout

TPS560430-Q1

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12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 TPS560430-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

《AN-1149 开关电源布局指南》

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 商标

E2E is a trademark of Texas Instruments.

SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

TPS560430-Q1

www.ti.com.cn

ZHCSJC7A –JANUARY 2019–REVISED AUGUST 2019

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS560430YFQDBVRQ1

TPS560430YQDBVRQ1

ACTIVE

SOT-23

DBV

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

1RTF

1RSF

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS560430YFQDBVRQ1 SOT-23

TPS560430YQDBVRQ1 SOT-23

DBV

3000

180.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS560430YFQDBVRQ1

TPS560430YQDBVRQ1

SOT-23

DBV

3000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

1.45 MAX

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

0.50

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS560430-Q1 [TI]

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TPS560430YDBVR

TPS560430YDBVT

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