TPS562200DDCT [TI]
采用 SOT-23 封装、具有高级 Eco-Mode™ 的 17V 输入、2A 同步降压稳压器 | DDC | 6 | -40 to 125;
| 型号： | TPS562200DDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-23 封装、具有高级 Eco-Mode™ 的 17V 输入、2A 同步降压稳压器 | DDC | 6 | -40 to 125 稳压器 |
| 文件： | 总36页 (文件大小：1676K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
TPS56x200 采用6 引脚SOT-23 封装的4.5V 至17V 输入、2A、3A 同步降压稳压
器
1 特性
3 说明
• TPS562200 - 集成有122mΩ 和72mΩ FET 的
2A 转换器
TPS562200 和 TPS563200 是采用 6 引脚 SOT-23 封
装的简单易用型2A 和3A 同步降压转换器。
• TPS563200 - 集成有68mΩ 和39mΩ FET 的3A
转换器
• 可实现快速瞬态响应的D-CAP2™ 控制拓扑
• 输入电压范围：4.5V 至17V
• 输出电压范围：0.76V 至7V
• 开关频率：650 kHz
• 高级Eco-Mode 脉冲跳跃
• 低关断电流（低于10µA）
• 1% 反馈电压精度(25°C)
• 从预偏置输出电压启动
• 逐周期过流限制
• 断续模式欠压保护
此器件被优化为使用尽可能少的外部组件即可运行，并
且可以实现低待机电流。
这些开关模式电源 (SMPS) 器件采用 D-CAP2 控制拓
扑，从而提供快速瞬态响应，并且在无需外部补偿组件
的情况下支持专用聚合物等低等效串联电阻 (ESR) 输
出电容器以及超低ESR 陶瓷电容器。
TPS562200 和 TPS563200 可在高级 Eco-mode 下运
行，从而能在轻载运行期间保持高效率。这些器件采用
6 引脚 1.6mm × 2.9mm SOT (DDC) 封装，额定工作
环境温度范围为–40°C 至85°C。
器件信息(1)
• 非锁存OVP、UVLO 和TSD 保护
• 固定软启动：1ms
• 使用TPS563252 在更小的封装中实现更高的效率
和频率
输出电流（最大值）
器件型号
TPS562200
TPS563200
封装
2A
3A
DRL (SOT-236, 6)
• 使用WEBENCH® 工具创建定制设计
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 数字电视电源
• 高清蓝光光盘™播放器
• 网络家庭终端设备
• 数字机顶盒(STB)
TPS562200
TPS563200
100
90
LO
3
5
4
2
6
1
VIN
VIN
SW
VBST
GND
VOUT
CO
EN
CIN
VOUT
EN
CBST
80
VFB
RFB1
RFB2
70
VOUT = 1.8 V
60
50
40
30
20
10
0
VOUT = 3.3 V
Copyright © 2016, Texas Instruments Incorporated
简化原理图
VOUT = 5 V
0.001
0.01 0.1
IOUT - Output Current (A)
1
10
C007
Tps562200 效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Applications.................................................. 15
8.3 Power Supply Recommendations.............................26
8.4 Layout....................................................................... 26
9 Device and Documentation Support............................28
9.1 Device Support......................................................... 28
9.2 接收文档更新通知..................................................... 28
9.3 支持资源....................................................................28
9.4 Trademarks...............................................................28
9.5 静电放电警告............................................................ 28
9.6 术语表....................................................................... 28
10 Mechanical, Packaging, And Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings(1) ....................................5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements..................................................7
6.7 Typical Characteristics TPS562200............................8
6.8 Typical Characteristics TPS563200..........................10
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (June 2016) to Revision E (May 2023)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 添加了 TPS563252 信息.....................................................................................................................................1
• 更新了商标信息.................................................................................................................................................. 1
• 通篇去除了图像的颜色........................................................................................................................................1
Changes from Revision C (August 2015) to Revision D (June 2016)
Page
• Updated the Pinout image in Pin Configuration And Functions .........................................................................4
• Changed RθJB for TPS562200 From: 3.4 To: 13.4 in Thermal Information ...................................................... 6
• 节7.3.1, changed text From: "proportional to the converter input voltage, VIN, and inversely proportional to
the output voltage, VO" To: "inversely proportional to the converter input voltage, VIN, and proportional to the
output voltage, VO"........................................................................................................................................... 13
Changes from Revision B (July 2014) to Revision C (August 2015)
Page
• 将特性部分从“集成122mΩ 和72mΩ FET ('562200)”更改为“TPS562200 - 集成有122mΩ 和72mΩ FET
的 2A 转换器”...................................................................................................................................................1
• 将特性部分从“集成68mΩ 和39mΩ FET ('563200)”更改为“TPS563200 - 集成有68mΩ 和39mΩ FET 的
3A 转换器”........................................................................................................................................................1
• 添加了节 1：650kHz 开关频率...........................................................................................................................1
• 将特性部分从“逐周期间断过流限制”更改为：逐周期过流限制......................................................................1
• 添加了特性：断续模式欠压保护.........................................................................................................................1
• 将“说明”第一段中的文本从“采用SOT-23 封装...”修改为“采用6 引脚SOT-23 封装...”.........................1
• Moved Storage temperature range, Tstg From: Handling Ratings To: Absolute Maximum Ratings ...................5
• Changed the Handling Ratings table to the ESD Ratings table..........................................................................5
• Changed the TPS562200 Thermal Information values.......................................................................................6
• Changed VOVP Description in the Electrical Characteristics From: OVP Detect (L > H) To: OVP Detect, and
the TYP value From: 125% To: 125% x Vfbth.................................................................................................... 7
• Changed VUVP Description in the Electrical Characteristics From: Hiccup detect (H < L) To: Hiccup detect ,
and the TYP value From: 65% To: 65% x Vfbth................................................................................................. 7
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English Data Sheet: SLVSCB0
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• Changed the Output Current (A) scale of 图6-7 ............................................................................................... 8
• Changed VOUT = 5 V To VOUT = 3.3 V in 图6-15 .............................................................................................10
• Changed the X axis From: Junction Temperature To: Ambient Temperature in 图6-16 ..................................10
• Added a NOTE to the Application and Implementation section........................................................................15
• Changed column heading C8 + C9 (µF) To: C5 + C6 (µF) in 表8-2 ............................................................... 17
• Changed column heading C8 + C9 (µF) To: C5 + C6 + C7 (µF) in 表8-2 .......................................................22
Changes from Revision A (January 2014) to Revision B (July 2014)
Page
• 添加了特性说明部分、器件功能模式、应用和实现部分、电源相关建议部分、器件和文档支持部分以及机
械、封装和可订购信息 部分............................................................................................................................... 1
• 将数据表标题从“4.5V 至17V 输入，2A 同步降压...”修改为“4.5V 至17V 输入，2A/3A 同步降压..”.........1
• 将器件编号从TPS563209 更改为 TPS563200.................................................................................................. 1
• 将特性部分从“2% 反馈电压精度 (25°C)”更改为：1% 反馈电压精度 (25°C).................................................1
• Added the Timing Requirements table ...............................................................................................................7
• Added 表8-1 ....................................................................................................................................................15
• Changed 表8-2 ............................................................................................................................................... 17
• Deleted sentence following 表8-2 "For higher output voltages, additional phase boost can be achieved by
adding a feed forward capacitor (C7) in parallel with R2."................................................................................17
• Added Application Information for the TPS563200 device .............................................................................. 22
• Added 表8-3 ....................................................................................................................................................22
Changes from Revision * (January 2014) to Revision A (January 2014)
Page
• 将器件状态从“产品预发布”更改为“量产”....................................................................................................1
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English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
5 Pin Configuration and Functions
GND
SW
1
2
3
6
5
4
VBST
EN
VIN
VFB
图5-1. DDC Package 6 Pin (SOT) Top View
表5-1. Pin Functions
PIN
DESCRIPTION
NAME
GND
NUMBER
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
Connect sensitive VFB to this GND at a single point.
1
SW
VIN
VFB
EN
2
3
4
5
Switch node connection between high-side NFET and low-side NFET.
Input voltage supply pin. The drain terminal of high-side power NFET.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
Supply input for the high-side NFET gate drive circuit. Connect a 0.1µF capacitor between VBST and SW
pins.
VBST
6
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English Data Sheet: SLVSCB0
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6 Specifications
6.1 Absolute Maximum Ratings(1)
TJ = -40°C to 150°C(unless otherwise noted)
MIN
–0.3
MAX
UNIT
V
VIN, EN
VBST
19
25
V
–0.3
–0.3
–0.3
–0.3
–2
VBST (10-ns transient)
VBST (vs SW)
27.5
6.5
6.5
19
V
Input voltage range
V
VFB
V
SW
V
SW (10-ns transient)
21
V
–3.5
–40
–55
Operating junction temperature, TJ
Storage temperature range, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TJ = -40°C to 150°C(unless otherwise noted)
MIN
MAX
17
23
26
6
UNIT
VIN
Supply input voltage range
VBST
4.5
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
V
VBST (10-ns transient)
VBST(vs SW)
VI
Input voltage range
EN
17
5.5
17
20
85
V
VFB
SW
SW (10-ns transient)
TA
Operating free-air temperature
°C
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English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
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UNITS
6.4 Thermal Information
TPS562200
DDC (SOT)
(6 PINS)
89.0
TPS563200
DDC (SOT)
(6 PINS)
87.9
THERMAL METRIC (1)
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.5
42.2
13.4
13.6
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.2
1.9
13.2
13.3
ψJB
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSCB0
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6.5 Electrical Characteristics
TJ = -40°C to 150°C, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
TPS562200
TPS563200
230
190
3
330
µA
VIN current, TA = 25°C, EN = 5V,
VFB = 0.8 V
Operating –non-switching
supply current
I(VIN)
290
I(VINSDN) Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
10
µA
LOGIC THRESHOLD
VEN(H)
VEN(L)
REN
EN high-level input voltage
EN low-level input voltage
EN pin resistance to GND
EN
1.6
V
V
EN
0.6
VEN = 12 V
225
450
772
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
Eco-mode operation
mV
VFB(TH)
VFB threshold voltage
TA = 25°C, VO = 1.05 V, continuous mode operation
VFB = 0.8V, TA = 25°C
758
765
0
772
mV
µA
I(VFB)
VFB input current
±0.1
MOSFET
TPS562200
122
68
mΩ
mΩ
mΩ
mΩ
RDS(on)h High side switch resistance
TA = 25°C, VBST –SW = 5.5 V
TPS563200
TPS562200
TPS563200
72
RDS(on)l
Low side switch resistance
TA = 25°C
39
CURRENT LIMIT
DC current, VOUT = 1.05 V, LOUT = 2.2 µF
DC current, VOUT = 1.05 V, LOUT = 1.5 µF
TPS562200
TPS563200
2.5
3.5
3.2
4.2
4.3
5.3
A
A
Iocl
Current limit (1)
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
155
35
Thermal shutdown
threshold(1)
TSDN
°C
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
125%
x Vfbth
VOVP
VUVP
Output OVP threshold
Output Hiccup threshold
OVP Detect
65% x
Vfbth
Hiccup detect
tHiccupOn Hiccup On Time
tHiccupOff Hiccup Off Time
UVLO
Relative to soft-start time
Relative to soft-start time
1
7
ms
ms
Wake up VIN voltage
Hysteresis VIN voltage
3.45
0.13
3.75
0.32
4.05
0.55
UVLO
UVLO threshold
V
(1) Not production tested
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
260
ns
ns
tOFF(MIN)
SOFT START
tss
Minimum off time
TA = 25°C, VFB = 0.5 V
310
1.3
Soft-start time
Internal soft-start time, TA = 25°C
0.7
1
ms
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English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
6.7 Typical Characteristics TPS562200
VIN = 12 V (unless otherwise noted).
400
350
300
250
200
150
100
50
6
5
4
3
2
1
0
0
œ50
0
50
100
150
œ50
0
50
100
150
C001
C002
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
图6-1. Supply Current vs Junction Temperature
EN = 0 V
图6-2. VIN Shutdown Current vs Junction Temperature
0.780
60
50
40
30
20
10
0
0.775
0.770
0.765
0.760
0.755
0.750
œ10
œ50
0
50
100
150
0
3
6
9
12
15
18
C003
C004
TJ - Junction Temperature (°C)
EN Input Voltage (V)
图6-4. En Current vs En Voltage
IO = 1 A
图6-3. Vfb Voltage vs Junction Temperature
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 1.8 V
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 5 V
0.001
0.01 0.1
IOUT - Output Current (A)
1
10
0.001
0.01 0.1
IOUT - Output Current (A)
1
10
C007
C008
图6-5. Efficiency vs Output Current
VIN = 5 V
图6-6. Efficiency vs Output Current
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English Data Sheet: SLVSCB0
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6.7 Typical Characteristics TPS562200 (continued)
VIN = 12 V (unless otherwise noted).
2.5
800
750
700
650
600
550
500
VOUT = 1.8 V
VOUT = 5 V
2.0
VOUT = 3.3 V
VOUT = 0.76 V to 3.3 V
1.5
VOUT = 5 V
1.0
VOUT = 1.2 V
VOUT = 7 V
VOUT = 1.05 V
0.5
0.0
0
25
50
75
100
4
6
8
10
12
14
16
18
C009
C010
TA - Ambient Temperature (°C)
VIN - Input Voltage (V)
图6-7. Output Current vs Ambient Temperature
IOUT = 500 mA
图6-8. Switching Frequency vs Input Voltage
800
700
600
500
400
300
200
100
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.05 V
0
0.01
0.10
1.00
10.00
C011
IO - Output Current (A)
图6-9. Switching Frequency vs Output Current
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6.8 Typical Characteristics TPS563200
VIN = 12 V (unless otherwise noted).
400
350
300
250
200
150
100
50
6
5
4
3
2
1
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (èC)
Junction Temperature (èC)
D037
D038
图6-10. Supply Current vs Junction Temperature
EN = 0 V
图6-11. VIN Shutdown Current vs Junction Temperature
0.780
60
50
40
30
20
10
0
0.775
0.770
0.765
0.760
0.755
0.750
œ10
0
3
6
9
12
15
18
-50
-25
0
25
50
75
100
C019
EN Input Voltage (V)
Junction Temperature (èC)
D039
图6-13. En Current vs En Voltage
IO = 1 A
图6-12. Vfb Voltage vs Junction Temperature
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 3.3 V
VOUT = 1.8 V
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
D040
D041
图6-14. Efficiency vs Output Current
VIN = 5 V
图6-15. Efficiency vs Output Current
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6.8 Typical Characteristics TPS563200 (continued)
VIN = 12 V (unless otherwise noted).
4
800
750
700
650
600
550
500
3
2
1
VO = 0.76 V to 3.3 V
VO = 5 V
VO = 7 V
VO = 1.05 V
VO = 7 V
0
4
6
8
10 12
Input Voltage (V)
14
16
18
0
25
50
75
100
TA - Ambient Temperature (èC)
D043
D042
IOUT = 1 A
图6-17. Switching Frequency vs Input Voltage
图6-16. Output Current vs Ambient Temperature
900
VO = 1.05 V
VO = 7 V
750
600
450
300
150
0
0.001
0.01 0.02 0.05 0.1 0.2
IO - Output Current (A)
0.5
1
2 3 45
D044
图6-18. Switching Frequency vs Output Current
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7 Detailed Description
7.1 Overview
The TPS562200 and TPS563200 are 2-A and 3-A synchronous step-down converters. The proprietary D-CAP2
control scheme supports low ESR output capacitors such as specialty polymer capacitors and multi-layer
ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2
control scheme can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
3
VIN
+
UVP
VUVP
Hiccup
VREG5
Control Logic
Regulator
UVLO
+
OVP
VOVP
4
VFB
VBST
6
PWM
Voltage
Reference
Ref
SS
+
+
HS
Soft Start
Ton
One-Shot
2
1
SW
XCON
VREG5
LS
TSD
OCL
threshold
OCL
+
GND
+
ZC
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7.3 Feature Description
7.3.1 The Adaptive On-Time Control And PWM Operation
The main control loop of the TPS562200 and TPS563200 are adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2 control scheme. The D-CAP2 control scheme combines adaptive
on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component
count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at
the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 control scheme.
7.3.2 Advanced Eco-mode Control
The TPS562200 and TPS563200 are designed with Advanced Eco-mode to maintain high light load efficiency.
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction
and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on-
time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The
transition point to the light load operation IOUT(LL) current can be calculated in Equation 1.
V
IN - VOUT ´ V
)
(
1
OUT
IOUT(LL)
=
´
2´L ´ ƒSW
V
IN
(1)
7.3.3 Soft Start And Pre-Biased Soft Start
The TPS562200 and TPS563200 have an internal 1 ms soft-start. When the EN pin becomes high, the internal
soft-start function begins ramping up the reference voltage to the PWM comparator. If the output capacitor is pre-
biased at startup, the devices initiate switching and start ramping up only after the internal reference voltage
becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly
into regulation point.
7.3.4 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over
current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing
the available output current. When a switching cycle occurs where the switch current is not above the lower OCL
threshold, the counter is reset and the OCL threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
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from the converter. This can cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. Then, the device shuts down after the UVP delay time
(typically 14 µs) and re-start after the hiccup time (typically 12 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.5 Over Voltage Protection
TPS562200 and TPS563200 detect overvoltage condition by monitoring the feedback voltage (VFB). When the
feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and
both the high-side MOSFET driver and the low-side MOSFET driver turn off. This function is non-latch operation.
7.3.6 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562200 and TPS563200 can operate in their normal switching modes. Normal continuous conduction mode
(CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS562200 and TPS563200 operate
at a quasi-fixed frequency of 650 kHz.
7.4.2 Eco-mode Operation
When the TPS562200 and TPS563200 are in the normal CCM operating mode and the switch current falls to 0
A, the TPS562200 and TPS563200 begin operating in pulse skipping Eco-mode. Each switching cycle is
followed by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the
Eco-mode threshold voltage. As the output current decreases the perceived time between switching pulses
increases.
7.4.3 Standby Operation
When the TPS562200 and TPS563200 are operating in either normal CCM or Eco-mode, they can be placed in
standby by asserting the EN pin low.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS562200 and TPS563200 are typically used as step down converters, which convert a voltage from 4.5 V
–17 V to a lower voltage. WEBENCH software is available to aid in the design and analysis of circuits
8.2 Typical Applications
8.2.1 Tps562200 4.5-V To 17-V Input, 1.05-V Output Converter
U1
L1 2.2 uH
TPS562200
VOUT = 1.05 V, 2 A
VIN = 4.5 V to 17 V
3
5
4
2
6
1
VIN
VIN
EN
SW
VBST
GND
VOUT
C4
R1 10.0 k
R2
3.74 k
EN
C1
10 µF
C2
10 µF
C3
C5
22 µF
C6
22 µF
0.1 µF
VFB
R3
10.0 k
Not Installed
图8-1. Tps562200 1.05v/2a Reference Design
8.2.1.1 Design Requirements
To begin the design process, the user must know a few application parameters:
表8-1. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
4.5 V to 17 V
1.05 V
Output current
2 A
Output voltage ripple
20 mVpp
8.2.1.2 Detailed Design Procedures
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the WEBENCH Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
8.2.1.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT
.
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To improve efficiency at light loads consider using larger value resistors, too high of resistance is more
susceptible to noise and voltage errors from the VFB input current are more noticeable.
R2
æ
ö
VOUT = 0.765 ´ 1+
ç
÷
R3
è
ø
(2)
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8.2.1.2.3 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
F =
P
2p LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 control scheme introduces a high frequency
zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade
above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the
double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost
provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this
requirement use the values recommended in Table 1.
表8-2. TPS562200 Recommended Component Values
L1(uH)
Output Voltage (V)
C5 + C6 (µF)
R2 (kΩ)
R3 (kΩ)
MIN
1.5
TYP
2.2
MAX
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
1.5
1.5
1.5
1.5
2.2
2.2
3.3
3.3
2.2
2.2
2.2
2.2
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
6.5
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 方程式 4, 方程式 5
and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the
RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for ƒSW
.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of 方程式 5 and the RMS
current of 方程式6.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(4)
(5)
IlP-P
IlPEAK = IO +
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A
The capacitor value and ESR determines the amount of output voltage ripple. The device is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use 方程式 7 to
determine the required RMS current rating for the output capacitor.
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VOUT ´ VIN - VOUT
(
12 ´ V ´LO ´ ƒSW
)
ICO(RMS)
=
IN
(7)
For this design, two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.1.2.4 Input Capacitor Selection
The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.
TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor(C3)
from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating must
be greater than the maximum input voltage.
8.2.1.2.5 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
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8.2.1.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0.5
1
Output Current (A)
1.5
2
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
D032
D033
图8-2. Tps562200 Efficiency
图8-3. Tps562200 Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
0.5
1
Output Current (A)
1.5
2
0
0.5
1
Output Current (A)
1.5
2
D034
D034
图8-4. Tps562200 Load Regulation, VI = 5 V
图8-5. Tps562200 Load Regulation, VI = 12 V
0.5
0.4
0.3
0.2
0.1
0
IO = 2 A
VI = 100 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10 12
Input Voltage (V)
14
16
18
Time = 1 µsec / div
D036
图8-6. Tps562200 Line Regulation
图8-7. Tps562200 Input Voltage Ripple
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IO = 10 mA
IO = 250 mA
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 1 µsec / div
Time = 20 µsec / div
图8-9. Tps562200 Output Voltage Ripple
图8-8. Tps562200 Output Voltage Ripple
IO = 2 A
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
IO = 500 mA / div
SW = 5 V / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Time = 1 µsec / div
Time = 200 µsec / div
图8-10. Tps562200 Output Voltage Ripple
图8-11. Tps562200 Transient Response
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Time = 2 msec / div
图8-13. Tps562200 Start Up Relative to En
图8-12. Tps562200 Start Up Relative to VI
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VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Time = 2 msec / div
图8-14. Tps562200 Shut Down Relative to VI
图8-15. Tps562200 Shut Down Relative to En
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8.2.2 Tps563200 4.5-V To 17-V Input, 1.05-V Output Converter
U1
L1 1.5 uH
TPS563200
VOUT = 1.05 V, 3 A
VIN = 4.5 V to 17 V
3
5
4
2
6
1
VIN
VIN
EN
SW
VBST
GND
VOUT
C4
R1 10.0k
R2
3.74k
EN
C1
10µF
C2
10µF
C3
0.1µF
C5
22µF
C6
22µF
C7
22µF
0.1µF
VFB
R3
10.0k
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图8-16. Tps563200 1.05v/3a Reference Design
8.2.2.1 Design Requirements
To begin the design process, the user must know a few application parameters:
表8-3. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
4.5 V to 17 V
1.05 V
Output current
3 A
Output voltage ripple
20 mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563200 is the same as for TPS562200 except for inductor selection.
8.2.2.2.1 Output Filter Selection
表8-4. Tps563200 Recommended Component Values
L1 (µH)
Output Voltage (V)
C5 + C6 + C7 (µF)
R2 (kΩ)
R3 (kΩ)
MIN
TYP
MAX
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
2.2
2.2
1.5
1.5
1.5
1.5
2.2
2.2
2.2
3.3
3.3
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
6.5
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 方程式 8, 方程式 9
and 方程式 10. The inductor saturation current rating must be greater than the calculated peak current and the
RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for ƒSW
.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of 方程式 9 and the RMS
current of 方程式10.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(8)
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IlP-P
IlPEAK = IO +
2
(9)
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(10)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3 A and an RMS current rating of 4.9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 μF to 68 μF. Use Equation
6 to determine the required RMS current rating for the output capacitor. For this design three TDK
C3216X5R0J226M 22μF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS
current is 0.292 A and each output capacitor is rated for 4 A.
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8.2.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
D027
D028
图8-17. Tps563200 Efficiency
图8-18. Tps563200 Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
D029
D030
图8-19. Tps563200 Load Regulation, VI = 5 V
图8-20. Tps563200 Load Regulation, VI = 12 V
0.5
0.4
0.3
0.2
0.1
0
IO = 3 A
VI = 50 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10 12
Input Voltage (V)
14
16
18
Time = 1 µsec / div
D031
图8-21. Tps563200 Line Regulation
图8-22. Tps563200 Input Voltage Ripple
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English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
IO = 0 mA
IO = 300 mA
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 1 µsec / div
Time = 5 msec / div
图8-23. Tps563200 Output Voltage Ripple
图8-24. Tps563200 Output Voltage Ripple
IO = 3 A
VO = 50 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SW = 5 V / div
IO = 1 A / div
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 1 µsec / div
Time = 200 µsec / div
图8-25. Tps563200 Output Voltage Ripple
图8-26. Tps563200 Transient Response
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
图8-27. Tps563200 Start-up Relative to VI
图8-28. Tps563200 Start-up Relative to En
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Product Folder Links: TPS562200 TPS563200
English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
VO = 500 mV / div
EN = 10 V / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
图8-29. Tps563200 Shut Down Relative to VI
图8-30. Tps563200 Shutdown Relative to En
8.3 Power Supply Recommendations
The TPS562200 and TPS563200 are designed to operate from input supply voltage in the range of 4.5 V to 17
V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
8.4 Layout
8.4.1 Layout Guidelines
1. VIN and GND traces must be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor must be placed as close to the device as possible to minimize trace
impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path must be connected to the upper feedback resistor
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop must be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node must be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin must be as wide as possible to minimize its
trace impedance.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSCB0
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8.4.2 Layout Example
GND
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
FEEDBACK
RESISTORS
GND
SW
VBST
TO ENABLE
CONTROL
EN
VFB
VIN
Vias to the
internal SW
node copper
HIGH FREQUENCY
INPUT BYPASS
CAPACITOR
SW node copper
pour area on internal
or bottom layer
INPUT BYPASS
CAPACITOR
VIN
图8-31. Typical Layout
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Product Folder Links: TPS562200 TPS563200
English Data Sheet: SLVSCB0
TPS562200, TPS563200
ZHCSC24E –JANUARY 2014 –REVISED MAY 2023
www.ti.com.cn
9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the WEBENCH Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
D-CAP2™ and TI E2E™ are trademarks of Texas Instruments.
蓝光光盘™ is a trademark of Blu-ray Disc Association.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSCB0
28
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PACKAGE OPTION ADDENDUM
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11-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS562200DDCR
TPS562200DDCT
TPS563200DDCR
TPS563200DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
200
200
320
320
Samples
Samples
Samples
Samples
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS562200DDCR
TPS562200DDCT
TPS563200DDCR
TPS563200DDCT
SOT-23-
THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
SOT-23-
THIN
SOT-23-
THIN
3000
250
SOT-23-
THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS562200DDCR
TPS562200DDCT
TPS563200DDCR
TPS563200DDCT
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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