TPS562207S [TI]
采用 SOT563 封装的 4.3V 至 17V 输入、2A FCCM 模式同步降压转换器;
| 型号： | TPS562207S |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT563 封装的 4.3V 至 17V 输入、2A FCCM 模式同步降压转换器 转换器 |
| 文件： | 总23页 (文件大小：1493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS562207S
ZHCSM44 – OCTOBER 2020
采用 SOT563 封装的 TPS562207S 4.3V 至 17V 输入、2A FCCM 模式
同步降压转换器
1 特性
3 说明
•
•
•
•
•
带集成 140mΩ 和 84mΩ FET 的 2A 转换器
TPS562207S 是一款采用 SOT563 封装的简单易用型
2A 同步降压转换器。
具有快速瞬态响应的 D-CAP2™ 模式控制
输入电压范围：4.3V 至 17V
输出电压范围：0.804V 至 7V
强制连续导通模式
该器件经过优化，更大限度地减少了运行所需的外部器
件并可实现低待机电流。
该开关模式电源 (SMPS) 器件采用 D-CAP2 模式控
制，能够提供快速瞬态响应，并且在无需外部补偿器件
的情况下支持专用聚合物等低等效串联电阻 (ESR) 输
出电容以及超低 ESR 陶瓷电容器。
• 580kHz 开关频率
小于 3µA 的低关断电流
• 1.5% 反馈电压精度 (25°C)
•
•
•
•
•
•
支持预偏置启动
TPS562207S 采用强制连续导通模式 (FCCM) 运行，
从而保持固定的开关频率并实现很小的输出电压纹波。
TPS562207S 采用 6 引脚 1.6mm × 1.6mm SOT563
(DRL) 封装，额定结温范围为 –40°C 至 125°C。
逐周期过流限制
断续模式过流保护
非锁存欠压保护 (UVP) 和热关断 (TSD) 保护
固定软启动：1.2ms
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
TPS562207S
DRL (6)
1.60mm x 1.60mm
•
•
•
•
•
电视 SMPS 电源
智能扬声器
有线网络
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
数字机顶盒 (STB)
监控
100%
90%
80%
70%
60%
50%
40%
30%
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
20%
10%
0
0.001
0.01
0.1
1
2
Iload (A)
简化版原理图
Eff
TPS562207S 效率
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEE2
TPS562207S
ZHCSM44 – OCTOBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................16
11 Layout...........................................................................17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Receiving Notification of Documentation Updates..18
12.2 Support Resources................................................. 18
12.3 Trademarks.............................................................18
12.4 Electrostatic Discharge Caution..............................18
12.5 Glossary..................................................................18
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
October 2020
*
Initial release
5 Device Comparison Table
PART NUMBER
WORK MODE AT LIGHT LOADING
TPS562202S
ECO
TPS562207S
FCCM
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6 Pin Configuration and Functions
1
VIN
SW
6
FB
EN
2
3
5
4
GND
BST
图 6-1. 6-Pin SOT563 DRL Package (Top View)
表 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
1
I
Input voltage supply pin
SW
2
O
Switch node connection between high-side NFET and low-side NFET
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive FB to this GND at a single point.
GND
BST
3
4
—
Supply input for the high-side NFET gate drive circuit. Connect a 0.1-μF capacitor between
the BST and SW pin.
O
EN
FB
5
6
I
I
Enable input control. Active high and must be pulled up to enable the device.
Converter feedback input. Connect to output voltage with feedback resistor divider.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN, EN
BST
25
V
BST (10 ns transient)
27
V
Input voltage
BST (vs SW)
6.5
6.5
19
V
FB
V
SW
V
SW (10 ns transient)
21
V
–3.5
–40
–55
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.3
NOM
MAX
17
UNIT
VIN
Supply input voltage range
V
BST
23
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
BST (10 ns transient)
26
BST (vs SW)
6
VI
Input voltage range
EN
17
V
FB
5.5
17
SW
SW (10 ns transient)
20
TJ
Operating junction temperature
125
°C
7.4 Thermal Information
TPS562207S
DRL
THERMAL METRIC(1)
UNIT
6 PINS
141.0
75
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
RθJA _effective Junction-to-ambient thermal resistance with TI EVM board(2)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
42.0
25.5
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TPS562207S
THERMAL METRIC(1)
DRL
6 PINS
1.0
UNIT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
ψJT
ψJB
25.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) This RθJA_effective is tested on TI EVM board(2 layer, copper thickness is 2 OZ) at VIN = 12V, VOUT = 5V, IOUT = 2A , TA = 25oC.
7.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
Operating – non-switching
supply current
IVIN
VIN current, EN = 5 V, VFB = 1 V
590
1
750
3
µA
µA
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.35
1.05
400
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.8
VEN = 12 V
225
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
VFB input current
TA = 25°C
VFB = 1 V
792
804
0
816
mV
µA
IFB
±0.1
MOSFET
RDS(on)h
RDS(on)l
High-side switch resistance
Low-side switch resistance
140
84
TA = 25°C, VBST – SW = 5.5 V
mΩ
mΩ
TA = 25°C
CURRENT LIMIT
Low side FET source current
Iocl_l_source
2.24
3.1
1.1
4
A
A
limit
Low side FET sink current
limit
INocl_l_sink
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
160
25
Thermal shutdown
TSDN
°C
threshold(1)
ON-TIME TIMER CONTROL
tOFF(MIN)
SOFT START
Tss
Minimum off time
Soft-start time
VFB = 0.5 V
220
1.2
310
ns
ms
Internal soft-start time, Test Vout from 10% to 90%
VO = 1.05 V
FREQUENCY
Fsw
Switching frequency
580
kHz
OUTPUT UNDERVOLTAGE
VUVP
Output UVP threshold
Hiccup detect (H > L)
65%
2.2
18
THICCUP_WAIT Hiccup on time
ms
ms
THICCUP_RE
Hiccup time before restart
UVLO
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TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.0
3.6
0.4
MAX UNIT
Wake up VIN voltage
Shutdown VIN voltage
Hysteresis VIN voltage
4.3
UVLO
UVLO threshold
3.3
V
(1) Not production tested.
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7.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.7
0.65
0.6
811
809
807
805
803
801
799
797
795
0.55
0.5
0.45
0.4
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (oC)
Junction Temperature (oC)
IQ
Vref
图 7-2. FB Voltage vs Junction Temperature
图 7-1. Supply Current vs Junction Temperature
1.18
1.45
1.15
1.12
1.09
1.06
1.03
1
1.42
1.39
1.36
1.33
1.3
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (oC)
Junction Temperature (oC)
ENLt
ENHt
图 7-3. EN Off-threshold Voltage vs Junction
图 7-4. EN On-threshold Voltage vs Junction
Temperature
Temperature
260
230
200
170
140
110
80
150
130
110
90
70
50
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (oC)
Junction Temperature (oC)
HSR
LSR
图 7-5. High-Side Rds-On vs Junction Temperature
图 7-6. Low-Side Rds-On vs Junction Temperature
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640
600
560
520
480
440
640
600
560
520
480
440
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
4
6
8
10
Vin (V)
12
14
16
18
0
0.2 0.4 0.6 0.8
1
Iout_set (A)
1.2 1.4 1.6 1.8
2
Freq
Freq
图 7-7. Switching Frequency vs Input Voltage
图 7-8. Switching Frequency vs Output Current
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
30%
30%
Vin = 5 V
Vin = 9 V
Vin = 5 (V)
Vin = 9 (V)
20%
20%
Vin = 12 V
Vin = 17 V
Vin = 12 (V)
Vin = 17 (V)
10%
0
10%
0
0.001
0.01
0.1
Output Current (A)
1
2
0.001
0.01
0.1
1 2
I_load (A)
EffV
EffV
图 7-9. VOUT = 0.95 V Efficiency, L = 2.2 µH
图 7-10. VOUT = 1.05 V Efficiency, L = 2.2 µH
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
0.001
0.01
0.1
Output Current (A)
1
2
0.001
0.01
0.1
Output Current (A)
1
2
EffV
EffV
图 7-11. VOUT = 1.5 V Efficiency, L = 2.2 µH
图 7-12. VOUT = 1.8 V Efficiency, L = 2.2 µH
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 5 (V)
Vin = 9 (V)
Vin = 12 (V)
Vin = 17 (V)
Vin = 9 (V)
Vin = 12 (V)
Vin = 17 (V)
0
0.001
0.01
0.1
1
2
0.001
0.01
0.1
1
2
I_load (A)
I_load (A)
EffV
EffV
图 7-13. VOUT = 3.3 V Efficiency, L = 3.3 µH
图 7-14. VOUT = 5 V Efficiency, L = 4.7 µH
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8 Detailed Description
8.1 Overview
The TPS562207S is a 2-A synchronous buck converter. The proprietary D-CAP2 mode control supports low-
ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP2 mode control can reduce the output
capacitance required to meet a specific level of performance.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562207S is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and
inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to
reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2
mode control.
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8.3.2 Soft Start and Pre-Biased Soft Start
The TPS562207S have an internal 1.2-ms soft start. When the EN pin becomes high, the internal soft-start
function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at start-up, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage, VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
8.3.3 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain-to-source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
Vout, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter. This can cause the output voltage to fall. When the FB voltage falls below the UVP threshold
voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time (typically 24
µs) and re-starts after the hiccup time (typically 18 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
The TPS562207S works in Forced Continuous Conduction Mode (FCCM). To support light load operation, the
current flowing through low-side FET is allowed to be negative, which means the current flow from drain-to-
source of low-side FET. This negative current is compared with low-side FET sink current limit to prevent device
from being over-current damaged. Once the sink current crosses the limit, the low-side FET turns off and the
high-side FET turns on to limit the negative current from overcurrent.
8.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
8.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection. The device will resume normal working once the
temperature return below the recovery threshold value (typically 135°C).
8.4 Device Functional Modes
8.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562207S can operate in their normal switching modes. In continuous conduction mode (CCM), the
TPS562207S operates at a quasi-fixed frequency of 580 kHz.
8.4.2 Standby Operation
The TPS562207S can be placed in standby mode by asserting the EN pin low.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The devices are typical buck DC-DC converters. It typically uses to convert a higher dc voltage to a lower dc
voltage with a maximum available output current of 2 A. The following design procedure can be used to select
component values for the TPS562207S. This section presents a simplified discussion of the design process.
9.2 Typical Application
The application schematic in 图 9-1 was developed to meet the previous requirements. This circuit is available
as the evaluation module (EVM). The sections provide the design procedure.
图 9-1 shows the TPS562207S 4.3-V to 17-V input, 1.05-V output converter schematics.
图 9-1. 1.05-V/2-A Reference Design
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9.2.1 Design Requirements
表 9-1 shows the design parameters for this application.
表 9-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
Output voltage
4.3 to 17 V
1.05 V
Transient response, load step: 10% ~
90% of full loading
ΔVout = ±5%
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
200 mV
20 mV
2 A
580 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using 方程式 1 to calculate VOUT
.
To improve efficiency at very light loads, consider using larger value resistors. Too high of resistance will be more
susceptible to noise and voltage errors from the FB input current will be more noticeable.
Vout=0.804 x (1 + RFBT/RFBB)
(1)
9.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
=
2p LOUT ì COUT
(2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –
40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the
gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The
inductor and capacitor for the output filter must be selected so that the double pole of 方程式 2 is located below
the high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in 表 9-2.
表 9-2. Recommended Component Values
C8 + C9 (µF)
OUTPUT
VOLTAGE (V)
TYP L1
(µH)
CFF (pF)
R1 (kΩ)
R2 (kΩ)
MIN
20
20
20
20
20
20
20
20
20
20
TYP
44
44
44
44
44
44
44
44
44
44
MAX
110
110
110
110
110
110
110
110
110
110
0.85
0.9
1
0.55
1.2
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
2.2
2.2
2.2
2.2
2.2
2.2
2.2
3.3
3.3
4.7
-
-
2.4
-
1.05
1.2
1.5
1.8
2.5
3.3
5
3.0
-
4.9
-
8.6
-
12.3
21.0
31.0
52.0
-
-
10-220
10-220
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表 9-2. Recommended Component Values (continued)
C8 + C9 (µF)
OUTPUT
VOLTAGE (V)
TYP L1
(µH)
CFF (pF)
R1 (kΩ)
R2 (kΩ)
MIN
TYP
MAX
6.5
70.5
10.0
4.7
20
44
110
10-220
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using 方程式 3, 方程式
4, and 方程式 5. The inductor saturation current rating must be greater than the calculated peak current and the
RMS or heating current rating must be greater than the calculated RMS current.
V
- VOUT
VOUT
IN(MAX)
IlP-P
=
ì
V
LO ì fSW
IN(MAX)
(3)
(4)
IlP-P
IlPEAK = IO
+
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(5)
For this design example, the calculated peak current is 2.35 A and the calculated RMS current is 2.01 A. The
inductor used is a WE 74437349022.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562207S is intended for
use with ceramic or other low-ESR capacitors. Recommended values range from 20 µF to 110 µF. Use 方程式 6
to determine the required RMS current rating for the output capacitor.
VOUT ì V - VOUT
(
)
IN
ICO(RMS)
=
12 ì V ì LO ì fSW
IN
(6)
For this design two MuRata GRM21BR61A226ME44L 22-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
9.2.2.3 Input Capacitor Selection
The TPS562207S requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 1 to ground is necessary to provide additional high frequency filtering. The capacitor
voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Bootstrap Capacitor Selection
A typical 0.1-µF ceramic capacitor must be connected between the BST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
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9.2.3 Application Curves
1.07
1.07
1.06
1.05
1.04
1.03
1.06
1.05
1.04
1.03
0
0.4
0.8 1.2
Output Current (A)
1.6
2
4
6
8
10 12
Input Voltage (V)
14
16
18
Load
Load
图 9-2. Load Regulation with Different Loading
图 9-3. Load Regulation with Different Input
Voltage
Vin = 100 mV/div
Vout = 20 mV/div
SW = 5V/div
Iout = 2A/div
SW = 5V/div
Iout = 2A/div
1us/div
1us/div
图 9-4. Input Voltage Ripple
图 9-5. Output Voltage Ripple, Iout = 0.2 A
Vout = 20 mV/div
Vout = 500 mV/div
SW = 5V/div
Iout = 2A/div
SW = 5V/div
1us/div
10ms/div
图 9-6. Output Voltage Ripple, Iout = 2 A
图 9-7. Hiccup, Iout = 5 A
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Vout = 50 mV/div
Vout = 50 mV/div
Iout = 1A/div
Iout = 1A/div
400us/div
400us/div
图 9-8. Transient Response, 0.2 to 1.8 A
图 9-9. Transient Response, 1 to 2 A
Vin = 5 V/div
EN = 2V/div
Vin = 5 V/div
EN = 5V/div
Vout = 500 mV/div
Vout = 500 mV/div
2ms/div
2ms/div
图 9-10. Start-Up Relative to VIN
图 9-11. Start-Up Relative to EN
Vin = 5 V/div
Vin = 5 V/div
EN = 5V/div
EN = 2V/div
Vout = 500 mV/div
Vout = 500 mV/div
2ms/div
2ms/div
图 9-12. Shutdown Relative to VIN
图 9-13. Shutdown Relative to EN
10 Power Supply Recommendations
The TPS562207S is designed to operate from input supply voltage in the range of 4.3 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO / 0.75.
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11 Layout
11.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the FB node should be as small as possible to avoid noise coupling.
10.The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
11.2 Layout Example
VIN
GND
CIN
RFBB
RFBT
VIN
SW
FB
EN
EN
Control
SW
GND
BST
CBST
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
图 11-1. TPS562207S Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
D-CAP2™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS562207SDRLR
ACTIVE
SOT-5X3
DRL
6
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
S207
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
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EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
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EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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相关型号：
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