TPS56300PWPR_技术文档

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SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

PWP PACKAGE

(TOP VIEW)

D

2.8 V – 5.5 V Input Voltage Range

Programmable Dual Output Controller

Supports Popular DSP and Microcontroller

Core and I/O Voltages

− Switching Regulator Controls Core

Voltage

− Low Dropout Controller Regulates I/O

Voltage

1

2

3

4

5

6

7

8

9

28

VID0

VID1

SLOWST

VHYST

DROOP

OCP

IOUT

PWRGD

VSEN−LDO

NGATE−LDO

INHIBIT

27

26

25

24

23

22

21

20

19

18

17

16

15

VREFB

VSEN−RR

ANAGND

BIAS

VLDODRV

CPC1

Thermal

Pad

D

Programmable Slow-Start Ensures

Simultaneous Powerup of Both Outputs

IOUTLO

HISENSE

LOSENSE/LOHIB

HIGHDR

BOOT

BOOTLO

LOWDR

D

Power Good Output Monitors Both Outputs

10

D

Fast Ripple Regulator Reduces Bulk

Capacitance for Lower System Costs

11

12

13

14

V

CC

CPC2

VDRV

DRVGND

D

1.5% Reference Voltage Tolerance

Efficiencies Greater than 90%

Overvoltage, Undervoltage, and Adjustable

Overcurrent Protection

PowerPAD Package

D

Drives Low-Cost Logic Level N-Channel

MOSFETs Through Entire Input Voltage

Range

D

Evaluation Module TPS56300EVM−139

Available

description

The high performance TPS56300 synchronous-buck regulator provides two supply voltages to power the core and

I/O of digital signal processors, such as the ‘C6000 family. The ripple regulator, using hysteretic control with droop

compensation, is configured for the core voltage and features fast transient response time reducing output bulk

capacitance (continued).

typical design

See Note A

+

NOTE A: See Table 1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments Incorporated.

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Copyright  2000, Texas Instruments Incorporated

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1

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ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

description (continued)

The LDO controller drives an external N-channel power MOSFET and functions as an LDO regulator, suitable for

powering the I/O or as a power distribution switch. To promote better system reliability during power up, voltage

sequencing and protection are controlled such that the core and I/O power up together with the same slow-start

voltage. At power down, the LDO and ripple regulator are discharged towards ground for added protection. The

TPS56300 also includes inhibit, slowstart, and under-voltage lockout features to aide in controlling power

sequencing. A tri-level voltage identification network (VID) sets both regulated voltages to any of 9 preset voltage

pairs from 1.3 V to 3.3 V. Other voltages are possible by implementing an external voltage divider. Strong MOSFET

drivers, with a typical peak current rating of 2-A sink and source are included on chip, enabling high system currents

beyond 30 A. The high-side driver features a floating bootstrap driver with the internal bootstrap synchronous rectifier.

Many protection features are incorporated within the device to ensure better system integrity. An open-drain output

POWER GOOD status circuit monitors both output voltages, and is pulled low if either output fall below the threshold.

An over current shutdown circuit protects the high-side power MOSFET against short-to-ground faults at load or the

phase node, while over voltage protection turns off the output drivers and LDO controller if either output exceeds its

threshold. Under voltage protection turns off the high-side and low-side MOSFET drivers and the LDO controller if

either output is 25% below V

. Lossless current-sensing is done by detecting the drain-source voltage drop across

REF

the high-side power MOSFET while it is conducting. The TPS56300 is fully compliant with TI DSP power requirements

such as the ‘C6000 family.

AVAILABLE OPTIONS

PACKAGES

T

J

EVALUATION MODULE

TSSOP

(PWP)

†

−40°C to 125°C

TPS56300PWP

TPS56300EVM−139 (SLVP139)

†

The PWP package is also available taped and reel. To order, add an R to the end of

the part number (e.g., TPS56300PWPR).

2

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ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

functional block diagram

LOSENSE/

LOHIB

19

IOUTLO HISENSE

IOUT

PWRGD

25

21

20

26

+

−

8

Bias

>0.93xVSEN−RR

VDRV >0.93xVSEN−LDO

Reg.

9

VLDODRV

22

SHUTDOWN

INHIBIT

VDRV UVLO

Vcc UVLO

Delay

INHIBIT

11

10

Vcc

HIGHDR

RR_OVP

Fault

Latch

S

LDO_OVP

CPC1

Q

RR_UVP *

R

LDO_UVP *

BOOT

12

CPC2

SHUTDOWN

27

24

23

OCP

VDRV

+

−

125 mV

5 V

13

VDRV

VSEN−LDO

NGATE−LDO

SHUTDOWN

VLDODRV

E/A

1

2

VID0

VID1

−

+

SLOWST

SHUTDOWN

Vref_LDO

VID

See table 1

Vbias

Hysteresis

Comparator

SLOWST

17

18

16

15

BOOT

Ivrefb/5

Vref_RR

SLOWST

Adaptive

Deadtime

3

+

HIGHDR

BOOTLO

−

SHUTDOWN

Hysteresis

Setting

VDRV

SHUTDOWN

LOWDR

7

5

4

28

6

14

ANAGND

RR−Ripple Regulator

VREFB

VHYST DROOP VSEN−RR

DRVGND

* UVP is disabled during

slowstart

Synchronous

FET

3

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ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

Terminal Functions

TERMINAL

DESCRIPTION

NAME

VID0

NO.

1

Voltage Identification input 0. VID pins are tri-level programming pins that set the output voltages for both convert-

ers. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to

Vbias/2, allowing floating voltage set to logic 1 (see table 1).

VID1

2

3

Voltage Identification input 1 (see VID0 above and table 1).

SLOWST

Slow start (soft start). A capacitor from pin 3 to GND sets the slowstart time for VOUT-RR and VOUT-LDO. Both

supplies will ramp-up together while tracking the slow-start voltage.

VHYST

4

5

6

Hysteresis set pin. The hysteresis is set by 2 × (VREFB − Vhyst).

VREFB

Buffered ripple regulator reference voltage from VID network.

VSEN-RR

Ripple regulator VOLTAGE SENSE input. This pin is connected to the ripple regulator output. It is used to sense

the ripple regulator voltage for regulation, OVP, UVP, and Powergood functions.. It is recommended that an RC

low pass filter be connected at this pin to filter high frequency noise.

ANAGND

BIAS

7

8

9

Analog ground

Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.

VLDODRV

Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + V – 300mV. Used

IN

as supply for LDO driver and Bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.

CPC1

10

11

Connect one end of Charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to

CPC2.

V

CC

3.3 V or 5 V supply (2.8 V – 5.5 V). Recommended that a low ESR capacitor be connected directly from V

DRVGND. (Bulk capacitors supplied at power stage input).

to

CC

CPC2

VDRV

12

13

Other end of charge pump capacitor from CPC1.

Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5V). Recom-

mended that a 10-µF capacitor be connected to DRVGND.

DRVGND

LOWDR

BOOTLO

BOOT

14

15

16

17

Drive ground. Ground for FET drivers. Connect to source of low-side FET.

Low drive. Output drive to synchronous rectifier low-side FET.

Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.

Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET

driver.

HIGHDR

18

19

High drive. Output drive to high-side power switching FETs

LOSENSE/

LOHIB

Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in cur-

rent sensing and the anti-cross-conduction to eliminate shoot-through current.

HISENSE

IOUTLO

INHIBIT

20

21

22

High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.

Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.

Inhibits the drive signals to the MOSFET drivers. IC is in low Iq state if INHIBIT is grounded. It is recommended

that an external pullup resistor be connected to 5 V.

NGATE-LDO

VSEN−LDO

23

24

Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.

LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation,

OVP, UVP, and power good functions.

PWRGD

25

Power good. Power good signal goes high when output voltage is about 93% of V

LDO. This is an open-drain output.

for both ripple regulator and

REF

4

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SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

Terminal Functions (continued)

TERMINAL

NAME

IOUT

I/O

DESCRIPTION

NO.

26

Current signal output. Output voltage on this pin is proportional to the load current as measured across

the high-side FETs on-resistance. The voltage on this pin equals 2 × R

× IOUT, where Ron is the

ON

equivalent on-resistance of the high-side FETs

OCP

DROOP

27

28

Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between

IOUT pin and ANAGND.

Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current.

The amount of droop compensation is set with a resistor divider between the IOUT pin and ANAGND.

§¶

Table 1. Voltage Identification Code

†

‡

VREF−LDO

VID Terminals

VREF−RR

(Vdc)

VID1

VID0

0

1

2

0

1

2

0

1

2

0

1

2

1.30

1.50

1.30

1.80

1.30

2.50

1.30

1.50

1.80

1.5

1.80

3.30

1.30

3.30

2.50

3.30

2.50

†

‡

§

0 = ground (GND), 1 = floating(Vbias/2), 2 = (Vbias)

RR = Ripple Regulator, LDO = Low Drop-Out Regulator

Vbias/2 is internal, leave VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used to

avoid erroneous level.

External resistors may be used as a voltage divider (from V

voltages to other values.

¶

to VSEN−xx to Gnd) to program output

OUT

5

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SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

†

absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)

Supply voltage range, V

(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

CC

Input voltage range: VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V

BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

BOOTLO to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 15 V

DRV to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

BIAS to ANAGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+ 0.3 V

CC

OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

VID0, VID1 (tri-level terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VBIAS + 0.3 V

PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

LOSENSE, LOHIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 14 V

IOUTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V

HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

VSEN−LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

VSEN−RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mV

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

‡

PWP

T

A

< 25°C

Derating Factor

0.0358 W/°C

T

A

= 70°C

T = 85°C

A

PowerPAD mounted

PowerPAD unmounted

3.58 W

1.78 W

1.96 W

0.98 W

1.43 W

0.71 W

0.0178 W/°C

JUNCTION-CASE THERMAL RESISTANCE TABLE

Junction-case thermal resistance 0.72 °C/W

‡

Test Board Conditions:

1. Thickness: 0.062”

2. 3”x 3” (for packages < 27 mm long)

3. 4” x 4” (for packages > 27 mm long)

4. 2 oz. Copper traces located on the top of the board (0.071 mm thick )

5. Copper areas located on the top and bottom of the PCB for soldering

6. Power and ground planes, 1oz. Copper (0.036 mm thick)

7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch

8. Thermal isolation of power plane

For more information, refer to TI technical brief SLMA002.

6

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

input

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

V

CC

Supply voltage range

2.8

3.3

5.5

V

INHIBIT = 0 V,

= 5 V

I

Quiescent current

15

mA

CC

V

CC

NOTE 2. Ensured by design, not production tested.

reference/voltage identification

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

D0−D1 High level input voltage (2)

Vbias − 0.3 V

V

bias

* 1

2

bias

2

D0−D1 Mid level floating voltage (1)

V

) 1

D0−D1 Low level input voltage (0)

Input pull-to-mid resistance

cumulative reference

0.3

V

36.5

73

95

KΩ

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

V

= 1.3 V,

Hysteresis window = 30 mV,

REF

T = 25°C

−1.3

0.25

1.3

J

V

= 1.3 V,

Hysteresis window = 30 mV,

See Note 2

REF

T = −40°C,

−0.2

Cumulative accuracy ripple regulator

%

J

V

= full range, Hysteresis window = 30 mV,

REF

Droop = 0,

−1.5

−2

1.5

See Note 2

V

= 1.3 V,

I =0.1 A,

O

REF

Closed Loop,

T = 25°C,

Pass device = IRFZ24N,

See Note 2

2

J

Cumulative accuracy LDO

%

V

= full range,

I =0.1 A,

O

Pass device = IRFZ24N,

REF

Closed Loop,

See Note 2

−2.5

2.5

NOTE 2. Ensured by design, not production tested.

hysteretic comparator(ripreg)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Input bias current

See Note 2

500

nA

mV

V

− V

= 15 mV,

VREFB

VHYST

Hysteresis accuracy

−3.5

60

3.5

Hysteresis window = 30mV

Maximum hysteresis setting

V

− V = 30 mV, See Note 2

VREFB

VHYST

Propagation delay time from VSENSE to

HIGHDR or LOWDR

(excluding deadtime)

10 mV overdrive, 1.3 V <= V

See Note 2

<= 3.3 V

REF

150

5

250

ns

Prefilter pole frequency

See Note 2

MHz

NOTE 2. Ensured by design, not production tested.

7

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ꢇ

ꢂ

ꢁ

ꢌ

ꢍ

ꢒ

ꢓ

ꢂ

ꢈ

ꢁ

ꢊ

ꢔ

ꢕ

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ꢏ

ꢀ

ꢓ

ꢌ

ꢊ

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ꢍ

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ꢂ

ꢒ

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ꢒ

ꢏ

ꢕ

ꢎ

ꢏ

ꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

overvoltage protection

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

OVP ripple regulator trip point (RR)

Upper threshold

112

115

120

%V

REF

Upper threshold − lower threshold,

See Note 2

Hysteresis (RR)

10

1

mV

Comparator propagation delay time (RR)

V

= 30mV,

See Note 2

µs

overdrive

Deglitch time (includes comparator

propagation delay time) (RR)

V

2.25

112

11

overdrive

OVP LDO trip point (LDO)

Hysteresis (LDO)

Upper threshold

115

10

1

120

%V

REF

Upper threshold − lower threshold,

See Note 2

mV

µs

Comparator propagation delay time (LDO)

V

= 50mV,

See Note 2

overdrive

Deglitch time (includes comparator

propagation delay time) (LDO)

V

2.25

11

µs

overdrive

NOTE 2. Ensured by design, not production tested.

undervoltage protection

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

UVP ripple regulator trip point (RR)

Lower threshold

70

75

80

%V

REF

Upper threshold − lower threshold,

See Note 2

Hysteresis (RR)

10

1

mV

Comparator propagation delay time (RR)

V

= 50mV,

See Note 2

µs

overdrive

Deglitch time (includes comparator

propagation delay time) (RR)

V

0.1

70

1

ms

overdrive

UVP LDO trip point (LDO)

Hysteresis (LDO)

Lower threshold

75

10

1

80

%V

REF

Upper threshold − lower threshold,

See Note 2

mV

µs

Comparator propagation delay time (LDO)

V

= 50mV,

See Note 2

overdrive

Deglitch time (includes comparator

propagation delay time) (LDO)

V

0.1

1

ms

overdrive

NOTE 2. Ensured by design, not production tested.

inhibit comparator

PARAMETER

CONDITIONS

MIN

TYP

2.1

MAX UNITS

2.35

V

Start threshold

T = −40°C,

J

See Note 2

2.1

Stop threshold

1.79

V

NOTE 2. Ensured by design, not production tested.

VDRV UVLO

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Start threshold

Hysteresis

See Note 2

4.9

V

See Note 2

0.3

4.4

0.35

Stop threshold

NOTE 2. Ensured by design, not production tested.

8

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ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

slowstart

PARAMETER

CONDITIONS

MIN

10.4

3

TYP

MAX UNITS

V

= 0.5V,

(S/S)

Resistance from VREFB pin to ANAGND = 20 kΩ

VREFB = 1.3 V, Ichg = (I /5)

Charge current

13

15.6

µA

VREFB

= 1.3 V

Discharge current

V

(S/S)

mA

mV

nA

Comparator input offset voltage

Comparator input bias current

Hysteresis accuracy

10

100

7.5

See Note 2

10

−7.5

mV

ns

Comparator propagation delay

Overdrive = 10 mV,

See Note 2

560

1000

NOTE 2. Ensured by design, not production tested.

V

UVLO

CC

PARAMETER

CONDITIONS

MIN

TYP

2.72

2.71

MAX UNITS

See Note 2

2.80

V

Start threshold

Stop threshold

T = −40°C,

J

See Note 2

2.48

V

NOTE 2. Ensured by design, not production tested.

power good

PARAMETER

CONDITIONS

MIN

TYP

93

MAX UNITS

V

and VDRV above UVLO thresholds

90

95

IN

T = −40°C,

Undervoltage trip point ripple regulator

(VSENSE−RR)

%V

REF

See Note 2

and VDRV above UVLO thresholds

93

J

V

90

93

95

IN

T = −40°C,

Undervoltage trip point LDO

(VSENSE−LDO)

%V

REF

See Note 2

93

J

Output saturation voltage

Leakage current

I

=5 mA

0.5

1

0.75

V

O

V

= 4.5V

µA

mV

PGD

REF

= 1.3V, 1.5V, or 1.8V

= 2.5V, or 3.3V

50

75

Hysteresis

100

125

Comparator high–low transition time

(propagation delay only)

See Note 2

1

µs

Comparator low–high transition time

(propagation delay + deglitch)

See Note 2

0.2

2

ms

NOTE 2. Ensured by design, not production tested.

droop compensation

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

54 mV

Initial accuracy

V

= 50 mV

46

DROOP

overcurrent protection (RR)

PARAMETER

OCP trip point

MIN

TYP

MAX UNITS

118

130

142

300

mV

nA

µs

Input bias current

Comparator propagation delay time

V

= 30mV,

See Note 2

1

overdrive

Deglitch time (includes comparator

propagation delay time)

V

2.25

11

µs

overdrive

NOTE 2. Ensured by design, not production tested.

9

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ꢇ

ꢂ

ꢁ

ꢌ

ꢍ

ꢒ

ꢓ

ꢂ

ꢈ

ꢁ

ꢊ

ꢔ

ꢕ

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ꢀ

ꢓ

ꢌ

ꢊ

ꢒꢓ

ꢍ

ꢎ

ꢀꢖ

ꢂ

ꢒ

ꢗꢈ

ꢒ

ꢏ

ꢕ

ꢎ

ꢏ

ꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

high-side VDS sensing

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Gain

2

V/V

V

= 3.3 V,

V

= 3.2 V,

HISENSE

Differential input to Vds sensing amp = 100 mV

IOUTLO

Initial accuracy

194

69

208

250

mV

V

=2.8 V to 5.5 V,

− V

HISENSE

HISENSE IOUTLO

Common-mode rejection ratio

Sink current (IOUTLO)

75

dB

nA

µA

=100 mV

2.8 V < V

IOUTLO

< 5.5 V

V

= 0.5 V,

=2.8 V

V

=3.3 V,

IOUT

IOUTLO

HISENSE

Source current (IOUT)

500

50

V

= 0.05 V,

=3.3 V

=3.35 V,

IOUT

IOUTLO

HISENSE

Sink current (IOUT)

Output voltage swing

µA

V

=5.5 V,

=4.5 V,

=3 V,

R

= 10 kΩ

0

1.75

1.5

HISENSE

HISENSE =

IOUT

= 10 kΩ

V

0

0.75

LOSENSE high level input voltage

LOSENSE low level input voltage

LOSENSE high level input voltage

LOSENSE low level input voltage

LOSENSE high level input voltage

LOSENSE low level input voltage

=2.8 V,

=4.5 V,

=5.5 V,

See Note 2

1.77

V

1.49

2.4

2.85

3.80

3.2

90

6 V,

70

80

4.5 V,

3.6 V,

2.8 V,

100

120

180

Sample/hold resistance

Ω

90

120

V

= 2.55 V,

HISENSE

pulsed from 2.55 V to 2.45 V,

4

3.5

3

IOUTLO

100 ns rise and fall times,

See Note 2

V

= 2.8 V,

HISENSE

pulsed from 2.8 V to 2.7 V,

IOUTLO

100 ns rise and fall times,

See Note 2

Response time (measured from 90% of

µs

V

to 90% of V )

V

= 4.5 V,

IOUTLO

IOUT

HISENSE

pulsed from 4.5V to 4.4V,

IOUTLO

100 ns rise and fall times,

See Note 2

V

= 5.5 V,

HISENSE

pulsed from 5.5 V to 5.9 V,

3

IOUTLO

100 ns rise and fall times,

See Note 2

500

100

Short circuit protection rising edge delay

Sample/hold switch turnon/turnoff delay

LOSENSE grounded,

See Note 2

300

30

ns

2.8V < V

V

< 5.5V,

HISENSE

= V

,

See Note 2

LOSENSE

HISENSE

NOTE 2. Ensured by design, not production tested.

10

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

buffered reference

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

REF

+1.5%

REF

I

=50 µA,

Accuracy from V

nominal

V

REF

REFB

REF

−1.5%

VREFB output voltage

V

Accuracy from V

See Note 2

REFB

J

REF

V

−0.6%

REF

T = −40°C,

VREFB load regulation

10 µA < I

REFB

< 500 µA

2

mV

NOTE 2. Ensured by design, not production tested.

thermal shutdown

PARAMETER

CONDITIONS

MIN

TYP

145

10

MAX UNITS

Over temperature trip point

Hysteresis

See Note 2

°C

NOTE 2. Ensured by design, not production tested.

synch charge pump regulator

PARAMETER

CONDITIONS

MIN

200

5.05

TYP

300

5.2

MAX UNITS

Internal oscillator frequency

2.8 V < V < 5.5 V, I

IN DRV

= 50 mA,

VDRV=5 V

See Note 2

400

kHz

V

Internal oscillator turnon threshold

Internal oscillator turnon hysteresis

V

above UVLO threshold,

CC

V

20

mV

NOTE 2. Ensured by design, not production tested.

hysteretic comparator (charge pump)

PARAMETER

CONDITIONS

above UVLO threshold,

MIN

TYP

MAX UNITS

Threshold

Hysteresis

V

See Note 2

5.05

5.2

V

IN

above UVLO threshold,

20

mV

IN

NOTE 2. Ensured by design, not production tested.

bias regulator

PARAMETER

CONDITIONS

2.8V < V < 5.5 V, Rip reg operating See Note 3

MIN

TYP

MAX UNITS

Output voltage

6.1

V

IN

NOTE 3. The BIAS regulator is designed to provide a quiet bias supply for TPS56300 controller. External loads should not be driven by the BIAS

Regulator.

deadtime circuit

PARAMETER

LOSENSE/LOHIB high level input voltage

LOSENSE/LOHIB low level input voltage

LOWDR high level input voltage

LOWDR low level input voltage

Driver nonoverlap time

CONDITIONS

MIN

TYP

MAX UNITS

V

=2.55 V – 5.5 V, See Note 2

2.4

V

HISENSE

1.33

V

=2.55 V–5.5 V,

See Note 2

3

1.7

V

C

= 9 nF, 10% threshold on LOWDR, VDRV=5 V

40

170

ns

lowdr

NOTE 2. Ensured by design, not production tested.

11

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ꢇ

ꢂ

ꢁ

ꢌ

ꢍ

ꢒ

ꢓ

ꢂ

ꢈ

ꢁ

ꢊ

ꢔ

ꢕ

ꢌ

ꢏ

ꢀ

ꢓ

ꢌ

ꢊ

ꢒꢓ

ꢍ

ꢎ

ꢀꢖ

ꢂ

ꢒ

ꢗꢈ

ꢒ

ꢏ

ꢕ

ꢎ

ꢏ

ꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

output drivers (see Note 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Duty cycle < 2%,

tpw < 100 us,

= 4.5V,

V

– V

0.7

2

BOOT

BOOTLO

= 4V (sink),

See Note 2 and Figure 15

HIGHDR

Duty cycle < 2%,

tpw < 100 us,

V

– V

= 4.5V,

= 0.5V (src),

1.2

1.3

1.4

2

BOOT

BOOTLO

See Note 2 and Figure 15

HIGHDR

Peak output current

A

Duty cycle < 2%,

= 4.5 V,

tpw < 100 µs,

V

DRV

V

= 4 V (sink)

LOWDR

See Note 2 and Figure 15

Duty cycle < 2%, tpw < 100 us,

V

= 4.5 V,

V

= 0.5 V (src),

DRV

See Note 2 and Figure 15

LOWDR

V

– V

= 4.5 V, V

= 0.5 V

BOOT

See Note 2

BOOTLO

HIGHDR

= 4 V,

HIGHDR

5

V

– V

= 4.5V, V

BOOT

See Note 2

BOOTLO

45

Output resistance

Ω

V

= 4.5V,

V

= 0.5V, See Note 2

9

DRV

LOWDR

= 4.5V,

= 4V,

See Note 2

45

DRV

LOWDR

C = 3.3 nF,

V

= 4.5V,

l

BOOT

HIGHDR rise/fall time (see Note 7)

LOWDR rise/fall time (see Note 7)

60

40

ns

V

=grounded

BOOTLO

C = 3.3 nF,

V

DRV

= 4.5V

l

INHIBIT grounded,

< UVLO; VBOOT=6V,

BOOTLO grounded

V

10

µA

IN

High-side driver quiescent current

INHIBIT connected to +5 V,

Fswx = 200KHz,

BOOTLO = 0

V

> UVLO

IN

VBOOT = 5.5 V,

= 50 pF

2

mA

C

HIGHDR

See Note 2

NOTES: 2. Ensured by design, not production tested.

5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the R

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

of the MOSFET transistor when

ds(on)

LDO N-channel output driver

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

V

= 7.5V,

= 0.9 × V

V

=3 V(src),

LDODRV

IOSENSE

N−DRV

190

1.5

200

µA

,

See Note 2

LDOREF

Peak output current

V

= 7.5V,

= 1.1 × V

V

N−DRV

LDOREF

=0 V(snk),

LDODRV

IOSENSE

mA

,

Open loop voltage gain

V

= 5.5 V,

7.5 V ≥ V

≥ 0.5 V,

3000

(70)

V/V

(dB)

IN

NGATE−LDO

(V

/ V

)

See Note 2

NGATE−LDO SENSE−LDO

f=1 kHz,

C

=10 µF,

T =125 °C,

J

O

Power supply ripple rejection

60

dB

5.5 V ≥ V ≥ 2.55 V, See Note 2

IN

NOTE 2. Ensured by design, not production tested.

12

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

electrical characteristics T = −40° to 125°C, V

= 2.8 V to 5.5 V (unless otherwise noted)

J

CC

V

and V

discharge

SENSE−RR

SENSE−LDO

PARAMETER

CONDITIONS

= 1.5 VS,ee Note 2

MIN

TYP

MAX UNITS

V

discharge FET current satura-

discharge series resistance

discharge FET propagation

SENSE−RR

tion

V

5

mA

SENSE−RR

V

SENSE−RR

(limits current)

INHIBIT = 0 V,

See Note 2

V

IN

= 5.5 V

1

kΩ

V

SENSE−RR

delay time

100

ns

mA

kΩ

ns

V

discharge FET current satu-

discharge series

SENSE−LDO

ration

V

= 3.3 V,

See Note 2

= 5.5 V,

5

1

SENSE−LDO

V

SENSE−LDO

INHIBIT = 0 V,

See Note 2

V

IN

resistance (limits current)

V

discharge FET

SENSE−LDO

propagation delay time

NOTE 2. Ensured by design, not production tested.

detailed description

reference/voltage identification

The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and

a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are programmed with each VID

setting. The 2 VID pins are inputs to the VID selection network and are tri-level inputs that may be set to GND, floating

(internally 2.5V), or VDRV. The VID codes allow the controller to power both current and future DSP products. The

output voltages may also be programmed by external resistor voltage dividers for any values not included in the VID

code settings. Refer to Table 1 for the VID code settings. The output voltages of the VID network, VREF−RR &

VREF−LDO, are within 1.5% of the nominal setting for all the VID range of 1.3V to 3.3V. The reference tolerance

conditions include a junction temperature range of −40°C to +125°C and a V

supply voltage range of 2.8 V to 5.5

CC

V. The VREF−RR output of the reference/VID network is indirectly brought out through a buffer to the VREFB pin.

The voltage on this pin will be within 1.5% of VREF−RR. It is not recommended to drive loads with VREFB, other than

setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current

for the slowstart capacitor. Refer to the Slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by

2 external resistors and is centered around V

. The 2 external resistors form a resistor divider from VREFB to

REF

ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the comparator will be equal

to twice the voltage difference that is across the VREFB and VHYST pins. The propagation delay from the comparator

inputs to the driver outputs is 250 ns maximum. The maximum hysteresis setting is 60 mv.

low-side driver

The low-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the driver

is 2 amps typical, source and sink. The bias to the low-side driver is internally connected to the regulated synchronous

charge pump output.

13

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

detailed description (continued)

high-side driver

The high-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the driver

is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap driver or as

a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is developed from the

charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected between the VDRV and BOOT

pins, is a synchronously-rectified MOSFET for improved drive efficiency. The maximum voltage that can be applied

between the BOOT pin and ground is 14 V. The driver can be referenced to ground by connecting BOOTLO to

DRVGND, and connecting a voltage ≥ (4.5 V + V ) to the BOOT pin.

CC

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching

transitions by actively controlling the turn-on time of the MOSFET drivers. The high-side driver is not allowed to turn

on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed to turn on until

the voltage at the junction of the 2 FETs (Vphase) is below 2 V.

current sensing

Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the high-side

FET is on. The sampling network consists of an internal 60-Ω switch and an external hold capacitor. Internal logic

controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage

transitions high, and the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only

when the high-side FET is conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side

voltage.

droop compensation

The droop compensation network reduces the load transient overshoot / undershoot on V

, relative to V

by an external resistor

(see

OUT

REF

application information for more details). V

is programmed to a voltage greater than V

OUT

REF

divider from V

to the VSENSE pin to reduce the undershoot on V

during a low to high load transient. The

OUT

overshoot during a high to low load transient is reduced by subtracting the voltage that is on the DROOP pin from

. The voltage on the IOUT pin is divided down with an external resistor divider, and connected to the DROOP

V

pin.

REF

inhibit

INHIBIT is a TTL compatible comparator pin that is used to enable the controller. When INHIBIT is lower than the

threshold, the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high (above 2.1

V), the short across the slowstart capacitor is released and normal converter operation begins. When another system

logic supply is connected to the INHIBIT pin, this pin controls power sequencing by locking out controller operation

until the system logic supply exceeds the input threshold voltage of the inhibit circuit; thus the +3.3-V supply and

another system logic supply (either +5 V or +12 V) must be above UVLO thresholds before the controller is allowed

to start up. Toggling the INHIBIT pin down clears the fault latch.

V

& VDRV undervoltage lockout

CC

The V

undervoltage lockout circuit disables the controller while the V

supply is below the 2.8-V start threshold.

CC

The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the 4.9 V start

threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO drive is off, and the

slowstart capacitor will be shorted. When V

capacitor is released and normal converter operation begins.

and VDRV exceed the start threshold, the short across the slowstart

CC

14

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆ

ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

detailed description (continued)

slowstart

The slowstart circuit controls the rate at which VOUT−RR and VOUT−LDO power up (at same time). A capacitor is

connected between the SLOWST and ANAGND pins and is charged by an internal current source. The value of the

current source is proportional to the reference voltage, so that the charging rate of C

regulator reference voltage. The slowstart charging current is determined by the following equation:

is proportional to the ripple

slowst

I

VREFB

I

+

SLOWSTART

5

Where I

is the current flowing out of the VREFB pin. It is recommended that no additional loads be connected

VREFB

to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine

the slowstart charging current. The maximum current that can be sourced by the VREFB circuit is 500 µA. The

equation for the slowstart time is:

T

+ 5 C

R

SLOWSTART

VREFB

Where R

is the total external resistance from VREFB to ANAGND.

VREFB

power good

The power good circuit monitors for an undervoltage condition on VOUT−RR and VOUT−LDO. The powergood

(PWRGD) pin is pulled low if either VOUT−RR is 7% below VREF−RR, or VOUT−LDO is 7% below VREF−LDO.

PWRGD is an open drain output. The powergood pin is also pulled down, if either V

thresholds.

or VDRV are below their UVLO

CC

overvoltage protection

The overvoltage protection circuit monitors VOUT−RR and VOUT−LDO for an overvoltage condition. If VOUT−RR

or VOUT−LDO are 15% above their reference voltage, then a fault latch is set and both output drivers and LDO are

turned off. The latch will remain set until the V

to 5 µs deglitch timer is included for noise immunity.

or inhibit voltages go below their undervoltage lockout values. A 1-µs

CC

overcurrent protection

The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold is

adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage connected to

the OCP pin. If the voltage on the OCP pin exceeds 125 mV, then a fault latch is set and the output drivers are turned

off. The latch will remain set until the V

5-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power

FET against a short-to-ground fault on the terminal common to both power FETs.

or inhibit voltages go below their undervoltage lockout values. A 1-µs to

CC

undervoltage protection

The undervoltage protection circuit monitors VOUT−RR and VOUT−LDO for an undervoltage condition. If VOUT−RR

or VOUT−LDO is 15% below their reference voltage, then a fault latch is set and both output drivers and LDO are

turned off. The latch will remain set until the V

or inhibit voltages go below their undervoltage lockout values. A

CC

100-µs to 1-ms deglitch timer is included for noise immunity.

15

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

detailed description (continued)

synchronous charge pump

The regulated synchronous charge pump provides drive voltage to the low-side driver at VDRV (5V), and to the

high-side driver when the high-side driver is configured as a floating driver. The minimum drive voltage is 4.5V, (typical

5V). The minimum short circuit current is 80 mA. The bootstrap capacitor is used to provide Vdrive for the high-side

FET, the power for VLDODRV, and the bias regulator. Instead of diodes, synchronous rectified MOSFETs are used

to reduce voltage drop losses and allow a lower input voltage threshold. The charge pump oscillator operates at 300

kHz until the UVLO VDRV is set; after which it is synchronized to the converter switching frequency and is turned on

and off to regulate VDRV at 5 V.

The charge pump is designed to operate at a switching frequency of 200 kHz to 400 kHz. Operation at low frequency

may require larger capacitors on CPC and VDRV pin. High frequency (> 400 kHz) may not be possible.

power sequence

The VOUT−LDO voltage is powered up with respect to the same slowstart reference voltage as the VOUT−RR. Also,

at power down, the VOUT−RR and VOUT−LDO are discharged to ground through P-channel MOSFETs in series with

1-kΩ resistors.

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT

vs

V

UVLO HYSTERESIS

vs

CC

JUNCTION TEMPERATURE

13

12

11

10

180

175

170

165

160

155

150

V

= 3.3 V

CC

Inhibit = 0 V

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1

Figure 2

16

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆ

ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

TYPICAL CHARACTERISTICS

V

UVLO START THRESHOLD VOLTAGE

SLOWSTART CHARGE CURRENT

vs

CC

vs

JUNCTION TEMPERATURE

2.750

2.725

2.700

2.675

2.650

15

14

13

12

11

10

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 3

Figure 4

†

SLOWSTART TIME

vs

SUPPLY CURRENT (VREFB)

SLOWSTART TIME

vs

SLOWSTART CAPACITANCE

1000

100

10

V

= 3.3 V

= 1.3 V

= 0.1 µF

CC

(VREFB)

V

= 3.3 V

CC

= 1.3 V

(VREFB)

J

C

S

J

I

T

= 65 µA

T

= 27°C

= 25°C

100

10

1

0.1

0.0001

1

10

100

1000

0.0010

0.0100

0.1000

1

I

− Supply Current (VREFB) − µA

CC

Slowstart Capacitance − µF

Figure 5

Figure 6

17

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

TYPICAL CHARACTERISTICS

DRIVER

RISE TIME

vs

DRIVER

FALL TIME

vs

LOAD CAPACITANCE

1000

100

1000

100

T

J

= 27°C

T = 27°C

J

High Side

Low Side

10

1

0.1

1

0.1

1

10

100

1

10

100

C

− Load Capacitance − nF

C

− Load Capacitance − nF

L

Figure 7

Figure 8

DRIVER

HIGH-SIDE OUTPUT RESISTANCE

vs

LOW-SIDE OUTPUT RESISTANCE

vs

JUNCTION TEMPERATURE

5.0

8

7

6

5

4

3

2

1

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 9

Figure 10

18

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆ

ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

TYPICAL CHARACTERISTICS

DRIVER

INPUT CURRENT

vs

VDRV UVLO START THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

OUTPUT VOLTAGE

5

4.5

4

4.70

4.69

4.68

4.67

4.66

4.65

3.5

3

2.5

2

2 A Typical

1.5

1

4.5 V

3

0.5

0

1

2

4

5

6

7

8

9

0

25

50

75

100

125

V

O

− Output Voltage − V

T

J

− Junction Temperature − °C

Figure 11

Figure 12

RIPPLE REGULATOR

VDRV UVLO HYSTERESIS

vs

POWERGOOD THRESHOLD

vs

JUNCTION TEMPERATURE

300

280

260

240

220

200

180

160

140

120

100

94.00

93.75

93.50

93.25

93.00

92.75

92.50

92.25

92.00

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 13

Figure 14

19

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

TYPICAL CHARACTERISTICS

INHIBIT START THRESHOLD VOLTAGE

INHIBIT HYSTERESIS VOLTAGE

vs

JUNCTION TEMPERATURE

2.100

2.075

2.050

2.025

2.000

140

130

120

110

100

90

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 15

Figure 16

RIPPLE REGULATOR OVP THRESHOLD

RIPPLE REGULATOR UVP THRESHOLD

vs

JUNCTION TEMPERATURE

118

117

116

115

77

76

75

74

114

113

112

73

72

71

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 17

Figure 18

20

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆ

ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

TYPICAL CHARACTERISTICS

LDO OVP THRESHOLD

vs

OCP THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

118

117

116

115

114

113

112

135

133

131

129

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 19

Figure 20

LDO UVP THRESHOLD

vs

JUNCTION TEMPERATURE

77

76

75

74

73

72

71

0

25

50

75

100

125

T

J

− Junction Temperature − °C

Figure 21

21

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

The design shown in this datasheet is a reference design for a DSP application. An evaluation module (EVM),

TPS56300EVM−139 (SLVP139), is available for customer testing and evaluation. The following figure is an

application schematic for reference. The circuit can be divided into the power-stage section and the control-circuit

section. The power stage must be tailored to the input/output requirements of the application. The control circuit is

basically the same for all applications with some minor tweaking of specific values. Table 2 shows the values of the

power stage components for various output-current options.

LDO

POWER

STAGE

TP6

FB2

TP5

+

J2

+

JP3

†

R14

L1

3.3 uH

+

TP8

TP7

Q1:A

J1

Q4

TP1

TP11

TP9

TP3

U1

TPS56300PWP

TP4

TP2 Q1:B

+

Q5

+

TP10

FB1

JP1

JP2

RIPPLE REGULATOR POWER STAGE

CONTROL SECTION

†

When an output current greater than 4 A is desired on the ripple regulator, please add a 10 Ω resistor (R14) between pin 18 and Q1:A.

Because the EVM is configured for 4 A and below, R14 is 0 Ω and is not included on the module.

Figure 22. EVM Schematic

Table 2. EVM Input and Outputs

V

IN

5 V

I

V

RR

1.8 V

I

V

LDO

3.3 V

I

IN

4 A

RR

4 A

LDO

0.5 A

22

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

Table 3. Ripple Regulator Power Stage Components

Ripple Regulator Section

Ref Des

C3, C6

Function

4A (EVM Design)

C3: open

C6: 150 µF

(Sanyo,

8A

12A

20A

Input Bulk Ca-

pacitor

C3: 150 µF

C6: 150 µF

(Sanyo,

C3: 150 µF

C6: 150 µF

(Sanyo,

C3: 150 µF

C6: 2x150 µF

(Sanyo,

6TPB150M)

C11, C2

Input high−freq

Capacitor

C2: 0.1 µF

C11: 0.1 µF

(muRata

C2: 0.33 µF

C11: 0.1 µF

C11: 0.33 µF

(muRata

GRM39X7R104K016A,

0.1 µF, 16−V, X7R)

GRM39X7R104K016A,

0.1 µF, 16−V, X7R)

GRM39X7R104K016A, 0.1

µF, 16−V, X7R)

GRM39X7R334K016A,

0.33 µF, 16−V, X7R)

C13, C14

Output Bulk Ca-

pacitor

C13: 150 µF

(Sanyo, 6TPB150M)

C14: open

C13: 150 µF

(Sanyo, 6TPB150M)

C14: open

C13: 150 µF

C14: 150 µF

(Sanyo, 6TPB150M)

C15,C30,

C31

Output Mid−freq

Capacitor

C15: open

C15: 10 µF

C30: 10 µF

C31: 10 µF

(muRata

C31: 10 µF

(muRata

GRM39X7R106K016A,

10 µF, 16−V, X7R)

GRM39X7R106K016A,

10 µF, 16−V, X7R)

GRM39X7R106K016A, 10

µF, 16−V, X7R)

GRM39X7R106K016A,

10 µF, 16−V, X7R)

C16

Output High−freq open

Capacitor

0.1 µF

(muRata

0.1 µF

(muRata

0.1 µF

(muRata

GRM39X7R104K016A,

0.1 µF, 16−V, X7R)

GRM39X7R104K016A, 0.1

µF, 16−V, X7R)

GRM39X7R104K016A,

0.1 µF, 16−V, X7R)

L1

L2

Input filter

3.3 µH

1.5 µH

1 µH

Coilcraft

Coiltronics

DO3316P−332, 5.4 A

DO3316P−332,5.4 A

DO3316P−152,6.4 A

UP3B−1R0, 12.5−A

Output filter

3.3 µH

Coilcraft

3.3 µH

Coilcraft

1.5 µH

Coilcraft

3.3 µH

Micrometals,

DO3316P−332, 5.4 A

DO5022P−332HC, 10 A

DO5022P−152HC,

15 A

T68−8/90 Core w/7T, #16,

25 A

R8

Low Side Gate

Resistor

10 Ω

5.1 Ω

Q1A,Q4

Q1B,Q5

Power Switch

Q1A: Dual FET

IRF7311

Q4: IRF7811

Q5: IRF7811

Q4: 2xIRF7811

Q5: 2xIRF7811

Q4: 2xIRF7811

Synchronous

Switch

Q1B: Dual FET

IRF7311

Q5:

2xIRF7811

The values listed in Table 3 are recommendations based on actual test circuits. Many variations of the above are

possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not more,

dependent upon the layout than on the specific components, as long as the device parameters are not exceeded.

Fast-response, low-noise circuits require circuits require critical attention to the layout details.

23

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ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

Table 4. LDO Power Stage Components

LDO Section

Ref. Des

Q2:A

Part

V

IN

V

Description

OUT

†

IRF7811(EVM)

or

V

IN

V

IN

− V

DROPOUT

Used as a power distribution switch for LDO

output control

Si4410, IRF7413

FDS6680

Q2:A

Q2: B

IRF9410, Si9410

Low cost solution for low LDO output cur-

rent (V −V

)*I

< 1 W

IN OUT OUT

IRF7811

Higher current and still surface mount

1 W < (V −V )*I ) < 2 W

IN OUT OUT

IRLZ24N

High output current requiring heat sink. Low

cost but through−hole package.

(V −V

)*I

> 2 W

IN OUT OUT

†

V = I × Rdson. It should be as small as possible.

DROPOUT OUT

frequency calculation

With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the hysteresis

window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance in the output

inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and the turnon

resistance of high-side and low-side MOSFET. It is a very complex equation if everything is included. To make it more

useful to designers, a simplified equation is developed that considers only the most influential factors. The tolerance

of the result for this equation is about 30%:

–9

_ESR*ǒ_250 10

Ǔ

)T

ȡ

_dȣ

ǒ

Ǔ

V

V * V

ȧ

Ȥ

OUT

IN

OUT

C

out

Ȣ

f

+

s

–9

ǒ

_dǓ_) V

hys

ǒ

_INǓ

V

V ESR 250 10 ) T

L

* ESL V

IN

OUT

Where fs is the switching frequency (Hz); V

is the output voltage (V); V is the input voltage (V); C

is the output

IN

OUT

capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent series

inductance in the output capacitor (H); L

(S); Vhys is the hysteresis window (V).

is the output inductance (H); Td is output feedback RC filter time constant

OUT

hysteresis window

The changeable hysteresis window in TPS56300 is used for switching frequency and output voltage ripple

adjustment. The hysteresis window setup is decided by a two-resistor voltage divider on VREFB and VHYST pin. Two

times of the voltage drop on the top resistor is the hysteresis window. The formula is shown in the following:

R13

Vhyswindow = 2 × VREFB× (1 −

)

R11 + R13

Where Vhyswindow is the hysteresis window (V); VREFB is the regulated voltage from VREVB (pin 5); R11 is the

top resistor in the voltage divider; R13 is the bottom resistor in the voltage divider. The maximum hysteresis window

is 60 mV.

24

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

slowstart

Slowstart reduces the start-up stresses on the power-stage components and reduces the input current surge. The

minimum slowstart time is limited to 1 ms due to the power good function deglitch time. Slowstart timing is dependent

of the timing capacitor value on the slowstart pin. The following formula can be used for setting the slowstart timing:

T

+ 5 C

R

SLOWSTART

VREFB

is the capacitor value on SLOWST (pin 3). R is the total

VREFB

T

is the slowstart time; C

SLOWSTART

resistance on VREFB (pin 5).

SLOWSTART

current limit

Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. The IOUT signal

is used for the current limit and the droop function. The voltage at IOUT at the output current trip point will be:

V

+ R

I 2

IOUT

ON

O

R

is the high-side on-time resistance; I is the output current. The current limit is calculated by using the formula:

ON

O

_R4ǒ_{IO MAX}

ǒ

_* 0.125Ǔ

2 R

Ǔ

ON

R5 +

0.125

Where R4 is the bottom resistor in the voltage divider on OCP pin, and R5 is the top resistor; I

is the maximum

O(MAX)

current allowed; R

is the high-side FET on-time resistance.

ON

Since the FET on-time resistance varies according to temperature, the current limit is basically for catastrophic failure.

droop compensation

Droop compensation with the offset resistor divider from V

to the VSENSE is used to keep the output voltage in

OUT

range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during light

loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. This allows the output

voltage to swing a greater amount and still remain within the tolerance window. The maximum droop voltage is set

with R6 and R7:

R6

R6 ) R7

V

+ V

Ǔ

ǒ

Ǔ

ǒ

DROOP max

IOUT max

Where V

is the maximum droop voltage; V

is the maximum VIOUT that reflects the maximum

IOUT(max)

DROOP(max)

output current (full load); R6 is the bottom resistor of the divider connected to the DROOP pin, R7 is the top resistor.

The offset voltage is set to be half of the maximum droop voltage higher than the nominal output voltage, so the whole

droop voltage range is symmetrical to the nominal output voltage. The formula for setting the offset voltage is:

25

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ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

1

2

R12

_{R10 ) R12}Ǔ

ǒ

V

+

V

+ V

Ǔ

ǒ

OFFSET

DROOP max

O

Where V

is the desired offset voltage; V

is the droop voltage at full load; Vo is the nominal output

OFFSET

DROOP(max)

voltage; R10 is the top resistor of the offset resistor divider, and R12 is the bottom one.

Therefore, with the setup above, at light load, the output voltage is:

1

2

V

+ V

Ǔ

) V

+ V

)

Ǔ

V

ǒ

Ǔ

ǒ

O nom

And, at full load, the output voltage is:

+ V

OFFSET

O nom

DROOP

O NO LOAD

1

V

* V

+ V

*

Ǔ

V

ǒ

Ǔ

ǒ

Ǔ

O nom

OFFSET

O nom

DROOP

O FULL LOAD

2

output inductor ripple current

The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The equation

for calculating the inductor current ripple is exhibited in the following:

ǒ

Rdson ) R

_LǓ

V

* V

* I

out

IN

OUT

I

+

D Ts

ripple

L

OUT

Where I

voltage (V); I

is the peak-to-peak ripple current (A) through the inductor; V is the input voltage (V); V

is the output

ripple

IN

OUT

is the output current; Rdson is the on-time resistance of MOSFET (Ω); R is the output inductor

OUT

L

equivalent series resistance; D is the duty cycle; and Ts is the switch cycle (S). From the equation, it can be seen that

the current ripple can be adjusted by changing the output inductor value.

Example:

V

IN

= 5 V; V

= 1.8 V; I

= 5 A; Rdson = 10 mΩ; R = 5 mΩ; D = 0.36; Ts = 5 µs; L

= 6 µH

OUT

L

OUT

Then, the ripple I

= 1 A.

ripple

output capacitor RMS current

Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current in the

output capacitor can be calculated as:

∆I

12

I

=

O(rms)

Where I

(A).

is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple current

O(rms)

Example:

∆I = 1 A, so I_O(rms)= 0.29 A

input capacitor RMS current

The input capacitor RMS current is important for input capacitor design. Assuming the input ripple current totally goes

into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as:

26

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

2

1

12

(

)

₊Ǹ

I

D 1 * D )

D I

I(rms)

O

ripple

Where I

is the input RMS current in the input capacitor (A); I is the output current (A); Iripple is the peak-to-peak

O

I(rms)

output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the highest input RMS current

usually occurs at the lowest input voltage, so it is the worst case design for input capacitor ripple current.

Example:

I

= 5 A; D = 0.36; I

= 1 A,

O

ripple

Then, I

= 2.46 A

I(rms)

layout and component value consideration

Good power supply results will only occur when care is given to proper design and layout. Layout and component

value will affect noise pickup and generation and can cause a good design to perform with less than expected results.

With a range of current from milliamps to tens or even hundreds of amps, good power supply layout and component

selection, especially for a fast ripple controller, is much more difficult than most general PCB design. The general

design should proceed from the switching node to the output, then back to the driver section, and, finally, to placing

the low-level components. In the following list are several specific points to consider before layout and component

selection for TPS56300:

1. All sensitive analog components should be referenced to ANAGND. These include components connected

to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOSENSE/LOHIB.

2. The input voltage range for TPS56300 is low from 2.8-V to 5.5-V, so it has a voltage tripler (charge pump)

inside to deliver proper voltage for internal circuitry. To avoid any possible noise coupling, a low ESR

capacitor on V

is recommended.

CC

3. For the same reason in Item 2, the ANAGND and DRVGND should be connected as close as possible to

the IC.

4. The bypass capacitor should be placed close to the TPS56300.

5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power

FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection

to the FETs since BOOTLO will have large peak current flowing through it.

6. The bulk storage capacitors across V should be placed close to the power FETs. High-frequency bypass

IN

capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the

high-side FET and to the source of the low-side FET.

7. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the

high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize

differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to

where HISENSE connects to V , to reduce high-frequency noise coupling on HISENSE.

IN

The EVM board (SLVP-139) is used in the test. The test results are shown in the following.

27

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ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

RIPPLE OUTPUT

LOAD REGULATION (1.8 V)

RIPPLE OUTPUT EFFICIENCY (1.8 V)

100

80

1.83

V

IN

= 3.3 V

1.825

V

IN

= 5 V

V

IN

= 5 V

1.82

60

1.815

40

20

0

V

= 3.3 V

IN

1.81

1.805

1.8

0

1

2

3

4

5

0

1

2

3

4

5

I

O

− Output Current − A

I

O

− Output Current − A

Figure 23

Figure 24

RIPPLE OUTPUT

LINE REGULATION (1.8 V)

LDO OUTPUT

LOAD REGULATION (3.3 V)

1.83

3.32

3.315

3.31

1.825

1.82

1.815

1.81

3.305

3.3

1.805

1.8

3.295

3.29

2

3

4

5

6

7

2

3

4

5

6

7

V

IN

− Input Voltage − V

V

IN

− Input Voltage − V

Figure 25

Figure 26

28

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

HYSTERESIS CONTROL

TRANSIENT RESPONSE

DROOP COMPENSATION EFFECT

6

10

Load Current

4

2

5

0

400 A/µs

4 A

0

No Droop

280 mV

Recovery Time

−5

100

Output Voltage

200

0

−100

−200

100

0

220 mV

Output Voltage

With Droop

−100

0

5

10 15 20 25 30 35 40 45 50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

t − Time − µs

t − Time − ms

Figure 27

Figure 28

SLOWSTART

6

5

4

3.3 V

3

2

1

1.8 V

0

−1

−2

0

4

8

12 16 20 24 28 32 36 40

t − Time − ms

Figure 29

29

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

layouts

Figure 30. Top Layer

Figure 31. Bottom Layer (Top View)

30

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ꢇꢈꢉ ꢊꢋꢌ ꢈꢀ ꢁꢈ ꢀ ꢊ ꢌ ꢍꢋꢎ ꢏꢁꢈꢀꢋꢐ ꢌ ꢊꢀꢉ ꢑꢒ

ꢇꢂ ꢁ ꢁꢌ ꢍ ꢒꢓ ꢂꢈ ꢁꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊ ꢊꢒ ꢓ ꢍ ꢎꢀ ꢖ ꢂꢒ ꢗ ꢈꢒ ꢏ ꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

bill of materials

REF

PN

Description

MFG

Size

C

C1

10TPA33M

Std

Capacitor, POSCAP, 33 µF, 10 V Sanyo

Capacitor, Ceramic, 10 µF, 16 V Sanyo

Capacitor, POSCAP, 150 µF, 6 V Sanyo

Capacitor, Ceramic, 0.1 µF, 16 V Sanyo

C2, C20, C21, C30, C31

C3. C6, C8, C13, C25

1210

D

6TPB150M

Std

C4, C5, C11, C12, C23, C26,

C27,

603

C7, C22

C9

Std

Capacitor, Ceramic, 1 µF, 16 V

Sanyo

805

1210

603

D

Open

C10, C16

C14, C15

C17, C24

Capacitor, Ceramic, 1000 pF, 16 Sanyo

V

603

C18, C19

D1

Std

Capacitor, Ceramic, 1 µF, 16 V

Diode, LED, Green, 2.1 V SM

Inductor, 3.3 µH, 5.4 A

Sanyo

805

SML-LX2832G

DO3316P-332

ED2227

Lumwx

Coilcraft

1210

L1, L2

J1

0.5 × 0.37 in

5.08 mm

Terminal Block, 4-pin, 15 A, 5.08 OST

mm

J2

ED1515

Terminal Block, 3-pin, 6 A, 3.5

mm

OST

n, 6 A,

JP1, JP2

S1132-3-ND

Header, Right straight, 3-pin, 0.1 Sullins

ctrs, 0.3” pins

#S1132-3-ND

JP1shunt

J3

929950-00-ND

S1132-2-ND

Shunt jumper, 0.1” (for JP1)

3M

0.1”

Header, Right straight, 2-pin, 0.1 Sullins

ctrs, 0.3” pins

#S1132-2-ND

Q1

Open

SO-8

?

Q2:A, Q4, Q5

Q2:B

Q3

IRF7811

MOSFET, N-ch, 30 V, 10 mΩ

Open

2N7002DICT-N

MOSFET, N-ch, 115 mA, 1.2 Ω

Resistor, 10 kohms, 5 %

Resistor, 1 kohms, 1%

Resistor, 0 ohms, 1%

Diodes, Inc.

TO-236

603

1206

603

R3

std

R4

std

R5

std

R6

std

Resistor, 1 kohms, 1%

Resistor, 3.32 kohms, 1%

Resistor, 10 ohms, 5 %

Resistor, 2.7 ohms, 5 %

Resistor, 150 ohms, 5 %

Resistor, 100 ohms, 1 %

Resistor, 10 kohms, 5 %

Resistor, 20.0 kohms, 1 %

Test Point, Red

R7

std

R8

std

R9

std

R10

std

R11

std

R12

std

R13

std

TP1−TP10

TP11

240−345

131−4244−00

Farnell

Adaptor, 3.5-mm probe clip ( or

131−5031−00)

Tektronix

U1

TPS56300PWP

Dual controller

TSSOP−28pin

31

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ

ꢇ ꢈꢉꢊ ꢋꢌꢈ ꢀ ꢁꢈ ꢀ ꢊꢌ ꢍꢋꢎ ꢏꢁ ꢈꢀꢋꢐ ꢌꢊꢀꢉꢑ ꢒ

ꢇ ꢂꢁ ꢁꢌꢍ ꢒꢓ ꢂꢈ ꢁ ꢁꢊꢔ ꢕꢌ ꢏꢀ ꢓꢌ ꢊꢊ ꢒꢓ ꢍꢎ ꢀꢖ ꢂꢒ ꢗꢈ ꢒꢏꢕꢎ ꢏꢑ

SLVS261B − DECEMBER 1999 − SEPTEMBER 2000

APPLICATION INFORMATION

Power Supply

+

−

Load

5−V, 5−A Supply

0 − 4 A

−

+

6.8 Ohms

2 W

Note: All wire pairs should be twisted.

Figure 32. Test Setup

32

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS56300PWPR

HTSSOP PWP

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 28

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS56300PWPR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS56300PWPR
厂家：	TEXAS INSTRUMENTS
描述：	Dual Output, Low Input Voltage Controllers with Sequencing 28-HTSSOP 开关光电二极管
文件：	总40页 (文件大小：1178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS56300PWPR [TI]

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