TPS563300_技术文档

TPS563300

ZHCSPP3 –JULY 2022

采用SOT583 封装的TPS563300 3.8V 至28V、3A 同步降压转换器

1 特性

3 说明

• 专用于多种应用

TPS563300 是一款易于使用的高效同步降压转换器，

具有 3.8V 至 28V 的宽输入电压范围，并支持高达 3A

的持续输出电流和0.8V 至22V 的输出电压。

– 3.8V 至28V 输入电压范围

– 0.8V 至22V 输出电压范围

– 3A 持续输出电流

– 0.8V ± 1.5% 基准电压(25°C)

– –40°C 至150°C 的工作结温范围

– 集成式76mΩ和32mΩMOSFET

– 20µA 低静态电流（典型值）

– 以最大98% 的占空比运行

– 精密EN 阈值

该器件采用固定频率峰值电流控制模式，可实现快速瞬

态响应以及出色的线路和负载调节。该器件具有经过优

化的内部环路补偿功能，因此在宽输出电压和工作频率

范围内无需外部补偿元件。脉冲频率调制 (PFM) 模式

可在很大程度上提高轻负载效率。低静态电流特性有益

于在低功耗运行时延长电池寿命。该器件还具有展频功

能，有助于降低EMI 噪声。

• 解决方案尺寸小巧且易于使用

– 具有内部补偿的峰值电流模式

– 可实现高轻载效率的脉冲频率调制(PFM)

– 500 kHz 固定开关频率

该器件提供包括 OTP、OVP、UVLO、逐周期过流限

制以及断续模式 UVP 在内的全面保护。该器件采用

0.5mm 引脚间距的小型 SOT583 (1.6mm × 2.1mm) 封

装，并且具有经过优化的引脚排列，可简化 PCB 布局

并提供良好的EMI 性能。

– 低电磁干扰，具有扩展频谱性能

– 支持带预偏置输出的启动

– 用于高侧和低侧MOSFET 的逐周期过流限制

– 非闭锁OTP、OCP、OVP、UVP 和UVLO 保

护

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS563300

SOT583 (8)

1.60mm × 2.10mm

– 1.6mm × 2.1mm SOT583 封装

• 使用TPS563300 并借助WEBENCH^®Power

Designer 创建定制设计

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 楼宇自动化、电器、工业PC

• 多功能打印机、企业投影仪

• 便携式电子产品、联网外设

• 智能扬声器、监视器

• 具有5V、12V、19V、24V 输入的分布式电源系统

100

90

V_IN

VIN

GND

EN

BST

SW

FB

C_BST

C_IN

L

V_OUT

R_FBT

80

V_EN

C_OUT

R_FBB

NC

70

60

VOUT=3.3V

VOUT=5V

VOUT=12V

50

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2 3

TPS563300 效率（V_IN= 24V，f_SW= 500kHz）

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSES9

TPS563300

ZHCSPP3 –JULY 2022

www.ti.com.cn

Table of Contents

8 Application and Implementation..................................21

8.1 Application Information............................................. 21

8.2 Typical Application.................................................... 21

8.3 Best Design Practices...............................................30

8.4 Power Supply Recommendations.............................30

8.5 Layout....................................................................... 31

9 Device and Documentation Support............................34

9.1 Device Support......................................................... 34

9.2 Documentation Support............................................ 34

9.3 接收文档更新通知..................................................... 34

9.4 支持资源....................................................................34

9.5 Trademarks...............................................................34

9.6 Electrostatic Discharge Caution................................35

9.7 术语表....................................................................... 35

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................11

7.1 Overview................................................................... 11

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................19

Information.................................................................... 35

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

July 2022

*

Initial release

2

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5 Pin Configuration and Functions

NC

EN

FB

1

2

8

7

6

5

NC

BST

SW

VIN 3

4

GND

图5-1. 8-Pin SOT583 DRL Package (Top View)

表5-1. Pin Functions

Type⁽¹⁾

Description

Name

NO.

NC

1

A

Reserved pin. The user must leave this pin floating.

Enable input to converter. Driving EN high or leaving this pin floating enables the converter.

An external resistor divider can be used to implement an adjustable V_INUVLO function.

EN

2

3

Supply input pin to the internal LDO and high-side FET. Input bypass capacitors must be

directly connected to this pin and GND.

VIN

P

G

P

Ground pin. Connected to the source of the low-side FET as well as the ground pin for the

controller circuit. Connect to system ground and the ground side of C_INand C_OUT. The path

to C_INmust be as short as possible.

GND

SW

4

5

Switching output of the convertor. Internally connected to the source of the high-side FET

and drain of the low-side FET. Connect to the power inductor.

Bootstrap capacitor connection for the high-side FET driver. Connect a high-quality, 100-nF

ceramic capacitor from this pin to the SW pin.

BST

NC

FB

6

7

8

P

A

Reserved pin. The user must leave this pin floating.

Output feedback input. Connect FB to the tap of an external resistor divider from the output

to GND to set the output voltage.

(1) A = Analog, P = Power, G = Ground

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6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted⁽¹⁾

MIN

–0.3

–3

MAX

UNIT

V_IN

30

Input voltage

EN

6

FB

6

SW, DC

30

V

SW, transient < 10 ns

BST

31

Output voltage

SW + 6

6

–0.3

–40

–65

BST–SW

T_J

Operating junction temperature⁽²⁾

150

°C

T_stg

Storage temperature

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Operating at junction temperatures greater than 150°C, although possible, degrades the lifetime of the device.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/JEDEC

JS-002, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted⁽¹⁾

MIN

NOM

MAX

UNIT

V_IN

3.8

28

EN

5.5

Input voltage

–0.1

0.8

FB

5.5

V_OUT

22

V

SW, DC

28

–0.1

–3

SW, transient < 10 ns

BST

29

Output voltage

SW + 5.5

5.5

–0.1

0

BST-SW

Ouput current I_OUT

3

A

Temperature Operating junction temperature, T_J

150

°C

–40

(1) The Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee

specific performance limits. For compliant specifications, see the Electrical Characteristics.

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6.4 Thermal Information

DRL (SOT583), 8 PINS

THERMAL METRIC⁽¹⁾

UNIT

JEDEC⁽²⁾

EVM⁽³⁾

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

112.2

29.1

19.3

1.6

N/A

°C/W

N/A

Junction-to-top characterization parameter

Junction-to-board characterization parameter

N/A

19.2

N/A

Ψ_JB

Junction-to-ambient thermal resistance on official

EVM board

R_{θJA_EVM}

N/A

60.2

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design purposes. These

values were simulated on a standard JEDEC board. They do not represent the performance obtained in an actual application.

(3) The real R_θJAon TI EVM is approximately 60.2°C/W, test condition: V_IN= 24 V, V_OUT= 5 V, I_OUT= 3 A, T_A= 25°C

6.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life

of the product containing it. T_J= –40°C to +150°C, V_IN= 3.8 V to 30 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY (VIN PIN)

V_IN

Operation input voltage

3.8

28

V

µA

V

I_Q

Nonswitching quiescent current

Shutdown supply current

EN = 5 V, V_FB= 0.85 V

20

2

I_SHDN

V_EN= 0 V

Rising threshold

Falling threshold

Hysteresis

3.4

3.1

3.6

3.3

300

3.8

3.5

Input undervoltage lockout

thresholds

V_{IN_UVLO}

V

mV

ENABLE (EN PIN)

V_{EN_RISE}Enable threshold

V_{EN_FALL}

Rising enable threshold

Falling disable threshold

1.21

1.17

1.28

V

Disable threshold

1.1

I_p

I_h

EN pullup current

V_EN= 1.0 V

V_EN= 1.5 V

0.7

1.4

µA

EN pullup hysteresis current

VOLTAGE REFERENCE (FB PIN)

T_J= 25°C

788

784

800

812

816

0.15

mV

μA

V_FB

FB voltage

T_J= –40°C to 150°C

V_FB= 0.8 V

I_FB

Input leakage current

INTEGRATED POWER MOSFETS

R_{DSON_HS}High-side MOSFET on-resistance

R_{DSON_LS}Low-side MOSFET on-resistance

CURRENT LIMIT

76

32

T_J= 25°C, V_BST–SW = 5 V

mΩ

T_J= 25°C

I_{HS_LIMIT}

I_{LS_LIMIT}

I_{PEAK_MIN}

SOFT START

T_SS

High-side MOSFET current limit

4.2

2.9

5

5.8

4.5

A

Low-side MOSFET current limit

Minimum peak inductor current

3.8

0.75

Fixed internal soft-start time

Time from 0% × V_OUTto 100% × V_OUT

2

ms

OSCILLATOR FREQUENCY (RT PIN)

f_SWSwitching center frequency

450

500

550

kHz

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The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life

of the product containing it. T_J= –40°C to +150°C, V_IN= 3.8 V to 30 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

t_{ON_MIN}

Minimum ON pulse width

Minimum OFF pulse width

Maximum ON pulse width

70

ns

(1)

t_{OFF_MIN}

t_{ON_MAX}

140

7

ns

μs

OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION

112%

115%

5%

118%

OVP detect (L→H)

V_OVP

Output OVP threshold

Hysteresis

V_UVP

Output UVP threshold

65%

UVP detect (H→L)

UV hiccup ON time before entering

hiccup mode after soft start ends

t_{hiccup_ON}

256

μs

10.5 ×

t_SS

t_{hiccup_OFF}

UV hiccup OFF time before restart

S

THERMAL SHUTDOWN

(1)

T_SHDN

Thermal shutdown threshold

Shutdown temperature

Hysteresis

165

30

°C

(1)

T_HYS

SPREAD SPECTRUM FREQUENCY

f_SW

128

/

f_m

Modulation frequency

kHz

f_spread

Internal spread oscillator frequency

±6%

(1) Not production tested, specified by design

6

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6.6 Typical Characteristics

T_J= –40°C to 150°C, V_IN= 12 V, unless otherwise noted

5

4

3

2

1

0

140

120

100

80

60

40

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-1. Shutdown Current vs Junction Temperature 图6-2. High-Side R_DSONvs Junction Temperature

50

45

40

35

30

25

20

820

815

810

805

800

795

790

785

780

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-3. Low-Side R_DSONvs Junction Temperature 图6-4. Feedback Voltage vs Junction Temperature

1.35

1.3

1.25

1.2

1.3

1.25

1.2

1.15

1.1

1.15

1.1

1.05

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-5. Enable Threshold vs Junction Temperature 图6-6. Disable Threshold vs Junction Temperature

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3.65

3.6

3.5

3.45

3.4

3.35

3.3

3.55

3.5

3.25

3.2

3.45

3.15

3.1

3.4

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-7. V_INUVLO Rising Threshold vs Junction

图6-8. V_INUVLO Falling Threshold vs Junction

Temperature

600

575

550

525

500

475

450

425

400

5.2

5.15

5.1

5.05

5

4.95

4.9

4.85

4.8

-40

0

40

80

120

160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-9. Switching Frequency vs Junction

图6-10. High-Side Current Limit vs Junction

Temperature

4

3.9

3.8

3.7

3.6

3.5

3.4

117

116

115

114

113

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-11. Low-Side Current Limit vs Junction

图6-12. OVP Threshold vs Junction Temperature

Temperature

8

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66

100

95

90

85

80

75

70

65

60

55

50

65

64

Vin=6V

Vin=12V

Vin=19V

Vin=24V

63

-40 -20

0

20

40

60

80 100 120 140 160

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2 3

Junction Temperature (°C)

图6-13. UVP Threshold vs Junction Temperature 图6-14. Efficiency, V_OUT= 3.3 V, f_SW= 500 kHz, L =

4.7 µH

100

95

90

85

80

75

70

65

60

55

50

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

Vin=6V

Vin=12V

Vin=19V

Vin=24V

Vin=19V

Vin=24V

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2

3

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2 3

图6-15. Efficiency, V_OUT= 12 V , f_SW= 500 kHz, L =

图6-16. Load Regulation, V_OUT= 3.3 V,

12 µH

f_SW= 500 kHz

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

Iout=0A

Iout=0.03A

Iout=0.3A

Iout=1.5A

Iout=3A

-0.2

-0.4

-0.6

-0.2

-0.4

-0.6

-0.8

-1

Vin=19V

Vin=24V

-0.8

-1

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2

3

5

7.5 10 12.5 15 17.5 20 22.5 25 27.5 30

Vin (V)

图6-17. Load Regulation, V_OUT= 12 V,

图6-18. Line Regulation, V_OUT= 3.3 V,

f_SW= 500 kHz

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1

0.8

0.6

0.4

0.2

0

600

500

400

300

200

100

0

Iout=0A

Vin=6V

Iout=0.03A

Iout=0.3A

Iout=1.5A

Iout=3A

Vin=12V

Vin=19V

Vin=24V

Vin=30V

-0.2

-0.4

-0.6

-0.8

-1

12

14

16

18

20

22

24

26

28

30

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2 3

Vin (V)

图6-19. Line Regulation, V_OUT= 12 V,

图6-20. Switching Frequency vs Load Current,

f_SW= 500 kHz

V_OUT= 3.3 V

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7 Detailed Description

7.1 Overview

The TPS563300 is a 28-V, 3-A, synchronous buck (step-down) converter with two integrated n-channel

MOSFETs. The device employs fixed-frequency peak current control mode for fast transient response and good

line and load regulation. With the optimized internal loop compensation, the device eliminates the external

compensation components over a wide range of output voltage and switching frequency.

The integrated 76-mΩ and 32-mΩ MOSFETs allow for high-efficiency power supply designs with continuous

output currents up to 3 A. The feedback reference voltage is designed at 0.8 V. The output voltage can be

stepped down from 0.8 V to 22 V. The device is ideally suited for systems powered from the following power-bus

rails:

• 5-V

• 12-V

• 19-V

• 24-V

The TPS563300 has been designed for safe monotonic start-up into prebiased loads. The default start-up is at

V_INequal to 3.8 V. After the device is enabled, the output rises smoothly from 0 V to its regulated voltage. The

total operating current is 20 μA (typical) when not switching under no load. When the device is disabled, the

supply current is approximately 2 µA (typical). The pulse frequency modulation (PFM) mode maximizes the light

load efficiency. These features are extremely beneficial for long battery life time in low-power operation.

The EN pin has an internal pullup current that can be used to adjust the input voltage undervoltage lockout

(UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the

internal pullup current. This device also has frequency spread spectrum feature, which helps with lowering down

EMI noise.

The device has the on-time extension function with a maximum on time of 7 μs (typical). During the low dropout

operation, the high-side MOSFET can turn on up to 7 μs, then the high-side MOSFET turns off and the low-side

MOSFET turns on with a minimum off time of 140 ns (typical). The device supports the maximum 98% duty

cycle.

The device reduces the external component count by integrating the bootstrap circuit. The bias voltage for the

integrated high-side MOSFET is supplied by a capacitor between the BST and SW pins. A UVLO circuit monitors

the bootstrap capacitor voltage, V_BST-SW. When it falls below a preset threshold of 2.5 V (typical), the SW pin is

pulled low to recharge the bootstrap capacitor.

Cycle-by-cycle current limiting on the high-side MOSFET protects the device in overload situations and is

enhanced by a low-side sourcing current limit, which prevents current runaway. The TPS563300 provides output

undervoltage protection (UVP) when the regulated output voltage is lower than 65% of the nominal voltage due

to overcurrent being triggered, approximately 256-μs (typical) deglitch time later, both the high-side and low-

side MOSFET turn off and the device steps into hiccup mode.

The device minimizes excessive output overvoltage transient by taking advantage of the overvoltage

comparator. When the regulated output voltage is greater than 115% of the nominal voltage, the overvoltage

comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output

voltage is lower than 110%.

Thermal shutdown disables the device when the die temperature, T_J, exceeds 165°C and enables the device

again after T_Jdecreases below the hysteresis amount of 30°C.

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7.2 Functional Block Diagram

EN

VCC

Enable

LDO

VIN

I_SS

Precision

Enable

BST

HSI Sense

NC

REF

EA

FB

R_C

C_C

TSD

UVLO

PWM CONTROL LOGIC

PFM

SW

Detector

Slope

Comp

Ton_min/Toff_min

Detector

Freq

Foldback

HICCUP

Detector

Zero

Cross

LSI Sense

Oscillator

FB

GND

NC

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7.3 Feature Description

7.3.1 Fixed Frequency Peak Current Mode

The following operation description of the TPS563300 refers to the functional block diagram and to the

waveforms in 图 7-1. The TPS563300 is a synchronous buck converter with integrated high-side (HS) and low-

side (LS) MOSFETs (synchronous rectifier). The TPS563300 supplies a regulated output voltage by turning on

the HS and LS NMOS switches with controlled duty cycle. During high-side switch on time, the SW pin voltage

swings up to approximately V_IN, and the inductor current, i_L, increases with linear slope (V_IN– V_OUT) / L. When

the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot–through dead

time. Inductor current discharges through the low-side switch with a slope of –V_OUT/ L. The control parameter

of a buck converter is defined as Duty Cycle D = t_ON/ t_SW, where t_ONis the high-side switch on time and t_SWis

the switching period. The converter control loop maintains a constant output voltage by adjusting the duty cycle

D. In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

V_IN

D = t_ON/ T_SW

t_ON

t_OFF

t

0

T_SW

i_L

I_LPK

I_OUT

∆i_L

t

0

图7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS563300 employs the fixed-frequency peak current mode control. A voltage feedback loop is used to get

accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak

inductor current is sensed from the HS switch and compared to the peak current threshold to control the on time

of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external

components, making it easy to design, and provides stable operation with almost any combination of output

capacitors. The converter operates with fixed switching frequency at normal-load condition. At light-load

condition, the TPS563300 operates in PFM mode to maintain high efficiency.

7.3.2 Pulse Frequency Modulation

The TPS563300 is designed to operate in pulse frequency modulation (PFM) mode at light load currents to

boost light-load efficiency.

When the load current is lower than half of the peak-to-peak inductor current in CCM, the TPS563300 operates

in discontinuous conduction mode (DCM). In DCM operation, the low-side switch is turned off when the inductor

current drops to approximately 0 A to improve efficiency. Both switching losses and conduction losses are

reduced in DCM when compared to forced CCM operation at light load.

At even lighter current load, pulse frequency modulation (PFM) mode is activated to maintain high-efficiency

operation. When either the minimum high-side switch on time, t_{ON_MIN}, or the minimum peak inductor current,

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I_{PEAK_MIN}(typically 750 mA), is reached, the switching frequency decreases to maintain regulation. In PFM

mode, the switching frequency is decreased by the control loop to maintain output voltage regulation when load

current reduces. Switching loss is further reduced in PFM operation due to less frequent switching actions. Since

the integrated current comparator catches the peak inductor current only, the average load current entering PFM

mode varies with the applications and external output LC filters.

In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.

The duration of the burst depends on how long it takes the feedback voltage catches V_REF. The periodicity of

these bursts is adjusted to regulate the output, while zero current crossing detection turns off the low-side

MOSFET to maximize efficiency. This mode provides high light-load efficiency by reducing the amount of input

supply current required to regulate the output voltage at small loads. PWM trades off very good light-load

efficiency for larger output voltage ripple and variable switching frequency.

7.3.3 Voltage Reference

The internal reference voltage, V_REF, is designed at typical 0.8 V, the negative feedback system of converter

produces a precise ±2% feedback voltage V_FBover full temperature by scaling the output of a temperature

stable internal band-gap circuit.

7.3.4 Output Voltage Setting

A precision 0.8-V internal reference voltage, V_REF, is used to maintain a tightly regulated output voltage over the

entire operating temperature range. The output voltage is set by a resistor divider from the output voltage to the

FB pin. TI recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select

the bottom-side resistor, R_FBB, for the desired divider current and use 方程式 1 to calculate the top-side resistor,

R_FBT. Lower R_FBBincreases the divider current and reduces efficiency at very light load. Larger R_FBBmakes the

FB voltage more susceptible to noise, so the larger R_FBBvalue requires more carefully designed feedback path

on the PCB. Setting R_FBB= 10 kΩ and R_FBTin the range of 10 kΩ to 300 kΩ is recommended for most

applications.

The tolerance and temperature variation of the resistor dividers affect the output voltage regulation.

V_OUT

R_FBT

FB

R_FBB

图7-2. Output Voltage Setting

V_OUT- V_REF

R_FBT

=

× R_FBB

V_REF

(1)

where

• V_REFis 0.8 V.

• R_FBBis 10 kΩ (recommended).

7.3.5 Enable and Adjusting Undervoltage Lockout

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage exceeds the enable

threshold voltage, V_{EN_RISE}, the TPS563300 begins operation. If the EN pin voltage is pulled below the disable

threshold voltage, V_{EN_FALL}, the converter stops switching and enters shutdown mode.

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The EN pin has an internal pullup current source, which allows the user to float the EN pin to enable the device.

If an application requires control of the EN pin, use open-drain or open-collector or GPIO output logic to interface

with the pin.

The TPS563300 implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is

disabled when the VIN pin voltage falls below the internal V_{IN_UVLO}threshold. The internal V_{IN_UVLO}threshold

has a hysteresis of typical 300 mV. If an application requires a higher UVLO threshold on the VIN pin, the EN pin

can be configured as shown in 图 7-3. When using the external UVLO function, setting the hysteresis at a value

greater than 500 mV is recommended.

The EN pin has a small pullup current, I_p, which sets the default state of the EN pin to enable when no external

components are connected. The pullup hysteresis current, I_h, is used to control the hysteresis voltage for the

UVLO function when the EN pin voltage crosses the enable threshold. Use 方程式 2 and 方程式 3 to calculate

the values of R1 and R2 for a specified UVLO threshold. Once R1 and R2 are settled down, the V_ENcan be

calculated by 方程式4, which must be lower than 5.5 V with max V_IN.

VIN

Device

R1

R2

Ip

Ih

EN

图7-3. Adjustable V_INUndervoltage Lockout

(2)

(3)

(4)

R₁ì V_{EN_FALL}

R₂=

V_STOP- V_{EN_FALL}+ R ì I +I

(

)

1

p

h

R ì V +R ìR ì I +I

(

)

2

IN

1

2

p

h

V_EN

=

R₁+R₂

where

• I_pis 0.7 µA.

• I_his 1.4 µA.

• V_{EN_FALL}is 1.17 .

• V_{EN_RISE}is 1.21 V.

• V_STARTis the input voltage enabling the device.

• V_STOPis the input voltage disabling the device.

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7.3.6 Minimum On Time, Minimum Off Time, and Frequency Foldback

Minimum on time, t_{ON_MIN}, is the smallest duration of time that the high-side switch can be on. t_{ON_MIN}is typically

70 ns in the TPS563300. Minimum off time, t_{OFF_MIN}, is the smallest duration that the high-side switch can be off.

t_{OFF_MIN}is typically 140 ns. In CCM operation, t_{ON_MIN}and t_{OFF_MIN}limit the voltage conversion range without

switching frequency foldback.

The minimum duty cycle without frequency foldback allowed is:

D_MIN= t_{ON_MIN}× f_SW

(5)

The maximum duty cycle without frequency foldback allowed is:

D_MAX= 1 F t_{OFF _MIN}× f_SW

(6)

Given a required output voltage, the maximum V_INwithout frequency foldback is:

V_OUT

V

=

IN_MAX

f_SW× t_{ON_MIN}

(7)

The minimum V_INwithout frequency foldback is:

V_OUT

V

IN_MIN

=

1 F f_SW× t_{OFF _MIN}

(8)

In TPS563300, a frequency foldback scheme is employed once t_{ON_MIN}or t_{OFF_MIN}is triggered, which can

extend the maximum duty cycle or lower the minimum duty cycle.

The on time decreases while V_INvoltage increases. Once the on time decreases to t_{ON_MIN}, the switching

frequency starts to decrease while V_INcontinues to go up, which lowers the duty cycle further to keep V_OUTin

regulation according to 方程式5.

The frequency foldback scheme also works once larger duty cycle is needed under low V_INcondition. The

frequency decreases once the device hits its t_{OFF_MIN}, which extends the maximum duty cycle according to 方程

式 6. Wide range of frequency foldback allows the TPS563300 output voltage to stay in regulation with a much

lower supply voltage V_IN, which allows a lower effective dropout.

With frequency foldback, V_{IN_MAX}is raised, and V_{IN_MIN}is lowered by decreased f_SW

.

7.3.7 Frequency Spread Spectrum

In order to reduce EMI, the TPS563300 introduces frequency spread spectrum. The jittering span is typically Δfc

= ±6% of the switching frequency with the modulation frequency of f_m= f_SW/ 128. The purpose of spread

spectrum is to eliminate peak emissions at specific frequencies by spreading emissions across a wider range of

frequencies than a part with fixed frequency operation. 图7-4 shows the frequency spread spectrum modulation.

图7-5 shows the energy is spread out at the center frequency, f_c.

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fmax = fc * (1 + 6%)

Center Frequency fc

fmin = fc * (1 - 6%)

Modulation Frequency fm = fsw/128

图7-4. Frequency Spread Spectrum Diagram

Energy

f^m

Frequency

f_c

图7-5. Energy vs Frequency

7.3.8 Overvoltage Protection

The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.

The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. If the FB pin

voltage is greater than the OVP threshold of 115%, the high-side MOSFET is turned off, which prevents current

from flowing to the output and minimizes output overshoot. When the FB pin voltage drops lower than the OVP

threshold minus hysteresis, the high-side MOSFET is allowed to turn on at the next clock cycle. This function is

non-latch operation.

7.3.9 Overcurrent and Undervoltage Protection

The TPS563300 incorporates both peak and valley inductor current limits to provide protection to the device from

overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current

run-away during short circuits on the output, while both peak and valley limits work together to limit the maximum

output current of the converter. Hiccup mode is also incorporated for sustained short circuits.

The high-side switch current is sensed when it is turned on after a set blanking time (t_{ON_MIN}), the peak current

of high-side switch is limited by the peak current threshold, I_{HS_LIMIT}. The current going through the low-side

switch is also sensed and monitored. When the low-side switch turns on, the inductor current begins to ramp

down.

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As the device is overloaded, a point is reached where the valley of the inductor current cannot reach below

I_{LS_LIMIT}before the next clock cycle, then the low-side switch is kept on until the inductor current ramps below

the valley current threshold, I_{LS_LIMIT}, then the low-side switch is turned off and the high-side switch is turned on

after a dead time. When this occurs, the valley current limit control skips that cycle, causing the switching

frequency to drop. Further overload causes the switching frequency to continue to drop, but the output voltage

remains in regulation. As the overload is increased, both the inductor current ripple and peak current increase

until the high-side current limit, I_{HS_LIMIT}, is reached. When this limit is tripped, the switch duty cycle is reduced

and the output voltage falls out of regulation, which represents the maximum output current from the converter

and is given approximately by 方程式 9. The output voltage and switching frequency continue to drop as the

device moves deeper into overload while the output current remains at approximately I_OMAX. If the inductor ripple

current is large, the high-side current limit can be tripped before the low-side limit is reached. In this case, 方程式

10 gives the approximate maximum output current.

I_{HS _LIMIT}+I_{LS _LIMIT}

I_OMAX

ö

2

(9)

(V -V_OUT

)

V_OUT

IN

I_OMAXö I_{HS _LIMIT}

-

ì

2ìL ì f_SW

V

IN

(10)

Furthermore, if a severe overload or short circuit causes the FB voltage to fall below V_UVPthreshold, 65% of the

_REF, and triggering current limit, and the condition occurs for more than the hiccup on time (typically 256 μs),

V

the converter enters hiccup mode. In this mode, the device stops switching for hiccup off time, 10.5 × t_SS, and

then goes to a normal restart with soft-start time. If the overload or short-circuit condition remains, the device

runs in current limit and then shuts down again. This cycle repeats as long as the overload or short-circuit

condition persists. This mode of operation reduces the temperature rise of the device during a sustained

overload or short circuit condition on the output. Once the output short is removed, the output voltage recovers

normally to the regulated value.

7.3.10 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 165°C

(typical), the device goes into thermal shut down, both the high-side and low-side power FETs are turned off.

When T_Jdecreases below the hysteresis amount of 30°C (typical), the converter resumes normal operation,

beginning with a soft start.

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7.4 Device Functional Modes

7.4.1 Modes Overview

The TPS563300 moves among CCM, DCM, and PFM modes as the load changes. Depending on the load

current, the TPS563300 is in one of below modes:

• Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple

• Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation

• Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load

7.4.2 Heavy Load Operation

The TPS563300 operates in continuous conduction mode (CCM) when the load current is higher than half of the

peak-to-peak inductor current. In CCM operation, the output voltage is regulated by switching at a constant

frequency and modulating the duty cycle to control the power to the load. CCM provides excellent line and load

regulation and minimum output voltage ripple, and the maximum continuous output current of 3 A can be

supplied by the TPS563300.

7.4.3 Light-Load Operation

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the

device operates in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM

operation, the LS switch is turned off when the inductor current drops to I_{LS_ZC}(150 mA typical) to improve

efficiency. Both switching losses and conduction losses are reduced in DCM when compared to forced CCM

operation at light load.

At even lighter current load, pulse frequency modulation (PFM) mode is activated to maintain high efficiency

operation. When either the minimum on time, t_{ON_MIN}, or the minimum peak inductor current, I_{PEAK_MIN}(typically

750 mA) is reached, the switching frequency decreases to maintain regulation. In PFM mode, switching

frequency is decreased by the control loop to maintain output voltage regulation when load current reduces.

Switching loss is further reduced in PFM operation due to less frequent switching actions. The output current for

mode change depends on the input voltage, inductor value, and the programmed switching frequency. For

applications where the switching frequency must be known for a given condition, the transition between PFM

and CCM must be carefully tested before the design is finalized.

7.4.4 Dropout Operation

The dropout performance of any buck converter is affected by the R_DSONof the power MOSFETs, the DC

resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level

approaches the output voltage, the off time of the high-side MOSFET starts to approach the minimum value.

Beyond this point, the switching frequency becomes erratic and the output voltage can fall out of regulation. To

avoid this problem, the TPS563300 automatically reduces the switching frequency (on-time extension function)

to increase the effective duty cycle and maintain in regulation until the switching frequency reach to the lowest

limit of about 140 kHz, the period is equal to (t_{ON_MAX}+ t_{OFF_MIN}) (typically 7.14 μS). In this condition, the

difference voltage between V_INand V_OUTis defined as dropout voltage. The typical overall dropout

characteristics can be found as 图7-6.

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5.5

5

4.5

4

3.5

3

Io=0.5A

Io=3A

4

4.5

5

5.5

6

6.5

7

7.5

8

Vin (V)

图7-6. Overall Dropout Characteristic, V_OUT= 5 V

7.4.5 Minimum On-Time Operation

Every switching converter has a minimum controllable on time dictated by the inherent delays and blanking times

associated with the control circuits, which imposes a minimum switch duty cycle and, therefore, a minimum

conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend

the minimum controllable duty cycle, the TPS563300 automatically reduces the switching frequency when the

minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage

at the maximum input voltage. Use 方程式 11 to find an estimate for the approximate input voltage for a given

output voltage before frequency foldback occurs. The values of t_{ON_MIN}and f_SWcan be found in 节6.5.

V_OUT

V_IN≤

t_{ON_MIN}× f_SW

(11)

As the input voltage is increased, the switch on time (duty-cycle) reduces to regulate the output voltage. When

the on time reaches the minimum on time, t_{ON_MIN}, the switching frequency drops while the on time remains

fixed.

7.4.6 Shutdown Mode

The EN pin provides electrical ON and OFF control for the device. When V_ENis below typical 1.1 V, the

TPS563300 is in shutdown mode. The device also employs VIN UVLO protection. If V_INvoltage is below their

respective UVLO level, the converter is turned off too.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS563300 is a highly integrated, synchronous, step-down, DC-DC converter. This device is used to

convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 3 A.

8.2 Typical Application

The application schematic of 图 8-1 was developed to meet the requirements of the device. This circuit is

available as the TPS563300EVM evaluation module. The design procedure is given in this section.

图8-1. TPS563300 5-V Output, 3-A Reference Design

8.2.1 Design Requirements

表8-1 shows the design parameters for this application.

表8-1. Design Parameters

Parameter

Input voltage

Conditions

MIN

TYP

24

5

MAX

Unit

V

V_IN

5.5

28

V_OUT

I_OUT

Output voltage

Output current rating

V

3

A

Load step from 0.5 A→2.5 A→

0.5 A, 0.8-A/μS slew rate

±5% ×

V_OUT

Transient response

V

ΔV_OUT

V_IN(ripple)

V_OUT(ripple)

F_SW

Input ripple voltage

400

30

500

2

mV

kHz

mS

V

Output ripple voltage

Switching frequency

t_SS

Soft-start time

V_START

V_STOP

T_A

Start input voltage (Rising V_IN)

Stop input voltage (Falling V_IN)

Ambient temperature

8

7

V

25

°C

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Create a custom design using the TPS563300 with the WEBENCH^®Power Designer

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%

tolerance or better divider resistors. Referring to the application schematic of 图 8-1, start with 10.2 kΩ for R7

and use 方程式 12 to calculate R6 = 53.6 kΩ. To improve efficiency at light loads, consider using larger value

resistors. If the values are too high, the converter is more susceptible to noise and voltage errors from the FB

input leakage current are noticeable.

V_OUT- V_REF

V_REF

R₆=

ìR₇

(12)

表8-2 shows the recommended components value for common output voltages.

8.2.2.3 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the BST to SW pins for proper operation. TI

recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor C5 must have a 16-V

or higher voltage rating.

In addition, adding one BST resistor R4 to reduce the spike voltage on the SW node, the resistance smaller than

10 Ω is recommended to be used between BST to the bootstrap capacitor.

8.2.2.4 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1

is connected between VIN and the EN pin of the TPS563300 and R2 is connected between EN and GND. The

UVLO has two thresholds: one for power up when the input voltage is rising and one for power down or

brownouts when the input voltage is falling. For the example design, the supply turns on and start switching

when the input voltage increases above 8 V (V_START). After the converter starts switching, it continues to do so

until the input voltage falls below 7 V (V_STOP). 方程式 2 and 方程式 3 can be used to calculate the values for the

upper and lower resistor values. For the stop voltages specified, the nearest standard resistor value for R1 is 511

kΩand for R2 is 80.7 kΩ.

8.2.2.5 Output Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The

inductance is based on the desired peak-to-peak ripple current, Δi_L, which can be calculated by 方程式13.

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V_OUT

V

F V_OUT

IN_MAX

¿I_L=

×

V

L × f_SW

IN_MAX

(13)

Usually, define K coefficient represents the amount of inductor ripple current relative to the maximum output

current of the device, a reasonable value of K must be 20% to 60%, experience shows that the best value of K is

40%. Since the ripple current increases with the input voltage, the maximum input voltage is always used to

calculate the minimum inductance L. Use 方程式14 to calculate the minimum value of the output inductor.

(V -V_OUT

)

V_OUT

IN

L =

ì

f_SWìK ìI_{OUT _MAX}

V

IN

(14)

where

• K is the ripple ratio of the inductor current (ΔI_L/ I_{OUT_MAX}).

In general, it is preferable to choose lower inductance in switching power supplies, because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of

an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load

can be falsely triggered. Too low of an inductance also generates more inductor core loss since the current ripple

is larger. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors.

After inductance L is determined, the maximum inductor peak current and RMS current can be calculated by 方

程式15 and 方程式16.

¿I_L

I_{L_PEAK}= I_OUT

+

2

(15)

2

¿I_L

2

¨

I_OUT

I_{L_RMS}

=

+

12

(16)

Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit,

I_{HS_LIMIT}(see 节6.5), which ensures that the inductor does not saturate even during a short circuit on the output.

When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current

to rise very rapidly. Although the valley current limit, I_{LS_LIMIT}, is designed to reduce the risk of current runaway, a

saturated inductor can cause the current to rise to high values very rapidly, this can lead to component damage,

so do not allow the inductor to saturate. In any case, the inductor saturation current must not be less than the

maximum peak inductor current at full load.

For this design example, choose the following values:

• K = 0.4

• V_{IN_MAX}= 30 V

• f_SW= 500 kHz

• I_{OUT_MAX}= 3 A

The inductor value is calculated to be 6.94 μH. Choose the nearest standard value of 6.8 μH. This gives a new

K value of 0.408. The max I_{HS_LIMIT}is 5.8 A, the calculated peak current is 3.61 A, and the calculated RMS

current is 3.02 A. The chosen inductor is a Würth Elektronik, 74439346068, 6.8 μH, which has a saturation

current rating of 10 A and a RMS current rating of 6.5 A.

The maximum inductance is limited by the minimum current ripple required for the peak current mode control to

perform correctly. To avoid subharmonic oscillation, as a rule-of-thumb, the minimum inductor ripple current must

be no less than about 10% of the device maximum rated current (3 A) under nominal conditions.

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8.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters, which is generally desired to use as little

output capacitance as possible to keep cost and size down. The output capacitance, C_OUT, must be chosen with

care since it directly affects the following specifications:

• Steady state output voltage ripple

• Loop stability

• Output voltage overshoot and undershoot during load current transient

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple

going through the equivalent series resistance (ESR) of the output capacitors:

¿V_{OUT _ESR}= ¿I_L× ESR = K × I_OUT× ESR

(17)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

¿I_L

K × I_OUT

¿V_{OUT _C}

=

8 × f_SW× C_OUT8 × f_SW× C_OUT

(18)

K is the ripple ratio of the inductor current (ΔI_L/ I_{OUT_MAX}). The two components in the voltage ripple are not in

phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.

Output capacitance is usually limited by the load transient requirements rather than the output voltage ripple if

the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a large

load step happens, output capacitors provide the required charge before the inductor current can slew up to the

appropriate level. The control loop of the converter usually needs eight or more clock cycles to regulate the

inductor current equal to the new load level. The output capacitance must be large enough to supply the current

difference for about eight clock cycles to maintain the output voltage within the specified range. 方程式19 shows

the minimum output capacitance needed for specified V_OUTovershoot and undershoot.

K²

»

ÿ

Ÿ

DI_OUT

f_SWì DV_OUTìK

C_OUT

í

ì (1-D)ì(1+ K) +

(2 -D)

…

12

…

Ÿ

⁄

(19)

where

• D is V_OUT/ V_IN(duty cycle of steady state).

• ΔV_OUTis the output voltage change.

• ΔI_OUTis the output current change.

For this design example, the target output ripple is 30 mV. Presuppose ΔV_{OUT_ESR}= ΔV_{OUT_C}= 30 mV and

choose K = 0.4. 方程式 17 yields ESR no larger than 25 mΩand 方程式 18 yields C_OUTno smaller than 10 μF.

For the target overshoot and undershoot limitation of this design, ΔV_{OUT_SHOOT}< 5% × V_OUT= 250 mV for an

output current step of ΔI_OUT= 1.5 A. C_OUTis calculated to be no smaller than 25 μF by 方程式 19. In summary,

the most stringent criterion for the output capacitor is 25 μF. Considering the ceramic capacitor has DC bias de-

rating, it can be achieved with a bank of 2 × 22-μF, 35-V, ceramic capacitor C3216X5R1V226M160AC in the

1206 case size.

More output capacitors can be used to improve the load transient response. Ceramic capacitors can easily meet

the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel

with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic

capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as

needed.

The recommendations given in 表 8-2 provide typical and minimum values of output capacitance for the given

conditions. These values are the effective figures. If the minimum values are to be used, the design must be

tested over all of the expected application conditions, including input voltage, output current, and ambient

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temperature. This testing must include both bode plot and load transient assessments. The maximum value of

total output capacitance can be referred to the application note (C_OUTselection and C_FFselection) on the

TPS62933 product page. Large values of output capacitance can adversely affect the start-up behavior of the

converter as well as the loop stability. If values larger than noted here must be used, then a careful study of start-

up at full load and loop stability must be performed.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and bode plots are the best way to validate any given design and must always be completed

before the application goes into production. In addition to the required output capacitance, a small ceramic

placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF

to 100 nF can help reduce spikes on the output caused by inductor and board parasitics.

表8-2 shows the recommended LC combination.

表8-2. Recommended LC Combination

Minimum Effective C_OUT

V_OUT(V)

R_TOP(kΩ) R_DOWN(kΩ)

Typical Inductor L (μH)

Typical Effective C_OUT(μF)

(μF)

3.3

5

31.3

52.5

10.0

4.7

6.8

12

40

20

15

10

12

140.0

10

8.2.2.7 Input Capacitor Selection

The TPS563300 device requires an input decoupling capacitor and, depending on the application, a bulk input

capacitor. The typical recommended value for the decoupling capacitor is 10 μF, and an additional 0.1-µF

capacitor from the VIN pin to ground is recommended to provide high frequency filtering.

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. X5R and X7R ceramic dielectrics are recommended because they have a high capacitance-to-volume

ratio and are fairly stable over temperature. The capacitor must also be selected with the DC bias taken into

account. The effective capacitance value decreases as the DC bias increases.

The capacitor voltage rating needs to be greater than the maximum input voltage. The capacitor must also have

a ripple current rating greater than the maximum input current ripple of the TPS563300. The input ripple current

can be calculated using 方程式20.

V

_{IN_MIN}- V_OUT

V_OUT

I_{CIN_RMS}= I_OUT

ì

V

IN_MIN

(20)

For this example design, two TDK CGA5L1X7R1H106K160AC (10-μF, 50-V, 1206, X7R) capacitors have been

selected. The effective capacitance under input voltage of 24 V for each one is 3.45 μF. The input capacitance

value determines the input ripple voltage of the converter. The input voltage ripple can be calculated using 方程

式21. Using the design example values, I_{OUT_MAX}= 3 A, C_{IN_EFF}= 2 × 3.45 = 6.9 μF, and f_SW= 500 kHz, yields

an input voltage ripple of 222 mV and a RMS input ripple current of 1.22 A.

I_{OUT _MAX}ì0.25

DV

=

+ (I_{OUT _MAX}ìR_{ESR _MAX})

IN

C_INì f_SW

(21)

where

• R_{ESR_MAX}is the maximum series resistance of the input capacitor (approximately 1.5 mΩof two capacitors in

paralleled).

8.2.2.8 Feedforward Capacitor C_FFSelection

In some cases, a feedforward capacitor can be used across R_FBTto improve the load transient response or

improve the loop phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values of

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R_FBTin combination with the parasitic capacitance at the FB pin can create a small signal pole that interferes

with the loop stability. A C_FFhelps mitigate this effect. Use lower values to determine if any advantage is gained

by the use of a C_FFcapacitor.

The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor

Application Report is helpful when experimenting with a feedforward capacitor.

For this example design, a 10-pF capacitor C9 can be mounted to boost load transient performance.

8.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the TPS563300 dissipates internal power while operating. The effect of

this power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the following:

• Ambient temperature

• Power loss

• Effective thermal resistance, R_θJA, of the device

• PCB combination

The maximum internal die temperature for the TPS563300 must be limited to 150°C. This establishes a limit on

the maximum device power dissipation and, therefore, the load current. 方程式 22 shows the relationships

between the important parameters. It is easy to see that larger ambient temperatures (T_A) and larger values of

R_θJAreduce the maximum available output current. The converter efficiency can be estimated by using the

curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the desired

operating conditions cannot be found in one of the curves, then interpolation can be used to estimate the

efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the

efficiency can be measured directly. The correct value of R_θJAis more difficult to estimate. As stated in the

Semiconductor and IC Package Thermal Metrics Application Report, the value of R_θJAgiven in the Thermal

Information table is not valid for design purposes and must not be used to estimate the thermal performance of

the application. The values reported in that table were measured under a specific set of conditions that are rarely

obtained in an actual application. The data given for R_θJC(bott)and Ψ_JTcan be useful when determining thermal

performance. See the Semiconductor and IC Package Thermal Metrics Application Report for more information

and the resources given at the end of this section.

(T_J-T_A)

R_qJA

h

1

I_{OUT _MAX}

=

ì

1- h V_OUT

(22)

where

ŋ is the efficiency.

•

The effective R_θJAis a critical parameter and depends on many factors such as the following:

• Power dissipation

• Air temperature/flow

• PCB area

• Copper heat-sink area

• Number of thermal vias under the package

• Adjacent component placement

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8.2.3 Application Curves

V_IN= 24 V, V_OUT= 5 V, L₁= 6.8 µH, C_OUT= 44 µF, T_A= 25°C (unless otherwise noted)

100

95

90

85

80

75

70

65

60

55

50

1

0.8

0.6

0.4

0.2

0

Vin=6V

Vin=12V

Vin=19V

Vin=24V

-0.2

-0.4

-0.6

-0.8

-1

Vin=6V

Vin=12V

Vin=19V

Vin=24V

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2

3

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2

3

图8-2. Efficiency

图8-3. Load Regulation

1

0.8

0.6

0.4

0.2

0

600

550

500

450

400

350

300

250

200

150

100

50

Vin=6V

Vin=12V

Vin=19V

Vin=24V

Vin=30V

-0.2

-0.4

-0.6

-0.8

-1

Iout=0A

Iout=0.03A

Iout=0.3A

Iout=1.5A

Iout=3A

0

5

7.5 10 12.5 15 17.5 20 22.5 25 27.5 30

Vin (V)

0.001

0.005

0.02 0.05 0.1 0.2

I-Load (A)

0.5

1

2

3

图8-4. Line Regulation

图8-5. Switching Frequency vs Load Current

90

60

30

0

300

200

100

0

-30

-60

-90

-100

-200

Mag (dB)

Phase (deg)

-300

100 200 5001000

10000

Frequency (Hz)

100000

1000000

图8-7. Case Temperature, V_IN= 24 V,

I_OUT= 3 A, f_SW= 500 kHz

图8-6. Loop Frequency Response, I_OUT= 3 A, BW

= 49.4 kHz, PM = 57°, GM = –12 dB

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VIN = 10V/div

VOUT = 2V/div

VIN = 10V/div

VOUT = 2V/div

SS = 2V/div

IL = 2A/div

SS = 2V/div

IL = 2A/div

4mS/div

图8-8. Start-Up Relative to V_IN, I_OUT= 3 A

图8-9. Shutdown Relative to V_IN, I_OUT= 3 A

EN = 2V/div

VOUT = 2V/div

SS = 2V/div

IL = 2A/div

SS = 2V/div

IL = 2A/div

2mS/div

图8-10. Start-Up Through EN, I_OUT= 3 A

图8-11. Shutdown Through EN, I_OUT= 3 A

VOUT = 20mV/div (AC coupled)

IL = 500mA/div

4mS/div

4uS/div

图8-12. Steady State, I_OUT= 0 A

图8-13. Steady State, I_OUT= 0.1 A

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VOUT = 20mV/div (AC coupled)

IL = 500mA/div

2uS/div

图8-14. Steady State, I_OUT= 0.5 A

图8-15. Steady State, I_OUT= 1 A

VOUT = 20mV/div (AC coupled)

IL = 1A/div

2uS/div

图8-17. Steady State, I_OUT= 3 A

图8-16. Steady State, I_OUT= 2 A

VOUT = 200mV/div (AC coupled)

IOUT = 2A/div

100uS/div

图8-19. Load Transient Response, 1 to 3 A, Slew

Rate = 0.8 A/μS

图8-18. Load Transient Response, 0.5 to 2.5 A,

Slew Rate = 0.8 A/μS

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VIN = 10V/div

VOUT = 2V/div

VIN = 10V/div

VOUT = 2V/div

SS = 2V/div

IL = 2A/div

SS = 2V/div

IL = 2A/div

20mS/div

图8-20. V_OUTHard Short Protection

图8-21. V_OUTHard Short Recovery

8.3 Best Design Practices

• Do not exceed the Absolute Maximum Ratings.

• Do not exceed the Recommended Operating Conditions.

• Do not exceed the ESD Ratings.

• Do not allow the output voltage to exceed the input voltage, nor go below ground.

• Do not use the value of R_θJAgiven in the Thermal Information table to design your application. See 节

8.2.2.9.

• Follow all the guidelines and suggestions found in this data sheet before committing the design to production.

TI application engineers are ready to help critique your design and PCB layout to help make your project a

success.

• Use a 100-nF capacitor connected directly to the VIN and GND pins of the device. See 节8.2.2.7 for details.

8.4 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 3.8 V and 30 V. This input

supply must be well regulated and compatible with the limits found in the specifications of this data sheet. In

addition, the input supply must be capable of delivering the required input current to the loaded converter. The

average input current can be estimated with 方程式23.

V_OUTìI_OUT

I

=

IN

V ì h

IN

(23)

where

ŋ = efficiency

•

If the converter is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic

input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to

the converter. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is

applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the

converter to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the

distance from the input supply to the converter and use an aluminum or tantalum input capacitor in parallel with

the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce

any overshoots. A value in the range of 20 μF to 100 μF is usually sufficient to provide input damping and help

hold the input voltage steady during large load transients.

It is recommended that the input supply must not be allowed to fall below the output voltage by more than 0.3 V.

Under such conditions, the output capacitors discharges through the body diode of the high-side power

MOSFET. The resulting current can cause unpredictable behavior, and in extreme cases, possible device

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damage. If the application allows for this possibility, then use a Schottky diode from VIN to VOUT to provide a

path around the converter for this current.

In some cases, a transient voltage suppressor (TVS) is used on the input of converters. One class of this device

has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the converter, the output capacitors discharges through the device, as mentioned above.

Sometimes, for other system considerations, an input filter is used in front of the converter. This can lead to

instability as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple

Success with Conducted EMI from DCDC Converters User's Guide provides helpful suggestions when designing

an input filter for any switching converter.

8.5 Layout

8.5.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of a good schematic design. Even if the converter regulates correctly, bad PCB layout can

mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI

performance of the converter is dependent on the PCB layout to a great extent. In a buck converter, the most

critical PCB feature is the loop formed by the input capacitors and power ground, as shown in 图 8-22. This loop

carries large transient currents that can cause large transient voltages when reacting with the trace inductance.

These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in

this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance.

TI recommends a 2-layer board with 2-oz copper thickness of top and bottom layer, and proper layout provides

low current conduction impedance, proper shielding, and lower thermal resistance. 图8-23 and 图8-24 show the

recommended layouts for the critical components of the TPS563300.

• Place the inductor, input and output capacitors, and the IC on the same layer.

• Place the input and output capacitors as close as possible to the IC. The VIN and GND traces must be as

wide as possible and provide sufficient vias on them to minimize trace impedance. The wide areas are also of

advantage from the view point of heat dissipation.

• Place a 0.1-µF ceramic decoupling capacitor or capacitors as close as possible to VIN and GND, which is key

to EMI reduction.

• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.

• Place a BST capacitor and resistor close to BST pin and SW node. > 10-mil width trace is recommended to

reduce the parasitic inductance.

• Place the feedback divider as close as possible to the FB pin. > 10-mil width trace is recommended for heat

dissipation. Connect a separate V_OUTtrace to the upper feedback resistor. Place the voltage feedback loop

away from the high-voltage switching trace. The feedback loop preferably has ground shield.

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VIN

KEEP

CURRENT

LOOP

C_IN

SW

SMALL

GND

图8-22. Current Loop With Fast Edges

8.5.2 Layout Example

图8-23. TPS563300 Top Layout Example

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图8-24. TPS563300 Bottom Layout Example

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9 Device and Documentation Support

9.1 Device Support

9.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

9.1.2 Development Support

9.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS563300 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2 Documentation Support

9.2.1 Related Documentation

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

• Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters with

Feedforward Capacitor application report

• Texas Instruments, AN-2162 Simple Success with Conducted EMI from DCDC Converters user's guide

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DRL0008A

SOT-5X3 - 0.6 mm max height

S

C

A

L

E

8

.

0

PLASTIC SMALL OUTLINE

1.3

1.1

B

A

PIN 1

ID AREA

1

8

6X 0.5

2.2

2.0

2X 1.5

NOTE 3

5

4

0.27

0.17

8X

1.7

1.5

0.05

0.00

0.1

C A B

0.05

C

0.6 MAX

SEATING PLANE

0.05 C

0.18

0.08

SYMM

0.4

0.2

8X

SYMM

4224486/E 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4.Reference JEDEC Registration MO-293, Variation UDAD

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EXAMPLE BOARD LAYOUT

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8

8X (0.3)

1

SYMM

6X (0.5)

5

4

(R0.05) TYP

(1.48)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:30X

0.05 MIN

AROUND

0.05 MAX

AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDERMASK DETAILS

4224486/E 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

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EXAMPLE STENCIL DESIGN

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8

8X (0.3)

1

SYMM

6X (0.5)

5

4

(R0.05) TYP

(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4224486/E 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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型号：	TPS563300
厂家：	TEXAS INSTRUMENTS
描述：	采用 SOT-583 封装、3.8V 至 28V 输入、3A 同步降压转换器转换器
文件：	总40页 (文件大小：3783K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS563300 [TI]

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