TPS564208 [TI]
采用 FCCM 模式的 4.5V 至 17V 输入电压、4A 输出电流、同步降压转换器;
| 型号： | TPS564208 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 FCCM 模式的 4.5V 至 17V 输入电压、4A 输出电流、同步降压转换器 转换器 |
| 文件： | 总28页 (文件大小：1246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
TPS564208 采用 SOT-23 封装的 4.5V 至 17V 输入、4A 同步降压稳压器
1 特性
3 说明
1
•
TPS564208 具有 50mΩ 和 22mΩ 集成场效应晶体
管 (FET) 的 4A 转换器
TPS564208 是一款采用 SOT-23 封装的简单易用型
4A 同步降压转换器。
•
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™模式控制，具有快速动态响应特性
输入电压范围：4.5V 至 17V
输出电压范围：0.76V 至 7V
连续电流模式
该器件经过优化，最大限度地减少了运行所需的外部组
件并且可以实现低待机电流。
这些开关模式电源 (SMPS) 器件采用 D-CAP2 模式控
制，能够提供快速瞬态响应，并且在无需外部补偿组件
的情况下支持诸如高分子聚合物等低等效串联电阻
(ESR) 输出电容以及超低 ESR 陶瓷电容器。
560kHz 开关频率
低关断电流（小于 10µA）
1.6% 反馈电压精度 (25°C)
从预偏置输出电压中启动
逐周期过流限制
TPS564208 采用 6 引脚 1.6-mm × 2.9-mm SOT
(DDC) 封装，额定结温范围为 –40°C 至 125°C。
断续模式过流保护
器件信息(1)
非锁存欠压保护 (UVP) 和热关断 (TSD) 保护
固定软启动时间：1.0ms
结合使用 TPS564208 和 WEBENCH® 电源设计器
创建定制设计方案
器件型号
TPS564208
封装
DDC (6)
封装尺寸（标称值）
1.60mm x 2.90mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
空白
空白
空白
•
•
•
•
•
数字电视电源
高清 蓝光™光盘播放器
网络家庭终端设备
数字机顶盒 (STB)
安全监控
简化原理图
CBST
TPS564208 效率
100%
90%
80%
70%
60%
50%
40%
TPS564208
1
2
6
5
GND
VBST
EN
LO
VOUT
SW
VIN
EN
CO
3
4
VIN
VFB
VOUT
RFB1
RFB2
CIN
30%
20%
10%
0
VOUT = 1.05 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 4
D018
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDG0
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 开发支持................................................................ 20
11.2 接收文档更新通知 ................................................. 20
11.3 社区资源................................................................ 20
11.4 商标....................................................................... 20
11.5 静电放电警告......................................................... 20
11.6 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
Changes from Revision A (October 2017) to Revision B
Page
•
Changed the IVIN MAX value From: 780 µA To: 820 µA in the Electrical Characteristics ..................................................... 5
Changes from Original (March 2016) to Revision A
Page
•
•
•
已添加 WEBENCH® 电源设计器链接 特性 ........................................................................................................................... 1
Changed VFBTH spec MIN from 739 to 745, TYP from 759 to 760, and MAX from 779 to 775 ............................................ 5
已添加 使用 WEBENCH® 工具创建定制设计方案................................................................................................................ 20
2
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
2
3
6
5
4
VBST
EN
SW
VIN
VFB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
GND
1
—
SW
VIN
VFB
EN
2
3
4
5
O
I
Switch node connection between high-side NFET and low-side NFET.
Input voltage supply pin. The drain terminal of high-side power NFET.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
I
I
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
VBST
6
O
Copyright © 2016–2017, Texas Instruments Incorporated
3
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN, EN
VBST
25
V
VBST (10 ns transient)
27
V
Input voltage
VBST (vs SW)
6.5
6.5
19
V
VFB
V
SW
V
SW (10 ns transient)
–3.5
–40
–55
21
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
17
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
23
VBST (10 ns transient)
26
VBST (vs SW)
6.0
17
VI
Input voltage range
EN
V
VFB
5.5
17
SW
SW (10 ns transient)
20
TJ
Operating junction temperature
125
°C
6.4 Thermal Information
TPS564208
DDC (SOT)
6 PINS
86.3
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
39.4
13.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.8
ψJB
13.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
Operating – non-switching
supply current
IVIN
VIN current, EN = 5 V, VFB = 1 V
VIN current, EN = 0 V
640
0.9
820
5
µA
µA
IVINSDN
Shutdown supply current
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.6
225
745
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.8
VEN = 12 V
425
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
VFB input current
VO = 1.05 V, continuous mode operation
VFB = 0.8 V
760
0
775
mV
µA
IVFB
±0.1
MOSFET
RDS(on)h
RDS(on)l
High-side switch resistance
Low-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
TA = 25°C
50
22
mΩ
mΩ
CURRENT LIMIT
Iocl
Current limit(1)
DC current, VOUT = 1.05 V, L1 = 1.5 µH
4.2
6
7.7
A
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
172
38
Thermal shutdown
threshold(1)
TSDN
°C
ON-TIME TIMER CONTROL
tOFF(MIN)
SOFT START
tSS
Minimum off time
VFB = 0.68 V
220
1
280
ns
ms
Soft-start time
Internal soft-start time
FREQUENCY
Fsw
Switching frequency
VIN = 12 V, VO = 1.05 V, FCCM mode
560
kHz
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
Hiccup detect (H > L)
65%
1.9
THICCUP_WAIT Hiccup on time
ms
ms
THICCUP_RE
Hiccup time before restart
15.5
UVLO
Wake up VIN voltage
Shutdown VIN voltage
Hysteresis VIN voltage(1)
4
3.6
0.4
4.3
UVLO
UVLO threshold
3.3
V
(1) Not production tested.
Copyright © 2016–2017, Texas Instruments Incorporated
5
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.8
0.75
0.7
0.762
0.761
0.76
0.65
0.6
0.759
0.758
0.757
0.756
0.55
0.5
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
Junction Temperature (èC)
Junction Temperature (èC)
D001
D002
Figure 1. TPS564208 Supply Current vs Junction
Temperature
Figure 2. VFB Voltage vs Junction Temperature
1.23
1.2
1.45
1.42
1.39
1.36
1.33
1.3
1.17
1.14
1.11
1.08
1.05
1.02
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
Junction Temperature (èC)
Junction Temperature (èC)
D003
D004
Figure 3. EN Pin UVLO Low Voltage vs Junction
Temperature
Figure 4. TPS564208 EN Pin UVLO High Voltage vs Junction
Temperature
80
70
60
50
40
30
20
32
28
24
20
16
12
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
Junction Temperature (èC)
Junction Temperature (èC)
D005
D006
Figure 5. High-Side Rds-On vs Junction Temperature
Figure 6. Low-Side Rds-On vs Junction Temperature
6
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
620
580
570
560
550
540
530
520
Vout = 1.8 V
Vout = 3.3 V
Vout = 5 V
600
580
560
540
520
500
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
4
6
8
10
12
14
16
18
0.0001
0.001
0.01
0.1
1
4
Input Voltage (V)
Output Current (A)
D007
D008
IOUT = 1 A
VIN = 12 V
Figure 7. TPS564208 Switching Frequency vs Input Voltage
Figure 8. TPS564208 Switching Frequency vs Output
Current
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.001
0.01
0.1
1
4
0.001
0.01
0.1
1
4
Output Current (A)
Output Current (A)
D009
D010
Figure 9. TPS564208 VOUT = 1.05 V Efficiency, L = 2.2 µH
Figure 10. TPS564208 VOUT = 1.5 V Efficiency, L = 2.2 µH
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.001
0.01
0.1
1
4
0.001
0.01
0.1
1
4
Output Current (A)
Output Current (A)
D011
D012
Figure 11. TPS564208 VOUT = 1.8 V Efficiency, L = 2.2 µH
Figure 12. TPS564208 VOUT = 3.3 V Efficiency, L = 2.2 µH
Copyright © 2016–2017, Texas Instruments Incorporated
7
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
VIN = 5 V
VIN = 9 V
VIN = 12 V
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
0.0001
0.001
0.01
0.1
1
4
Output Current (A)
D013
Figure 13. TPS564208 VOUT = 5 V Efficiency, L = 3.3 µH
8
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
7 Detailed Description
7.1 Overview
The TPS564208 is a 4-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports
low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without
complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the
output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
3
VIN
VUVP
+
Hiccup
VREG5
UVP
Control Logic
Regulator
UVLO
œ
VFB
4
6
VBST
œ
+
+
PWM
Voltage
Reference
Ref
HS
SS
Soft Start
Turn-On
One Shot
XCON
2
1
SW
VREG5
LS
TSD
OCL
Threshold
œ
OCL
+
GND
+
ZC
œ
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016–2017, Texas Instruments Incorporated
9
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS564208 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN,
and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference
voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode
control.
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS564208 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converter ramps up smoothly into regulation point.
10
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
Feature Description (continued)
7.3.3 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-starts after the hiccup time (typically 15.5 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS564208 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS564208 operates at a quasi-fixed frequency of 560
kHz.
7.4.2 Standby Operation
When the TPS564208 is operating in normal CCM, it may be placed in standby by asserting the EN pin low.
Copyright © 2016–2017, Texas Instruments Incorporated
11
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with
a maximum available output current of 4 A. The following design procedure can be used to select component
values for the TPS564208. Alternately, the WEBENCH® software may be used to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic in Figure 14 shows the TPS564208 4.5-V to 17-V input, 1.05-V output converter
design meeting the requirements for 4-A output. This circuit is available as the evaluation module (EVM). The
sections provide the design procedure.
C7 0.1 ꢁF
TPS564208
1
2
6
5
GND
SW
VBST
EN
L1
VOUT = 1.05 V / 4A
R3 10 kꢀ
EN
VOUT
2.2 ꢁH
C9
22 ꢁF
C8
22 ꢁF
3
4
VIN
VFB
VOUT
R1 3.09 kꢀ
R2
10 kꢀ
C4
1
C1
C2
C3
10 ꢁF
10 ꢁF 0.1 ꢁF
1
Not Installed
VIN
1
VIN = 4.5 V to 17 V
Copyright © 2017, Texas Instruments Incorporated
Figure 14. TPS564208 1.05-V, 4-A Reference Design
12
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 17 V
1.05 V
Output voltage
Transient response, 2-A load step
Input ripple voltage
ΔVout = ±5%
400 mV
30 mV
Output ripple voltage
Output current rating
Operating frequency
4 A
560 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS564208 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of
resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will
be more noticeable.
R1
æ
ö
VOUT = 0.760 ´ 1 +
ç
÷
R2
è
ø
(1)
8.2.2.3 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
=
2p LOUT ì COUT
(2)
Copyright © 2016–2017, Texas Instruments Incorporated
13
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
L1 (µH)
TYP
2.2
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
C8 + C9 (µF)
MIN
1.5
1.5
1.5
1.5
1.5
2.2
2.2
3.3
3.3
MAX
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
2.2
2.2
2.2
2.2
2.2
2.2
3.3
6.5
3.3
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 560 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS
current of Equation 6.
V
- VOUT
VOUT
IN(MAX)
IlP-P
IlPEAK = IO
ILO(RMS)
=
ì
V
LO ì fSW
IN(MAX)
(3)
(4)
IlP-P
+
1
2
2
=
IO
+
IlP-P
12
(5)
For this design example, the calculated peak current is 4.4 A and the calculated RMS current is 4 A. The
inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS564208 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 6
to determine the required RMS current rating for the output capacitor.
VOUT ì V - VOUT
(
)
IN
ICO(RMS)
=
12 ì V ì LO ì fSW
IN
(6)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.4 Input Capacitor Selection
The TPS564208 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
14
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
8.2.2.5 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
Copyright © 2016–2017, Texas Instruments Incorporated
15
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
8.2.3 Application Curves
3%
2%
1%
0
3%
2%
1%
0
-1%
-2%
-3%
-1%
-2%
-3%
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Current (A)
Output Current (A)
D015
D014
VIN = 5 V
VOUT1 = 1.05 V
VIN = 12 V
VOUT1 = 1.05 V
Figure 15. TPS564208 Load Regulation, VIN = 5 V
Figure 16. TPS564208 Load Regulation, VIN = 12 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
1.058
1.057
1.056
1.055
1.054
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
4
6
8
10
12
14
16
18
0.001
0.01
0.1
1
4
Input Voltage (V)
Output Current (A)
D016
D017
IOUT = 1 A
Figure 17. TPS564208 Line Regulation
Figure 18. TPS564208 Efficiency, Vout = 1.05 V
VOUT = 10 mV/div
VIN =100mV/div
LX=5V/div
LX= 5V/div
IOUT = 2A/div
IL = 500 mA/div
1 µs/div
Figure 19. TPS564208 Input Voltage Ripple
1 µs/div
Figure 20. TPS564208 Output Voltage Ripple, No Load
16
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
VOUT = 10 mV/div
VOUT = 10 mV/div
LX=5V/div
IL = 2 A/div
LX=5V/div
IOUT = 5 A/div
1 µs/div
1 µs/div
Figure 21. TPS564208 Output Voltage Ripple, IOUT 2 A
Figure 22. TPS564208 Output Voltage Ripple, IOUT 4 A
VOUT = 10 mV/div
VOUT = 10 mV/div
IOUT = 1 A/div
IOUT = 1 A/div
100 µs/div
100 µs/div
Figure 23. TPS564208 Transient Response 0.1 to 2 A
Figure 24. TPS564208 Transient Response, 1 to 3 A
VOUT = 10 mV/div
VIN = 5 V/div
VEN = 5 V/div
IOUT = 2 A/div
VOUT = 500 mV/div
2 ms/div
100 µs/div
Figure 26. TPS564208 Startup Relative to VIN
Figure 25. TPS564208 Transient Response, 2 to 4 A
Copyright © 2016–2017, Texas Instruments Incorporated
17
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
VOUT = 500 mV/div
400 µs/div
20 ms/div
Figure 27. TPS564208 Startup Relative to EN
Figure 28. TPS564208 Shutdown Relative to VIN
VIN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
400 µs/div
Figure 29. TPS564208 Shutdown Relative to EN
9 Power Supply Recommendations
The TPS564208 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO / 0.75.
18
Copyright © 2016–2017, Texas Instruments Incorporated
TPS564208
www.ti.com.cn
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
GND
Vias to the
Internal SW
Node Copper
Additional
Vias to the
GND Plane
Output
Capacitor
BOOST
CAPACITOR
Output
Inductor
GND
SW
VBST
EN
Feedback
Resistors
To Enable
Control
VFB
Vias to the
Internal SW
Node Copper
VIN
VIN
Input Bypass
Capacitor
SW Node Copper
Pour Area on
Internal
or Bottom Layer
Figure 30. TPS564208 Layout Example
版权 © 2016–2017, Texas Instruments Incorporated
19
TPS564208
ZHCSEW2B –MARCH 2016–REVISED DECEMBER 2017
www.ti.com.cn
11 器件和文档支持
11.1 开发支持
11.1.1 使用 WEBENCH® 工具创建定制设计方案
请单击此处，结合使用 TPS564208 器件和 WEBENCH® 电源设计器创建定制设计方案。
1. 首先键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
D-CAP2, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
蓝光 is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
20
版权 © 2016–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS564208DDCR
TPS564208DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
4208
4208
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS564208DDCR
TPS564208DDCT
SOT-23-
THIN
DDC
DDC
6
6
3000
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23-
THIN
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS564208DDCR
TPS564208DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS564208DDCR
采用 FCCM 模式的 4.5V 至 17V 输入电压、4A 输出电流、同步降压转换器 | DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564208DDCT
采用 FCCM 模式的 4.5V 至 17V 输入电压、4A 输出电流、同步降压转换器 | DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564242
采用 SOT-563 封装的 3V 至 16V 输入电压、4A ECO 模式同步降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564242DRLR
采用 SOT-563 封装的 3V 至 16V 输入电压、4A ECO 模式同步降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564252
3-V to 17-V input voltage, 4-A ECO mode, synchronous buck converterWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564252DRLR
3-V to 17-V input voltage, 4-A ECO mode, synchronous buck converter | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564255
3-V to 17-V input voltage, 4-A OOA mode, synchronous buck converter with PGWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564255DRLR
3-V to 17-V input voltage, 4-A OOA mode, synchronous buck converter with PG | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564257
3-V to 17-V input voltage, 4-A FCCM mode, synchronous buck converterWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS564257DRLR
3-V to 17-V input voltage, 4-A FCCM mode, synchronous buck converter | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS56428
4.5V to 18 V Input, 4-A Synchronous Step-Down Converter with Advanced Eco-modeâ¢Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS56428DDA
4.5V to 18 V Input, 4-A Synchronous Step-Down Converter with Advanced Eco-modeâ¢Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明