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TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

具有电压调节功能 TPS56x20 4.5V 至 17V 输入、12A/9A/7A/5A 输出、同

步降压电压稳压器

1 特性

2 应用范围

1

•

D-CAP2™控制

•

用于消费类应用的媒体处理器：

数字电视、机顶盒（STB、DVD/蓝光播放器、有线

/卫星调制解调器）

–

输入电压范围：4.5V 至 17V

开关频率：500kHz

•

片上系统处理器

高密度配电系统

已针对 1.0µH 至 2.2µH 电感器进行优化

•

输出电压精度为 ±1%

经由 I²C 兼容接口实现的特性

3 说明

–

输出电压 (VID)：0.6V 至 1.8V，步长 10mV

自动跳跃 Eco-mode™ON/OFF（轻负载）

电流限制目标：40% 至 60%

TPS56X20 一款同步直流-直流转换器 IC（集成电

路），此转换器具有电压调节控制功能，以便为要求内

核电压 (V_CORE) 调整的微处理器 (MCU) 供电。最初加

电后，输出电压可由 I²C 兼容总线上发送的 VID 代码

编程/调节。

使能集成电路 (IC)，回读电源正常 (Power-

good)

–

断续模式保护 ON/OFF

这个降压转换器采用一个自适应接通时间 D-CAP2 模

式控制，此模式控制在无需外部组件的情况下提供极快

的瞬态响应。与传统的电压/电流模式控制不同，D-

CAP2 支持较高负载下的 PWM 模式与轻负载情况下的

Eco-mode™模式之间的无缝转换。Eco-mode 在轻负

载时保持高效率。

•

IC 端子特性

–

使用外部电阻器启动

VFB 引脚上的输出电压：0.6V 至 1.8V

–

可调节软启动，

单调预偏置启动

–

Power-good

I²C 地址编程（2 位）

器件信息

•

逐周期过流限制控制

热关断 (TSD)

器件型号

封装

封装尺寸

带散热片薄型小外形

尺寸封装 (HTSSOP) 7.80mm × 4.40mm

欠压闭锁 (UVLO)

TPS56C20

(24)

薄型小外形尺寸封装 (TSSOP) (PWP)，此类封装

具有 PowerPAD™

TPS56920

TPS56720

TPS56520

HTSSOP (20)

6.50mm x 4.40mm

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCB6

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

典型应用电路

3.3 V

U1

R1

1.0kΩ

R2

1.0kΩ

R3

1.0kΩ

R4

10.0k

TPS56520

TPS56720

TPS56920

PWRGD

20

19

18

17

16

15

14

13

11

12

1

2

3

4

EN

VFB

VOUT

SS

VIN

SDA

SCL

A1

µProcessor ^SCL

R5

18.2kΩ

A1

A0

GND

5

6

A0

VREG5

PGOOD

VBST

SW

VIN

C4

2.2µF

C5

0.01µF

R6

22kΩ

7

VIN

PVIN

PGND

8

C3

0.1µF

AGND

C1

10µF

C2

4.7µF

9

L1

SW

VOUT

10

SW

PGND

AGND

1.5µH

C6

100µF

PGND

2

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

8.4 Device Functional Modes........................................ 19

8.5 Programming........................................................... 19

8.6 Register Maps......................................................... 21

Applications and Implementation ...................... 25

9.1 Application Information............................................ 25

9.2 Typical Application .................................................. 25

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information ................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements.............................................. 10

7.7 Switching Characteristics........................................ 10

7.8 Typical Characteristics............................................ 11

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

9

10 Power Supply Recommendations ..................... 33

11 Layout................................................................... 33

11.1 Layout Guidelines ................................................. 33

11.2 Layout Example .................................................... 34

12 器件和文档支持 ..................................................... 35

12.1 器件支持................................................................ 35

12.2 文档支持 ............................................................... 35

12.3 相关链接................................................................ 35

12.4 商标....................................................................... 35

12.5 静电放电警告......................................................... 35

12.6 Glossary................................................................ 35

13 机械、封装和可订购信息....................................... 35

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (February 2016) to Revision E

Page

•

Changed T_JMAX from 125°C to 150°C in Absolute Maximum Ratings ................................................................................ 7

Changes from Revision C (July 2014) to Revision D

Page

•

从数据表标题中删除了 SWIFT™............................................................................................................................................ 1

Moved the Storage Temperature to the Absolute Maximum Ratings ................................................................................... 7

Changed Handling Ratings To: ESD Ratings ........................................................................................................................ 7

Changes from Revision B (March 2014) to Revision C

Page

•

Changed Figure 57 image for clarification. .......................................................................................................................... 34

内容表，并已将修订历史记录移至第 2 页。

Changes from Revision A (January 2014) to Revision B

Page

•

已更改为新的数据表格式。..................................................................................................................................................... 1

已添加添加了器件信息表 ....................................................................................................................................................... 1

已添加 .................................................................................................................................................................................... 3

Moved Abs Max Ratings, Handling Ratings, Recommended Operating Conditions, Thermal Info, and Elec

Characteristics tables to the "Specifications" section ............................................................................................................ 7

Changes from Original (November 2013) to Revision A

Page

•

已更改数据表标题以包括“SWIFT^TM稳压器...” ...................................................................................................................... 1

3

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

5 说明（续）

TPS56X20 支持超低 ESR 陶瓷电容器和低等效串联电阻 (ESR) 输出电容器，诸如高分子钽固体电解电容器

(POSCAP) 或高分子聚合物电容器 (SP-CAP)。此器件针对小尺寸 1.0µH 至 2.2µH 电感器进行了优化，节省了印刷

电路板 (PCB) 面积。

TPS56X20 器件采用 HTSSOP 封装。

Table 1. List of Devices

TPS56520

5A

TPS56720

7A

TPS56920

9A

TPS56C20

12A

Output Current

HS/LS Rdson Numbers

Package

44mΩ/32mΩ

PWP-20

30mΩ/24mΩ

PWP-20

26mΩ/19mΩ

PWP-20

13mΩ/9mΩ

PWP-24

4

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

6 Pin Configuration and Functions

TPS56520/720/920

20-Pin PWP Package with PowerPAD

(TOP VIEW)

1

EN

VFB 20

19

2

3

4

5

6

7

VOUT

SDA

SCL

SS 18

17

A1

A0

GND

(PowerPAD)

16

VREG5

HTSSOP-20

PGOOD 15

VIN

VBST

14

13

12

PVIN

8

9

PVIN

SW

PGND

10

SW 11

PGND

Pin Functions

I/O

DESCRIPTION

NAME

EN

NUMBER

1

2

I

I/O

I

Enable. Pull High to enable converter.

Data I/O terminal.

SDA

SCL

3

Clock I/O terminal.

A1, A0

VIN

4,5

6

Chip address.

I

Supply Input for 5.5V linear regulator.

PVIN

PGND

7,8

9,10

I

Power inputs and connects to high side MOSFET drains.

I/O

Ground returns for low-side MOSFETs. Input of current comparator.

Switch node connections for both the high-side NFETs and low-side NFETs. Input of current

comparator.

SW

11,12,13

14

I/O

I

Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between

VBST and SW terminals. An internal diode is connected between VREG5 and VBST.

VBST

PGOOD

Open drain power good output. Low means the output voltage of the corresponding output is

out of regulation.

15

O

Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at

least 2.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is

active when EN is H-level.

VREG5

16

O

GND

SS

17

18

I/O

O

Signal GND. Connect sensitive SS and VFB returns to GND at a single point.

Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program

Soft-Start time.

VOUT

VFB

19

20

I

Connection to output voltage

D-CAP2 feedback input. Connect to output voltage with resistor divider.

Exposed Thermal

Pad

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be

connected to GND.

Back side

I/O

5

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

TPS56C20

24-Pin PWP Package with PowerPAD

(TOP VIEW)

1

EN

VFB

VOUT

SS

24

23

2

3

4

5

6

SDA

SCL

A1

22

21

20

GND

A0

VREG5

TPS56C20

PGOOD ¹⁹

VIN

HTSSOP 24

(PowerPAD)

7

8

PVIN

18

17

16

VBST

SW

PVIN

9

PGND

SW

10

PGND

15

14

13

SW

11 PGND

¹²PGND

Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

EN

1

I

I/O

I

Enable. Pull High to enable according converter.

Data I/O terminal.

SDA

SCL

2

3

Clock I/O terminal.

A1, A0

VIN

4,5

Chip address.

6

I

Supply Input for 5.5V linear regulator.

Power inputs and connects to both high side NFET drains.

Ground returns for low-side MOSFETs. Input of current comparator.

PVIN

PGND

7,8

I

9,10,11,12

I/O

13,14,15,

16, 17

Switch node connections for both the high-side NFETs and low-side NFETs. Input of current

comparator.

SW

I/O

I

Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between

VBST and SW terminals. An internal diode is connected between VREG5 and VBST.

VBST

PGOOD

18

19

Open drain power good output. Low means the output voltage of the corresponding output is

out of regulation.

O

Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least

3.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is active

when EN is H-level.

VREG5

20

O

GND

SS

21

22

I/O

O

Signal GND. Connect sensitive SS and VFB returns to GND at a single point.

Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program Soft-

Start time.

VOUT

VFB

23

24

I

Connection to output voltage

D-CAP2 feedback inputs. Connect to output voltage with resistor divider.

Exposed Thermal

Pad

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be

connected to GND.

Back side

I/O

6

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

VALUE

UNIT

MIN

–0.3

–2

MAX

20

VIN,PVIN, EN

VBST

26

VBST (10ns transient)

28

VFB, VOUT, SDA, SCL

3.6

6.5

20

Input voltage

A0, A1

V

VBST–SW

SW

SW (10ns transient)

–3

22

VREG5,SS,PGOOD

–0.3

–0.1

–40

–55

6.5

0.3

5

Overvoltage

PGND

Sink Current

PGOOD

mA

°C

T_J

Operating Junction temperature

Storage temperature

150

T_STG

°C

(1) These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those

indicated under Recommended Operating Conditions.

(2) All voltages are with respect to IC GND terminal.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human Body Model (HBM)⁽²⁾

Charged Device Model (CDM)⁽³⁾

Electrostatic

discharge⁽¹⁾

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

0.6

0

NOM

MAX

17

1.87

5

UNIT

V

VIN

Operating input voltage

Output voltage

VOUT

V

TPS56520

TPS56720

TPS56920

TPS56C20

0

7

I_OUT

Output current

A

0

9

0

12

125

T_J

Operating junction temperature range

–40

°C

7

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

UNIT

7.4 Thermal Information

TPS56520/720/920

TPS56C20

PWP (24)

32.8

THERMAL METRIC⁽¹⁾

PWP (20)

36.8

22.5

19.5

0.6

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

16

14.2

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

19.2

1.4

14

θ_JCbot

0.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_J= –40°C to 125°C, VIN=4.5V to 17V, PVIN=4.5V to 17V (Unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE

VIN

Operating input voltage

VIN supply current

VIN, PVIN

4.5

17

1150

200

V

I_IN

25°C, EN=5V, VFB=0.8V (non switching), VIN=12V

25°C, EN=0V, VIN=12V

920

140

µA

I_VINSDN

VIN shutdown current

FEEDBACK VOLTAGE

25°C, external regulation mode, PVIN=12V,

VOUT=1.1V, IOUT=50mA, pulse skipping

0.594

0.591

0.6

0.606

0.609

V

25°C, external regulation mode, VOUT=1.1V,

continuous current mode

V_VFB

VFB voltage

External regulation mode, VOUT=1.1V, continuous

current mode

VOUT VOLTAGE (INTERNAL VID CONTROL)

25°C, relative to target VOUT, PVIN=12V,

VOUT=0.6V~1.87V, LOUT=1.5µH

–1%

0%

1%

Target

VOUT

V_VOUT

VOUT voltage

Relative to target VOUT, PVIN=12V, LOUT=1.5µH

Relative to target VOUT, LOUT=1.5µH

–1.5%

–2%

0%

1.5%

2%

VREG5 OUTPUT

V_VREG5

MOSFET

r_DS(on)H

r_DS(on)L

r_DS(on)H

r_DS(on)L

r_DS(on)H

r_DS(on)L

r_DS(on)H

r_DS(on)L

VREG5 Output Voltage

25°C , 6V< VIN <17V, I_VREG5= 5mA, VFB=1V

5.2

5.5

5.7

V

High side switch resistance TPS56520

Low side switch resistance TPS56520

High side switch resistance TPS56720

Low side switch resistance TPS56720

High side switch resistance TPS56920

Low side switch resistance TPS56920

High side switch resistance TPS56C20

Low side switch resistanceTPS56C20

VBST-SW=5.5V

VIN=12V

44

32

30

24

26

19

13

9

mΩ

VBST-SW=5.5V

VIN=12V

VBST-SW=5.5V

VIN=12V

VBST-SW=5.5V

VIN=12V

POWER GOOD

VOUT or VFB falling (fault) VO=1.1V

VOUT or VFB rising (good) VO=1.1V

VOUT or VFB rising (fault) VO=1.1V

VOUT or VFB falling (good) VO=1.1V

VPGOOD=0.5V

80%

85%

V_PGOODTH

PGOOD threshold

115%

110%

5.2

I_PGOODDLY

PGOOD sink current

3.15

mA

8

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Electrical Characteristics (continued)

T_J= –40°C to 125°C, VIN=4.5V to 17V, PVIN=4.5V to 17V (Unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC THRESHOLD

V_ENH

V_ENL

EN H-level threshold voltage

EN L-level threshold voltage

1.85

V

0.6

CURRENT LIMIT⁽¹⁾

Current Limit TPS56520

LOUT= 1.5µH

5.6

7.8

9

12

A

Current Limit TPS56720

I_OCL

Current Limit TPS56920

10

15

Current Limit TPS56C20

13.2

1.25

1.75

2.25

3

20

Reverse Current Limit TPS56520

Reverse Current Limit TPS56720

Reverse Current Limit TPS56920

Reverse Current Limit TPS56C20

5.3

6.5

6.2

8.2

I_OCLR

OUTPUT UNDERVOLTAGE PROTECTION (UVP)

V_OVP

V_UVP

Output OVP trip threshold

Output UVP trip threshold

OVP detect (L>H)

UVP detect (H>L)

125%

60%

VOUT

THERMAL SHUTDOWN

Shutdown temperature⁽¹⁾

Hysteresis⁽¹⁾

160

23

°C

T_SDN

Thermal shutdown Threshold

Pre-thermal warning threshold

130

UVLO

UVLO Threshold

Wake up to VREG5 voltage

Hysteresis VREG5 voltage

3.45

0.45

3.9

4.2

V

0.56

0.61

(1) Ensured by design. Not production tested.

9

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

7.6 Timing Requirements

MIN

TYP

MAX

UNIT

SOFT START

Issc

SS charge current

VSS=0.5V , 25 °C

VSS=0.5V

–6.4

0.14

–6

–5.6

0.26

µA

IssD

SS discharge current

0.2

mA

SERIAL INTERFACE^{(1) (2) (3)}

V_IL

LOW level input voltage

0.6

V

V_IH

V_hys

HIGH level input voltage

1.8

Hysteresis of Schmitt trigger inputs

0.11

LOW level output voltage (Open drain, 3mA

sink current)

V_OL

t_SP

0.4

V

Pulse width of spikes suppressed by input

filter

32

ns

f_scl

SCL clock frequency

400

kHz

us

ns

us

t_HD;STA

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

Hold time (repeated) START condition.

LOW period of SCL clock

HIGH period of SCL clock

Set-up time for a repeated START condition

Data Hold time

0.6

1.3

0.6

50

900

Data set-up time

100

Rise time (SDA or SCL)

20+0.1Cb(4)

0.6

300

t_f

Fall time (SDA or SCL)

t_SU;STO

Set-up time for STOP condition

Bus free time between STOP and START

condition

t_BUF

C_b

1.3

us

Capacitive load for each bus line

400

pF

(1) Ensured by design. Not production tested.

(2) Refer to Figure 1 below for I²C Timing Definitions

(3) Cb = capacitance of bus line in pF

V

IH

V

IL

Figure 1. I²C Timing Definitions (reproduced from Phillips I²C spec Version 1.1)

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ON-TIME TIMER CONTROL

T_ON

SW On Time

SW=12V, VOUT=1.1V

25°C, VFB= 0.5V

180

285

ns

(1)

T_OFF

SW Minimum off time

(1) Ensured by design. Not production tested.

10

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

7.8 Typical Characteristics

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

60

1,100

1,050

1,000

950

V_IN= 17 V

50

40

30

20

10

0

900

850

œ10

800

0

2

4

6

8

10

12

14

16

18

œ50

0

50

100

150

C003

C001

EN Input Voltage (V)

T_JJunction Temperature (°C)

Figure 2. TPS56X20 Enable Input Current

Figure 3. TPS56520 Quiescent Current

200

150

100

50

700

650

600

550

500

450

400

I_OUT= 5 A

V_OUT= 1.8V

V_OUT= 0.6V

V_OUT= 1.0V

0

œ50

0

50

100

150

4

6

8

10

12

14

16

18

C002

C004

T_JJunction Temperature (°C)

V_IN- Input Voltage (V)

Figure 4. TPS56520 Shutdown Quiescent Current

Figure 5. TPS56520 Switching Frequency

600

0.606

0.604

0.602

0.600

0.598

0.596

0.594

I_O= 50 mA, V_OUT= 1.1 V

V_OUT= 1.0V

V_OUT= 1.8V

V_OUT= 0.6V

550

500

450

400

0.0

1.0

2.0

3.0

4.0

5.0

œ50

0

50

100

150

C005

C006

I_O- Output Current (A)

T_JJunction Temperature (°C)

Figure 6. TPS56520 Switching Frequency,

Eco-mode™ = OFF

Figure 7. TPS56520 Feedback Voltage

11

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Typical Characteristics (continued)

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

8.00

1,000

950

900

850

800

V_SS= 0.5 V

7.50

7.00

6.50

6.00

5.50

5.00

4.50

4.00

œ50

0

50

100

150

œ50

0

50

100

150

C006

C008

T_JJunction Temperature (°C)

Figure 8. TPS56520 Soft Start Charging Current

Figure 9. TPS56720 Quiescent Current

200

150

100

50

700

650

600

550

500

450

400

I_OUT= 7 A

V_OUT= 0.6V

V_OUT= 1.0V

V_OUT= 1.8V

0

œ50

0

50

100

150

4

6

8

10

12

14

16

18

C009

C011

T_JJunction Temperature (°C)

V_IN- Input Voltage (V)

Figure 10. TPS56720 Shutdown Quiescent Current

Figure 11. TPS56720 Switching Frequency

600

0.606

0.604

0.602

0.600

0.598

0.596

0.594

I_O= 50 mA, V_OUT= 1.1 V

V_OUT= 1.0V

V_OUT= 1.8V

V_OUT= 0.6V

550

500

450

400

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

œ50

0

50

100

150

C012

C013

I_O- Output Current (A)

T_JJunction Temperature (°C)

Figure 12. TPS56720 Switching Frequency,

Eco-mode™ = OFF

Figure 13. TPS56720 Feedback Voltage

12

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Typical Characteristics (continued)

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

8.00

1,100

1,050

1,000

950

V_SS= 0.5 V

7.50

7.00

6.50

6.00

5.50

5.00

4.50

4.00

900

850

800

œ50

0

50

100

150

œ50

0

50

100

150

C014

C015

T_JJunction Temperature (°C)

Figure 14. TPS56720 Soft Start Charging Current

Figure 15. TPS56920 Quiescent Current

200

150

100

50

700

650

600

550

500

450

400

I_OUT= 9 A

V_OUT= 1.8V

V_OUT= 1.0V

V_OUT= 0.6V

0

œ50

0

50

100

150

4

6

8

10

12

14

16

18

C016

C018

T_JJunction Temperature (°C)

V_IN- Input Voltage (V)

Figure 16. TPS56920 Shutdown Quiescent Current

Figure 17. TPS56920 Switching Frequency

600

0.606

0.604

0.602

0.600

0.598

0.596

0.594

I_O= 50 mA, V_OUT= 1.1 V

V_OUT= 1.0V

V_OUT= 0.6V

V_OUT= 1.8V

550

500

450

400

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

œ50

0

50

100

150

C019

C020

I_O- Output Current (A)

T_JJunction Temperature (°C)

Figure 18. TPS56920 Switching Frequency,

Eco-mode™ = OFF

Figure 19. TPS56920 Feedback Voltage

13

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Typical Characteristics (continued)

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

8.00

1,100

1,050

1,000

950

V_SS= 0.5 V

7.50

7.00

6.50

6.00

5.50

5.00

4.50

4.00

900

850

800

œ50

0

50

100

150

œ50

0

50

100

150

C021

C022

T_JJunction Temperature (°C)

Figure 20. TPS56920 Soft Start Charging Current

Figure 21. TPS56C20 Quiescent Current

200

150

100

50

700

650

600

550

500

450

400

I_OUT= 12 A

V_OUT= 1.8V

V_OUT= 1.0V

V_OUT= 0.6V

0

œ50

0

50

100

150

4

6

8

10

12

14

16

18

C023

C025

T_JJunction Temperature (°C)

V_IN- Input Voltage (V)

Figure 22. TPS56C20 Shutdown Quiescent Current

Figure 23. TPS56C20 Switching Frequency

600

0.606

0.604

0.602

0.600

0.598

0.596

0.594

I_O= 50 mA, V_OUT= 1.1 V

V_OUT= 1.0V

V_OUT= 1.8V

V_OUT= 0.6V

550

500

450

400

350

0.0

2.0

4.0

6.0

8.0

10.0

12.0

œ50

0

50

100

150

C026

C027

I_O- Output Current (A)

T_JJunction Temperature (°C)

Figure 24. TPS56C20 Switching Frequency,

Eco-mode™ = OFF

Figure 25. TPS56C20 Feedback Voltage

14

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Typical Characteristics (continued)

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

8.00

V_SS= 0.5 V

7.50

7.00

6.50

6.00

5.50

5.00

4.50

4.00

œ50

0

50

100

150

C028

T_JJunction Temperature (°C)

Figure 26. TPS56C20 Soft Start Charging Current

15

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS56X20 is a synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each

channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the

required output capacitance required to meet a specific level of performance. The output voltage of the

TPS56X20 can be set by either VFB with divider resistors (Adjusting the Output Voltage by External Regulation

Mode) or I2C compatible interface (Programming the Output Voltage by Internal Regulation Mode).

When only external regulation mode is used in a TPS56X20 application, the VOUT terminal should be tied to the

output voltage of the converter and SDA & SCL terminals should be grounded. A0 & A1 terminals may be

floating.

When only internal regulation mode is used in a TPS56X20 application, the VFB terminal should be connected to

the output voltage of the converter.

The integrated MOSFETs allow for high efficiency power supply designs. The MOSFETs have been sized to

optimize efficiency for lower duty cycle applications.

8.2 Functional Block Diagram

6

1

16

VIN

EN

VREG5

EN

UVLO

EN

Logic

VREG5

+

7

8

PVIN

OV

EN

-

+25%

VREG5

INT

19

20

VOUT

VFB

Control Logic

14

VBST

-

EXT

+PWM

+

1 shot

13

12

11

SW

18

SS

XCON

ON

VREG5

0,6V

VREF

INT

EXT

¹⁰PGND

DAC

VOUT = 0.6V

to 1.87V

9

+

SW

PGND

INT=

VID I²C

Output

Voltage

Selected

ZC

-

PGND

SW

7 bits

+

17

OCP

GND

OCP

-

2

3

4

5

Serial

Interface

SDA

SCL

A1

VALLEY CURRENT LIMIT

EN

-

+15%

+

Chip ADDR

01101 A₁A₀

15

PGOOD

OV

UVLO

TSD

AO

PWM

COMPARATOR

INPUT

Protection

Logic

-

+

-15%

Figure 27. TPS56520, TPS56720 and TPS56920 20 Terminal

16

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Functional Block Diagram (continued)

6

20

VIN

VREG5

EN

UVLO

1

EN

Logic

VREG5

+

7

PVIN

OV

8

EN

-

PVIN

+25%

VREG5

INT

23

24

VOUT

VFB

Control Logic

18

VBST

-

17

SW

EXT

+PWM

+

16

SW

1 shot

15

14

13

22

SS

XCON

ON

VREG5

0,6V

VREF

INT

EXT

12

11

10

9

PGND

DAC

VOUT = 0.6V

to 1.87V

+

SW

INT=

VID I²C

Output

Voltage

Selected

ZC

-

PGND

SW

7 bits

+

21

OCP

GND

OCP

-

2

3

4

5

Serial

Interface

SDA

SCL

A1

VALLEY CURRENT LIMIT

EN

-

+15%

+

Chip ADDR

01101 A₁A₀

19

PGOOD

OV

UVLO

TSD

AO

PWM

COMPARATOR

INPUT

Protection

Logic

-

+

-15%

Figure 28. TPS56C20 24 Terminal

8.3 Feature Description

8.3.1 PWM Operation

The main control loop of the TPS56X20 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ mode control. D-CAP2™ control combines constant on-time control with an

internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal

timer expires. This timer is set by the converter’s input voltage, VIN, and the output voltage, VOUT, to maintain a

pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset

and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.

An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR

induced output ripple from D-CAP2™ mode control.

8.3.2 PWM Frequency and Adaptive On-Time Control

TPS56X20 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS56X20 runs with a pseudo-constant frequency of 500 kHz by using the input voltage and output voltage to

set the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output

voltage, therefore, when the duty ratio is VO/PVIN, the frequency is constant.

17

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Feature Description (continued)

8.3.3 VIN and Power VIN Terminals (VIN and PVIN)

The device allows for a variety of applications by using the VIN and PVIN terminals together or separately. The

VIN terminal voltage supplies the internal control circuits of the device. The PVIN terminal voltage provides the

input voltage to the power converter system. The input voltage for VIN and PVIN can range from 4.5V to 17V.

8.3.4 Auto-Skip Eco-mode™ Control

The TPS56X20 is designed with Auto-Skip Eco-mode™ to increase light load efficiency.

8.3.5 Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN terminal becomes high, 6-µA current begins charging the

capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained

during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.6 V and SS terminal

source current is 6µA.

C_SS(nF)´ VFB(V)

Tss(ms) =

Issc(mA)

(1)

The TPS56X20 contains a unique circuit to prevent current from being pulled from the output during startup if the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start

becomes greater than internal feedback voltage, VFB), the controller slowly activates synchronous rectification

by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOUT)

starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. When pre-

biased conditions exist, it is recommended to disable the device by pulling the EN terminal to ground.

8.3.6 Power Good

The power-good function is activated after soft start has finished. The PGOOD output is an open drain output.

When the output voltage is between 85% and 110% of the target value, internal comparator detect power good

state and the power good signal becomes high. If the output voltage is lower than 80% or greater than 115% of

the target value, the power good signal becomes low.

8.3.7 Overcurrent Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The

switch current is monitored by measuring the low-side FET switch voltage between the SW terminal and GND.

This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,

VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current

decreases linearly. The average value of the switch current is the load current Iout. The TPS56X20 constantly

monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.

If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented

per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below

the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching

cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in

the same manner.

There are some important considerations for this type of overcurrent protection. The peak current is the average

load current plus one half of the peak-to-peak inductor current. The valley current is the average load current

minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent

threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the

output voltage tends to fall as the demanded load current may be higher than the current available from the

converter. When the output voltage becomes lower than 60% of the target voltage, the UVP comparator detects

it. Depending on the values of Hiccup Mode bit and UVP Latchoff Mode bit in the Control A and Control B

registers, the device may enter Hiccup Mode or Latchoff Mode or keep running under cycle-by-cycle current

limiting.

18

TPS56C20, TPS56920, TPS56720, TPS56520

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Feature Description (continued)

The TPS56X20 also implements reverse overcurrent protection. When reverse overcurrent protection is

triggered, the high-side MOSFET turns on for the preset on-time and then the low-side MOSFET turns on to

monitor the switch valley current. The high-side MOSFET turns on again if either VFB pin voltage drops below

reference voltage, or the reverse switch current hits the reverse current trip point.

8.3.8 UVLO Protection

Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 terminal. When the VREG5 voltage

is lower than UVLO threshold voltage, the TPS56X20 is shut off. This protection is non-latching.

8.4 Device Functional Modes

8.4.1 Operation at Light Loads

The TPS56x20 works in Auto-Skip Eco-mode^TMat light load to boost the efficiency. As the output current

decreases from heavy load condition, the inductor current is also reduced and eventually comes to the where its

ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load

current further decreases the converter run into discontinuous conduction mode. The on-time is kept same as it

was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller

load current to the level of the nominal output voltage. The transition point to the light load operation I_O(LL)current

can be estimated with Equation 2 with 500kHz used as ƒsw.

PVIN - V

´ V

OUT

(

)

1

OUT

IOUT

=

´

(LL)

2´L_O´ ƒ_SW

PVIN

(2)

8.5 Programming

8.5.1 I²C Interface

The TPS56X20 implements a subset of the Phillips I²C specification Ver. 1.1. The TPS56X20 is a Slave-Only (it

never becomes a Master, and so never pulls down the SCL terminal on the I²C bus). An I²C transaction consists

of either writing a data byte to one of the TPS56X20’s internal registers which requires a 3-byte transaction or

reading back one byte from a register which requires a 4-byte transaction. The protocols follow the System

Management Bus (SMBUS) Specification Ver. 2.0 Write Byte and Read Byte protocols. This spec is available on

the Internet for further reading, but the subset implemented in TPS56X20 is described below.

Long-form address modes, multi-byte data transfers and Packet Error Code (PEC) protocols are not supported in

this implementation, though a Check Sum bit unique to the TPS56X20 is implemented and described below. The

SMBUS Send Byte protocol (the 2-byte protocol used in TPS56921) is not implemented on TPS56X20.

The I²C interface terminals are composed of the SDA (Data) and SCL (Clock) terminals, and the A0 and A1

terminals to set up the chip’s address. SDA and SCL are designed to be used with pullup resistors to 3.3V. A0

and A1 are designed to be either grounded (logic LOW) or left open (logic HIGH) and should not tie to a high

voltage.

8.5.2 I²C Protocol

Input voltage – Logic levels for I²C SDA and SCL terminals are not fixed. For the TPS56X20, a logic “0” (LOW)

should be 0V and a logic “1” (HIGH) can be any voltage between 1.8V and 3.3V. Logic HIGH is generated by

external pullup resistors (see next paragraph).

Output voltage – the I²C bus has external pullup resistors, one for SCL and one for SDA. These pull up to a

voltage called VDD which must lie between 1.8V and 3.3V. The outputs are pulled down to their logic LOW levels

by open-drain outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be

selected so that the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is

less than 3.3mA.

Data format – One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data

on the SDA line must be stable during the HIGH period of the SCL clock line. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW.

19

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Programming (continued)

START and STOP conditions – A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a

START condition. A LOW to HIGH transition on the SDA line while the SCL line is HIGH defines a STOP

condition. START and STOP conditions are always generated by the Master. The bus is considered to be BUSY

after the condition. It is considered to be free again after a minimum of 4.7µS after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated

START are functionally identical.

Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for

an ACK signal put onto the bus by the TPS56X20 pulling down on the bus to acknowledge receipt of the data). In

the following diagrams, shaded blocks indicate SDA data generated by the TPS56X20 being sent to the Master

I²C controller, while white blocks indicate SDA data generated by the Master being received by the TPS56X20.

The Master always generates the SCL signal.

Sending data to the TPS56X20 is accomplished using the following 3-byte sequence, referred to as a Write Byte

transaction as follows:

Wr

S

Chip Address

A

Register Address

A

Data Byte

A

P

A6 A5 A4 A3 A2 A1 A0

0

ACK R7 R6 R5 R4 R3 R2 R1 R0

D7 D6 D5 D4 D3 D2 D1 D0 ACK

ACK

SDA

SCL

Start Condition

Stop Condition

Figure 29. A complete Write Byte transfer, adapted from SMBUS spec

Reading back data from the TPS56X20 is accomplished using the following 4-byte sequence, referred to as a

Read Byte transaction:

Wr

Rd

S

Chip Address

A

Register Address

A

Sr

Chip Address

A

Data Byte

A

P

A6 A5 A4 A3 A2 A1 A0

0

ACK R7 R6 R5 R4 R3 R2 R1 R0 ACK

A6 A5 A4 A3 A2 A1 A0

1

ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SDA

SCL

Start Condition

Stop Condition

Repeated Start

Figure 30. A complete Read Byte transfer, adapted from SMBUS spec

On the TPS56X20, the I2C bus is inactive until:

1. Both SDA and SCL have been at a logic high simultaneously to prevent power sequencing issues

2. VREG5 is in regulation.

Control registers should not be written to during the Soft Start time, but can be written before VOUT is enabled or

after the PGOOD terminal or status register go high, indicating that soft start is complete.

Until a VOUT command has been accepted, the TPS56X20’s output voltage will be determined by the external

resistor divider feedback to the VFB terminals, the condition of the EN terminals, and the capacitance on the SS

terminals.

When the TPS56X20 receives a Chip Address code it recognizes to be its own, it will respond by sending an

ACK (pulling down on the SDA bus during the next clock on the SCL bus). If the address is not recognized, the

TPS56X20 assumes that the I²C message is intended for another chip on the bus, and it takes no action. It will

disregard data sent thereafter until the next START is begun.

If, after recognizing its Chip Address, the TPS56X20 receives a valid Register Address, it will send an ACK and

prepare to receive a Data Byte to be sent to that Register.

If a valid Data Byte is then received, it will send an ACK and will set the output voltage to the desired value. If the

byte is deemed invalid, ACK will not be sent and the Master will need to retry by sending a STOP sequence

followed by a new START sequence and an initiating resend of the entire address/data packet. When sending

data to the Output Voltage register, the output voltage will only change upon receipt of a valid data byte.

20

TPS56C20, TPS56920, TPS56720, TPS56520

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Programming (continued)

8.5.3 I²C Chip Address Byte

The 7-bit address of the TPS56X20 can be any number between 34h (0110100) and 37h (0110111). The 5

MSB’s are set internally and the 2 LSB’s are customer-selectable via the A1 and A0 terminals, allowing up to 4

TPS56X20’s to be controlled on the same I2C bus. When the Master is sending the address as an 8-bit value,

the 7-bit address should be sent followed by a trailing 0 to indicate this is a WRITE operation. A0 and A1 must be

floated for logic 1. Do not tie them to external voltage source. The following codes assume this trailing zero.

Table 2. TPS56X20 Address as a Function of A1 and A0 Terminals

A1

A0

Address (binary)

01101000

Address (hex)

Ground (0)

Open (1)

Ground (0)

Open (1)

Ground (0)

Open (1)

68h

6Ah

6Ch

6Eh

01101010

01101100

01101110

8.6 Register Maps

8.6.1 I²C Register Address Byte

The TPS56X20 contains four customer-accessible registers. Register 0 is the Output Voltage register. Registers

8 and 9 set several operating features for the regulator. The lower 3 bits of Register 9 sets the current limit for

the high-current, etc. Register 24 provides the status of the regulator. The register map is as follows:

Register

Name

Addr

(Decimal)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

VOUT[6:0]

—

Bit 2

Bit 1

Bit 0

VOUT

0

Odd Parity

Internal Mode

Hiccup

Mode On

ECO Mode

On

Control A

8

PGOOD Delay [1:0]

OVP

DAC Settle [1:0]

UVP

Control B

9

Enable

—

Latchoff

Mode Off

Latchoff

Mode Off

—

Current Limit [2:0]

Status

(Read Only)

OT Shut

Down

Early OT

Warn

24

TI Only

PGOOD

8.6.2 Output Voltage Registers

The lower 7 bits of the Output Voltage Register controls the VOUT of the TPS56X20. These bits are the 7-bit

selector for one of the output voltages.

As previously mentioned, when the IC powers up, the startup and output voltage regulation conditions are set by

the external resistor divider feedback to the VFB terminal, the condition of the EN terminal, and the capacitance

on the SS terminal.

Bringing the EN terminal high (or setting the Enable bit in Control register 9 high) begins a soft-start ramp on the

regulator.

After applying VIN, VREG5 will come into regulation and the I2C interface will active. The user can activate soft

start and VOUT by bring the EN terminal high or programming the Enable bit in Control Register 9.

By default, the part will regulate VOUT using the external feedback resistors connected to the VFB terminal. The

user can then program VOUT by writing any VOUT code. Alternatively, if the EN terminal is low, soft start and

VOUT can be enabled by writing the desired VOUT code and programming the Enable bit to a one.

21

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www.ti.com.cn

Table 3. Ideal VOUT vs VOUT[6:0] Code

Code

0

Binary

VOUT

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

Code

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Binary

VOUT

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

Code

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

Binary

VOUT

1.24

1.25

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

1.38

1.39

1.40

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

Code

96

Binary

VOUT

1.56

1.57

1.58

1.59

1.60

1.61

1.62

1.63

1.64

1.65

1.66

1.67

1.68

1.69

1.70

1.71

1.72

1.73

1.74

1.75

1.76

1.77

1.78

1.79

1.80

1.81

1.82

1.83

1.84

1.85

1.86

1.87

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

1

97

2

98

3

99

4

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

8.6.3 CheckSum Bit (VOUT Register Only)

The CheckSum bit should be set by the Master controller to be the exclusive-NOR of the D[6:0] bits (odd parity).

This will be used by the TPS56X20 to check that a valid data byte was received. If CheckSum is not equal to the

exclusive-NOR of these bits, the TPS56X20 assumes that an error occurred during the data transmission, and it

will not send an ACK bit, nor will it reset the VOUT to the received code (or, if the Control register, will not reset

the register contents as requested). The Master should try again to send the data. When reading back the VOUT

register, the parity bit is also sent back.

22

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

8.6.4 Control Registers

There are 4 control registers: Registers 0, 8, 9 and 24.

Table 4. Summary of Default Control Bits

DEFAULT

(BINARY)

CONTROL BIT(s)

FUNCTION

VOUT code, 7 bits VOUT[6:0] + odd parity checksum bit at VOUT[7]

Writing a valid code to this register also sets Internal Mode.

VOUT[7:0]

0110010

Sending an invalid code (checksum incorrect) to this register does not change register contents

or set Internal/Enable bits.

1. If set to 1, the part switches to INTERNAL mode and VOUT register value controls output

voltage.

0

Internal Mode

(EXTERNAL

mode)

2. Writing a valid code to the VOUT register sets this Internal Mode bit to 1.

3. The part can be set back to EXTERNAL control mode at any time by writing this bit to 0.

Part defaults to PGOOD Delay = 26.4µS

PGOOD Delay [1:0]

Hiccup Mode

11

1

Part defaults to Hiccup Mode On. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

ECO Mode

0

Part defaults to ECO Mode Off

Part defaults to DAC Settle = 25µS

Part defaults to Disabled.

DAC Settle [1:0]

11

Enable

0

1

This bit can be set to 1 by writing the bit to 1. The external EN terminal being set to 1 overrides

the register value (you cannot disable the part by writing a 0 if the EN terminal is high).

OVP Latchoff Mode

Disable

Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

UVP Latchoff Mode

Disable

Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

1

CurLim[2:0]

111

Selects default current limit value

Enable: This bit can be used to enable the regulator just like setting the EN terminal high. The EN terminal has

priority (if EN=high, the Enable bit does nothing, the chip is already enabled). This allows the customer to tie EN

to GND externally or leave the EN terminal floating (the terminal is pulled low internally) and subsequently enable

the regulator by I²C software control.

DAC Settle [1:0]: When a new VOUT voltage is selected, this happens by setting an internal DAC to a new

internal VREF voltage. If this happens instantly, the regulator loop will be thrown out of regulation and the

DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. This can cause

VOUT overshoots (or undershoots) or head to high transient input currents. Therefore, an analog filter on the

DAC output causes this internal VREF to change more slowly. The DAC Settle[1:0] bits change the filter time

constant as follows:

DAC Settle [1:0]

Typical Filter Time Constant

00

01

10

11

6 µs

10 µs

15 µs

25 µs

The power-up default value of the DAC Settle[1:0] bits is 11.

Internal Mode: This bit can be interrogated to discover whether the chip is running in EXT Mode (using external

resistor dividers to VFB terminal to set the output voltage) or INT Mode (using codes set in Output Voltage

register to set the output voltage). Further, it can be set by the user to force either Internal or External mode.

Writing a valid value to a VOUT register always sets External to 1 on the corresponding regulator.

In default, the TPS56X20 will start up into external mode and the output voltage is set by VFB with divider

resistors. If starting up into internal VID mode is desired, the input voltage should be applied first, write Internal

Mode bit to "1" the next, then enable the device by EN terminal or EN bit.

23

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Current Limit [2:0]: Set the low-side valley current limit threshold for the regulator. Power-up default setting is

[111].

TPS56520

TPS56720

TPS56920

TPS56C20

Typical Current

Limit

Typical Current

Limit

Typical Current

Limit

Typical Current

Limit

Current Limit [2:0]

Units

000

001

010

011

100

101

110

111

1.72

2.28

2.88

3.44

4.32

5.32

6.4

3

3.8

4.76

5.8

5.08

6.16

Amps

3.6

4.58

5.52

6.68

8.24

9.92

12.12

7.68

6.88

8.52

10.32

12.52

15.16

9.12

11.16

13.44

16.24

19.76

7.84

PGOOD Delay [1:0]: Especially for low load currents, large jumps in the I²C-controlled VOUT setting may have a

long settling time compared to the UV/OV thresholds. If this happens, it will cause the PGOOD signal to

temporarily indicate a fault condition. If this is not the desired behavior, it is possible to “blank” the PGOOD being

pulled down for some number of µS according to the table below.

PGOOD Delay

FUNCTION

[1:0]

00

01

10

11

Set delay from PGOOD fault to PGOOD terminal pulldown to 0µS

Set delay from PGOOD fault to PGOOD terminal pulldown to 6.6µS

Set delay from PGOOD fault to PGOOD terminal pulldown to 13.2µS

Set delay from PGOOD fault to PGOOD terminal pulldown to 26.4µS (Default)

On power-up, the delay defaults to 26.4 µS. The user can reset the blanking time using these codes at any time

without affecting any other device behavior.

8.6.5 Latchoff

Latchoff turns the output voltage off in the event of an overvoltage or undervoltage condition. V_OUTwill not be

enabled again until the EN terminal or EN bit is cycled. By default Latchoff Mode is disabled, but overvoltage

protection (OVP) and undervoltage protection (UVP) Latchoff Modes can be enabled by setting the OVP and

UVP Latchoff Mode Off bits to zero. Power cycling Vin will reset these bits to their default values. If either

Latchoff Mode is enabled, Hiccup Mode On should be disabled.

24

TPS56C20, TPS56920, TPS56720, TPS56520

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

9 Applications and Implementation

9.1 Application Information

The devices are synchronous step down DC-DC converters rated at different output currents whose output

voltage can be dynamically scaled by sending commands over an I2C interface. The section below discusses the

design of the external components to complete the power supply design by using a typical application as a

reference

9.2 Typical Application

9.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter

3.3 V

U1

R1

1.0kW

R2

1.0kW

R3

1.0kW

R4

10.0kW

TPS56520

TPS56720

TPS56920

1

PWRGD

20

19

18

17

16

15

14

13

11

12

EN

VFB

VOUT

SS

2

3

4

SDA

SCL

SDA

SCL

A1

R5

18.2kW

C8

2

A1

GND

5

6

A0

VREG5

PGOOD

VBST

SW

VIN = PVIN = 4.5-17V

VIN

C5

2.2µF

C6

0.01µF

R6

22kW

7

VIN

PVIN

PGND

8

C4

0.1µF

C1

10µF

C2

10µF

C3

4.7µF

9

L1

SW

AGND

10

SW

VOUT

PGND

AGND

1.5µH

C7

100µF

PGND

DNP R3 for digital EN control

Optional

1

2

Figure 31. Typical Application Schematic – TPS56520, TPS56720 and TPS56920

9.2.1.1 Design Requirements

To begin the design process, the user must know a few application parameters:

•

Input voltage range

Output voltage

Output current

Output voltage ripple

Input voltage ripple

25

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

Table 5. Design Example

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

4.5V to 17V

1.1V

Output voltage

Transient response, 3A-9A load step

Output voltage ripple

Input ripple voltage

ΔV_OUT= ±5%

25mV

400mA

Output current rating

12A

Operating Frequency

500kHz

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB terminal. It is recommended to

use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate V_OUT

.

To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to

noise, and the voltage errors from the VFB input current are more noticeable.

R5

æ

ö

V_OUT= 0.6 ´ 1+

ç

÷

R6

è

ø

(3)

9.2.1.2.1.1 Output Filter Selection

The output filter used with the TPS56X20 is an LC circuit. This LC filter has double pole at:

1

F =

P

2p L_OUT´ C_OUT

(4)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal

gain of the TPS56X20. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls

off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that

reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the

zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole

of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the

high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the

values recommended in Table 6.

Table 6. Recommended Component Values

Output Voltage (V)

R5 (kΩ)

14.7

18.2

22

R6 (kΩ)

22

C8 (pF)

DNP

L1 (µH)

1.0-2.2

C7 (µF)

44-100

1

1.1

1.2

1.5

1.8

22

DNP

22

DNP

33

22

DNP

44.2

22

DNP

For higher output voltages additional phase boost can be achieved by adding a feed forward capacitor (C6) in

parallel with R5.

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,

Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak

current and the RMS or heating current rating must be greater than the calculated RMS current. Use 500 kHz for

f_SW

.

Use 500 kHz for f_SW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS

current of Equation 7.

V

- V_OUT

V_OUT

IN(MAX)

Il_P-P

=

´

V

L_O´ ¦_SW

IN(MAX)

(5)

26

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

Il_P-P

Il_PEAK= I_O+

2

(6)

(7)

1

2

I_LO(RMS)

=

I_O

+

Il_P-P

12

The capacitor value and ESR determines the amount of output voltage ripple. The TPS56X20 is intended for use

with ceramic or other low ESR capacitors. Recommended values range from 44µF to 100µF. Use Equation 8 to

determine the required RMS current rating for the output capacitor.

V

x (V - V

)

OUT

IN

OUT

I

=

Co(RMS)

12 x V x L

IN

x

f_SW

O

(8)

9.2.1.2.2 Input Capacitor Selection

The TPS56X20 requires an input decoupling capacitor and a bulk capacitor depending on the application. A

ceramic capacitor of 20µF or above is recommended for the decoupling capacitors from PVIN to PGND.

Additionally, a 4.7 µF ceramic capacitor from VIN to GND is also recommended. The capacitors voltage rating

needs to be greater than the maximum input voltage.

9.2.1.2.3 Bootstrap Capacitor Selection

The 0.1 µF ceramic capacitors must be connected between the VBST to SW terminals for proper operation. It is

recommended to use ceramic capacitors with a dielectric of X5R or better.

9.2.1.2.4 VREG5 Capacitor Selection

For the TPS56920/720/520, a 2.2 µF ceramic capacitor must be connected between the VREG5 to GND

terminals for proper operation.

9.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 5 V

V_IN= 12 V

0.0

1.0

2.0

3.0

4.0

5.0

0.01

0.1

Output Current - A

1

10

C029

C030

Output Current - A

Figure 32. TPS56520 Efficiency

Figure 33. TPS56520 Eco-mode™ Efficiency

27

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

0.10

0.08

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40

V_IN= 12 V

0.06

V_IN= 12 V

0.04

0.02

0.00

-0.02

-0.04

V_IN= 5 V

-0.06

-0.08

-0.10

0.0

1.0

2.0

3.0

4.0

5.0

0.0

1.0

2.0

3.0

4.0

5.0

C031

C032

Output Current - A

Figure 34. TPS56520 Load Regulation

Figure 35. TPS56520 Load Regulation with Eco-mode™

0.10

0.08

100

90

I_OUT= 10 mA,

Eco-mode = OFF

Eco-mode = ON

0.06

80

0.04

70

V_IN= 5 V

0.02

60

0.00

50

40

30

20

10

0

V_IN= 12 V

œ0.02

œ0.04

œ0.06

œ0.08

œ0.10

I_OUT= 5 A

5

8

11

14

17

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

C033

C034

Input Voltage - V

Output Current - A

Figure 36. TPS56520 Line Regulation

Figure 37. TPS56720 Efficiency

100

90

80

70

60

50

40

30

20

10

0

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

V_IN= 12 V

V_IN= 5 V

V_IN= 12 V

V_IN= 5 V

0.01

0.1

Output Current - A

1

10

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

C036

C035

Output Current - A

Figure 38. TPS56720 Eco-mode™ Efficiency

Figure 39. TPS56720 Load Regulation

28

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

0.20

0.15

I_OUT= 10 mA,

Eco-mode = OFF

I_OUT= 10 mA,

Eco-mode = ON

V_IN= 12 V

0.10

0.05

0.00

œ0.05

œ0.10

œ0.15

œ0.20

V_IN= 5 V

I_OUT= 7 A

-0.40

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

5

8

11

14

17

C037

C038

Output Current - A

Input Voltage - V

Figure 40. TPS56720 Load Regulation with Eco-mode™

Figure 41. TPS56720 Line Regulation

100

90

100

90

80

70

60

50

40

30

20

10

0

80

70

V_IN= 5 V

60

V_IN= 5 V

V_IN= 12 V

50

40

30

20

10

0

V_IN= 12 V

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

0.01

0.1

Output Current - A

1

10

C039

C040

Output Current - A

Figure 42. TPS56920 Efficiency

Figure 43. TPS56920 Eco-mode™ Efficiency

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40

V_IN= 12 V

V_IN= 5 V

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

C041

C042

Output Current - A

Figure 44. TPS56920 Load Regulation

Figure 45. TPS56520 Load Regulation with Eco-mode™

29

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ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

0.20

I_OUT= 10 mA,

Eco-mode = OFF

I_OUT= 10 mA,

Eco-mode = ON

0.15

0.10

V = 50 mV/div (ac coupled)

OUT

0.05

0.00

œ0.05

œ0.10

œ0.15

œ0.20

I

OUT

= 2 A/div

I_OUT= 9 A

2.25 A to 6.75 A load step,

slew rate = 500 mA / µsec

5

8

11

14

17

C043

Input Voltage - V

Time = 200 µs/div

Figure 46. TPS56920 Line Regulation

Figure 47. TPS56920 Transient Response

I_OUT= 9 A

V

= 100 mV/div (ac coupled)

IN

V

= 20 mV/div (ac coupled)

OUT

PH = 5 V/div

Time = 1 µs/div

Figure 48. TPS56920 Input Voltage Ripple

Figure 49. TPS56920 Output Voltage Ripple

V

= 10 V/div

IN

EN = 5 V/div

V

= 1 V/div

OUT

PGOOD = 2 V/div

Time = 2 ms/div

Figure 50. TPS56920 Start Up Relative to V_IN

30

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

9.2.3 TPS56C20 12-A Converter

3.3 V

R1

1.0kW

R2

1.0kW

R3

1.0kW

R4

10.0kW

U1

1

PWRGD

TPS56C20

24

23

22

21

20

19

18

17

16

15

14

13

EN

VFB

VOUT

SS

2

3

4

SDA

SCL

SDA

SCL

R5

18.2kW

C8

2

A1

GND

VREG5

PGOOD

VBST

SW

5

6

A0

VIN = PVIN = 4.5-17V

VIN

7

C5

3.3µF

C6

0.01µF

R6

22kW

VIN

PVIN

PGND

8

C1

10µF

C2

10µF

C3

4.7µF

9

SW

10

11

12

AGND

SW

C4

0.1µF

PGND

AGND

L1

SW

VOUT

1.5µH

PGND

C7

100µF

PGND

DNP R3 for digital EN control

Optional

1

2

Figure 51. Typical Schematic – TPS56C20

9.2.3.1 Design Requirements

To begin the design process, the user must know a few application parameters:

•

Input voltage range

Output voltage

Output current

Output voltage ripple

Input voltage ripple

9.2.3.2 Design Procedure

Follow the design procedure for the TPS56X20 converter listed above. For the TPS56C20, a 3.3 µF ceramic

capacitor must be connected between the VREG5 to GND terminals for proper operation. Do not load the

VREG5 terminal with any other load. It is recommended to use a ceramic capacitor with a dielectric of X5R or

better.

9.2.3.3 TPS56C20 Application Performance Curves

V_IN= 12 V, V_OUT= 1.0 V, T_a= 25 °C, unless otherwise specified.

31

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

100

90

100

90

80

70

60

50

40

30

20

10

0

80

70

V_IN= 5 V

60

V_IN= 5 V

50

40

30

20

10

0

V_IN= 12 V

0.0

2.0

4.0

6.0

8.0

10.0

12.0

0.01

0.1

1

Output Current - A

10

100

C044

C045

Output Current - A

Figure 52. TPS56C20 Efficiency

Figure 53. TPS56C20 Eco-mode™ Efficiency

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40

V_IN= 12 V

V_IN= 5 V

0.0

2.0

4.0

6.0

8.0

10.0

12.0

0.0

2.0

4.0

6.0

8.0

10.0

12.0

C046

C047

Output Current - A

Figure 54. TPS56C20 Load Regulation

Figure 55. TPS56C20 Load Regulation with Eco-mode™

0.40

0.30

I_OUT= 10 mA,

Eco-mode = OFF

I_OUT= 10 mA,

Eco-mode = ON

0.20

0.10

0.00

œ0.10

œ0.20

œ0.30

œ0.40

I_OUT= 12 A

5

8

11

Input Voltage - V

14

17

C048

Figure 56. TPS56C20 Line Regulation

32

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

10 Power Supply Recommendations

The devices are designed to operate from an input supply range between 4.5 V and 17 V. This input supply must

be well regulated. If the input supply is located more than a few inches from the TPS56X20 device, additional

bulk capacitance may be required in addition to the ceramic bypass capacitors.

11 Layout

11.1 Layout Guidelines

1. Keep the input switching current loop as small as possible. And avoid the input switching current through

thermal Pad.

2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback terminal of the device.

3. Keep analog and non-switching components away from switching components.

4. Make a single point connection from the signal ground to power ground.

5. Do not allow switching current to flow under the device.

6. Keep the pattern lines for VIN and PGND broad.

7. Exposed pad of device must be connected to PGND with solder.

8. VREG5 capacitor should be placed near the device, and connected to GND.

9. Output capacitor should be connected to a broad pattern of the PGND.

10. Voltage feedback loop should be as short as possible, and preferably with ground shield.

11. Kelvin connections should be brought from the output to the feedback terminal of the device.

12. Providing sufficient via is preferable for VIN, SW and PGND connection.

13. PCB pattern for VIN, SW, and PGND should be as broad as possible.

14. Input capacitors should be placed as near as possible to the device.

15. The topside and the bottom side of the PCB should be filled with as much ground plane as possible that has

an uninterrupted heat flow path. The ground plane should be made as large as possible. The PVIN cap

should connect to PGND and the VIN cap should connect to GND.

33

TPS56C20, TPS56920, TPS56720, TPS56520

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

www.ti.com.cn

11.2 Layout Example

Additional Thermal

Vias

Feedback Resistors

VFB

VOUT

SS

EN

Analog Traces on

SDA

the Bottom Layer

Soft Start Cap

SCL

Exposed Thermal

Pad Area

A1

GND

AGND

A0

VREG5

PGOOD

VIN normally

connected to PVIN

VREG5 Cap

VIN

VBST

SW

PVIN Input Bypass

Capacitors

PVIN

PGND

SW

Trace on the

Bottom Layer

PGND

SW

PGND

Power Ground

Output Inductor

Power Ground

Output

Capacitor

VOUT

Figure 57. TPS56X20 Board Layout

34

TPS56C20, TPS56920, TPS56720, TPS56520

www.ti.com.cn

ZHCSC57E –NOVEMBER 2013–REVISED DECEMBER 2017

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

要获得 TPS56C20 Pspice 模型，请访问 www.ti.com.cn/product/cn/tps56x20。

要获得 TPS56920 Pspice 模型，请访问 www.ti.com.cn/product/cn/tps56x20。

要获得 TPS56720 Pspice 模型，请访问 www.ti.com.cn/product/cn/tps56x20。

要获得 TPS56520 Pspice 模型，请访问 www.ti.com.cn/product/cn/tps56x20。

12.2 文档支持

12.2.1 相关文档

《TPS56X20-614，12A，SWIFT^TM稳压器评估模块用户指南》，SBAU227

12.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问

链接。

表 7. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

TPS56C20

TPS56920

TPS56720

TPS56520

12.4 商标

D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

35

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS56520PWPR

TPS56720PWPR

TPS56920PWPR

TPS56C20PWPR

HTSSOP PWP

20

24

2000

330.0

16.4

6.95

7.1

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS56520PWPR

TPS56720PWPR

TPS56920PWPR

TPS56C20PWPR

HTSSOP

PWP

20

24

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TPS56520PWP

TPS56720PWP

TPS56920PWP

TPS56C20PWP

PWP

HTSSOP

20

24

70

60

530

10.2

3600

3.5

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PWP 24

4.4 x 7.6, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224742/B

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS56C20PWP
厂家：	TEXAS INSTRUMENTS
描述：	具有电压调节的 4.5V 至 17V、12A 同步降压转换器 \| PWP \| 24 \| -40 to 85 开关光电二极管输出元件转换器
文件：	总47页 (文件大小：2340K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS56C20PWP [TI]

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