TPS61021A [TI]

具有 0.5V 超低输入电压的 3A 升压转换器;


型号：	TPS61021A
厂家：	TEXAS INSTRUMENTS
描述：	具有 0.5V 超低输入电压的 3A 升压转换器升压转换器
文件：	总27页 (文件大小：5282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS61021A

ZHCSFA0 –JUNE 2016

TPS61021A 具有 0.5V 超低输入电压的 3A 升压转换器

1 特性

3 说明

•

输入电压范围：0.5V 至 4.4V

TPS61021A 为由碱性电池、镍氢电池、锂锰电池或锂

离子电池供电的便携式或智能设备提供了一套电源解决

方案。TPS61021A 能够在电池放电至 1.8V 的低电压

时提供 3.3V 电压和 1.5A 电流输出。TPS61021A 支

持 0.5V 输入电压，从而延长了电池的运行时间。

启动时的最小输入电压为 0.9V

可设置的输出电压范围：1.8V 到 4.0V

效率高达 91%（V_IN= 2.4V、V_OUT= 3.3V 且 I_OUT

= 1.5A 时）

•

2.0MHz 开关频率

TPS61021A 在重负载条件下以 2MHz 开关频率工作，

并且可在轻负载时进入省电模式，从而在整个负载电流

范围内保持高效率。该器件在轻负载条件下从 V_OUT仅

消耗 17μA 静态电流。在关断期间，负载与输入完全断

开。此外，TPS61021A 还提供有 4.35V 输出过压保

护、输出短路保护和热关断保护。

I_OUT> 1.5A，V_OUT= 3.3V（V_IN> 1.8V 时）

17µA 典型静态电流

-40°C 至 125°C 温度范围内的基准电压精度为

±2.5%

•

轻负载下的脉冲频率调制 (PFM) 工作模式

关断时输入与输出真正断开

输出过压保护

TPS61021A 需要使用的外部组件数量较少，因此拥有

非常小巧的解决方案尺寸。该器件支持在 2MHz 开关

频率下使用低值电感或输出电容。

输出短路保护

热关断保护

2mm × 2mm 晶圆级小外形无引线 (WSON) 封装

TPS61021A 采用 2.0mm x 2.0mm WSON 封装。

器件信息⁽¹⁾

2 应用

•

电池供电类物联网 (IoT) 设备

器件型号

TPS61021A

封装

WSON (8)

封装尺寸（标称值）

2.00mm x 2.00mm

游戏控制

温控器

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

便携式医疗设备

超级电容备用系统

典型应用电路

VIN

VOUT

PGND

TPS61021A_FB

OFF

AGND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDM0

TPS61021A

ZHCSFA0 –JUNE 2016

www.ti.com.cn

特性.......................................................................... 1

Application and Implementation ........................ 12

8.1 Application Information............................................ 12

8.2 Typical Application ................................................. 12

Power Supply Recommendations...................... 17

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 8

7.1 Overview ................................................................... 8

7.2 Functional Block Diagram ......................................... 8

7.3 Feature Description................................................... 8

7.4 Device Functional Modes........................................ 10

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Example .................................................... 18

10.3 Thermal Considerations........................................ 18

11 器件和文档支持 ..................................................... 19

11.1 器件支持 ............................................................... 19

11.2 社区资源................................................................ 19

11.3 商标....................................................................... 19

11.4 静电放电警告......................................................... 19

11.5 Glossary................................................................ 19

12 机械、封装和可订购信息....................................... 19

12.1 Package Option Addendum .................................. 20

4 修订历史记录

日期

修订版本

注释

2016 年 6 月

首次发布。

TPS61021A

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ZHCSFA0 –JUNE 2016

5 Pin Configuration and Functions

DSG Package

8-Pin WSON with Thermal Pad

Top View

AGND

VIN

PGND

VOUT

Pin Functions

I/O

DESCRIPTION

NAME

AGND

NO.

Signal ground of the IC

Voltage feedback of adjustable output voltage

Boost converter output

VOUT

3,4

PWR

Enable logic input. Logic high voltage enables the device. Logic low voltage disables the

device and turns it into shutdown mode.

6,7

PWR

The switch pin of the converter. It is connected to the drains of the internal power MOSFETs.

VIN

IC power supply input

Power ground

PGND

PWR

TPS61021A

ZHCSFA0 –JUNE 2016

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

UNIT

EN, FB

3.6

4.6

Voltage range at terminals⁽²⁾

VIN, SW, VOUT

10% duty cycle

4.8

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.5

1.8

0.2

1.0

3.0

NOM

MAX

4.4

UNIT

V_IN

V_OUT

Input voltage range

Output voltage setting range

Effective inductance range

Effective input capacitance range

4.0

0.47

4.7

1.3

µH

µF

°C

C_IN

_OUT≤ 0.3 A

200

125

C_OUT

T_J

Effective output capacitance range

Operating junction temperature

I_OUT> 0.3 A

–40

6.4 Thermal Information

TPS61021A

DSG (WSON)

8 PINS

71.1

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

95.2

41.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.1

ψ_JB

42.0

R_θJC(bot)

13.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

TPS61021A

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ZHCSFA0 –JUNE 2016

6.5 Electrical Characteristics

T_J= –40°C to 125°C, V_IN= 2.4 V and V_OUT= 3.3 V. Typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

0.5

4.4

0.9

0.5

V_INrising

0.8

0.4

V_{IN_UVLO}

Under-voltage lockout threshold

V_INfalling

0.28

IC enabled, No load, No switching

Quiescent current into VIN pin

Quiescent current into VOUT pin

V_IN= 1.8 V to 3.6 V, V_FB= V_REF

0.1 V, T_Jup to 85°C

3.0

µA

I_Q

IC enabled, No load, No switching

V_OUT= 1.8 V to 4.0 V, V_FB= V_REF

0.1 V, T_Jup to 85°C

µA

Shutdown current into VIN and SW

IC disabled, V_IN= 1.8 V to 3.6 V, T_J

up to 85°C

I_SD

0.5

3.0

OUTPUT

V_OUT

Output voltage setting range

1.8

4.0

PWM mode

PFM mode

775

795

801

815

V_REF

V_OVP

Reference voltage at the FB pin

Output over-voltage protection

threshold

V_OUTrising

4.15

4.35

0.1

4.60

V_{OVP_HYS}

I_{FB_LKG}

Over-voltage protection hysteresis

Leakage current at FB pin

µA

I_{SW_LKG}

Leakage current into SW pin

IC disabled, T_Jup to 85°C

3.0

IC disabled, V_OUT= 4.0 V, T_Jup to

85°C

I_{VOUT_LKG}Leakage current into VOUT pin

µA

POWER SWITCH

High-side MOSFET on resistance

R_DS(on)

V_OUT= 3.3 V

mΩ

Low-side MOSFET on resistance

V_IN= 2.4 V, V_OUT= 3.3 V, PWM

mode

f_SW

Switching frequency

2.0

MHZ

t_{OFF_min}

I_{LIM_SW}

Minimum off time

Valley current limit

120

V_IN= 2.4 V, V_OUT= 3.3 V

3.0

4.3

LOGIC INTERFACE

V_IN> 1.2 V

V_IN≤ 1.2 V

V_IN> 1.2 V

V_IN≤ 1.2 V

0.84

V_{EN_H}EN Logic high threshold

0.7 x V_IN

0.36

V_{EN_L}

EN Logic Low threshold

0.3 x VIN

PROTECTION

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

T_Jrising

150

°C

T_{SD_HYS}

T_Jfalling below T_SD

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ZHCSFA0 –JUNE 2016

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6.6 Typical Characteristics

V_IN= 2.4 V, V_OUT= 3.3 V, T_J= 25°C, unless otherwise noted

100

Vin = 0.9 V

Vin = 1.2 V

Vin = 1.8 V

Vin = 2.4 V

Vin = 3.0 V

Vout = 2.5 V

Vout = 3.3 V

Vout = 4.0 V

0.0001

0.001

0.01

0.1

0.0001

0.001

0.01

0.1

Output Current (A)

D001

V_IN= 0.9 V, 1.2 V, 1.8 V, 2.4 V, 3.0 V, and V_OUT= 3.3 V

V_IN= 2.4 V, and V_OUT= 2.5 V, 3.3 V, 4.0 V

图 1. Load Efficiency with Different Input

图 2. Load Efficiency with Different Output

3.4

3.35

3.3

3.25

3.2

Vin = 0.9 V

Vout = 2.5 V

Vout = 3.3 V

Vout = 4.0 V

Vin = 1.6 V

Vin = 2.4 V

Vin = 3.0 V

0.6

1.2

1.8

2.4

3.6

0.5

1.5

2.5

3.5

Input Voltage (V)

Output Current (A)

D001

V_IN= 0.7 V to 3.6 V, V_OUT= 2.5 V, 3.3 V, 4.0 V

V_IN= 0.9 V, 1.6 V, 2.4 V, 3.0 V, and V_OUT= 3.3 V

图 3. Maximum Output Current vs Input Voltage

图 4. Load Regulation

0.82

0.81

0.8

0.3

0.25

0.2

0.79

0.78

0.77

0.76

0.15

0.1

-40

-20

100 120 140

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.3

3.6

Temperature (°C)

Input Voltage (V)

D001

V_IN= 2.4 V, V_OUT= 3.3 V, T = –40°C to 125°C

V_IN= 0.9 V to 3.6 V, V_OUT= 4.0 V, No switching

图 5. Reference Voltage vs Temperature

图 6. Quiescent Current into VIN vs Input Voltage

TPS61021A

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ZHCSFA0 –JUNE 2016

Typical Characteristics (接下页)

V_IN= 2.4 V, V_OUT= 3.3 V, T_J= 25°C, unless otherwise noted

1.8

2.2

2.6

3.4

3.8

4.2

-40

-20

80 90

Output Voltage (V)

Temperature (°C)

D001

V_IN= 1.2 V, V_OUT= 1.8 V to 4.0 V, No switching

V_IN= 2.4 V, V_OUT= 3.3 V, No switching, T = –40°C to 85°C

图 7. Quiescent Current into VOUT vs Output Voltage

图 8. Quiescent Current into VOUT vs Temperature

1.5

0.5

-40

-20

80 90

Temperature (°C)

D001

V_IN= 2.4 V, Into VIN and SW, T = –40°C to 85°C

图 9. Shutdown Current vs Temperature

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ZHCSFA0 –JUNE 2016

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7 Detailed Description

7.1 Overview

The TPS61021A synchronous step-up converter is designed to operate from an input voltage supply range

between 0.5 V and 4.4 V with 3-A valley switch current limit. The TPS61021A typically operates at a quasi-

constant frequency pulse width modulation (PWM) at moderate to heavy load currents. The switching frequency

is 2 MHz when the input voltage is above 1.5 V. The switching frequency reduces down to 1 MHz when the input

voltage goes down from 1.5 V to 1 V. At light load currents, the TPS61021A converter operates in power-save

mode with pulse frequency modulation (PFM). During PWM operation, the converter uses adaptive constant on-

time valley current mode control scheme to achieve excellent line/load regulation and allows the use of a small

inductor and ceramic capacitors. Internal loop compensation simplifies the design process while minimizing the

number of external components.

7.2 Functional Block Diagram

VIN VOUT

Undervoltage

Lockout

VIN

VOUT

Valley Current

Sense

Logic

Gate Driver

PGND

Thermal

Shutdown

PWM Control

AGND

Over Voltage

Soft Startup

Protection &

Short Circuit

Protection

ëhÜÇ

ëw9C

7.3 Feature Description

7.3.1 Under-Voltage Lockout

The TPS61021A has a built-in under-voltage lockout (UVLO) circuit to ensure the device working properly. When

the input voltage is above the UVLO rising threshold of 0.9 V, the TPS61021A can be enabled to boost the

output voltage. After the TPS61021A starts up and the output voltage is above 1.6 V, the TPS61021A can work

with the input voltage as low as 0.5 V.

TPS61021A

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Feature Description (接下页)

7.3.2 Enable and Soft Start

When the input voltage is above the under-voltage lockout (UVLO) rising threshold and the EN pin is pulled to

logic high voltage, the TPS61021A is enabled and starts up. At the beginning, the switching frequency and

current limit are internally controlled. The load capability is limited. After the output voltage is above 1.6 V, the

peak current limit is determined by the output of an internal error amplifier which compares the feedback of the

output voltage and the internal reference voltage. Because the output voltage is below the setting target, the

peak current limit rises and thus the output voltage ramps quickly. The soft startup time varies with the different

output capacitance and load condition. The typical startup time is around 200 μs for a 44-μF output capacitor with

no load.

7.3.3 Switching Frequency

The TPS61021A switches at a quasi-constant 2-MHz frequency when the input voltage is above 1.5 V. When the

input voltage declines from 1.5 V to 1 V, the switching frequency will be reduced gradually to 1-MHz to improve

the efficiency and get higher boost ratio. When the input voltage is below 1 V, the switching frequency is fixed at

a quasi-constant 1 MHz.

7.3.4 Current Limit Operation

The TPS61021A employs a valley current limit sensing scheme. Current limit detection occurs during the off-time

by sensing of the voltage drop across the synchronous rectifier switch.

When the load current is increased such that the inductor current is above the current limit within the whole

switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before

the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached, the output

voltage decreases during further load increase.

The maximum continuous output current (I_OUT(CL)), before entering current limit (CL) operation, can be defined by

公式 1.

≈

’

I_OUT(CL)= 1-D ì I

DI_{L P-P}

(

)

LIM

∆

◊

(

)

(1)

Where:

D is the duty cycle

ΔI_L(P-P)is the inductor ripple current

The duty cycle can be estimated by 公式 2.

V ì h

V_OUT

D = 1-

(2)

Where:

V_OUTis the output voltage of the boost converter

V_INis the input voltage of the boost converter

η is the efficiency of the converter, use 90% for most applications

And the peak-to-peak inductor ripple current is calculated by 公式 3.

V ìD

L ì f_SW

DI_{L P-P}

(

)

(3)

Where:

L is the inductance value of the inductor

f_SWis the switching frequency

D is the duty cycle

V_INis the input voltage of the boost converter

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Feature Description (接下页)

7.3.5 Pass-Through Operation

When the input voltage is higher than the setting output voltage, the output voltage is higher than the target

regulation voltage. When the output voltage is 101% of the setting target voltage, the TPS61021A stops

switching and turns on the high side PMOS FET. The device works in pass-through mode. The output voltage is

the input voltage minus the voltage drop across the dc resistance (DCR) of the inductor and the on-resistance

(R_DS(on)) of the PMOS FET. When the output voltage drops below the 98% of the setting target voltage as the

input voltage declines or the load current increases, the TPS61021A resumes switching again to regulate the

output voltage.

7.3.6 Over-Voltage Protection

The TPS61021A has an output over-voltage protection (OVP) to protect the device in case that the external

feedback resistor divider is wrongly populated. When the output voltage is above 4.35 V typically, the device

stops switching. Once the output voltage falls 0.1 V below the OVP threshold, the device resumes operating

again. To prevent the high overshoot voltage during OVP when the FB pin voltage is too much lower than the

internal reference voltage, the TPS61021A limits the valley swtich current to approximate 100 mA when the FB

pin voltage is below 0.2 V and the output voltage is above 2.9V.

7.3.7 Output Short-to-Ground Protection

The TPS61021A starts to limit the output current when the output voltage is below 1.6 V. The lower the output

voltage reaches, the smaller the output current is. When the output voltage is below 1 V, the output current is

limited to approximate 100 mA. Once the short circuit is released, the TPS61021A goes through the soft startup

again to output the regulated voltage.

7.3.8 Thermal Shutdown

The TPS61021A goes into thermal shutdown once the junction temperature exceeds 150°C. When the junction

temperature drops below the thermal shutdown temperature threshold less the hysteresis, typically 130°C, the

device starts operating again.

7.4 Device Functional Modes

The TPS61021A has two switching operation modes, PWM mode in moderate to heavy load conditions and

power save mode with pulse frequency modulation (PFM) in light load conditions.

7.4.1 PWM Mode

The TPS61021A uses a quasi-constant 2.0-MHz frequency pulse width modulation (PWM) at moderate to heavy

load current. Based on the input voltage to output voltage ratio, a circuit predicts the required on-time. At the

beginning of the switching cycle, the NMOS switching FET, shown in the functional block diagram, is turned on.

The input voltage is applied across the inductor and the inductor current ramps up. In this phase, the output

capacitor is discharged by the load current. When the on-time expires, the main switch NMOS FET is turned off,

and the rectifier PMOS FET is turned on. The inductor transfers its stored energy to replenish the output

capacitor and supply the load. The inductor current declines because the output voltage is higher than the input

voltage. When the inductor current hits a value which the error amplifier outputs, the next switching cycle starts

again.

The TPS61021A has a built-in compensation circuit that can accommodate a wide range of input voltage, output

voltage, inductor value and output capacitor value for stable operation.

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Device Functional Modes (接下页)

7.4.2 Power Save Mode

The TPS61021A integrates a power save mode with pulse frequency modulation (PFM) to improve efficiency at

light load. When the load current decreases, the inductor valley current set by the output of the error amplifier

declines to regulate the output voltage. When the inductor valley current hits the low limit of approximate 100

mA, the output voltage will exceed the setting voltage as the load current decreases further. When the FB

voltage hits the PFM reference voltage, the TPS61021A goes into the power save mode. In the power save

mode, when the FB voltage rises and hits the PFM reference voltage, the device continuous switching for several

cycles because of the delay time of the internal comparator. Then it stops switching. The load is supplied by the

output capacitor and the output voltage declines. When the FB voltage falls below the PFM reference voltage,

after the delay time of the comparator, the device starts switching again to ramp up the output voltage.

Output

Voltage

PFM mode at light load

1.008 x V_{OUT_NOM}

V_{OUT_NOM}

PWM mode at heavy load

图 10. Output Voltage in PWM Mode and PFM Mode

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS61021A is a synchronous boost converter designed to operate from an input voltage supply range

between 0.5 V and 4.4 V with 3-A valley switch current limit. The TPS61021A typically operates at a quasi-

constant 2-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents when the input

voltage is above 1.5 V. The switching frequency changes to 1-MHz gradually with the input voltage changing

from 1.5 V to 1 V to get better efficiency and high step-up ratio. At light load currents, the TPS61021A converter

operates in power-save mode with pulse frequency modulation (PFM) to achieve high efficiency over the entire

load current range.

8.2 Typical Application

The TPS61021A provides a power supply solution for portable or smart devices powered by batteries or super-

capacitors. With 3-A switch current capability, the TPS61021A can output 3.3 V and 1.5 A from two alkaline

batteries in series even if the battery voltage is down to 1.8 V.

1.8 V ~ 3.2 V

0.47 µH

10 µF

VIN

3.3 V

VOUT

2 x 22 µF

PGND

316 kꢀ

10 pF

TPS61021A

OFF

100 kꢀ

AGND

图 11. 2-Cell Alkaline Battery to 3.3-V Boost Converter

8.2.1 Design Requirements

The design parameters are listed in 表 1.

表 1. Design Parameters

PARAMETERS

Input voltage

VALUES

1.8 V to 3.2 V

3.3 V

Output voltage

Output current

1.5 A

Output voltage ripple

±50 mV

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8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Output Voltage

The output voltage is set by an external resistor divider (R1, R2 in 图 11). When the output voltage is regulated,

the typical voltage at the FB pin is V_REF. Thus the resistor divider is determined by 公式 4.

≈

∆

’

V_OUT

V_REF

R1=

Where:

-1 ìR2

◊

(4)

V_OUTis the regulated output voltage

V_REFis the internal reference voltage at the FB pin

For best accuracy, R2 should be kept smaller than 400 kΩ to ensure the current flowing through R2 is at least

100 times larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity

against noise injection. Changing the R2 towards a higher value reduces the quiescent current for achieving

highest efficiency at low load currents.

8.2.2.2 Inductor Selection

Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the

inductor is the most important component in power regulator design. There are three important inductor

specifications, inductor value, saturation current, and dc resistance (DCR).

The TPS61021A is designed to work with inductor values between 0.33 µH and 1.0 µH. Follow 公式 5 to 公式 7

to calculate the inductor’s peak current for the application. To calculate the current in the worst case, use the

minimum input voltage, maximum output voltage, and maximum load current of the application. To have enough

design margins, choose the inductor value with -30% tolerances, and low power-conversion efficiency for the

calculation.

In a boost regulator, the inductor dc current can be calculated by 公式 5.

V_OUTìI_OUT

I_{L DC}

(

)

V ì h

(5)

(6)

(7)

Where:

V_OUTis the output voltage of the boost converter

I_OUTis the output current of the boost converter

V_INis the input voltage of the boost converter

η is the power conversion efficiency, use 90% for most applications

The inductor ripple current is calculated by 公式 6.

V ìD

DI_{L P-P}

(

)

L ì f_SW

Where:

D is the duty cycle, which can be calculated by 公式 2

L is the inductance value of the inductor

f_SWis the switching frequency

V_INis the input voltage of the boost converter

Therefore, the inductor peak current is calculated by 公式 7.

DI_{L P-P}

(

)

I_{L P}= I_{L DC}

(

)

(

)

Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor

current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic

hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The

inductor’s saturation current must be higher than the calculated peak inductor current. 表 2 lists the

recommended inductors for the TPS61021A.

TPS61021A

ZHCSFA0 –JUNE 2016

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表 2. Recommended Inductors for the TPS61021A

DCR MAX SATURATION CURRENT

SIZE (LxWxH)

PART NUMBER

L(µH)

VENDOR⁽¹⁾

(mΩ)

8.36

(A)

6.6

8.0

5.7

5.4

XFL4015-471ME

744383360047

0.47

1.0

4.0×4.0×1.5

3.0x3.0x2.0

2.5×2.0×1.2

4.0×4.0×2.1

Coilcraft

Wurth Elecktronik

Toko

DFE252012P-R47M

XFL4020-102ME

11.9

Coilcraft

(1) See Third-party Products disclaimer

8.2.2.3 Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple

voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a ceramic

capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by 公式

I_OUTìD_MAX

f_SWì V_RIPPLE

C_OUT

(8)

Where:

D_MAXis the maximum switching duty cycle

V_RIPPLEis the peak to peak output ripple voltage

I_OUTis the maximum output current

f_SWis the switching frequency

The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are

used. The output peak to peak ripple voltage caused by the ESR of the output capacitors can be calculated by 公

式 9.

V_RIPPLE(ESR)= I_L(P)ìR_ESR

(9)

Care must be taken when evaluating a ceramic capacitor’s derating under dc bias voltage, aging, and ac signal.

For example, the dc bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than

50% of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure

adequate capacitance at the required output voltage. Increasing the output capacitor makes the output ripple

voltage smaller in PWM mode.

It is recommended to use the X5R or X7R ceramic output capacitor in the range of 10 μF to 200 μF effective

capacitance. For output current less than 300 mA, the effective output capacitance could be reduced to 3.0 μF.

The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is

below the range, the boost regulator can potentially become unstable.

8.2.2.4 Feedforward Capacitor Selection

A feedforward capacitor between the VOUT pin and FB pin induces a pair of zero and pole in the loop transfer

function. Setting the proper zero frequency can increase the phase margin to improve the loop stability. The

TPS61021A needs a feedforward capacitor (C3 in 图 11) in most applications. It is recommended to set the zero

frequency (f_FFZ) to 50 kHz when the effective output capacitance is less than 40 μF. For large output capacitance

more than 40 μF, it is recommended to set the zero frequency (f_FFZ) to 5 kHz. The value of the feedforward

capacitor can be calculated by 公式 10.

C3 =

2pì f_FFZìR1

(10)

Where:

R1 is the resistor between the VOUT pin and FB pin

f_FFZis the zero frequency created by the feedforward capacitor

TPS61021A

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8.2.2.5 Input Capacitor Selection

Multilayer X5R or X7R ceramic capacitors are excellent choices for input decoupling of the step-up converter as

they have extremely low ESR and are available in small footprints. Input capacitors should be located as close

as possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be

used to reduce input current ripple without limitations. Take care when using only ceramic input capacitors. When

a ceramic capacitor is used at the input and the power is being supplied through long wires, a load step at the

output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability

or could even damage the part. Additional bulk capacitance (tantalum or aluminum electrolytic capacitor) should

in this circumstance be placed between ceramic input capacitor and the power source to reduce ringing that can

occur between the inductance of the power source leads and ceramic input capacitor.

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8.2.3 Application Curves

V_IN= 2.4 V, V_OUT= 3.3 V, I_OUT= 2 A

V_IN= 2.4 V, V_OUT= 3.3 V, I_OUT= 100 mA

图 12. Switching Waveform at Heavy Load

图 13. Switching Waveform at Light Load

V_IN= 2.4 V, V_OUT= 3.3 V, 12 Ω resistance load

图 15. Shutdown Waveform

V_IN= 2.4 V, V_OUT= 3.3 V, 12 Ω resistance load

图 14. Startup Waveform

V_IN= 2.4 V, V_OUT= 3.3 V, I_OUT= 1 A to 2 A

V_IN= 1.6 V to 2.4 V, V_OUT= 3.3 V, I_OUT= 1 A

图 16. Load Transient

图 17. Line Transient

TPS61021A

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 0.5 V to 4.4 V. This input supply

must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or

aluminum electrolytic capacitor with a value of 100 µF. The input power supply’s output current needs to be rated

according to the supply voltage, output voltage and output current of the TPS61021A.

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10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents,

layout is an important design step. If the layout is not carefully done, the regulator could suffer from instability

and noise problems. To maximize efficiency, switch rise and fall time are very fast. To prevent radiation of high

frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the

length and area of all traces connected to the SW pin, and always use a ground plane under the switching

regulator to minimize interplane coupling. The input capacitor needs not only to be close to the VIN pin, but also

to the PGND pin in order to reduce input supply ripple.

The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then

the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise

and fall time and should be kept as short as possible. Therefore, the output capacitor needs not only to be close

to the VOUT pin, but also to the PGND pin to reduce the overshoot at the SW pin and VOUT pin.

10.2 Layout Example

GND

AGND

VIN

PGND

VOUT

GND

VIN

图 18. Layout Example

10.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions.

Calculate the maximum allowable dissipation, P_D(max), and keep the actual power dissipation less than or equal to

P_D(max). The maximum-power-dissipation limit is determined using 公式 11.

125 - T_A

P_{D max}

(

)

R_qJA

(11)

Where:

T_Ais the maximum ambient temperature for the application

_θJAis the junction-to-ambient thermal resistance given in the Thermal Information table.

The TPS61021A comes in a thermally-enhanced WSON package. This package includes a thermal pad that

improves the thermal capabilities of the package. The real junction-to-ambient thermal resistance of the package

greatly depends on the PCB type, layout, and thermal pad connection. Using thick PCB copper and soldering the

thermal pad to a large ground plate to enhance the thermal performance. Using more vias connects the ground

plate on the top layer and bottom layer around the IC without solder mask also improves the thermal capability.

TPS61021A

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11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。

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12.1 Package Option Addendum

12.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

(1)

(2)

(3)

Orderable Device

TPS61021ADSGR

TPS61021ADSGT

Status

Pins

Eco Plan

Lead/Ball Finish MSL Peak Temp

Op Temp (°C)

–40 to 125

Device Marking⁽⁴⁾⁽⁵⁾

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

Level-2-260C-1

YEAR

ACTIVE

WSON

DSG

3000

250

11G

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

Level-2-260C-1

YEAR

WSON

–40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TPS61021A

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12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS61021ADSGR

TPS61021ADSGT

WSON

DSG

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

TPS61021A

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

35.0

TPS61021ADSGR

TPS61021ADSGT

WSON

DSG

210.0

185.0

35.0

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

0.32

0.18

PIN 1 INDEX AREA

2.1

1.9

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8

0.7

SEATING PLANE

0.05

0.00

SIDE WALL

0.08 C

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

EXPOSED

THERMAL PAD

(DIM A) TYP

0.9 0.1

6X 0.5

1.5

1.6 0.1

0.32

0.18

PIN 1 ID

(45 X 0.25)

0.4

0.2

0.1

C A B

0.05

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

8X (0.25)

(0.55)

SYMM

(1.6)

6X (0.5)

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

SYMM

8X (0.25)

(0.45)

SYMM

(0.7)

6X (0.5)

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TPS61021A [TI]

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