TPS61175QPWPRQ1 [TI]
具有软启动功能和可编程开关频率的 3A、40V 高压升压转换器 | PWP | 14 | -40 to 125;
| 型号： | TPS61175QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有软启动功能和可编程开关频率的 3A、40V 高压升压转换器 | PWP | 14 | -40 to 125 升压转换器 开关 高压 软启动 |
| 文件： | 总27页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61175-Q1
ZHCSD56 –DECEMBER 2014
TPS61175-Q1 具有软启动和可编程开关频率的 3A 高电压升压转换器
1 特性
3 说明
1
•
具有符合 AEC-Q100 的下列结果：
TPS61175-Q1 是一款单片开关稳压器，带有集成的
3A/40V 电源开关。 此器件可配置成多种标准开关稳压
器拓扑，包括升压、SEPIC 和反激式。 此器件具有宽
输入电压范围，可支持输入电压来自多节电池或者
5V、12V 稳压电源轨的应用。
–
器件温度 1 级：-40℃ 至 125°C 结温工作温度
范围
•
•
•
•
•
•
•
•
输入电压范围为 2.9V 至 18V
3A、40V 内部开关
高效率电源转换：高达 93%
由外部电阻设置频率：200KHz 至 2.2MHz
同步外部开关频率
TPS61175-Q1 使用电流模式脉宽调制 (PWM) 控制来
调节输出电压。 PWM 的开关频率可由外部电阻或外
部时钟信号设定。 用户可将开关频率编程设定在
200kHz 至 2.2MHz 之间。
满载条件下采用用户定义的软启动
轻载条件下输出调节可跳过开关周期
此器件的可编程软启动功能可限制启动期间的浪涌电
流，并且还具有逐脉冲过流限制和热关断等其它内置保
护特性。 TPS61175-Q1 采用带有 PowerPAD 的 14
引脚 HTSSOP 封装。
14 引脚散热薄型小外形尺寸 (HTSSOP) 封装，具
有 PowerPAD™
2 应用范围
•
•
•
•
5V 至 12V、24V 的功率转换
器件信息(1)
支持单端初级电感转换器 (SEPIC)、反激式拓扑
非对称用户数字环路 (ADSL) 调制解调器
TV 调谐器
器件型号
封装
封装尺寸（标称值）
TPS61175-Q1
HTSSOP (14)
5.00mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
V
D1
V
IN
OUT
L1
C2
C1
TPS61175
R1
VIN
SW
SW
EN
FREQ
SS
FB
PGND
PGND
PGND
NC
R2
COMP
Syn
R4
R3
C3
AGND
C4
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCN9
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
11.3 Thermal Considerations........................................ 20
12 器件和文档支持 ..................................................... 21
12.1 商标....................................................................... 21
12.2 静电放电警告......................................................... 21
12.3 术语表 ................................................................... 21
13 机械封装和可订购信息 .......................................... 21
8
5 修订历史记录
日期
修订版本
注释
2014年12月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
6 Pin Configuration and Functions
TSSOP 14-PIN
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
PGND
PGND
PGND
NC
SW
SW
VIN
EN
FREQ
FB
SS
SYNC
AGND
8
COMP
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
The input supply pin for the IC. Connect VIN to a supply voltage between 2.9 V and 18 V. It is acceptable
for the voltage on the pin to be different from the boost power stage input for applications requiring voltage
beyond VIN range.
3
I
SW
FB
1,2
9
I
I
This is the switching node of the IC. Connect SW to the switched side of the indu1ctor.
Feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider to program the
output voltage.
Enable pin. When the voltage of this pin falls below the enable threshold for more than 10 ms, the IC turns
off.
EN
4
8
I
Output of the internal transconductance error amplifier. An external RC network is connected to this pin to
compensate the regulator.
COMP
SS
O
O
O
Soft start programming pin. A capacitor between the SS pin and GND pin programs soft start timing. See
application section for information on how to size the SS capacitor.
5
Switch frequency program pin. An external resistor is connected to this pin to set switch frequency. See
application section for information on how to size the FREQ resistor.
FREQ
10
AGND
PGND
7
I
I
I
Signal ground of the IC
12,13,14
Power ground of the IC. It is connected to the source of the PWM switch.
Switch frequency synchronous pin. Customers can use an external signal to set the IC switch frequency
between 200-kHz and 2.2-MHz. If not used, this pin should be tied to AGND as short as possbile to avoid
noise coupling.
SYNC
6
NC
11
I
Reserved pin. Must connect this pin to ground.
The thermal pad should be soldered to the analog ground. If possible, use thermal via to connect to top and
internal ground plane layers for ideal power dissipation.
Thermal Pad
Copyright © 2014, Texas Instruments Incorporated
3
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
20
20
3
(2)
Supply Voltages on pin VIN
Voltages on pins EN(2)
V
V
V
V
V
Voltage on pin FB, FREQ and COMP(2)
Voltage on pin SYNC, SS(2)
Voltage on pin SW(2)
7
40
Continuous Power Dissipation
Operating Junction Temperature Range
Storage temperature, Tstg
See the Thermal Information Table
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
±2000
All pins except 1, 7, 8,
and 14
V(ESD)
Electrostatic discharge
±500
±750
V
Charged-device model (CDM), per AEC
Q100-011
Pins 1, 7, 8, and 14
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.9
VIN
4.7
200
4.7
4.7
NOM
MAX
18
UNIT
V
VIN
VO
L
Input voltage range
Output voltage range
Inductor(1)
38
V
47
μH
kHz
μF
μF
V
fSW
CI
Switching frequency
2200
Input Capacitor
CO
VSYN
TA
Output Capacitor
External Switching Frequency Logic
Operating ambient temperature
Operating junction temperature
5
125
125
–40
–40
°C
°C
TJ
(1) The inductance value depends on the switching frequency and end application. While larger values may be used, values between 4.7-
μH and 47-μH have been successfully tested in various applications. Refer to the Inductor Selection for detail.
4
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
7.4 Thermal Information
TPS61175-Q1
THERMAL METRIC(1)
PWP
14 PINS
45.2
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.9
30.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
29.9
RθJC(bot)
5.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
FSW = 1.2 MHz (Rfreq = 80 kΩ), VIN = 3.6V, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
2.9
18
3.5
1.5
2.7
V
IQ
Operating quiescent current into Vin
Shutdown current
Device PWM switching without load
EN = GND
mA
μA
V
ISD
VUVLO
Vhys
Under-voltage lockout threshold
Under-voltage lockout hysteresis
2.5
130
mV
ENABLE AND REFERENCE CONTROL
V(ENh)
V(ENl)
EN logic high voltage
EN logic low voltage
SYN logic high voltage
SYN logic low voltage
EN pull down resistor
VIN = 2.9 V to 18 V
VIN = 2.9 V to 18 V
1.2
1.2
V
V
0.4
V(SYNh)
V(SYNl)
R(EN)
V
0.4
V
400
800
1600
kΩ
VOLTAGE AND CURRENT CONTROL
VREF
IFB
Voltage feedback regulation voltage
Voltage feedback input bias current
Comp pin sink current
1.204
1.229
1.254
200
V
nA
μA
μA
V
Isink
VFB = VREF + 200 mV, VCOMP = 1 V
VFB = VREF –200 mV, VCOMP = 1 V
50
Isource
VCCLP
Comp pin source current
130
Comp pin Clamp Voltage
High Clamp, VFB = 1 V
Low Clamp, VFB = 1.5 V
3
0.75
V(CTH)
Gea
Rea
Comp pin threshold
Duty cycle = 0%
0.95
340
10
V
Error amplifier transconductance
Error amplifier output resistance
Error amplifier crossover frequency
240
440
μmho
MΩ
fea
500
KHz
FREQUENCY
Rfreq = 480 kΩ
0.16
1.0
0.21
1.2
0.26
1.4
fS
Oscillator frequency
Rfreq = 80 kΩ
MHz
V
Rfreq = 40 kΩ
1.76
89%
2.2
2.64
Dmax
Maximum duty cycle
FREQ pin voltage
VFB = 1.0 V, Rfreq = 80 kΩ
93%
1.229
V(FREQ)
Copyright © 2014, Texas Instruments Incorporated
5
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
Electrical Characteristics (continued)
FSW = 1.2 MHz (Rfreq = 80 kΩ), VIN = 3.6V, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(ON)
N-channel MOSFET on-resistance
N-channel leakage current
VIN = VGS = 3.6 V
VIN = VGS = 3.0 V
0.13
0.13
0.25
0.3
Ω
ILN_NFET
OC, OVP AND SS
ILIM N-Channel MOSFET current limit
ISS Soft start bias current
THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold
Thysteresis Thermal shutdown threshold hysteresis
VDS = 40 V, TA = 25°C
1
μA
D = Dmax
VSS = 0 V
3
3.8
6
5
A
μA
160
15
°C
°C
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
ms
ENABLE AND REFERENCE CONTROL
toff
FREQUENCY
tmin_on Minimum on pulse width
Shutdown delay, SS discharge
EN high to low
10
Rfreq = 80 kΩ
60
ns
6
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
7.7 Typical Characteristics
100
90
100
V
= 12 V
V = 12 V
I
90
O
V = 5 V
I
V
= 24 V
O
80
70
80
V
= 35 V
O
70
60
50
60
50
0
0.2
0.4
0.6
0.8
1
1.2
0
0.2
0.4
0.6
0.8
1
1.2
I
- Output Current - A
I
- Output Current - A
O
O
VO = 24 V
VI = 5 V
Figure 2. Efficiency vs Output Current
Figure 1. Efficiency vs Output Current
5
400
380
4.5
4
360
340
320
3.5
3
0.2
-40
-20
0
20
40
60
80
100
120
0.4
0.6
0.8
1
T
- Free-Air Temperature - °C
Duty Cycle - %
A
Figure 3. Error Amplifier Transconductance vs Free-Air
Temperature
Figure 4. Overcurrent Limit vs Duty Cycle
4
1240
1235
3.9
3.8
3.7
1230
1225
1220
3.6
3.5
80
60
- Free-Air Temperature - °C
-40
-20
0
20
T - Free-Air Temperature - °C
A
40
60
80
100
120
-20
0
20
40
100
120
-40
T
A
Figure 5. Overcurrent Limit vs Free-Air Temperature
Figure 6. FB Voltages Free-Air Temperature
Copyright © 2014, Texas Instruments Incorporated
7
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS61175-Q1 integrates a 40-V low side switch FET for up to 38-V output. The device regulates the output
with current mode PWM (pulse width modulation) control. The PWM control circuitry turns on the switch at the
beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as
inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output
capacitor. When the inductor current rises to the threshold set by the error amplifier output, the power switch
turns off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the
output capacitor and supply the load current. This operation repeats each every switching cycle. As shown in the
block diagram, the duty cycle of the converter is determined by the PWM control comparator which compares the
error amplifier output and the current signal. The switching frequency is programmed by the external resistor or
synchronized to an external clock signal.
A ramp signal from the oscillator is added to the current ramp to provide slope compensation. Slope
compensation is necessary to avoid subharmonic oscillation that is intrinsic to the current mode control at duty
cycle higher than 50%. If the inductor value is lower than 4.7μH, the slope compensation may not be adequate.
The feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The
output of the error amplifier is connected to the COMP pin. An external RC compensation network is connected
to the COMP pin to optimize the feedback loop for stability and transient response.
8.2 Functional Block Diagram
L1
D1
C1
C2
R1
R2
FB
SW
VIN
FB
EN
EA
Gate
Driver
1.229 V
Reference
COMP
PWM Control
R3
C4
Current
Sensor
Ramp
Generator
+
Oscillator
SS
C3
FREQ
R4
SYNC
AGND
PGND
8
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
8.3 Feature Description
8.3.1 Switching Frequency
The switch frequency is set by a resistor (R4) connected to the FREQ pin of the TPS61175-Q1. Do not leave this
pin open. A resistor must always be connected for proper operation. See Table 1 and Figure 7 for resistor values
and corresponding frequencies.
Table 1. Switching Frequency vs External Resistor
R4 (kΩ)
443
256
176
80
fSW (kHz)
240
400
600
1200
2000
51
3500
3000
2500
2000
1500
1000
500
0
100
10
1000
External Resistor - kW
Figure 7. Switching Frequency vs External Resistor
Alternatively, the TPS61175-Q1 switching frequency will synchronize to an external clock signal that is applied to
the SYNC pin. The logic level of the external clock is shown in the specification table. The duty cycle of the clock
is recommended in the range of 10% to 90%. The resistor also must be connected to the FREQ pin when IC is
switching by the external clock. The external clock frequency must be within ±20% of the corresponding
frequency set by the resistor. For example, if the corresponding frequency as set by a resistor on the FREQ pin
is 1.2-MHz, the external clock signal should be in the range of 0.96-MHz to 1.44-MHz.
If the external clock signal is higher than the frequency per the resistor on the FREQ pin, the maximum duty
cycle specification (DMAX) should be lowered by 2%. For instance, if the resistor set value is 2.5MHz, and the
external clock is 3MHz, DMAX is 87% instead of 89%.
8.3.2 Soft Start
The TPS61175-Q1 has a built-in soft start circuit which significantly reduces the start-up current spike and output
voltage overshoot. When the IC is enabled, an internal bias current (6-μA typically) charges a capacitor (C3) on
the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the duty
cycle of PWM control, thereby the input inrush current is eliminated. Once the capacitor reaches 1.8-V, the soft
start cycle is completed and the soft start voltage no longer clamps the error amplifier output. Refer to Figure 7
for the soft start waveform. See Table 2 for C3 and corresponding soft start time. A 47-nF capacitor eliminates
the output overshoot and reduces the peak inductor current for most applications.
Copyright © 2014, Texas Instruments Incorporated
9
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
Table 2. Soft Start Time vs C3
VIN (V)
VOUT (V)
Load (A)
COUT (μF)
fSW (MHz)
C3 (nF)
47
tSS(ms)
4
Overshot (mV)
none
210
5
24
0.4
10
1.2
10
0.8
100
10
6.5
none
300
12
35
0.6
10
2
0.4
When the EN is pulled low for 10-ms, the IC enters shutdown and the SS capacitor discharges through a 5kΩ
resistor for the next soft start.
8.3.3 Overcurrent Protection
The TPS61175-Q1 has a cycle-by-cycle overcurrent limit protection that turns off the power switch once the
inductor current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the
next switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on
the output. When the FB voltage drops lower than 0.9-V, the switching frequency is automatically reduced to 1/4
of the set value. The switching frequency does not reset until the overcurrent condition is removed. This feature
is disabled during soft start.
8.3.4 Enable and Thermal Shutdown
The TPS61175-Q1 enters shutdown when the EN voltage is less than 0.4-V for more than 10-ms. In shutdown,
the input supply current for the device is less than 1.5-μA (max). The EN pin has an internal 800-kΩ pull down
resistor to disable the device when it is floating.
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The IC restarts when the junction temperature drops by 15°C.
8.3.5 Under Voltage Lockout (UVLO)
An under voltage lockout circuit prevents mis-operation of the device at input voltages below 2.5-V (typical).
When the input voltage is below the under voltage threshold, the device remains off and the internal switch FET
is turned off. The under voltage lockout threshold is set below minimum operating voltage of 2.9V to avoid any
transient VIN dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO
threshold and 2.9V, the device attempts to operate, but the specifications are not ensured.
8.4 Device Functional Modes
8.4.1 Minimum on Time and Pulse Skipping
Once the PWM switch is turned on, the TPS61175-Q1 has minimum ON pulse width of 60-ns. This sets the limit
of the minimum duty cycle of the PWM switch, and it is independent of the set switching frequency. When
operating conditions result in the TPS61175-Q1 having a minimum ON pulse width less than 60-ns, the IC enters
pulse-skipping mode. In this mode, the device keeps the power switch off for several switching cycles to keep the
output voltage from rising above the regulated voltage. This operation typically occurs in light load condition
when the PWM operates in discontinuous mode. Pulse skipping increases the output voltage ripple, see
Figure 15.
If the switching frequency is above 1.2 MHz, the pulse-skipping operation may not function. The TPS61175-Q1
will always run in PWM mode with minimum ON pulse width. To keep the output voltage in regulation, a
minimum load is required. The minimum load is related to the input voltage, output voltage, switching frequency,
external inductor value and the maximum value of the minimum ON pulse width. Use Equation 1 and Equation 2
to calculate the required minimum load at the worst case. The maximum tmin_ON could be estimated to 80 ns.
CSW is the total parasite capacitance at the switching node SW pin. It could be estimated to 100 pF.
2
V
x tmin_ON + (VOUT + VD - V ) x L x CSW
x ¦SW
(
)
IN
IN
1
2
I(min_load)
=
x
When VOUT + VD - V < V
IN IN
L x V
(
+ VD - V
IN
)
OUT
(1)
2
V
x tmin_ON + V
x
L x CSW
x ¦SW
(
)
IN
IN
1
2
I(min_load)
=
x
When VOUT + VD - V > V
IN IN
L x V
(
+ VD - V
IN
)
OUT
(2)
10
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
9 Application and Implementation
9.1 Application Information
The following section provides a step-by-step design approach for configuring the TPS61175-Q1 as a voltage
regulating boost converter, as shown in Figure 8. When configured as SEPIC or flyback converter, a different
design approach is required.
9.2 Typical Application
V
D1
V
IN
OUT
L1
C2
C1
TPS61175
R1
VIN
SW
SW
EN
FREQ
SS
FB
PGND
PGND
PGND
NC
R2
COMP
Syn
R4
R3
C3
AGND
C4
Figure 8. Boost Converter Configuration
Table 3. Design Parameters
9.2.1 Design Requirements
PARAMETERS
VALUES
5 V
Input voltage
Output voltage
24 V
Operating frequency
1.2 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Determining the Duty Cycle
The TPS61175-Q1 has a maximum worst case duty cycle of 89% and a minimum on time of 60 ns. These two
constraints place limitations on the operating frequency that can be used for a given input to output conversion
ratio. The duty cycle at which the converter operates is dependent on the mode in which the converter is running.
If the converter is running in discontinuous conduction mode (DCM), where the inductor current ramps to zero at
the end of each cycle, the duty cycle varies with changes to the load much more than it does when running in
continuous conduction mode (CCM). In continuous conduction mode, where the inductor maintains a dc current,
the duty cycle is related primarily to the input and output voltages as computed below:
V
+ V - V
D IN
OUT
D =
V
+ V
D
OUT
(3)
In discontinuous mode the duty cycle is a function of the load, input and output voltages, inductance and
switching frequency as computed below:
2 ´ (VOUT + VD ) ´ IOUT ´ L ´ ¦SW
D =
V
IN
(4)
All converters using a diode as the freewheeling or catch component have a load current level at which they
transition from discontinuous conduction to continuous conduction. This is the point where the inductor current
just falls to zero. At higher load currents, the inductor current does not fall to zero but remains flowing in a
positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape. This load
boundary between discontinuous conduction and continuous conduction can be found for a set of converter
parameters as follows.
Copyright © 2014, Texas Instruments Incorporated
11
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
2
(V
+ V - V ) ´ V
D IN IN
OUT
I
=
OUT(crit)
2
2 ´ (V
+ V ) ´ ¦
D
´ L
SW
OUT
(5)
For loads higher than the result of the equation above, the duty cycle is given by Equation 3 and for loads less
than the results of Equation 4, the duty cycle is given in Equation 5. For Equation 3 through Equation 5, the
variable definitions are as follows.
•
•
•
•
•
•
VOUT is the output voltage of the converter in V
VD is the forward conduction voltage drop across the rectifier or catch diode in V
VIN is the input voltage to the converter in V
IOUT is the output current of the converter in A
L is the inductor value in H
fSW is the switching frequency in Hz
Unless otherwise stated, the design equations that follow assume that the converter is running in continuous
mode.
9.2.2.2 Selecting the Inductor
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not
enough.
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can fall to some percentage of its 0-A value depending on how the inductor vendor defines
saturation current. For CCM operation, the rule of thumb is to choose the inductor so that its inductor ripple
current (ΔIL) is no more than a certain percentage (RPL% = 20–40%) of its average DC value (IIN(AVG) = IL(AVG)
)
V
´ D
(VOUT + VD - VIN ) ´ (1 - D)
L ´ ¦SW
1
IN
DIL =
=
=
L ´ ¦SW
é
ù
ö
æ
ç
è
1
1
L ´ ¦
´
+
ê
÷ú
SW
VOUT + VD - V
V
ê
ë
ú
û
IN
IN ø
POUT
£ RPL% ´
V
´ ηest
IN
(6)
(7)
Rearranging and solving for L gives
ηest ´ V
IN
L ³
é
ê
ù
ú
æ
ç
è
ö
÷
ø
1
1
¦
+
´ RPL% POUT
SW
VOUT + VD - V
V
IN
ê
ë
ú
û
IN
Choosing the inductor ripple current to closer to 20% of the average inductor current results in a larger
inductance value, maximizes the converter’s potential output current and minimizes EMI. Choosing the inductor
ripple current closer to 40% of IL(AVG) results in a smaller inductance value, and a physically smaller inductor,
improves transient response but results in potentially higher EMI and lower efficiency if the DCR of the smaller
packaged inductor is significantly higher. Using an inductor with a smaller inductance value than computed
above may result in the converter operating in DCM. This reduces the boost converter’s maximum output current,
causes larger input voltage and output ripple and typically reduces efficiency. Table 4 lists the recommended
inductor for the TPS61175-Q1.
Table 4. Recommended Inductors for TPS61175-Q1
L
(μH)
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
SIZE
(L × W × H mm)
PART NUMBER
VENDOR
D104C2
VLF10040
10
15
22
15
44
42
61
50
3.6
3.1
2.9
3.8
10.4x10.4x4.8
10.0x9.7x4.0
10.5x10.3x5.1
10.0x10.2x3.8
TOKO
TDK
CDRH105RNP
MSS1038
Sumida
Coilcraft
12
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
The device has built-in slope compensation to avoid subharmonic oscillation associated with current mode
control. If the inductor value is lower than 4.7μH, the slope compensation may not be adequate, and the loop can
be unstable. Applications requiring inductors above 47μH have not been evaluated. Therefore, the user is
responsible for verifying operation if they select an inductor that is outside the 4.7μH–47μH recommended range.
9.2.2.3 Computing the Maximum Output Current
The over-current limit for the integrated power FET limits the maximum input current and thus the maximum input
power for a given input voltage. Maximum output power is less than maximum input power due to power
conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change
the maximum current output (IOUT(MAX)). The current limit clamps the peak inductor current, therefore the ripple
has to be subtracted to derive maximum DC current.
V
´ IIN(AVG) ´ ηest
V
IN(NIM) ´ ILIM ´ ηest
IN(MIN)
IOUT(max)
=
=
VOUT
VOUT ´ (1 + RPL%/2)
(8)
where
•
•
ILIM = over current limit
ηest= efficiency estimate based on similar applications or computed above
For instance, when VIN = 12 V is boosted to VOUT = 24 V, the inductor is 10 uH, the Schottky forward voltage is
0.4-V and the switching frequency is 1.2-MHz; then the maximum output current is 1.2-A in typical condition,
assuming 90% efficiency and a %RPL = 20%.
9.2.2.4 Setting Output Voltage
To set the output voltage in either DCM or CCM, select the values of R1 and R2 according to the following
equation.
æ R1
ö
Vout = 1.229 V ´
+ 1
ç
÷
R2
è
ø
æ Vout
ö
R1 = R2 ´
- 1
ç
÷
1.229V
è
ø
(9)
Considering the leakage current through the resistor divider and noise decoupling into FB pin, an optimum value
for R2 is around 10k. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1 and
R2.
9.2.2.5 Setting the Switching Frequency
Choose the appropriate resistor from the resistance versus frequency table Table 1 or graph Figure 7. A resistor
must be placed from the FREQ pin to ground, even if an external oscillation is applied for synchronization.
Increasing switching frequency reduces the value of external capacitors and inductors, but also reduces the
power conversion efficiency. The user should set the frequency for the minimum tolerable efficiency.
9.2.2.6 Setting the Soft Start Time
Choose the appropriate capacitor from the soft start table Table 2. Increasing the soft start time reduces the
overshoot during start-up.
9.2.2.7 Selecting the Schottky Diode
The high switching frequency of the TPS61175-Q1 demands a high-speed rectification for optimum efficiency.
Ensure that the diode’s average and peak current rating exceed the average output current and peak inductor
current. In addition, the diode’s reverse breakdown voltage must exceed the switch FET rating voltage of 40V.
So, the VISHAY SS3P6L-E3/86A is recommended for TPS61175-Q1. The power dissipation of the diode's
package must be larger than IOUT(max) x VD
Copyright © 2014, Texas Instruments Incorporated
13
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
9.2.2.8 Selecting the Input and Output Capacitors
The output capacitor is mainly selected to meet the requirements for the output ripple and load transient. Then
the loop is compensated for the output capacitor selected. The output ripple voltage is related to the capacitor’s
capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by
(V
- V )I
IN out
OUT
C
=
out
V
´ Fs ´ V
ripple
OUT
(10)
where, Vripple= peak to peak output ripple. The additional output ripple component caused by ESR is calculated
using:
Vripple_ESR = I × RESR
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by
Equation 11.
ΔI
TRAN
C
=
OUT
2 ´ p ´ f
´ ΔV
TRAN
LOOP-BW
(11)
Where
•
•
•
ΔITRAN is the transient load current step
ΔVTRAN is the allowed voltage dip for the load current step
fLOOP-BW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero).
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the
switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, one
must add margin on the voltage rating to ensure adequate capacitance at the required output voltage.
For a typical boost converter implementation, at least 4.7μF of ceramic input and output capacitance is
recommended. Additional input and output capacitance may be required to meet ripple and/or transient
requirements.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
9.2.2.9 Compensating the Small Signal Control Loop
All continuous mode boost converters have a right half plane zero (ƒRHPZ) due to the inductor being removed
from the output during charging. In a traditional voltage mode controlled boost converter, the inductor and output
capacitor form a small signal double pole. For a negative feedback system to be stable, the fed back signal must
have a gain less than 1 before having 180 degrees of phase shift. With its double pole and RHPZ all providing
phase shift, voltage mode boost converters are a challenge to compensate. In a converter with current mode
control, there are essentially two loops, an inner current feedback loop created by the inductor current
information sensed across RSENSE (40 mΩ) and the output voltage feedback loop. The inner current loop allows
the switch, inductor and modulator to be lumped together into a small signal variable current source controlled by
the error amplifier, as shown in Figure 9.
14
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
(1-D)
RSENSE
R1
_
+
R
C2
O
2
V
C4
ref
C5
(optional)
R
R2
ESR
R3
Figure 9. Small Signal Model of a Current Mode Boost in CCM
The new power stage, including the slope compensation, small signal model becomes:
æ
ç
è
öæ
֍
øè
ö
÷
ø
s
s
1+
1-
2´ p´ ¦ESR
2´ p´ ¦RHPZ
ROUT ´(1- D)
2´RSENSE
GPS(s) =
´
´He(s)
s
1+
2´ p´ ¦P
(12)
Where
2
¦
=
P
2p ´ R ´ C2
O
(13)
(14)
1
¦
»
ESR
2p ´ RESR ´ C2
æ
ç
è
ö2
÷
RO
V
IN
¦
=
´
RHPZ
2p ´ L
VOUT ø
(15)
And
1
He(s) =
é
ù
æ
Se ö
s ´ 1+
êç
´ (1 - D) - 0.5
÷
ú
s2
Sn
è
ø
ë
û
1+
+
2
¦
SW
(p ´ ¦SW )
(16)
He(s) models the inductor current sampling effect as well as the slope compensation effect on the small signal
response.
NOTE
If Se slope dominates Sn, that is, when the inductance is oversized in order to give ripple
current much smaller than the recommended 0.2 – 0.4 times the average input current,
then the converter behaves more like a voltage mode converter, and the above model no
longer holds.
The slope compensation in TPS61175-Q1 is shown as follow
VOUT + VD - V
IN
Sn =
´ RSENSE
L
(17)
15
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
0.32 V / R4
16´ 1-D ´ 6pF
0.5 mA
Se =
+
6 pF
(
)
Where R4 is the frequency setting resistor
(18)
Figure 10 shows a bode plot of a typical CCM boost converter power stage
180
120
60
Gain
0
–60
–120
–180
Phase
f
P
f − Frequency − kHz
Figure 10. Bode Plot of Power Stage Gain and Phase
The TPS61175-Q1 COMP pin is the output of the internal trans-conductance amplifier. Equation 19 shows the
equation for feedback resistor network and the error amplifier.
s
1+
2´ p´ ¦Z
R2
HEA = GEA ´REA
´
´
R2 + R1
æ
ç
è
ö æ
ö
÷
ø
s
s
1+
´ 1+
÷ ç
ø è
2´ p´ ¦P1
2´ p´ ¦P2
(19)
where GEA and REA are the amplifier’s trans-conductance and output resistance located in the Electrical
Characteristics table.
1
¦
=
P1
2p ´ REA ´ C4
(20)
1
¦
=
(optional)
P2
2p´R3´ C5
C5 is optional and can be modeled as 10 pF stray capacitance.
(21)
and
1
¦
=
Z
2p ´ R3 ´ C4
(22)
Figure 11 shows a typical bode plot for transfer function H(s).
16
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
180
90
Phase
0
Kcomp
Gain
–90
–180
<–f 1
p
f 2
p
f
C
f
Z
f − Frequency − kHz
Figure 11. Bode Plot of Feedback Resistors and Compensated Amplifier Gain and Phase
The next step is to choose the loop crossover frequency, fC. The higher in frequency that the loop gain stays
above zero before crossing over, the faster the loop response will be and therefore the lower the output voltage
will droop during a step load. It is generally accepted that the loop gain cross over no higher than the lower of
either 1/5 of the switching frequency, fSW, or 1/3 of the RHPZ frequency, fRHPZ. To approximate a single pole roll-
off up to fP2, select R3 so that the compensation gain, KCOMP, at fC on Figure 11 is the reciprocal of the gain, KPW
,
read at frequency fC from the Figure 10 bode plot or more simply
KCOMP(fC) = 20 × log(GEA × R3 × R2/(R2+R1)) = 1/KPW(fC)
This makes the total loop gain, T(s) = GPS(s) × HEA(s), zero at the fC. Then, select C4 so that fZ ≅ fC/10 and
optional fP2> fC *10. Following this method should lead to a loop with a phase margin near 45 degrees. Lowering
R3 while keeping fZ ≅ fC/10 increases the phase margin and therefore increases the time it takes for the output
voltage to settle following a step load.
In the TPS61175-Q1, if the FB pin voltage changes suddenly due to a load step on the output voltage, the error
amplifier increases its transconductance for 8-ms in an effort to speed up the IC’s transient response and reduce
output voltage droop due to the load step. For example, if the FB voltage decreases 10-mV due to load change,
the error amplifier increases its source current through COMP by 5 times; if FB voltage increases 11-mV, the
sink current through COMP is increased to 3.5 times normal value. This feature often results in saw tooth ringing
on the output voltage, shown as Figure 13. Designing the loop for greater than 45 degrees of phase margin and
greater than 10db gain margin minimizes the amplitude of this ringing. This feature is disabled during soft start.
Copyright © 2014, Texas Instruments Incorporated
17
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
9.2.3 Application Curves
VOUT
500 mV/div
AC
VIN
1 V/div
AC
VOUT
100 mV/div
AC
ILOAD
200 mA/div
t - 100 ms/div
t - 200 ms/div
Figure 13. Load Transient Response
Figure 12. Line Transient Response
VOUT
1 V/div
SW
20 V/div
20 V offset
VOUT
20 mV/div
AC
IL
500 mA/div
IL
100 mA/div
VOUT
100 mV/div
AC
t - 400 ms/div
t - 400 ns/div
Figure 14. PWM Operation
Figure 15. Pulse Skipping
EN
2 V/div
VOUT
5 V/div
IL
500 mA/div
t - 1 ms/div
Figure 16. Soft Startup
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.9 V and 18 V. The input power
supply’s output current needs to be rated according to the supply voltage, output voltage and output current of
the TPS61175-Q1.
18
Copyright © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
11 Layout
11.1 Layout Guidelines
•
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as
well as noise problems. To maximize efficiency, switch rise and fall times are fast. To prevent radiation of
high frequency noise (this is, EMI), proper layout of the high frequency switching path is essential.
•
•
•
Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the
switching regulator to minimize interplane coupling.
The high current path including the switch, Schottky diode, and output capacitor, contains nanosecond rise
and fall times and should be kept as short as possible.
The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the
input supply ripple.
11.2 Layout Example
VIN
INPUT
CAPACITOR
VOUT
INDUCTOR
SCHOTTKEY
OUTPUT
CAPACITOR
SW
SW
PGND
PGND
PGND
NC
Minimize the area
of SW trace
SW
PGND
VIN
EN
SS
FREQ
FB
SYNC
AGND
FEEDBACK
COMP
Place enough
VIAs around
COMPESNATION
NETWORK
AGND
thermal pad to
enhance thermal
performance
Copyright © 2014, Texas Instruments Incorporated
19
TPS61175-Q1
ZHCSD56 –DECEMBER 2014
www.ti.com.cn
11.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61175-Q1. Calculate the maximum allowable dissipation,
PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is
determined using the following equation:
125°C - T
A
P
=
D(max)
R
qJA
(23)
where, TA is the maximum ambient temperature for the application. RθJA is the thermal resistance junction-to-
ambient given in the Thermal Information table.
The TPS61175-Q1 comes in a thermally enhanced TSSOP package. This package includes a thermal pad that
improves the thermal capabilities of the package. The RθJA of the TSSOP package greatly depends on the PCB
layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using
thermal vias underneath the thermal pad.
20
版权 © 2014, Texas Instruments Incorporated
TPS61175-Q1
www.ti.com.cn
ZHCSD56 –DECEMBER 2014
12 器件和文档支持
12.1 商标
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61175QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
61175Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X (0.6)
NOTE 5
2X (0.4)
NOTE 5
THERMAL
PAD
7
8
0.25
1.2 MAX
GAGE PLANE
2.59
1.89
15
0.15
0.05
0.75
0.50
0 -8
A
20
1
14
DETAIL A
TYPICAL
2.6
1.9
4229706/A 06/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.6)
METAL COVERED
BY SOLDER MASK
SYMM
14X (1.5)
(1.2) TYP
14
14X (0.45)
1
(5)
NOTE 9
(R0.05) TYP
SYMM
(0.6)
15
(2.59)
12X (0.65)
7
8
(
0.2) TYP
VIA
SEE DETAILS
(1.1) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4229706/A 06/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.6)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
14X (1.5)
14X (0.45)
14
1
(R0.05) TYP
(2.59)
SYMM
15
BASED ON
0.125 THICK
STENCIL
12X (0.65)
7
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 12X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 2.90
2.60 X 2.59 (SHOWN)
2.37 X 2.36
0.125
0.15
0.175
2.20 X 2.19
4229706/A 06/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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